drivers/spi/spi_bitbang.c

   1 /*
   2  * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/workqueue.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/spi/spi.h>
  28 #include <linux/spi/spi_bitbang.h>
  29
  30
  31 /*----------------------------------------------------------------------*/
  32
  33 /*
  34  * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
  35  * Use this for GPIO or shift-register level hardware APIs.
  36  *
  37  * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
  38  * to glue code.  These bitbang setup() and cleanup() routines are always
  39  * used, though maybe they're called from controller-aware code.
  40  *
  41  * chipselect() and friends may use use spi_device->controller_data and
  42  * controller registers as appropriate.
  43  *
  44  *
  45  * NOTE:  SPI controller pins can often be used as GPIO pins instead,
  46  * which means you could use a bitbang driver either to get hardware
  47  * working quickly, or testing for differences that aren't speed related.
  48  */
  49
  50 struct spi_bitbang_cs {
  51         unsigned        nsecs;  /* (clock cycle time)/2 */
  52         u32             (*txrx_word)(struct spi_device *spi, unsigned nsecs,
  53                                         u32 word, u8 bits);
  54         unsigned        (*txrx_bufs)(struct spi_device *,
  55                                         u32 (*txrx_word)(
  56                                                 struct spi_device *spi,
  57                                                 unsigned nsecs,
  58                                                 u32 word, u8 bits),
  59                                         unsigned, struct spi_transfer *);
  60 };
  61
  62 static unsigned bitbang_txrx_8(
  63         struct spi_device       *spi,
  64         u32                     (*txrx_word)(struct spi_device *spi,
  65                                         unsigned nsecs,
  66                                         u32 word, u8 bits),
  67         unsigned                ns,
  68         struct spi_transfer     *t
  69 ) {
  70         unsigned                bits = spi->bits_per_word;
  71         unsigned                count = t->len;
  72         const u8                *tx = t->tx_buf;
  73         u8                      *rx = t->rx_buf;
  74
  75         while (likely(count > 0)) {
  76                 u8              word = 0;
  77
  78                 if (tx)
  79                         word = *tx++;
  80                 word = txrx_word(spi, ns, word, bits);
  81                 if (rx)
  82                         *rx++ = word;
  83                 count -= 1;
  84         }
  85         return t->len - count;
  86 }
  87
  88 static unsigned bitbang_txrx_16(
  89         struct spi_device       *spi,
  90         u32                     (*txrx_word)(struct spi_device *spi,
  91                                         unsigned nsecs,
  92                                         u32 word, u8 bits),
  93         unsigned                ns,
  94         struct spi_transfer     *t
  95 ) {
  96         unsigned                bits = spi->bits_per_word;
  97         unsigned                count = t->len;
  98         const u16               *tx = t->tx_buf;
  99         u16                     *rx = t->rx_buf;
 100
 101         while (likely(count > 1)) {
 102                 u16             word = 0;
 103
 104                 if (tx)
 105                         word = *tx++;
 106                 word = txrx_word(spi, ns, word, bits);
 107                 if (rx)
 108                         *rx++ = word;
 109                 count -= 2;
 110         }
 111         return t->len - count;
 112 }
 113
 114 static unsigned bitbang_txrx_32(
 115         struct spi_device       *spi,
 116         u32                     (*txrx_word)(struct spi_device *spi,
 117                                         unsigned nsecs,
 118                                         u32 word, u8 bits),
 119         unsigned                ns,
 120         struct spi_transfer     *t
 121 ) {
 122         unsigned                bits = spi->bits_per_word;
 123         unsigned                count = t->len;
 124         const u32               *tx = t->tx_buf;
 125         u32                     *rx = t->rx_buf;
 126
 127         while (likely(count > 3)) {
 128                 u32             word = 0;
 129
 130                 if (tx)
 131                         word = *tx++;
 132                 word = txrx_word(spi, ns, word, bits);
 133                 if (rx)
 134                         *rx++ = word;
 135                 count -= 4;
 136         }
 137         return t->len - count;
 138 }
 139
 140 int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 141 {
 142         struct spi_bitbang_cs   *cs = spi->controller_state;
 143         u8                      bits_per_word;
 144         u32                     hz;
 145
 146         if (t) {
 147                 bits_per_word = t->bits_per_word;
 148                 hz = t->speed_hz;
 149         } else {
 150                 bits_per_word = 0;
 151                 hz = 0;
 152         }
 153
 154         /* spi_transfer level calls that work per-word */
 155         if (!bits_per_word)
 156                 bits_per_word = spi->bits_per_word;
 157         if (bits_per_word <= 8)
 158                 cs->txrx_bufs = bitbang_txrx_8;
 159         else if (bits_per_word <= 16)
 160                 cs->txrx_bufs = bitbang_txrx_16;
 161         else if (bits_per_word <= 32)
 162                 cs->txrx_bufs = bitbang_txrx_32;
 163         else
 164                 return -EINVAL;
 165
 166         /* nsecs = (clock period)/2 */
 167         if (!hz)
 168                 hz = spi->max_speed_hz;
 169         if (hz) {
 170                 cs->nsecs = (1000000000/2) / hz;
 171                 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
 172                         return -EINVAL;
 173         }
 174
 175         return 0;
 176 }
 177 EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
 178
 179 /**
 180  * spi_bitbang_setup - default setup for per-word I/O loops
 181  */
 182 int spi_bitbang_setup(struct spi_device *spi)
 183 {
 184         struct spi_bitbang_cs   *cs = spi->controller_state;
 185         struct spi_bitbang      *bitbang;
 186         int                     retval;
 187
 188         bitbang = spi_master_get_devdata(spi->master);
 189
 190         /* REVISIT: some systems will want to support devices using lsb-first
 191          * bit encodings on the wire.  In pure software that would be trivial,
 192          * just bitbang_txrx_le_cphaX() routines shifting the other way, and
 193          * some hardware controllers also have this support.
 194          */
 195         if ((spi->mode & SPI_LSB_FIRST) != 0)
 196                 return -EINVAL;
 197
 198         if (!cs) {
 199                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 200                 if (!cs)
 201                         return -ENOMEM;
 202                 spi->controller_state = cs;
 203         }
 204
 205         if (!spi->bits_per_word)
 206                 spi->bits_per_word = 8;
 207
 208         /* per-word shift register access, in hardware or bitbanging */
 209         cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
 210         if (!cs->txrx_word)
 211                 return -EINVAL;
 212
 213         retval = bitbang->setup_transfer(spi, NULL);
 214         if (retval < 0)
 215                 return retval;
 216
 217         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 218                         __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
 219                         spi->bits_per_word, 2 * cs->nsecs);
 220
 221         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 222          * setup, unless the hardware defaults cooperate to avoid confusion
 223          * between normal (active low) and inverted chipselects.
 224          */
 225
 226         /* deselect chip (low or high) */
 227         spin_lock(&bitbang->lock);
 228         if (!bitbang->busy) {
 229                 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 230                 ndelay(cs->nsecs);
 231         }
 232         spin_unlock(&bitbang->lock);
 233
 234         return 0;
 235 }
 236 EXPORT_SYMBOL_GPL(spi_bitbang_setup);
 237
 238 /**
 239  * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 240  */
 241 void spi_bitbang_cleanup(struct spi_device *spi)
 242 {
 243         kfree(spi->controller_state);
 244 }
 245 EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
 246
 247 static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
 248 {
 249         struct spi_bitbang_cs   *cs = spi->controller_state;
 250         unsigned                nsecs = cs->nsecs;
 251
 252         return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
 253 }
 254
 255 /*----------------------------------------------------------------------*/
 256
 257 /*
 258  * SECOND PART ... simple transfer queue runner.
 259  *
 260  * This costs a task context per controller, running the queue by
 261  * performing each transfer in sequence.  Smarter hardware can queue
 262  * several DMA transfers at once, and process several controller queues
 263  * in parallel; this driver doesn't match such hardware very well.
 264  *
 265  * Drivers can provide word-at-a-time i/o primitives, or provide
 266  * transfer-at-a-time ones to leverage dma or fifo hardware.
 267  */
 268 static void bitbang_work(struct work_struct *work)
 269 {
 270         struct spi_bitbang      *bitbang =
 271                 container_of(work, struct spi_bitbang, work);
 272         unsigned long           flags;
 273
 274         spin_lock_irqsave(&bitbang->lock, flags);
 275         bitbang->busy = 1;
 276         while (!list_empty(&bitbang->queue)) {
 277                 struct spi_message      *m;
 278                 struct spi_device       *spi;
 279                 unsigned                nsecs;
 280                 struct spi_transfer     *t = NULL;
 281                 unsigned                tmp;
 282                 unsigned                cs_change;
 283                 int                     status;
 284                 int                     (*setup_transfer)(struct spi_device *,
 285                                                 struct spi_transfer *);
 286
 287                 m = container_of(bitbang->queue.next, struct spi_message,
 288                                 queue);
 289                 list_del_init(&m->queue);
 290                 spin_unlock_irqrestore(&bitbang->lock, flags);
 291
 292                 /* FIXME this is made-up ... the correct value is known to
 293                  * word-at-a-time bitbang code, and presumably chipselect()
 294                  * should enforce these requirements too?
 295                  */
 296                 nsecs = 100;
 297
 298                 spi = m->spi;
 299                 tmp = 0;
 300                 cs_change = 1;
 301                 status = 0;
 302                 setup_transfer = NULL;
 303
 304                 list_for_each_entry (t, &m->transfers, transfer_list) {
 305                         if (bitbang->shutdown) {
 306                                 status = -ESHUTDOWN;
 307                                 break;
 308                         }
 309
 310                         /* override or restore speed and wordsize */
 311                         if (t->speed_hz || t->bits_per_word) {
 312                                 setup_transfer = bitbang->setup_transfer;
 313                                 if (!setup_transfer) {
 314                                         status = -ENOPROTOOPT;
 315                                         break;
 316                                 }
 317                         }
 318                         if (setup_transfer) {
 319                                 status = setup_transfer(spi, t);
 320                                 if (status < 0)
 321                                         break;
 322                         }
 323
 324                         /* set up default clock polarity, and activate chip;
 325                          * this implicitly updates clock and spi modes as
 326                          * previously recorded for this device via setup().
 327                          * (and also deselects any other chip that might be
 328                          * selected ...)
 329                          */
 330                         if (cs_change) {
 331                                 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
 332                                 ndelay(nsecs);
 333                         }
 334                         cs_change = t->cs_change;
 335                         if (!t->tx_buf && !t->rx_buf && t->len) {
 336                                 status = -EINVAL;
 337                                 break;
 338                         }
 339
 340                         /* transfer data.  the lower level code handles any
 341                          * new dma mappings it needs. our caller always gave
 342                          * us dma-safe buffers.
 343                          */
 344                         if (t->len) {
 345                                 /* REVISIT dma API still needs a designated
 346                                  * DMA_ADDR_INVALID; ~0 might be better.
 347                                  */
 348                                 if (!m->is_dma_mapped)
 349                                         t->rx_dma = t->tx_dma = 0;
 350                                 status = bitbang->txrx_bufs(spi, t);
 351                         }
 352                         if (status != t->len) {
 353                                 if (status > 0)
 354                                         status = -EMSGSIZE;
 355                                 break;
 356                         }
 357                         m->actual_length += status;
 358                         status = 0;
 359
 360                         /* protocol tweaks before next transfer */
 361                         if (t->delay_usecs)
 362                                 udelay(t->delay_usecs);
 363
 364                         if (!cs_change)
 365                                 continue;
 366                         if (t->transfer_list.next == &m->transfers)
 367                                 break;
 368
 369                         /* sometimes a short mid-message deselect of the chip
 370                          * may be needed to terminate a mode or command
 371                          */
 372                         ndelay(nsecs);
 373                         bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 374                         ndelay(nsecs);
 375                 }
 376
 377                 m->status = status;
 378                 m->complete(m->context);
 379
 380                 /* restore speed and wordsize */
 381                 if (setup_transfer)
 382                         setup_transfer(spi, NULL);
 383
 384                 /* normally deactivate chipselect ... unless no error and
 385                  * cs_change has hinted that the next message will probably
 386                  * be for this chip too.
 387                  */
 388                 if (!(status == 0 && cs_change)) {
 389                         ndelay(nsecs);
 390                         bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 391                         ndelay(nsecs);
 392                 }
 393
 394                 spin_lock_irqsave(&bitbang->lock, flags);
 395         }
 396         bitbang->busy = 0;
 397         spin_unlock_irqrestore(&bitbang->lock, flags);
 398 }
 399
 400 /**
 401  * spi_bitbang_transfer - default submit to transfer queue
 402  */
 403 int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
 404 {
 405         struct spi_bitbang      *bitbang;
 406         unsigned long           flags;
 407         int                     status = 0;
 408
 409         m->actual_length = 0;
 410         m->status = -EINPROGRESS;
 411
 412         bitbang = spi_master_get_devdata(spi->master);
 413         if (bitbang->shutdown)
 414                 return -ESHUTDOWN;
 415
 416         spin_lock_irqsave(&bitbang->lock, flags);
 417         if (!spi->max_speed_hz)
 418                 status = -ENETDOWN;
 419         else {
 420                 list_add_tail(&m->queue, &bitbang->queue);
 421                 queue_work(bitbang->workqueue, &bitbang->work);
 422         }
 423         spin_unlock_irqrestore(&bitbang->lock, flags);
 424
 425         return status;
 426 }
 427 EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
 428
 429 /*----------------------------------------------------------------------*/
 430
 431 /**
 432  * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 433  * @bitbang: driver handle
 434  *
 435  * Caller should have zero-initialized all parts of the structure, and then
 436  * provided callbacks for chip selection and I/O loops.  If the master has
 437  * a transfer method, its final step should call spi_bitbang_transfer; or,
 438  * that's the default if the transfer routine is not initialized.  It should
 439  * also set up the bus number and number of chipselects.
 440  *
 441  * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 442  * hardware that basically exposes a shift register) or per-spi_transfer
 443  * (which takes better advantage of hardware like fifos or DMA engines).
 444  *
 445  * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 446  * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 447  * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 448  * routine isn't initialized.
 449  *
 450  * This routine registers the spi_master, which will process requests in a
 451  * dedicated task, keeping IRQs unblocked most of the time.  To stop
 452  * processing those requests, call spi_bitbang_stop().
 453  */
 454 int spi_bitbang_start(struct spi_bitbang *bitbang)
 455 {
 456         int     status;
 457
 458         if (!bitbang->master || !bitbang->chipselect)
 459                 return -EINVAL;
 460
 461         INIT_WORK(&bitbang->work, bitbang_work);
 462         spin_lock_init(&bitbang->lock);
 463         INIT_LIST_HEAD(&bitbang->queue);
 464
 465         if (!bitbang->master->transfer)
 466                 bitbang->master->transfer = spi_bitbang_transfer;
 467         if (!bitbang->txrx_bufs) {
 468                 bitbang->use_dma = 0;
 469                 bitbang->txrx_bufs = spi_bitbang_bufs;
 470                 if (!bitbang->master->setup) {
 471                         if (!bitbang->setup_transfer)
 472                                 bitbang->setup_transfer =
 473                                          spi_bitbang_setup_transfer;
 474                         bitbang->master->setup = spi_bitbang_setup;
 475                         bitbang->master->cleanup = spi_bitbang_cleanup;
 476                 }
 477         } else if (!bitbang->master->setup)
 478                 return -EINVAL;
 479
 480         /* this task is the only thing to touch the SPI bits */
 481         bitbang->busy = 0;
 482         bitbang->workqueue = create_singlethread_workqueue(
 483                         bitbang->master->cdev.dev->bus_id);
 484         if (bitbang->workqueue == NULL) {
 485                 status = -EBUSY;
 486                 goto err1;
 487         }
 488
 489         /* driver may get busy before register() returns, especially
 490          * if someone registered boardinfo for devices
 491          */
 492         status = spi_register_master(bitbang->master);
 493         if (status < 0)
 494                 goto err2;
 495
 496         return status;
 497
 498 err2:
 499         destroy_workqueue(bitbang->workqueue);
 500 err1:
 501         return status;
 502 }
 503 EXPORT_SYMBOL_GPL(spi_bitbang_start);
 504
 505 /**
 506  * spi_bitbang_stop - stops the task providing spi communication
 507  */
 508 int spi_bitbang_stop(struct spi_bitbang *bitbang)
 509 {
 510         unsigned        limit = 500;
 511
 512         spin_lock_irq(&bitbang->lock);
 513         bitbang->shutdown = 0;
 514         while (!list_empty(&bitbang->queue) && limit--) {
 515                 spin_unlock_irq(&bitbang->lock);
 516
 517                 dev_dbg(bitbang->master->cdev.dev, "wait for queue\n");
 518                 msleep(10);
 519
 520                 spin_lock_irq(&bitbang->lock);
 521         }
 522         spin_unlock_irq(&bitbang->lock);
 523         if (!list_empty(&bitbang->queue)) {
 524                 dev_err(bitbang->master->cdev.dev, "queue didn't empty\n");
 525                 return -EBUSY;
 526         }
 527
 528         destroy_workqueue(bitbang->workqueue);
 529
 530         spi_unregister_master(bitbang->master);
 531
 532         return 0;
 533 }
 534 EXPORT_SYMBOL_GPL(spi_bitbang_stop);
 535
 536 MODULE_LICENSE("GPL");
 537