drivers/spi/spi_bitbang.c

   1 /*
   2  * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/workqueue.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/spi/spi.h>
  28 #include <linux/spi/spi_bitbang.h>
  29
  30
  31 /*----------------------------------------------------------------------*/
  32
  33 /*
  34  * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
  35  * Use this for GPIO or shift-register level hardware APIs.
  36  *
  37  * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
  38  * to glue code.  These bitbang setup() and cleanup() routines are always
  39  * used, though maybe they're called from controller-aware code.
  40  *
  41  * chipselect() and friends may use use spi_device->controller_data and
  42  * controller registers as appropriate.
  43  *
  44  *
  45  * NOTE:  SPI controller pins can often be used as GPIO pins instead,
  46  * which means you could use a bitbang driver either to get hardware
  47  * working quickly, or testing for differences that aren't speed related.
  48  */
  49
  50 struct spi_bitbang_cs {
  51         unsigned        nsecs;  /* (clock cycle time)/2 */
  52         u32             (*txrx_word)(struct spi_device *spi, unsigned nsecs,
  53                                         u32 word, u8 bits);
  54         unsigned        (*txrx_bufs)(struct spi_device *,
  55                                         u32 (*txrx_word)(
  56                                                 struct spi_device *spi,
  57                                                 unsigned nsecs,
  58                                                 u32 word, u8 bits),
  59                                         unsigned, struct spi_transfer *);
  60 };
  61
  62 static unsigned bitbang_txrx_8(
  63         struct spi_device       *spi,
  64         u32                     (*txrx_word)(struct spi_device *spi,
  65                                         unsigned nsecs,
  66                                         u32 word, u8 bits),
  67         unsigned                ns,
  68         struct spi_transfer     *t
  69 ) {
  70         unsigned                bits = spi->bits_per_word;
  71         unsigned                count = t->len;
  72         const u8                *tx = t->tx_buf;
  73         u8                      *rx = t->rx_buf;
  74
  75         while (likely(count > 0)) {
  76                 u8              word = 0;
  77
  78                 if (tx)
  79                         word = *tx++;
  80                 word = txrx_word(spi, ns, word, bits);
  81                 if (rx)
  82                         *rx++ = word;
  83                 count -= 1;
  84         }
  85         return t->len - count;
  86 }
  87
  88 static unsigned bitbang_txrx_16(
  89         struct spi_device       *spi,
  90         u32                     (*txrx_word)(struct spi_device *spi,
  91                                         unsigned nsecs,
  92                                         u32 word, u8 bits),
  93         unsigned                ns,
  94         struct spi_transfer     *t
  95 ) {
  96         unsigned                bits = spi->bits_per_word;
  97         unsigned                count = t->len;
  98         const u16               *tx = t->tx_buf;
  99         u16                     *rx = t->rx_buf;
 100
 101         while (likely(count > 1)) {
 102                 u16             word = 0;
 103
 104                 if (tx)
 105                         word = *tx++;
 106                 word = txrx_word(spi, ns, word, bits);
 107                 if (rx)
 108                         *rx++ = word;
 109                 count -= 2;
 110         }
 111         return t->len - count;
 112 }
 113
 114 static unsigned bitbang_txrx_32(
 115         struct spi_device       *spi,
 116         u32                     (*txrx_word)(struct spi_device *spi,
 117                                         unsigned nsecs,
 118                                         u32 word, u8 bits),
 119         unsigned                ns,
 120         struct spi_transfer     *t
 121 ) {
 122         unsigned                bits = spi->bits_per_word;
 123         unsigned                count = t->len;
 124         const u32               *tx = t->tx_buf;
 125         u32                     *rx = t->rx_buf;
 126
 127         while (likely(count > 3)) {
 128                 u32             word = 0;
 129
 130                 if (tx)
 131                         word = *tx++;
 132                 word = txrx_word(spi, ns, word, bits);
 133                 if (rx)
 134                         *rx++ = word;
 135                 count -= 4;
 136         }
 137         return t->len - count;
 138 }
 139
 140 int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 141 {
 142         struct spi_bitbang_cs   *cs = spi->controller_state;
 143         u8                      bits_per_word;
 144         u32                     hz;
 145
 146         if (t) {
 147                 bits_per_word = t->bits_per_word;
 148                 hz = t->speed_hz;
 149         } else {
 150                 bits_per_word = 0;
 151                 hz = 0;
 152         }
 153
 154         /* spi_transfer level calls that work per-word */
 155         if (!bits_per_word)
 156                 bits_per_word = spi->bits_per_word;
 157         if (bits_per_word <= 8)
 158                 cs->txrx_bufs = bitbang_txrx_8;
 159         else if (bits_per_word <= 16)
 160                 cs->txrx_bufs = bitbang_txrx_16;
 161         else if (bits_per_word <= 32)
 162                 cs->txrx_bufs = bitbang_txrx_32;
 163         else
 164                 return -EINVAL;
 165
 166         /* nsecs = (clock period)/2 */
 167         if (!hz)
 168                 hz = spi->max_speed_hz;
 169         if (hz) {
 170                 cs->nsecs = (1000000000/2) / hz;
 171                 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
 172                         return -EINVAL;
 173         }
 174
 175         return 0;
 176 }
 177 EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
 178
 179 /**
 180  * spi_bitbang_setup - default setup for per-word I/O loops
 181  */
 182 int spi_bitbang_setup(struct spi_device *spi)
 183 {
 184         struct spi_bitbang_cs   *cs = spi->controller_state;
 185         struct spi_bitbang      *bitbang;
 186         int                     retval;
 187
 188         bitbang = spi_master_get_devdata(spi->master);
 189
 190         /* REVISIT: some systems will want to support devices using lsb-first
 191          * bit encodings on the wire.  In pure software that would be trivial,
 192          * just bitbang_txrx_le_cphaX() routines shifting the other way, and
 193          * some hardware controllers also have this support.
 194          */
 195         if ((spi->mode & SPI_LSB_FIRST) != 0)
 196                 return -EINVAL;
 197
 198         if (!cs) {
 199                 cs = kzalloc(sizeof *cs, SLAB_KERNEL);
 200                 if (!cs)
 201                         return -ENOMEM;
 202                 spi->controller_state = cs;
 203         }
 204
 205         if (!spi->bits_per_word)
 206                 spi->bits_per_word = 8;
 207
 208         /* per-word shift register access, in hardware or bitbanging */
 209         cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
 210         if (!cs->txrx_word)
 211                 return -EINVAL;
 212
 213         retval = spi_bitbang_setup_transfer(spi, NULL);
 214         if (retval < 0)
 215                 return retval;
 216
 217         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 218                         __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
 219                         spi->bits_per_word, 2 * cs->nsecs);
 220
 221         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 222          * setup, unless the hardware defaults cooperate to avoid confusion
 223          * between normal (active low) and inverted chipselects.
 224          */
 225
 226         /* deselect chip (low or high) */
 227         spin_lock(&bitbang->lock);
 228         if (!bitbang->busy) {
 229                 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 230                 ndelay(cs->nsecs);
 231         }
 232         spin_unlock(&bitbang->lock);
 233
 234         return 0;
 235 }
 236 EXPORT_SYMBOL_GPL(spi_bitbang_setup);
 237
 238 /**
 239  * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 240  */
 241 void spi_bitbang_cleanup(const struct spi_device *spi)
 242 {
 243         kfree(spi->controller_state);
 244 }
 245 EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
 246
 247 static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
 248 {
 249         struct spi_bitbang_cs   *cs = spi->controller_state;
 250         unsigned                nsecs = cs->nsecs;
 251
 252         return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
 253 }
 254
 255 /*----------------------------------------------------------------------*/
 256
 257 /*
 258  * SECOND PART ... simple transfer queue runner.
 259  *
 260  * This costs a task context per controller, running the queue by
 261  * performing each transfer in sequence.  Smarter hardware can queue
 262  * several DMA transfers at once, and process several controller queues
 263  * in parallel; this driver doesn't match such hardware very well.
 264  *
 265  * Drivers can provide word-at-a-time i/o primitives, or provide
 266  * transfer-at-a-time ones to leverage dma or fifo hardware.
 267  */
 268 static void bitbang_work(void *_bitbang)
 269 {
 270         struct spi_bitbang      *bitbang = _bitbang;
 271         unsigned long           flags;
 272
 273         spin_lock_irqsave(&bitbang->lock, flags);
 274         bitbang->busy = 1;
 275         while (!list_empty(&bitbang->queue)) {
 276                 struct spi_message      *m;
 277                 struct spi_device       *spi;
 278                 unsigned                nsecs;
 279                 struct spi_transfer     *t = NULL;
 280                 unsigned                tmp;
 281                 unsigned                cs_change;
 282                 int                     status;
 283                 int                     (*setup_transfer)(struct spi_device *,
 284                                                 struct spi_transfer *);
 285
 286                 m = container_of(bitbang->queue.next, struct spi_message,
 287                                 queue);
 288                 list_del_init(&m->queue);
 289                 spin_unlock_irqrestore(&bitbang->lock, flags);
 290
 291                 /* FIXME this is made-up ... the correct value is known to
 292                  * word-at-a-time bitbang code, and presumably chipselect()
 293                  * should enforce these requirements too?
 294                  */
 295                 nsecs = 100;
 296
 297                 spi = m->spi;
 298                 tmp = 0;
 299                 cs_change = 1;
 300                 status = 0;
 301                 setup_transfer = NULL;
 302
 303                 list_for_each_entry (t, &m->transfers, transfer_list) {
 304                         if (bitbang->shutdown) {
 305                                 status = -ESHUTDOWN;
 306                                 break;
 307                         }
 308
 309                         /* override or restore speed and wordsize */
 310                         if (t->speed_hz || t->bits_per_word) {
 311                                 setup_transfer = bitbang->setup_transfer;
 312                                 if (!setup_transfer) {
 313                                         status = -ENOPROTOOPT;
 314                                         break;
 315                                 }
 316                         }
 317                         if (setup_transfer) {
 318                                 status = setup_transfer(spi, t);
 319                                 if (status < 0)
 320                                         break;
 321                         }
 322
 323                         /* set up default clock polarity, and activate chip;
 324                          * this implicitly updates clock and spi modes as
 325                          * previously recorded for this device via setup().
 326                          * (and also deselects any other chip that might be
 327                          * selected ...)
 328                          */
 329                         if (cs_change) {
 330                                 bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
 331                                 ndelay(nsecs);
 332                         }
 333                         cs_change = t->cs_change;
 334                         if (!t->tx_buf && !t->rx_buf && t->len) {
 335                                 status = -EINVAL;
 336                                 break;
 337                         }
 338
 339                         /* transfer data.  the lower level code handles any
 340                          * new dma mappings it needs. our caller always gave
 341                          * us dma-safe buffers.
 342                          */
 343                         if (t->len) {
 344                                 /* REVISIT dma API still needs a designated
 345                                  * DMA_ADDR_INVALID; ~0 might be better.
 346                                  */
 347                                 if (!m->is_dma_mapped)
 348                                         t->rx_dma = t->tx_dma = 0;
 349                                 status = bitbang->txrx_bufs(spi, t);
 350                         }
 351                         if (status != t->len) {
 352                                 if (status > 0)
 353                                         status = -EMSGSIZE;
 354                                 break;
 355                         }
 356                         m->actual_length += status;
 357                         status = 0;
 358
 359                         /* protocol tweaks before next transfer */
 360                         if (t->delay_usecs)
 361                                 udelay(t->delay_usecs);
 362
 363                         if (!cs_change)
 364                                 continue;
 365                         if (t->transfer_list.next == &m->transfers)
 366                                 break;
 367
 368                         /* sometimes a short mid-message deselect of the chip
 369                          * may be needed to terminate a mode or command
 370                          */
 371                         ndelay(nsecs);
 372                         bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 373                         ndelay(nsecs);
 374                 }
 375
 376                 m->status = status;
 377                 m->complete(m->context);
 378
 379                 /* restore speed and wordsize */
 380                 if (setup_transfer)
 381                         setup_transfer(spi, NULL);
 382
 383                 /* normally deactivate chipselect ... unless no error and
 384                  * cs_change has hinted that the next message will probably
 385                  * be for this chip too.
 386                  */
 387                 if (!(status == 0 && cs_change)) {
 388                         ndelay(nsecs);
 389                         bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 390                         ndelay(nsecs);
 391                 }
 392
 393                 spin_lock_irqsave(&bitbang->lock, flags);
 394         }
 395         bitbang->busy = 0;
 396         spin_unlock_irqrestore(&bitbang->lock, flags);
 397 }
 398
 399 /**
 400  * spi_bitbang_transfer - default submit to transfer queue
 401  */
 402 int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
 403 {
 404         struct spi_bitbang      *bitbang;
 405         unsigned long           flags;
 406         int                     status = 0;
 407
 408         m->actual_length = 0;
 409         m->status = -EINPROGRESS;
 410
 411         bitbang = spi_master_get_devdata(spi->master);
 412         if (bitbang->shutdown)
 413                 return -ESHUTDOWN;
 414
 415         spin_lock_irqsave(&bitbang->lock, flags);
 416         if (!spi->max_speed_hz)
 417                 status = -ENETDOWN;
 418         else {
 419                 list_add_tail(&m->queue, &bitbang->queue);
 420                 queue_work(bitbang->workqueue, &bitbang->work);
 421         }
 422         spin_unlock_irqrestore(&bitbang->lock, flags);
 423
 424         return status;
 425 }
 426 EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
 427
 428 /*----------------------------------------------------------------------*/
 429
 430 /**
 431  * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 432  * @bitbang: driver handle
 433  *
 434  * Caller should have zero-initialized all parts of the structure, and then
 435  * provided callbacks for chip selection and I/O loops.  If the master has
 436  * a transfer method, its final step should call spi_bitbang_transfer; or,
 437  * that's the default if the transfer routine is not initialized.  It should
 438  * also set up the bus number and number of chipselects.
 439  *
 440  * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 441  * hardware that basically exposes a shift register) or per-spi_transfer
 442  * (which takes better advantage of hardware like fifos or DMA engines).
 443  *
 444  * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup and
 445  * spi_bitbang_cleanup to handle those spi master methods.  Those methods are
 446  * the defaults if the bitbang->txrx_bufs routine isn't initialized.
 447  *
 448  * This routine registers the spi_master, which will process requests in a
 449  * dedicated task, keeping IRQs unblocked most of the time.  To stop
 450  * processing those requests, call spi_bitbang_stop().
 451  */
 452 int spi_bitbang_start(struct spi_bitbang *bitbang)
 453 {
 454         int     status;
 455
 456         if (!bitbang->master || !bitbang->chipselect)
 457                 return -EINVAL;
 458
 459         INIT_WORK(&bitbang->work, bitbang_work, bitbang);
 460         spin_lock_init(&bitbang->lock);
 461         INIT_LIST_HEAD(&bitbang->queue);
 462
 463         if (!bitbang->master->transfer)
 464                 bitbang->master->transfer = spi_bitbang_transfer;
 465         if (!bitbang->txrx_bufs) {
 466                 bitbang->use_dma = 0;
 467                 bitbang->txrx_bufs = spi_bitbang_bufs;
 468                 if (!bitbang->master->setup) {
 469                         if (!bitbang->setup_transfer)
 470                                 bitbang->setup_transfer =
 471                                          spi_bitbang_setup_transfer;
 472                         bitbang->master->setup = spi_bitbang_setup;
 473                         bitbang->master->cleanup = spi_bitbang_cleanup;
 474                 }
 475         } else if (!bitbang->master->setup)
 476                 return -EINVAL;
 477
 478         /* this task is the only thing to touch the SPI bits */
 479         bitbang->busy = 0;
 480         bitbang->workqueue = create_singlethread_workqueue(
 481                         bitbang->master->cdev.dev->bus_id);
 482         if (bitbang->workqueue == NULL) {
 483                 status = -EBUSY;
 484                 goto err1;
 485         }
 486
 487         /* driver may get busy before register() returns, especially
 488          * if someone registered boardinfo for devices
 489          */
 490         status = spi_register_master(bitbang->master);
 491         if (status < 0)
 492                 goto err2;
 493
 494         return status;
 495
 496 err2:
 497         destroy_workqueue(bitbang->workqueue);
 498 err1:
 499         return status;
 500 }
 501 EXPORT_SYMBOL_GPL(spi_bitbang_start);
 502
 503 /**
 504  * spi_bitbang_stop - stops the task providing spi communication
 505  */
 506 int spi_bitbang_stop(struct spi_bitbang *bitbang)
 507 {
 508         unsigned        limit = 500;
 509
 510         spin_lock_irq(&bitbang->lock);
 511         bitbang->shutdown = 0;
 512         while (!list_empty(&bitbang->queue) && limit--) {
 513                 spin_unlock_irq(&bitbang->lock);
 514
 515                 dev_dbg(bitbang->master->cdev.dev, "wait for queue\n");
 516                 msleep(10);
 517
 518                 spin_lock_irq(&bitbang->lock);
 519         }
 520         spin_unlock_irq(&bitbang->lock);
 521         if (!list_empty(&bitbang->queue)) {
 522                 dev_err(bitbang->master->cdev.dev, "queue didn't empty\n");
 523                 return -EBUSY;
 524         }
 525
 526         destroy_workqueue(bitbang->workqueue);
 527
 528         spi_unregister_master(bitbang->master);
 529
 530         return 0;
 531 }
 532 EXPORT_SYMBOL_GPL(spi_bitbang_stop);
 533
 534 MODULE_LICENSE("GPL");
 535