2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44 #define QUEUE_RUNNING 0
45 #define QUEUE_STOPPED 1
47 /* Value to send if no TX value is supplied */
48 #define SPI_IDLE_TXVAL 0x0000
51 /* Driver model hookup */
52 struct platform_device *pdev;
54 /* SPI framework hookup */
55 struct spi_master *master;
57 /* Regs base of SPI controller */
58 void __iomem *regs_base;
60 /* Pin request list */
64 struct bfin5xx_spi_master *master_info;
66 /* Driver message queue */
67 struct workqueue_struct *workqueue;
68 struct work_struct pump_messages;
70 struct list_head queue;
74 /* Message Transfer pump */
75 struct tasklet_struct pump_transfers;
77 /* Current message transfer state info */
78 struct spi_message *cur_msg;
79 struct spi_transfer *cur_transfer;
80 struct chip_data *cur_chip;
102 void (*write) (struct driver_data *);
103 void (*read) (struct driver_data *);
104 void (*duplex) (struct driver_data *);
114 u8 width; /* 0 or 1 */
116 u8 bits_per_word; /* 8 or 16 */
117 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
120 u8 pio_interrupt; /* use spi data irq */
121 void (*write) (struct driver_data *);
122 void (*read) (struct driver_data *);
123 void (*duplex) (struct driver_data *);
126 #define DEFINE_SPI_REG(reg, off) \
127 static inline u16 read_##reg(struct driver_data *drv_data) \
128 { return bfin_read16(drv_data->regs_base + off); } \
129 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
130 { bfin_write16(drv_data->regs_base + off, v); }
132 DEFINE_SPI_REG(CTRL, 0x00)
133 DEFINE_SPI_REG(FLAG, 0x04)
134 DEFINE_SPI_REG(STAT, 0x08)
135 DEFINE_SPI_REG(TDBR, 0x0C)
136 DEFINE_SPI_REG(RDBR, 0x10)
137 DEFINE_SPI_REG(BAUD, 0x14)
138 DEFINE_SPI_REG(SHAW, 0x18)
140 static void bfin_spi_enable(struct driver_data *drv_data)
144 cr = read_CTRL(drv_data);
145 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
148 static void bfin_spi_disable(struct driver_data *drv_data)
152 cr = read_CTRL(drv_data);
153 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
156 /* Caculate the SPI_BAUD register value based on input HZ */
157 static u16 hz_to_spi_baud(u32 speed_hz)
159 u_long sclk = get_sclk();
160 u16 spi_baud = (sclk / (2 * speed_hz));
162 if ((sclk % (2 * speed_hz)) > 0)
165 if (spi_baud < MIN_SPI_BAUD_VAL)
166 spi_baud = MIN_SPI_BAUD_VAL;
171 static int bfin_spi_flush(struct driver_data *drv_data)
173 unsigned long limit = loops_per_jiffy << 1;
175 /* wait for stop and clear stat */
176 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
179 write_STAT(drv_data, BIT_STAT_CLR);
184 /* Chip select operation functions for cs_change flag */
185 static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
187 if (likely(chip->chip_select_num)) {
188 u16 flag = read_FLAG(drv_data);
192 write_FLAG(drv_data, flag);
194 gpio_set_value(chip->cs_gpio, 0);
198 static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
200 if (likely(chip->chip_select_num)) {
201 u16 flag = read_FLAG(drv_data);
205 write_FLAG(drv_data, flag);
207 gpio_set_value(chip->cs_gpio, 1);
210 /* Move delay here for consistency */
211 if (chip->cs_chg_udelay)
212 udelay(chip->cs_chg_udelay);
215 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
216 static inline void bfin_spi_cs_enable(struct driver_data *drv_data, struct chip_data *chip)
218 u16 flag = read_FLAG(drv_data);
220 flag |= (chip->flag >> 8);
222 write_FLAG(drv_data, flag);
225 static inline void bfin_spi_cs_disable(struct driver_data *drv_data, struct chip_data *chip)
227 u16 flag = read_FLAG(drv_data);
229 flag &= ~(chip->flag >> 8);
231 write_FLAG(drv_data, flag);
234 /* stop controller and re-config current chip*/
235 static void bfin_spi_restore_state(struct driver_data *drv_data)
237 struct chip_data *chip = drv_data->cur_chip;
239 /* Clear status and disable clock */
240 write_STAT(drv_data, BIT_STAT_CLR);
241 bfin_spi_disable(drv_data);
242 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
244 /* Load the registers */
245 write_CTRL(drv_data, chip->ctl_reg);
246 write_BAUD(drv_data, chip->baud);
248 bfin_spi_enable(drv_data);
249 bfin_spi_cs_active(drv_data, chip);
252 /* used to kick off transfer in rx mode and read unwanted RX data */
253 static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
255 (void) read_RDBR(drv_data);
258 static void bfin_spi_u8_writer(struct driver_data *drv_data)
260 /* clear RXS (we check for RXS inside the loop) */
261 bfin_spi_dummy_read(drv_data);
263 while (drv_data->tx < drv_data->tx_end) {
264 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
265 /* wait until transfer finished.
266 checking SPIF or TXS may not guarantee transfer completion */
267 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
269 /* discard RX data and clear RXS */
270 bfin_spi_dummy_read(drv_data);
274 static void bfin_spi_u8_reader(struct driver_data *drv_data)
276 u16 tx_val = drv_data->cur_chip->idle_tx_val;
278 /* discard old RX data and clear RXS */
279 bfin_spi_dummy_read(drv_data);
281 while (drv_data->rx < drv_data->rx_end) {
282 write_TDBR(drv_data, tx_val);
283 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
285 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
289 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
291 /* discard old RX data and clear RXS */
292 bfin_spi_dummy_read(drv_data);
294 while (drv_data->rx < drv_data->rx_end) {
295 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
296 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
298 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
302 static void bfin_spi_u16_writer(struct driver_data *drv_data)
304 /* clear RXS (we check for RXS inside the loop) */
305 bfin_spi_dummy_read(drv_data);
307 while (drv_data->tx < drv_data->tx_end) {
308 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
310 /* wait until transfer finished.
311 checking SPIF or TXS may not guarantee transfer completion */
312 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
314 /* discard RX data and clear RXS */
315 bfin_spi_dummy_read(drv_data);
319 static void bfin_spi_u16_reader(struct driver_data *drv_data)
321 u16 tx_val = drv_data->cur_chip->idle_tx_val;
323 /* discard old RX data and clear RXS */
324 bfin_spi_dummy_read(drv_data);
326 while (drv_data->rx < drv_data->rx_end) {
327 write_TDBR(drv_data, tx_val);
328 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
330 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
335 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
337 /* discard old RX data and clear RXS */
338 bfin_spi_dummy_read(drv_data);
340 while (drv_data->rx < drv_data->rx_end) {
341 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
345 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
350 /* test if ther is more transfer to be done */
351 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
353 struct spi_message *msg = drv_data->cur_msg;
354 struct spi_transfer *trans = drv_data->cur_transfer;
356 /* Move to next transfer */
357 if (trans->transfer_list.next != &msg->transfers) {
358 drv_data->cur_transfer =
359 list_entry(trans->transfer_list.next,
360 struct spi_transfer, transfer_list);
361 return RUNNING_STATE;
367 * caller already set message->status;
368 * dma and pio irqs are blocked give finished message back
370 static void bfin_spi_giveback(struct driver_data *drv_data)
372 struct chip_data *chip = drv_data->cur_chip;
373 struct spi_transfer *last_transfer;
375 struct spi_message *msg;
377 spin_lock_irqsave(&drv_data->lock, flags);
378 msg = drv_data->cur_msg;
379 drv_data->cur_msg = NULL;
380 drv_data->cur_transfer = NULL;
381 drv_data->cur_chip = NULL;
382 queue_work(drv_data->workqueue, &drv_data->pump_messages);
383 spin_unlock_irqrestore(&drv_data->lock, flags);
385 last_transfer = list_entry(msg->transfers.prev,
386 struct spi_transfer, transfer_list);
390 if (!drv_data->cs_change)
391 bfin_spi_cs_deactive(drv_data, chip);
393 /* Not stop spi in autobuffer mode */
394 if (drv_data->tx_dma != 0xFFFF)
395 bfin_spi_disable(drv_data);
398 msg->complete(msg->context);
401 /* spi data irq handler */
402 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
404 struct driver_data *drv_data = dev_id;
405 struct chip_data *chip = drv_data->cur_chip;
406 struct spi_message *msg = drv_data->cur_msg;
407 int n_bytes = drv_data->n_bytes;
409 /* wait until transfer finished. */
410 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
413 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
414 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
417 dev_dbg(&drv_data->pdev->dev, "last read\n");
419 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
420 else if (n_bytes == 1)
421 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
422 drv_data->rx += n_bytes;
425 msg->actual_length += drv_data->len_in_bytes;
426 if (drv_data->cs_change)
427 bfin_spi_cs_deactive(drv_data, chip);
428 /* Move to next transfer */
429 msg->state = bfin_spi_next_transfer(drv_data);
431 disable_irq(drv_data->spi_irq);
433 /* Schedule transfer tasklet */
434 tasklet_schedule(&drv_data->pump_transfers);
438 if (drv_data->rx && drv_data->tx) {
440 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
441 if (drv_data->n_bytes == 2) {
442 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
443 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
444 } else if (drv_data->n_bytes == 1) {
445 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
446 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
448 } else if (drv_data->rx) {
450 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
451 if (drv_data->n_bytes == 2)
452 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
453 else if (drv_data->n_bytes == 1)
454 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
455 write_TDBR(drv_data, chip->idle_tx_val);
456 } else if (drv_data->tx) {
458 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
459 bfin_spi_dummy_read(drv_data);
460 if (drv_data->n_bytes == 2)
461 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
462 else if (drv_data->n_bytes == 1)
463 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
467 drv_data->tx += n_bytes;
469 drv_data->rx += n_bytes;
474 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
476 struct driver_data *drv_data = dev_id;
477 struct chip_data *chip = drv_data->cur_chip;
478 struct spi_message *msg = drv_data->cur_msg;
479 unsigned long timeout;
480 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
481 u16 spistat = read_STAT(drv_data);
483 dev_dbg(&drv_data->pdev->dev,
484 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
487 clear_dma_irqstat(drv_data->dma_channel);
490 * wait for the last transaction shifted out. HRM states:
491 * at this point there may still be data in the SPI DMA FIFO waiting
492 * to be transmitted ... software needs to poll TXS in the SPI_STAT
493 * register until it goes low for 2 successive reads
495 if (drv_data->tx != NULL) {
496 while ((read_STAT(drv_data) & TXS) ||
497 (read_STAT(drv_data) & TXS))
501 dev_dbg(&drv_data->pdev->dev,
502 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
503 dmastat, read_STAT(drv_data));
505 timeout = jiffies + HZ;
506 while (!(read_STAT(drv_data) & SPIF))
507 if (!time_before(jiffies, timeout)) {
508 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
513 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
514 msg->state = ERROR_STATE;
515 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
517 msg->actual_length += drv_data->len_in_bytes;
519 if (drv_data->cs_change)
520 bfin_spi_cs_deactive(drv_data, chip);
522 /* Move to next transfer */
523 msg->state = bfin_spi_next_transfer(drv_data);
526 /* Schedule transfer tasklet */
527 tasklet_schedule(&drv_data->pump_transfers);
529 /* free the irq handler before next transfer */
530 dev_dbg(&drv_data->pdev->dev,
531 "disable dma channel irq%d\n",
532 drv_data->dma_channel);
533 dma_disable_irq(drv_data->dma_channel);
538 static void bfin_spi_pump_transfers(unsigned long data)
540 struct driver_data *drv_data = (struct driver_data *)data;
541 struct spi_message *message = NULL;
542 struct spi_transfer *transfer = NULL;
543 struct spi_transfer *previous = NULL;
544 struct chip_data *chip = NULL;
546 u16 cr, dma_width, dma_config;
547 u32 tranf_success = 1;
550 /* Get current state information */
551 message = drv_data->cur_msg;
552 transfer = drv_data->cur_transfer;
553 chip = drv_data->cur_chip;
556 * if msg is error or done, report it back using complete() callback
559 /* Handle for abort */
560 if (message->state == ERROR_STATE) {
561 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
562 message->status = -EIO;
563 bfin_spi_giveback(drv_data);
567 /* Handle end of message */
568 if (message->state == DONE_STATE) {
569 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
571 bfin_spi_giveback(drv_data);
575 /* Delay if requested at end of transfer */
576 if (message->state == RUNNING_STATE) {
577 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
578 previous = list_entry(transfer->transfer_list.prev,
579 struct spi_transfer, transfer_list);
580 if (previous->delay_usecs)
581 udelay(previous->delay_usecs);
584 /* Setup the transfer state based on the type of transfer */
585 if (bfin_spi_flush(drv_data) == 0) {
586 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
587 message->status = -EIO;
588 bfin_spi_giveback(drv_data);
592 if (transfer->len == 0) {
593 /* Move to next transfer of this msg */
594 message->state = bfin_spi_next_transfer(drv_data);
595 /* Schedule next transfer tasklet */
596 tasklet_schedule(&drv_data->pump_transfers);
599 if (transfer->tx_buf != NULL) {
600 drv_data->tx = (void *)transfer->tx_buf;
601 drv_data->tx_end = drv_data->tx + transfer->len;
602 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
603 transfer->tx_buf, drv_data->tx_end);
608 if (transfer->rx_buf != NULL) {
609 full_duplex = transfer->tx_buf != NULL;
610 drv_data->rx = transfer->rx_buf;
611 drv_data->rx_end = drv_data->rx + transfer->len;
612 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
613 transfer->rx_buf, drv_data->rx_end);
618 drv_data->rx_dma = transfer->rx_dma;
619 drv_data->tx_dma = transfer->tx_dma;
620 drv_data->len_in_bytes = transfer->len;
621 drv_data->cs_change = transfer->cs_change;
623 /* Bits per word setup */
624 switch (transfer->bits_per_word) {
626 drv_data->n_bytes = 1;
627 width = CFG_SPI_WORDSIZE8;
628 drv_data->read = bfin_spi_u8_reader;
629 drv_data->write = bfin_spi_u8_writer;
630 drv_data->duplex = bfin_spi_u8_duplex;
634 drv_data->n_bytes = 2;
635 width = CFG_SPI_WORDSIZE16;
636 drv_data->read = bfin_spi_u16_reader;
637 drv_data->write = bfin_spi_u16_writer;
638 drv_data->duplex = bfin_spi_u16_duplex;
642 /* No change, the same as default setting */
643 transfer->bits_per_word = chip->bits_per_word;
644 drv_data->n_bytes = chip->n_bytes;
646 drv_data->write = chip->write;
647 drv_data->read = chip->read;
648 drv_data->duplex = chip->duplex;
651 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
653 write_CTRL(drv_data, cr);
655 if (width == CFG_SPI_WORDSIZE16) {
656 drv_data->len = (transfer->len) >> 1;
658 drv_data->len = transfer->len;
660 dev_dbg(&drv_data->pdev->dev,
661 "transfer: drv_data->write is %p, chip->write is %p\n",
662 drv_data->write, chip->write);
664 /* speed and width has been set on per message */
665 message->state = RUNNING_STATE;
668 /* Speed setup (surely valid because already checked) */
669 if (transfer->speed_hz)
670 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
672 write_BAUD(drv_data, chip->baud);
674 write_STAT(drv_data, BIT_STAT_CLR);
675 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
676 if (drv_data->cs_change)
677 bfin_spi_cs_active(drv_data, chip);
679 dev_dbg(&drv_data->pdev->dev,
680 "now pumping a transfer: width is %d, len is %d\n",
681 width, transfer->len);
684 * Try to map dma buffer and do a dma transfer. If successful use,
685 * different way to r/w according to the enable_dma settings and if
686 * we are not doing a full duplex transfer (since the hardware does
687 * not support full duplex DMA transfers).
689 if (!full_duplex && drv_data->cur_chip->enable_dma
690 && drv_data->len > 6) {
692 unsigned long dma_start_addr, flags;
694 disable_dma(drv_data->dma_channel);
695 clear_dma_irqstat(drv_data->dma_channel);
697 /* config dma channel */
698 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
699 set_dma_x_count(drv_data->dma_channel, drv_data->len);
700 if (width == CFG_SPI_WORDSIZE16) {
701 set_dma_x_modify(drv_data->dma_channel, 2);
702 dma_width = WDSIZE_16;
704 set_dma_x_modify(drv_data->dma_channel, 1);
705 dma_width = WDSIZE_8;
708 /* poll for SPI completion before start */
709 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
712 /* dirty hack for autobuffer DMA mode */
713 if (drv_data->tx_dma == 0xFFFF) {
714 dev_dbg(&drv_data->pdev->dev,
715 "doing autobuffer DMA out.\n");
717 /* no irq in autobuffer mode */
719 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
720 set_dma_config(drv_data->dma_channel, dma_config);
721 set_dma_start_addr(drv_data->dma_channel,
722 (unsigned long)drv_data->tx);
723 enable_dma(drv_data->dma_channel);
725 /* start SPI transfer */
726 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
728 /* just return here, there can only be one transfer
732 bfin_spi_giveback(drv_data);
736 /* In dma mode, rx or tx must be NULL in one transfer */
737 dma_config = (RESTART | dma_width | DI_EN);
738 if (drv_data->rx != NULL) {
739 /* set transfer mode, and enable SPI */
740 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
741 drv_data->rx, drv_data->len_in_bytes);
743 /* invalidate caches, if needed */
744 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
745 invalidate_dcache_range((unsigned long) drv_data->rx,
746 (unsigned long) (drv_data->rx +
747 drv_data->len_in_bytes));
750 dma_start_addr = (unsigned long)drv_data->rx;
751 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
753 } else if (drv_data->tx != NULL) {
754 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
756 /* flush caches, if needed */
757 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
758 flush_dcache_range((unsigned long) drv_data->tx,
759 (unsigned long) (drv_data->tx +
760 drv_data->len_in_bytes));
762 dma_start_addr = (unsigned long)drv_data->tx;
763 cr |= BIT_CTL_TIMOD_DMA_TX;
768 /* oh man, here there be monsters ... and i dont mean the
769 * fluffy cute ones from pixar, i mean the kind that'll eat
770 * your data, kick your dog, and love it all. do *not* try
771 * and change these lines unless you (1) heavily test DMA
772 * with SPI flashes on a loaded system (e.g. ping floods),
773 * (2) know just how broken the DMA engine interaction with
774 * the SPI peripheral is, and (3) have someone else to blame
775 * when you screw it all up anyways.
777 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
778 set_dma_config(drv_data->dma_channel, dma_config);
779 local_irq_save(flags);
781 write_CTRL(drv_data, cr);
782 enable_dma(drv_data->dma_channel);
783 dma_enable_irq(drv_data->dma_channel);
784 local_irq_restore(flags);
789 if (chip->pio_interrupt) {
790 /* use write mode. spi irq should have been disabled */
791 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
792 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
794 /* discard old RX data and clear RXS */
795 bfin_spi_dummy_read(drv_data);
798 if (drv_data->tx == NULL)
799 write_TDBR(drv_data, chip->idle_tx_val);
801 if (transfer->bits_per_word == 8)
802 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
803 else if (transfer->bits_per_word == 16)
804 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
805 drv_data->tx += drv_data->n_bytes;
808 /* once TDBR is empty, interrupt is triggered */
809 enable_irq(drv_data->spi_irq);
814 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
816 /* we always use SPI_WRITE mode. SPI_READ mode
817 seems to have problems with setting up the
818 output value in TDBR prior to the transfer. */
819 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
822 /* full duplex mode */
823 BUG_ON((drv_data->tx_end - drv_data->tx) !=
824 (drv_data->rx_end - drv_data->rx));
825 dev_dbg(&drv_data->pdev->dev,
826 "IO duplex: cr is 0x%x\n", cr);
828 drv_data->duplex(drv_data);
830 if (drv_data->tx != drv_data->tx_end)
832 } else if (drv_data->tx != NULL) {
833 /* write only half duplex */
834 dev_dbg(&drv_data->pdev->dev,
835 "IO write: cr is 0x%x\n", cr);
837 drv_data->write(drv_data);
839 if (drv_data->tx != drv_data->tx_end)
841 } else if (drv_data->rx != NULL) {
842 /* read only half duplex */
843 dev_dbg(&drv_data->pdev->dev,
844 "IO read: cr is 0x%x\n", cr);
846 drv_data->read(drv_data);
847 if (drv_data->rx != drv_data->rx_end)
851 if (!tranf_success) {
852 dev_dbg(&drv_data->pdev->dev,
853 "IO write error!\n");
854 message->state = ERROR_STATE;
856 /* Update total byte transfered */
857 message->actual_length += drv_data->len_in_bytes;
858 /* Move to next transfer of this msg */
859 message->state = bfin_spi_next_transfer(drv_data);
860 if (drv_data->cs_change)
861 bfin_spi_cs_deactive(drv_data, chip);
864 /* Schedule next transfer tasklet */
865 tasklet_schedule(&drv_data->pump_transfers);
868 /* pop a msg from queue and kick off real transfer */
869 static void bfin_spi_pump_messages(struct work_struct *work)
871 struct driver_data *drv_data;
874 drv_data = container_of(work, struct driver_data, pump_messages);
876 /* Lock queue and check for queue work */
877 spin_lock_irqsave(&drv_data->lock, flags);
878 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
879 /* pumper kicked off but no work to do */
881 spin_unlock_irqrestore(&drv_data->lock, flags);
885 /* Make sure we are not already running a message */
886 if (drv_data->cur_msg) {
887 spin_unlock_irqrestore(&drv_data->lock, flags);
891 /* Extract head of queue */
892 drv_data->cur_msg = list_entry(drv_data->queue.next,
893 struct spi_message, queue);
895 /* Setup the SSP using the per chip configuration */
896 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
897 bfin_spi_restore_state(drv_data);
899 list_del_init(&drv_data->cur_msg->queue);
901 /* Initial message state */
902 drv_data->cur_msg->state = START_STATE;
903 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
904 struct spi_transfer, transfer_list);
906 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
907 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
908 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
909 drv_data->cur_chip->ctl_reg);
911 dev_dbg(&drv_data->pdev->dev,
912 "the first transfer len is %d\n",
913 drv_data->cur_transfer->len);
915 /* Mark as busy and launch transfers */
916 tasklet_schedule(&drv_data->pump_transfers);
919 spin_unlock_irqrestore(&drv_data->lock, flags);
923 * got a msg to transfer, queue it in drv_data->queue.
924 * And kick off message pumper
926 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
928 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
931 spin_lock_irqsave(&drv_data->lock, flags);
933 if (drv_data->run == QUEUE_STOPPED) {
934 spin_unlock_irqrestore(&drv_data->lock, flags);
938 msg->actual_length = 0;
939 msg->status = -EINPROGRESS;
940 msg->state = START_STATE;
942 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
943 list_add_tail(&msg->queue, &drv_data->queue);
945 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
946 queue_work(drv_data->workqueue, &drv_data->pump_messages);
948 spin_unlock_irqrestore(&drv_data->lock, flags);
953 #define MAX_SPI_SSEL 7
955 static u16 ssel[][MAX_SPI_SSEL] = {
956 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
957 P_SPI0_SSEL4, P_SPI0_SSEL5,
958 P_SPI0_SSEL6, P_SPI0_SSEL7},
960 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
961 P_SPI1_SSEL4, P_SPI1_SSEL5,
962 P_SPI1_SSEL6, P_SPI1_SSEL7},
964 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
965 P_SPI2_SSEL4, P_SPI2_SSEL5,
966 P_SPI2_SSEL6, P_SPI2_SSEL7},
969 /* first setup for new devices */
970 static int bfin_spi_setup(struct spi_device *spi)
972 struct bfin5xx_spi_chip *chip_info;
973 struct chip_data *chip = NULL;
974 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
977 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
980 /* Only alloc (or use chip_info) on first setup */
982 chip = spi_get_ctldata(spi);
984 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
986 dev_err(&spi->dev, "cannot allocate chip data\n");
991 chip->enable_dma = 0;
992 chip_info = spi->controller_data;
995 /* chip_info isn't always needed */
997 /* Make sure people stop trying to set fields via ctl_reg
998 * when they should actually be using common SPI framework.
999 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1000 * Not sure if a user actually needs/uses any of these,
1001 * but let's assume (for now) they do.
1003 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1004 dev_err(&spi->dev, "do not set bits in ctl_reg "
1005 "that the SPI framework manages\n");
1009 chip->enable_dma = chip_info->enable_dma != 0
1010 && drv_data->master_info->enable_dma;
1011 chip->ctl_reg = chip_info->ctl_reg;
1012 chip->bits_per_word = chip_info->bits_per_word;
1013 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1014 chip->cs_gpio = chip_info->cs_gpio;
1015 chip->idle_tx_val = chip_info->idle_tx_val;
1016 chip->pio_interrupt = chip_info->pio_interrupt;
1019 /* translate common spi framework into our register */
1020 if (spi->mode & SPI_CPOL)
1021 chip->ctl_reg |= CPOL;
1022 if (spi->mode & SPI_CPHA)
1023 chip->ctl_reg |= CPHA;
1024 if (spi->mode & SPI_LSB_FIRST)
1025 chip->ctl_reg |= LSBF;
1026 /* we dont support running in slave mode (yet?) */
1027 chip->ctl_reg |= MSTR;
1030 * Notice: for blackfin, the speed_hz is the value of register
1031 * SPI_BAUD, not the real baudrate
1033 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1034 chip->flag = (1 << (spi->chip_select)) << 8;
1035 chip->chip_select_num = spi->chip_select;
1037 switch (chip->bits_per_word) {
1040 chip->width = CFG_SPI_WORDSIZE8;
1041 chip->read = bfin_spi_u8_reader;
1042 chip->write = bfin_spi_u8_writer;
1043 chip->duplex = bfin_spi_u8_duplex;
1048 chip->width = CFG_SPI_WORDSIZE16;
1049 chip->read = bfin_spi_u16_reader;
1050 chip->write = bfin_spi_u16_writer;
1051 chip->duplex = bfin_spi_u16_duplex;
1055 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1056 chip->bits_per_word);
1060 if (chip->enable_dma && chip->pio_interrupt) {
1061 dev_err(&spi->dev, "enable_dma is set, "
1062 "do not set pio_interrupt\n");
1066 * if any one SPI chip is registered and wants DMA, request the
1067 * DMA channel for it
1069 if (chip->enable_dma && !drv_data->dma_requested) {
1070 /* register dma irq handler */
1071 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1074 "Unable to request BlackFin SPI DMA channel\n");
1077 drv_data->dma_requested = 1;
1079 ret = set_dma_callback(drv_data->dma_channel,
1080 bfin_spi_dma_irq_handler, drv_data);
1082 dev_err(&spi->dev, "Unable to set dma callback\n");
1085 dma_disable_irq(drv_data->dma_channel);
1088 if (chip->pio_interrupt && !drv_data->irq_requested) {
1089 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1090 IRQF_DISABLED, "BFIN_SPI", drv_data);
1092 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1095 drv_data->irq_requested = 1;
1096 /* we use write mode, spi irq has to be disabled here */
1097 disable_irq(drv_data->spi_irq);
1100 if (chip->chip_select_num == 0) {
1101 ret = gpio_request(chip->cs_gpio, spi->modalias);
1103 dev_err(&spi->dev, "gpio_request() error\n");
1106 gpio_direction_output(chip->cs_gpio, 1);
1109 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1110 spi->modalias, chip->width, chip->enable_dma);
1111 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1112 chip->ctl_reg, chip->flag);
1114 spi_set_ctldata(spi, chip);
1116 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1117 if (chip->chip_select_num > 0 &&
1118 chip->chip_select_num <= spi->master->num_chipselect) {
1119 ret = peripheral_request(ssel[spi->master->bus_num]
1120 [chip->chip_select_num-1], spi->modalias);
1122 dev_err(&spi->dev, "peripheral_request() error\n");
1127 bfin_spi_cs_enable(drv_data, chip);
1128 bfin_spi_cs_deactive(drv_data, chip);
1133 if (chip->chip_select_num == 0)
1134 gpio_free(chip->cs_gpio);
1136 peripheral_free(ssel[spi->master->bus_num]
1137 [chip->chip_select_num - 1]);
1140 if (drv_data->dma_requested)
1141 free_dma(drv_data->dma_channel);
1142 drv_data->dma_requested = 0;
1145 /* prevent free 'chip' twice */
1146 spi_set_ctldata(spi, NULL);
1153 * callback for spi framework.
1154 * clean driver specific data
1156 static void bfin_spi_cleanup(struct spi_device *spi)
1158 struct chip_data *chip = spi_get_ctldata(spi);
1159 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect)) {
1166 peripheral_free(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1]);
1168 bfin_spi_cs_disable(drv_data, chip);
1171 if (chip->chip_select_num == 0)
1172 gpio_free(chip->cs_gpio);
1175 /* prevent free 'chip' twice */
1176 spi_set_ctldata(spi, NULL);
1179 static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1181 INIT_LIST_HEAD(&drv_data->queue);
1182 spin_lock_init(&drv_data->lock);
1184 drv_data->run = QUEUE_STOPPED;
1187 /* init transfer tasklet */
1188 tasklet_init(&drv_data->pump_transfers,
1189 bfin_spi_pump_transfers, (unsigned long)drv_data);
1191 /* init messages workqueue */
1192 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1193 drv_data->workqueue = create_singlethread_workqueue(
1194 dev_name(drv_data->master->dev.parent));
1195 if (drv_data->workqueue == NULL)
1201 static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1203 unsigned long flags;
1205 spin_lock_irqsave(&drv_data->lock, flags);
1207 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1208 spin_unlock_irqrestore(&drv_data->lock, flags);
1212 drv_data->run = QUEUE_RUNNING;
1213 drv_data->cur_msg = NULL;
1214 drv_data->cur_transfer = NULL;
1215 drv_data->cur_chip = NULL;
1216 spin_unlock_irqrestore(&drv_data->lock, flags);
1218 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1223 static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1225 unsigned long flags;
1226 unsigned limit = 500;
1229 spin_lock_irqsave(&drv_data->lock, flags);
1232 * This is a bit lame, but is optimized for the common execution path.
1233 * A wait_queue on the drv_data->busy could be used, but then the common
1234 * execution path (pump_messages) would be required to call wake_up or
1235 * friends on every SPI message. Do this instead
1237 drv_data->run = QUEUE_STOPPED;
1238 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1241 spin_lock_irqsave(&drv_data->lock, flags);
1244 if (!list_empty(&drv_data->queue) || drv_data->busy)
1247 spin_unlock_irqrestore(&drv_data->lock, flags);
1252 static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1256 status = bfin_spi_stop_queue(drv_data);
1260 destroy_workqueue(drv_data->workqueue);
1265 static int __init bfin_spi_probe(struct platform_device *pdev)
1267 struct device *dev = &pdev->dev;
1268 struct bfin5xx_spi_master *platform_info;
1269 struct spi_master *master;
1270 struct driver_data *drv_data = 0;
1271 struct resource *res;
1274 platform_info = dev->platform_data;
1276 /* Allocate master with space for drv_data */
1277 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1279 dev_err(&pdev->dev, "can not alloc spi_master\n");
1283 drv_data = spi_master_get_devdata(master);
1284 drv_data->master = master;
1285 drv_data->master_info = platform_info;
1286 drv_data->pdev = pdev;
1287 drv_data->pin_req = platform_info->pin_req;
1289 /* the spi->mode bits supported by this driver: */
1290 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1292 master->bus_num = pdev->id;
1293 master->num_chipselect = platform_info->num_chipselect;
1294 master->cleanup = bfin_spi_cleanup;
1295 master->setup = bfin_spi_setup;
1296 master->transfer = bfin_spi_transfer;
1298 /* Find and map our resources */
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1303 goto out_error_get_res;
1306 drv_data->regs_base = ioremap(res->start, resource_size(res));
1307 if (drv_data->regs_base == NULL) {
1308 dev_err(dev, "Cannot map IO\n");
1310 goto out_error_ioremap;
1313 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1315 dev_err(dev, "No DMA channel specified\n");
1317 goto out_error_free_io;
1319 drv_data->dma_channel = res->start;
1321 drv_data->spi_irq = platform_get_irq(pdev, 0);
1322 if (drv_data->spi_irq < 0) {
1323 dev_err(dev, "No spi pio irq specified\n");
1325 goto out_error_free_io;
1328 /* Initial and start queue */
1329 status = bfin_spi_init_queue(drv_data);
1331 dev_err(dev, "problem initializing queue\n");
1332 goto out_error_queue_alloc;
1335 status = bfin_spi_start_queue(drv_data);
1337 dev_err(dev, "problem starting queue\n");
1338 goto out_error_queue_alloc;
1341 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1343 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1344 goto out_error_queue_alloc;
1347 /* Reset SPI registers. If these registers were used by the boot loader,
1348 * the sky may fall on your head if you enable the dma controller.
1350 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1351 write_FLAG(drv_data, 0xFF00);
1353 /* Register with the SPI framework */
1354 platform_set_drvdata(pdev, drv_data);
1355 status = spi_register_master(master);
1357 dev_err(dev, "problem registering spi master\n");
1358 goto out_error_queue_alloc;
1361 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1362 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1363 drv_data->dma_channel);
1366 out_error_queue_alloc:
1367 bfin_spi_destroy_queue(drv_data);
1369 iounmap((void *) drv_data->regs_base);
1372 spi_master_put(master);
1377 /* stop hardware and remove the driver */
1378 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1380 struct driver_data *drv_data = platform_get_drvdata(pdev);
1386 /* Remove the queue */
1387 status = bfin_spi_destroy_queue(drv_data);
1391 /* Disable the SSP at the peripheral and SOC level */
1392 bfin_spi_disable(drv_data);
1395 if (drv_data->master_info->enable_dma) {
1396 if (dma_channel_active(drv_data->dma_channel))
1397 free_dma(drv_data->dma_channel);
1400 if (drv_data->irq_requested) {
1401 free_irq(drv_data->spi_irq, drv_data);
1402 drv_data->irq_requested = 0;
1405 /* Disconnect from the SPI framework */
1406 spi_unregister_master(drv_data->master);
1408 peripheral_free_list(drv_data->pin_req);
1410 /* Prevent double remove */
1411 platform_set_drvdata(pdev, NULL);
1417 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1419 struct driver_data *drv_data = platform_get_drvdata(pdev);
1422 status = bfin_spi_stop_queue(drv_data);
1427 bfin_spi_disable(drv_data);
1432 static int bfin_spi_resume(struct platform_device *pdev)
1434 struct driver_data *drv_data = platform_get_drvdata(pdev);
1437 /* Enable the SPI interface */
1438 bfin_spi_enable(drv_data);
1440 /* Start the queue running */
1441 status = bfin_spi_start_queue(drv_data);
1443 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1450 #define bfin_spi_suspend NULL
1451 #define bfin_spi_resume NULL
1452 #endif /* CONFIG_PM */
1454 MODULE_ALIAS("platform:bfin-spi");
1455 static struct platform_driver bfin_spi_driver = {
1458 .owner = THIS_MODULE,
1460 .suspend = bfin_spi_suspend,
1461 .resume = bfin_spi_resume,
1462 .remove = __devexit_p(bfin_spi_remove),
1465 static int __init bfin_spi_init(void)
1467 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1469 module_init(bfin_spi_init);
1471 static void __exit bfin_spi_exit(void)
1473 platform_driver_unregister(&bfin_spi_driver);
1475 module_exit(bfin_spi_exit);