2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/delay.h>
37 #include <mach/hardware.h>
38 #include <mach/pxa-regs.h>
39 #include <mach/regs-ssp.h>
41 #include <mach/pxa2xx_spi.h>
43 MODULE_AUTHOR("Stephen Street");
44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:pxa2xx-spi");
50 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
61 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
68 #define DEFINE_SSP_REG(reg, off) \
69 static inline u32 read_##reg(void const __iomem *p) \
70 { return __raw_readl(p + (off)); } \
72 static inline void write_##reg(u32 v, void __iomem *p) \
73 { __raw_writel(v, p + (off)); }
75 DEFINE_SSP_REG(SSCR0, 0x00)
76 DEFINE_SSP_REG(SSCR1, 0x04)
77 DEFINE_SSP_REG(SSSR, 0x08)
78 DEFINE_SSP_REG(SSITR, 0x0c)
79 DEFINE_SSP_REG(SSDR, 0x10)
80 DEFINE_SSP_REG(SSTO, 0x28)
81 DEFINE_SSP_REG(SSPSP, 0x2c)
83 #define START_STATE ((void*)0)
84 #define RUNNING_STATE ((void*)1)
85 #define DONE_STATE ((void*)2)
86 #define ERROR_STATE ((void*)-1)
88 #define QUEUE_RUNNING 0
89 #define QUEUE_STOPPED 1
92 /* Driver model hookup */
93 struct platform_device *pdev;
96 struct ssp_device *ssp;
98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
103 struct pxa2xx_spi_master *master_info;
105 /* DMA setup stuff */
110 /* SSP register addresses */
111 void __iomem *ioaddr;
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
124 struct list_head queue;
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
147 int (*write)(struct driver_data *drv_data);
148 int (*read)(struct driver_data *drv_data);
149 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
150 void (*cs_control)(u32 command);
166 int (*write)(struct driver_data *drv_data);
167 int (*read)(struct driver_data *drv_data);
168 void (*cs_control)(u32 command);
171 static void pump_messages(struct work_struct *work);
173 static int flush(struct driver_data *drv_data)
175 unsigned long limit = loops_per_jiffy << 1;
177 void __iomem *reg = drv_data->ioaddr;
180 while (read_SSSR(reg) & SSSR_RNE) {
183 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
184 write_SSSR(SSSR_ROR, reg);
189 static void null_cs_control(u32 command)
193 static int null_writer(struct driver_data *drv_data)
195 void __iomem *reg = drv_data->ioaddr;
196 u8 n_bytes = drv_data->n_bytes;
198 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
199 || (drv_data->tx == drv_data->tx_end))
203 drv_data->tx += n_bytes;
208 static int null_reader(struct driver_data *drv_data)
210 void __iomem *reg = drv_data->ioaddr;
211 u8 n_bytes = drv_data->n_bytes;
213 while ((read_SSSR(reg) & SSSR_RNE)
214 && (drv_data->rx < drv_data->rx_end)) {
216 drv_data->rx += n_bytes;
219 return drv_data->rx == drv_data->rx_end;
222 static int u8_writer(struct driver_data *drv_data)
224 void __iomem *reg = drv_data->ioaddr;
226 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
227 || (drv_data->tx == drv_data->tx_end))
230 write_SSDR(*(u8 *)(drv_data->tx), reg);
236 static int u8_reader(struct driver_data *drv_data)
238 void __iomem *reg = drv_data->ioaddr;
240 while ((read_SSSR(reg) & SSSR_RNE)
241 && (drv_data->rx < drv_data->rx_end)) {
242 *(u8 *)(drv_data->rx) = read_SSDR(reg);
246 return drv_data->rx == drv_data->rx_end;
249 static int u16_writer(struct driver_data *drv_data)
251 void __iomem *reg = drv_data->ioaddr;
253 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
254 || (drv_data->tx == drv_data->tx_end))
257 write_SSDR(*(u16 *)(drv_data->tx), reg);
263 static int u16_reader(struct driver_data *drv_data)
265 void __iomem *reg = drv_data->ioaddr;
267 while ((read_SSSR(reg) & SSSR_RNE)
268 && (drv_data->rx < drv_data->rx_end)) {
269 *(u16 *)(drv_data->rx) = read_SSDR(reg);
273 return drv_data->rx == drv_data->rx_end;
276 static int u32_writer(struct driver_data *drv_data)
278 void __iomem *reg = drv_data->ioaddr;
280 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
281 || (drv_data->tx == drv_data->tx_end))
284 write_SSDR(*(u32 *)(drv_data->tx), reg);
290 static int u32_reader(struct driver_data *drv_data)
292 void __iomem *reg = drv_data->ioaddr;
294 while ((read_SSSR(reg) & SSSR_RNE)
295 && (drv_data->rx < drv_data->rx_end)) {
296 *(u32 *)(drv_data->rx) = read_SSDR(reg);
300 return drv_data->rx == drv_data->rx_end;
303 static void *next_transfer(struct driver_data *drv_data)
305 struct spi_message *msg = drv_data->cur_msg;
306 struct spi_transfer *trans = drv_data->cur_transfer;
308 /* Move to next transfer */
309 if (trans->transfer_list.next != &msg->transfers) {
310 drv_data->cur_transfer =
311 list_entry(trans->transfer_list.next,
314 return RUNNING_STATE;
319 static int map_dma_buffers(struct driver_data *drv_data)
321 struct spi_message *msg = drv_data->cur_msg;
322 struct device *dev = &msg->spi->dev;
324 if (!drv_data->cur_chip->enable_dma)
327 if (msg->is_dma_mapped)
328 return drv_data->rx_dma && drv_data->tx_dma;
330 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
333 /* Modify setup if rx buffer is null */
334 if (drv_data->rx == NULL) {
335 *drv_data->null_dma_buf = 0;
336 drv_data->rx = drv_data->null_dma_buf;
337 drv_data->rx_map_len = 4;
339 drv_data->rx_map_len = drv_data->len;
342 /* Modify setup if tx buffer is null */
343 if (drv_data->tx == NULL) {
344 *drv_data->null_dma_buf = 0;
345 drv_data->tx = drv_data->null_dma_buf;
346 drv_data->tx_map_len = 4;
348 drv_data->tx_map_len = drv_data->len;
350 /* Stream map the rx buffer */
351 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
352 drv_data->rx_map_len,
354 if (dma_mapping_error(dev, drv_data->rx_dma))
357 /* Stream map the tx buffer */
358 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
359 drv_data->tx_map_len,
362 if (dma_mapping_error(dev, drv_data->tx_dma)) {
363 dma_unmap_single(dev, drv_data->rx_dma,
364 drv_data->rx_map_len, DMA_FROM_DEVICE);
371 static void unmap_dma_buffers(struct driver_data *drv_data)
375 if (!drv_data->dma_mapped)
378 if (!drv_data->cur_msg->is_dma_mapped) {
379 dev = &drv_data->cur_msg->spi->dev;
380 dma_unmap_single(dev, drv_data->rx_dma,
381 drv_data->rx_map_len, DMA_FROM_DEVICE);
382 dma_unmap_single(dev, drv_data->tx_dma,
383 drv_data->tx_map_len, DMA_TO_DEVICE);
386 drv_data->dma_mapped = 0;
389 /* caller already set message->status; dma and pio irqs are blocked */
390 static void giveback(struct driver_data *drv_data)
392 struct spi_transfer* last_transfer;
394 struct spi_message *msg;
396 spin_lock_irqsave(&drv_data->lock, flags);
397 msg = drv_data->cur_msg;
398 drv_data->cur_msg = NULL;
399 drv_data->cur_transfer = NULL;
400 drv_data->cur_chip = NULL;
401 queue_work(drv_data->workqueue, &drv_data->pump_messages);
402 spin_unlock_irqrestore(&drv_data->lock, flags);
404 last_transfer = list_entry(msg->transfers.prev,
408 /* Delay if requested before any change in chip select */
409 if (last_transfer->delay_usecs)
410 udelay(last_transfer->delay_usecs);
412 /* Drop chip select UNLESS cs_change is true or we are returning
413 * a message with an error, or next message is for another chip
415 if (!last_transfer->cs_change)
416 drv_data->cs_control(PXA2XX_CS_DEASSERT);
418 struct spi_message *next_msg;
420 /* Holding of cs was hinted, but we need to make sure
421 * the next message is for the same chip. Don't waste
422 * time with the following tests unless this was hinted.
424 * We cannot postpone this until pump_messages, because
425 * after calling msg->complete (below) the driver that
426 * sent the current message could be unloaded, which
427 * could invalidate the cs_control() callback...
430 /* get a pointer to the next message, if any */
431 spin_lock_irqsave(&drv_data->lock, flags);
432 if (list_empty(&drv_data->queue))
435 next_msg = list_entry(drv_data->queue.next,
436 struct spi_message, queue);
437 spin_unlock_irqrestore(&drv_data->lock, flags);
439 /* see if the next and current messages point
442 if (next_msg && next_msg->spi != msg->spi)
444 if (!next_msg || msg->state == ERROR_STATE)
445 drv_data->cs_control(PXA2XX_CS_DEASSERT);
450 msg->complete(msg->context);
453 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
455 unsigned long limit = loops_per_jiffy << 1;
457 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
463 static int wait_dma_channel_stop(int channel)
465 unsigned long limit = loops_per_jiffy << 1;
467 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
473 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
475 void __iomem *reg = drv_data->ioaddr;
478 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
479 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
480 write_SSSR(drv_data->clear_sr, reg);
481 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
482 if (drv_data->ssp_type != PXA25x_SSP)
485 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
487 unmap_dma_buffers(drv_data);
489 dev_err(&drv_data->pdev->dev, "%s\n", msg);
491 drv_data->cur_msg->state = ERROR_STATE;
492 tasklet_schedule(&drv_data->pump_transfers);
495 static void dma_transfer_complete(struct driver_data *drv_data)
497 void __iomem *reg = drv_data->ioaddr;
498 struct spi_message *msg = drv_data->cur_msg;
500 /* Clear and disable interrupts on SSP and DMA channels*/
501 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
502 write_SSSR(drv_data->clear_sr, reg);
503 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
504 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
506 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
507 dev_err(&drv_data->pdev->dev,
508 "dma_handler: dma rx channel stop failed\n");
510 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
511 dev_err(&drv_data->pdev->dev,
512 "dma_transfer: ssp rx stall failed\n");
514 unmap_dma_buffers(drv_data);
516 /* update the buffer pointer for the amount completed in dma */
517 drv_data->rx += drv_data->len -
518 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
520 /* read trailing data from fifo, it does not matter how many
521 * bytes are in the fifo just read until buffer is full
522 * or fifo is empty, which ever occurs first */
523 drv_data->read(drv_data);
525 /* return count of what was actually read */
526 msg->actual_length += drv_data->len -
527 (drv_data->rx_end - drv_data->rx);
529 /* Transfer delays and chip select release are
530 * handled in pump_transfers or giveback
533 /* Move to next transfer */
534 msg->state = next_transfer(drv_data);
536 /* Schedule transfer tasklet */
537 tasklet_schedule(&drv_data->pump_transfers);
540 static void dma_handler(int channel, void *data)
542 struct driver_data *drv_data = data;
543 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
545 if (irq_status & DCSR_BUSERR) {
547 if (channel == drv_data->tx_channel)
548 dma_error_stop(drv_data,
550 "bad bus address on tx channel");
552 dma_error_stop(drv_data,
554 "bad bus address on rx channel");
558 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
559 if ((channel == drv_data->tx_channel)
560 && (irq_status & DCSR_ENDINTR)
561 && (drv_data->ssp_type == PXA25x_SSP)) {
563 /* Wait for rx to stall */
564 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
565 dev_err(&drv_data->pdev->dev,
566 "dma_handler: ssp rx stall failed\n");
568 /* finish this transfer, start the next */
569 dma_transfer_complete(drv_data);
573 static irqreturn_t dma_transfer(struct driver_data *drv_data)
576 void __iomem *reg = drv_data->ioaddr;
578 irq_status = read_SSSR(reg) & drv_data->mask_sr;
579 if (irq_status & SSSR_ROR) {
580 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
584 /* Check for false positive timeout */
585 if ((irq_status & SSSR_TINT)
586 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
587 write_SSSR(SSSR_TINT, reg);
591 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
593 /* Clear and disable timeout interrupt, do the rest in
594 * dma_transfer_complete */
595 if (drv_data->ssp_type != PXA25x_SSP)
598 /* finish this transfer, start the next */
599 dma_transfer_complete(drv_data);
604 /* Opps problem detected */
608 static void int_error_stop(struct driver_data *drv_data, const char* msg)
610 void __iomem *reg = drv_data->ioaddr;
612 /* Stop and reset SSP */
613 write_SSSR(drv_data->clear_sr, reg);
614 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
615 if (drv_data->ssp_type != PXA25x_SSP)
618 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
620 dev_err(&drv_data->pdev->dev, "%s\n", msg);
622 drv_data->cur_msg->state = ERROR_STATE;
623 tasklet_schedule(&drv_data->pump_transfers);
626 static void int_transfer_complete(struct driver_data *drv_data)
628 void __iomem *reg = drv_data->ioaddr;
631 write_SSSR(drv_data->clear_sr, reg);
632 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
633 if (drv_data->ssp_type != PXA25x_SSP)
636 /* Update total byte transfered return count actual bytes read */
637 drv_data->cur_msg->actual_length += drv_data->len -
638 (drv_data->rx_end - drv_data->rx);
640 /* Transfer delays and chip select release are
641 * handled in pump_transfers or giveback
644 /* Move to next transfer */
645 drv_data->cur_msg->state = next_transfer(drv_data);
647 /* Schedule transfer tasklet */
648 tasklet_schedule(&drv_data->pump_transfers);
651 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
653 void __iomem *reg = drv_data->ioaddr;
655 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
656 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
658 u32 irq_status = read_SSSR(reg) & irq_mask;
660 if (irq_status & SSSR_ROR) {
661 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
665 if (irq_status & SSSR_TINT) {
666 write_SSSR(SSSR_TINT, reg);
667 if (drv_data->read(drv_data)) {
668 int_transfer_complete(drv_data);
673 /* Drain rx fifo, Fill tx fifo and prevent overruns */
675 if (drv_data->read(drv_data)) {
676 int_transfer_complete(drv_data);
679 } while (drv_data->write(drv_data));
681 if (drv_data->read(drv_data)) {
682 int_transfer_complete(drv_data);
686 if (drv_data->tx == drv_data->tx_end) {
687 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
688 /* PXA25x_SSP has no timeout, read trailing bytes */
689 if (drv_data->ssp_type == PXA25x_SSP) {
690 if (!wait_ssp_rx_stall(reg))
692 int_error_stop(drv_data, "interrupt_transfer: "
696 if (!drv_data->read(drv_data))
698 int_error_stop(drv_data,
699 "interrupt_transfer: "
700 "trailing byte read failed");
703 int_transfer_complete(drv_data);
707 /* We did something */
711 static irqreturn_t ssp_int(int irq, void *dev_id)
713 struct driver_data *drv_data = dev_id;
714 void __iomem *reg = drv_data->ioaddr;
716 if (!drv_data->cur_msg) {
718 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
719 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
720 if (drv_data->ssp_type != PXA25x_SSP)
722 write_SSSR(drv_data->clear_sr, reg);
724 dev_err(&drv_data->pdev->dev, "bad message state "
725 "in interrupt handler\n");
731 return drv_data->transfer_handler(drv_data);
734 static int set_dma_burst_and_threshold(struct chip_data *chip,
735 struct spi_device *spi,
736 u8 bits_per_word, u32 *burst_code,
739 struct pxa2xx_spi_chip *chip_info =
740 (struct pxa2xx_spi_chip *)spi->controller_data;
747 /* Set the threshold (in registers) to equal the same amount of data
748 * as represented by burst size (in bytes). The computation below
749 * is (burst_size rounded up to nearest 8 byte, word or long word)
750 * divided by (bytes/register); the tx threshold is the inverse of
751 * the rx, so that there will always be enough data in the rx fifo
752 * to satisfy a burst, and there will always be enough space in the
753 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
754 * there is not enough space), there must always remain enough empty
755 * space in the rx fifo for any data loaded to the tx fifo.
756 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
757 * will be 8, or half the fifo;
758 * The threshold can only be set to 2, 4 or 8, but not 16, because
759 * to burst 16 to the tx fifo, the fifo would have to be empty;
760 * however, the minimum fifo trigger level is 1, and the tx will
761 * request service when the fifo is at this level, with only 15 spaces.
764 /* find bytes/word */
765 if (bits_per_word <= 8)
767 else if (bits_per_word <= 16)
772 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
774 req_burst_size = chip_info->dma_burst_size;
776 switch (chip->dma_burst_size) {
778 /* if the default burst size is not set,
780 chip->dma_burst_size = DCMD_BURST8;
792 if (req_burst_size <= 8) {
793 *burst_code = DCMD_BURST8;
795 } else if (req_burst_size <= 16) {
796 if (bytes_per_word == 1) {
797 /* don't burst more than 1/2 the fifo */
798 *burst_code = DCMD_BURST8;
802 *burst_code = DCMD_BURST16;
806 if (bytes_per_word == 1) {
807 /* don't burst more than 1/2 the fifo */
808 *burst_code = DCMD_BURST8;
811 } else if (bytes_per_word == 2) {
812 /* don't burst more than 1/2 the fifo */
813 *burst_code = DCMD_BURST16;
817 *burst_code = DCMD_BURST32;
822 thresh_words = burst_bytes / bytes_per_word;
824 /* thresh_words will be between 2 and 8 */
825 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
826 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
831 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
833 unsigned long ssp_clk = clk_get_rate(ssp->clk);
835 if (ssp->type == PXA25x_SSP)
836 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
838 return ((ssp_clk / rate - 1) & 0xfff) << 8;
841 static void pump_transfers(unsigned long data)
843 struct driver_data *drv_data = (struct driver_data *)data;
844 struct spi_message *message = NULL;
845 struct spi_transfer *transfer = NULL;
846 struct spi_transfer *previous = NULL;
847 struct chip_data *chip = NULL;
848 struct ssp_device *ssp = drv_data->ssp;
849 void __iomem *reg = drv_data->ioaddr;
855 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
856 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
858 /* Get current state information */
859 message = drv_data->cur_msg;
860 transfer = drv_data->cur_transfer;
861 chip = drv_data->cur_chip;
863 /* Handle for abort */
864 if (message->state == ERROR_STATE) {
865 message->status = -EIO;
870 /* Handle end of message */
871 if (message->state == DONE_STATE) {
877 /* Delay if requested at end of transfer before CS change */
878 if (message->state == RUNNING_STATE) {
879 previous = list_entry(transfer->transfer_list.prev,
882 if (previous->delay_usecs)
883 udelay(previous->delay_usecs);
885 /* Drop chip select only if cs_change is requested */
886 if (previous->cs_change)
887 drv_data->cs_control(PXA2XX_CS_DEASSERT);
890 /* Check transfer length */
891 if (transfer->len > 8191)
893 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
894 "length greater than 8191\n");
895 message->status = -EINVAL;
900 /* Setup the transfer state based on the type of transfer */
901 if (flush(drv_data) == 0) {
902 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
903 message->status = -EIO;
907 drv_data->n_bytes = chip->n_bytes;
908 drv_data->dma_width = chip->dma_width;
909 drv_data->cs_control = chip->cs_control;
910 drv_data->tx = (void *)transfer->tx_buf;
911 drv_data->tx_end = drv_data->tx + transfer->len;
912 drv_data->rx = transfer->rx_buf;
913 drv_data->rx_end = drv_data->rx + transfer->len;
914 drv_data->rx_dma = transfer->rx_dma;
915 drv_data->tx_dma = transfer->tx_dma;
916 drv_data->len = transfer->len & DCMD_LENGTH;
917 drv_data->write = drv_data->tx ? chip->write : null_writer;
918 drv_data->read = drv_data->rx ? chip->read : null_reader;
920 /* Change speed and bit per word on a per transfer */
922 if (transfer->speed_hz || transfer->bits_per_word) {
924 bits = chip->bits_per_word;
925 speed = chip->speed_hz;
927 if (transfer->speed_hz)
928 speed = transfer->speed_hz;
930 if (transfer->bits_per_word)
931 bits = transfer->bits_per_word;
933 clk_div = ssp_get_clk_div(ssp, speed);
936 drv_data->n_bytes = 1;
937 drv_data->dma_width = DCMD_WIDTH1;
938 drv_data->read = drv_data->read != null_reader ?
939 u8_reader : null_reader;
940 drv_data->write = drv_data->write != null_writer ?
941 u8_writer : null_writer;
942 } else if (bits <= 16) {
943 drv_data->n_bytes = 2;
944 drv_data->dma_width = DCMD_WIDTH2;
945 drv_data->read = drv_data->read != null_reader ?
946 u16_reader : null_reader;
947 drv_data->write = drv_data->write != null_writer ?
948 u16_writer : null_writer;
949 } else if (bits <= 32) {
950 drv_data->n_bytes = 4;
951 drv_data->dma_width = DCMD_WIDTH4;
952 drv_data->read = drv_data->read != null_reader ?
953 u32_reader : null_reader;
954 drv_data->write = drv_data->write != null_writer ?
955 u32_writer : null_writer;
957 /* if bits/word is changed in dma mode, then must check the
958 * thresholds and burst also */
959 if (chip->enable_dma) {
960 if (set_dma_burst_and_threshold(chip, message->spi,
963 if (printk_ratelimit())
964 dev_warn(&message->spi->dev,
966 "DMA burst size reduced to "
967 "match bits_per_word\n");
972 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
974 | (bits > 16 ? SSCR0_EDSS : 0);
977 message->state = RUNNING_STATE;
979 /* Try to map dma buffer and do a dma transfer if successful */
980 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
982 /* Ensure we have the correct interrupt handler */
983 drv_data->transfer_handler = dma_transfer;
985 /* Setup rx DMA Channel */
986 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
987 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
988 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
989 if (drv_data->rx == drv_data->null_dma_buf)
990 /* No target address increment */
991 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
992 | drv_data->dma_width
996 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
998 | drv_data->dma_width
1002 /* Setup tx DMA Channel */
1003 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1004 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1005 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1006 if (drv_data->tx == drv_data->null_dma_buf)
1007 /* No source address increment */
1008 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1009 | drv_data->dma_width
1013 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1015 | drv_data->dma_width
1019 /* Enable dma end irqs on SSP to detect end of transfer */
1020 if (drv_data->ssp_type == PXA25x_SSP)
1021 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1023 /* Clear status and start DMA engine */
1024 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1025 write_SSSR(drv_data->clear_sr, reg);
1026 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1027 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1029 /* Ensure we have the correct interrupt handler */
1030 drv_data->transfer_handler = interrupt_transfer;
1033 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1034 write_SSSR(drv_data->clear_sr, reg);
1037 /* see if we need to reload the config registers */
1038 if ((read_SSCR0(reg) != cr0)
1039 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1040 (cr1 & SSCR1_CHANGE_MASK)) {
1042 /* stop the SSP, and update the other bits */
1043 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1044 if (drv_data->ssp_type != PXA25x_SSP)
1045 write_SSTO(chip->timeout, reg);
1046 /* first set CR1 without interrupt and service enables */
1047 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1048 /* restart the SSP */
1049 write_SSCR0(cr0, reg);
1052 if (drv_data->ssp_type != PXA25x_SSP)
1053 write_SSTO(chip->timeout, reg);
1056 /* FIXME, need to handle cs polarity,
1057 * this driver uses struct pxa2xx_spi_chip.cs_control to
1058 * specify a CS handling function, and it ignores most
1059 * struct spi_device.mode[s], including SPI_CS_HIGH */
1060 drv_data->cs_control(PXA2XX_CS_ASSERT);
1062 /* after chip select, release the data by enabling service
1063 * requests and interrupts, without changing any mode bits */
1064 write_SSCR1(cr1, reg);
1067 static void pump_messages(struct work_struct *work)
1069 struct driver_data *drv_data =
1070 container_of(work, struct driver_data, pump_messages);
1071 unsigned long flags;
1073 /* Lock queue and check for queue work */
1074 spin_lock_irqsave(&drv_data->lock, flags);
1075 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1077 spin_unlock_irqrestore(&drv_data->lock, flags);
1081 /* Make sure we are not already running a message */
1082 if (drv_data->cur_msg) {
1083 spin_unlock_irqrestore(&drv_data->lock, flags);
1087 /* Extract head of queue */
1088 drv_data->cur_msg = list_entry(drv_data->queue.next,
1089 struct spi_message, queue);
1090 list_del_init(&drv_data->cur_msg->queue);
1092 /* Initial message state*/
1093 drv_data->cur_msg->state = START_STATE;
1094 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1095 struct spi_transfer,
1098 /* prepare to setup the SSP, in pump_transfers, using the per
1099 * chip configuration */
1100 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1102 /* Mark as busy and launch transfers */
1103 tasklet_schedule(&drv_data->pump_transfers);
1106 spin_unlock_irqrestore(&drv_data->lock, flags);
1109 static int transfer(struct spi_device *spi, struct spi_message *msg)
1111 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1112 unsigned long flags;
1114 spin_lock_irqsave(&drv_data->lock, flags);
1116 if (drv_data->run == QUEUE_STOPPED) {
1117 spin_unlock_irqrestore(&drv_data->lock, flags);
1121 msg->actual_length = 0;
1122 msg->status = -EINPROGRESS;
1123 msg->state = START_STATE;
1125 list_add_tail(&msg->queue, &drv_data->queue);
1127 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1128 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1130 spin_unlock_irqrestore(&drv_data->lock, flags);
1135 /* the spi->mode bits understood by this driver: */
1136 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1138 static int setup(struct spi_device *spi)
1140 struct pxa2xx_spi_chip *chip_info = NULL;
1141 struct chip_data *chip;
1142 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1143 struct ssp_device *ssp = drv_data->ssp;
1144 unsigned int clk_div;
1146 if (!spi->bits_per_word)
1147 spi->bits_per_word = 8;
1149 if (drv_data->ssp_type != PXA25x_SSP
1150 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1151 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1152 "b/w not 4-32 for type non-PXA25x_SSP\n",
1153 drv_data->ssp_type, spi->bits_per_word);
1156 else if (drv_data->ssp_type == PXA25x_SSP
1157 && (spi->bits_per_word < 4
1158 || spi->bits_per_word > 16)) {
1159 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1160 "b/w not 4-16 for type PXA25x_SSP\n",
1161 drv_data->ssp_type, spi->bits_per_word);
1165 if (spi->mode & ~MODEBITS) {
1166 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1167 spi->mode & ~MODEBITS);
1171 /* Only alloc on first setup */
1172 chip = spi_get_ctldata(spi);
1174 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1177 "failed setup: can't allocate chip data\n");
1181 chip->cs_control = null_cs_control;
1182 chip->enable_dma = 0;
1183 chip->timeout = 1000;
1184 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1185 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1189 /* protocol drivers may change the chip settings, so...
1190 * if chip_info exists, use it */
1191 chip_info = spi->controller_data;
1193 /* chip_info isn't always needed */
1196 if (chip_info->cs_control)
1197 chip->cs_control = chip_info->cs_control;
1199 chip->timeout = chip_info->timeout;
1201 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1203 (SSCR1_TxTresh(chip_info->tx_threshold) &
1206 chip->enable_dma = chip_info->dma_burst_size != 0
1207 && drv_data->master_info->enable_dma;
1208 chip->dma_threshold = 0;
1210 if (chip_info->enable_loopback)
1211 chip->cr1 = SSCR1_LBM;
1214 /* set dma burst and threshold outside of chip_info path so that if
1215 * chip_info goes away after setting chip->enable_dma, the
1216 * burst and threshold can still respond to changes in bits_per_word */
1217 if (chip->enable_dma) {
1218 /* set up legal burst and threshold for dma */
1219 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1220 &chip->dma_burst_size,
1221 &chip->dma_threshold)) {
1222 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1223 "to match bits_per_word\n");
1227 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1228 chip->speed_hz = spi->max_speed_hz;
1232 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1233 spi->bits_per_word - 16 : spi->bits_per_word)
1235 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1236 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1237 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1238 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1240 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1241 if (drv_data->ssp_type != PXA25x_SSP)
1242 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1244 clk_get_rate(ssp->clk)
1245 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1248 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1250 clk_get_rate(ssp->clk)
1251 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1254 if (spi->bits_per_word <= 8) {
1256 chip->dma_width = DCMD_WIDTH1;
1257 chip->read = u8_reader;
1258 chip->write = u8_writer;
1259 } else if (spi->bits_per_word <= 16) {
1261 chip->dma_width = DCMD_WIDTH2;
1262 chip->read = u16_reader;
1263 chip->write = u16_writer;
1264 } else if (spi->bits_per_word <= 32) {
1265 chip->cr0 |= SSCR0_EDSS;
1267 chip->dma_width = DCMD_WIDTH4;
1268 chip->read = u32_reader;
1269 chip->write = u32_writer;
1271 dev_err(&spi->dev, "invalid wordsize\n");
1274 chip->bits_per_word = spi->bits_per_word;
1276 spi_set_ctldata(spi, chip);
1281 static void cleanup(struct spi_device *spi)
1283 struct chip_data *chip = spi_get_ctldata(spi);
1288 static int __init init_queue(struct driver_data *drv_data)
1290 INIT_LIST_HEAD(&drv_data->queue);
1291 spin_lock_init(&drv_data->lock);
1293 drv_data->run = QUEUE_STOPPED;
1296 tasklet_init(&drv_data->pump_transfers,
1297 pump_transfers, (unsigned long)drv_data);
1299 INIT_WORK(&drv_data->pump_messages, pump_messages);
1300 drv_data->workqueue = create_singlethread_workqueue(
1301 drv_data->master->dev.parent->bus_id);
1302 if (drv_data->workqueue == NULL)
1308 static int start_queue(struct driver_data *drv_data)
1310 unsigned long flags;
1312 spin_lock_irqsave(&drv_data->lock, flags);
1314 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1315 spin_unlock_irqrestore(&drv_data->lock, flags);
1319 drv_data->run = QUEUE_RUNNING;
1320 drv_data->cur_msg = NULL;
1321 drv_data->cur_transfer = NULL;
1322 drv_data->cur_chip = NULL;
1323 spin_unlock_irqrestore(&drv_data->lock, flags);
1325 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1330 static int stop_queue(struct driver_data *drv_data)
1332 unsigned long flags;
1333 unsigned limit = 500;
1336 spin_lock_irqsave(&drv_data->lock, flags);
1338 /* This is a bit lame, but is optimized for the common execution path.
1339 * A wait_queue on the drv_data->busy could be used, but then the common
1340 * execution path (pump_messages) would be required to call wake_up or
1341 * friends on every SPI message. Do this instead */
1342 drv_data->run = QUEUE_STOPPED;
1343 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1344 spin_unlock_irqrestore(&drv_data->lock, flags);
1346 spin_lock_irqsave(&drv_data->lock, flags);
1349 if (!list_empty(&drv_data->queue) || drv_data->busy)
1352 spin_unlock_irqrestore(&drv_data->lock, flags);
1357 static int destroy_queue(struct driver_data *drv_data)
1361 status = stop_queue(drv_data);
1362 /* we are unloading the module or failing to load (only two calls
1363 * to this routine), and neither call can handle a return value.
1364 * However, destroy_workqueue calls flush_workqueue, and that will
1365 * block until all work is done. If the reason that stop_queue
1366 * timed out is that the work will never finish, then it does no
1367 * good to call destroy_workqueue, so return anyway. */
1371 destroy_workqueue(drv_data->workqueue);
1376 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1378 struct device *dev = &pdev->dev;
1379 struct pxa2xx_spi_master *platform_info;
1380 struct spi_master *master;
1381 struct driver_data *drv_data = NULL;
1382 struct ssp_device *ssp;
1385 platform_info = dev->platform_data;
1387 ssp = ssp_request(pdev->id, pdev->name);
1389 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1393 /* Allocate master with space for drv_data and null dma buffer */
1394 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1396 dev_err(&pdev->dev, "can not alloc spi_master\n");
1400 drv_data = spi_master_get_devdata(master);
1401 drv_data->master = master;
1402 drv_data->master_info = platform_info;
1403 drv_data->pdev = pdev;
1404 drv_data->ssp = ssp;
1406 master->bus_num = pdev->id;
1407 master->num_chipselect = platform_info->num_chipselect;
1408 master->cleanup = cleanup;
1409 master->setup = setup;
1410 master->transfer = transfer;
1412 drv_data->ssp_type = ssp->type;
1413 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1414 sizeof(struct driver_data)), 8);
1416 drv_data->ioaddr = ssp->mmio_base;
1417 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1418 if (ssp->type == PXA25x_SSP) {
1419 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1420 drv_data->dma_cr1 = 0;
1421 drv_data->clear_sr = SSSR_ROR;
1422 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1424 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1425 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1426 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1427 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1430 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1432 dev_err(&pdev->dev, "can not get IRQ\n");
1433 goto out_error_master_alloc;
1436 /* Setup DMA if requested */
1437 drv_data->tx_channel = -1;
1438 drv_data->rx_channel = -1;
1439 if (platform_info->enable_dma) {
1441 /* Get two DMA channels (rx and tx) */
1442 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1446 if (drv_data->rx_channel < 0) {
1447 dev_err(dev, "problem (%d) requesting rx channel\n",
1448 drv_data->rx_channel);
1450 goto out_error_irq_alloc;
1452 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1456 if (drv_data->tx_channel < 0) {
1457 dev_err(dev, "problem (%d) requesting tx channel\n",
1458 drv_data->tx_channel);
1460 goto out_error_dma_alloc;
1463 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1464 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1467 /* Enable SOC clock */
1468 clk_enable(ssp->clk);
1470 /* Load default SSP configuration */
1471 write_SSCR0(0, drv_data->ioaddr);
1472 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1473 write_SSCR0(SSCR0_SerClkDiv(2)
1475 | SSCR0_DataSize(8),
1477 if (drv_data->ssp_type != PXA25x_SSP)
1478 write_SSTO(0, drv_data->ioaddr);
1479 write_SSPSP(0, drv_data->ioaddr);
1481 /* Initial and start queue */
1482 status = init_queue(drv_data);
1484 dev_err(&pdev->dev, "problem initializing queue\n");
1485 goto out_error_clock_enabled;
1487 status = start_queue(drv_data);
1489 dev_err(&pdev->dev, "problem starting queue\n");
1490 goto out_error_clock_enabled;
1493 /* Register with the SPI framework */
1494 platform_set_drvdata(pdev, drv_data);
1495 status = spi_register_master(master);
1497 dev_err(&pdev->dev, "problem registering spi master\n");
1498 goto out_error_queue_alloc;
1503 out_error_queue_alloc:
1504 destroy_queue(drv_data);
1506 out_error_clock_enabled:
1507 clk_disable(ssp->clk);
1509 out_error_dma_alloc:
1510 if (drv_data->tx_channel != -1)
1511 pxa_free_dma(drv_data->tx_channel);
1512 if (drv_data->rx_channel != -1)
1513 pxa_free_dma(drv_data->rx_channel);
1515 out_error_irq_alloc:
1516 free_irq(ssp->irq, drv_data);
1518 out_error_master_alloc:
1519 spi_master_put(master);
1524 static int pxa2xx_spi_remove(struct platform_device *pdev)
1526 struct driver_data *drv_data = platform_get_drvdata(pdev);
1527 struct ssp_device *ssp = drv_data->ssp;
1533 /* Remove the queue */
1534 status = destroy_queue(drv_data);
1536 /* the kernel does not check the return status of this
1537 * this routine (mod->exit, within the kernel). Therefore
1538 * nothing is gained by returning from here, the module is
1539 * going away regardless, and we should not leave any more
1540 * resources allocated than necessary. We cannot free the
1541 * message memory in drv_data->queue, but we can release the
1542 * resources below. I think the kernel should honor -EBUSY
1544 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1545 "complete, message memory not freed\n");
1547 /* Disable the SSP at the peripheral and SOC level */
1548 write_SSCR0(0, drv_data->ioaddr);
1549 clk_disable(ssp->clk);
1552 if (drv_data->master_info->enable_dma) {
1553 DRCMR(ssp->drcmr_rx) = 0;
1554 DRCMR(ssp->drcmr_tx) = 0;
1555 pxa_free_dma(drv_data->tx_channel);
1556 pxa_free_dma(drv_data->rx_channel);
1560 free_irq(ssp->irq, drv_data);
1565 /* Disconnect from the SPI framework */
1566 spi_unregister_master(drv_data->master);
1568 /* Prevent double remove */
1569 platform_set_drvdata(pdev, NULL);
1574 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1578 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1579 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1584 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1586 struct driver_data *drv_data = platform_get_drvdata(pdev);
1587 struct ssp_device *ssp = drv_data->ssp;
1590 status = stop_queue(drv_data);
1593 write_SSCR0(0, drv_data->ioaddr);
1594 clk_disable(ssp->clk);
1599 static int pxa2xx_spi_resume(struct platform_device *pdev)
1601 struct driver_data *drv_data = platform_get_drvdata(pdev);
1602 struct ssp_device *ssp = drv_data->ssp;
1605 /* Enable the SSP clock */
1606 clk_enable(ssp->clk);
1608 /* Start the queue running */
1609 status = start_queue(drv_data);
1611 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1618 #define pxa2xx_spi_suspend NULL
1619 #define pxa2xx_spi_resume NULL
1620 #endif /* CONFIG_PM */
1622 static struct platform_driver driver = {
1624 .name = "pxa2xx-spi",
1625 .owner = THIS_MODULE,
1627 .remove = pxa2xx_spi_remove,
1628 .shutdown = pxa2xx_spi_shutdown,
1629 .suspend = pxa2xx_spi_suspend,
1630 .resume = pxa2xx_spi_resume,
1633 static int __init pxa2xx_spi_init(void)
1635 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1637 module_init(pxa2xx_spi_init);
1639 static void __exit pxa2xx_spi_exit(void)
1641 platform_driver_unregister(&driver);
1643 module_exit(pxa2xx_spi_exit);