drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37
  38 #include <linux/spi/spi.h>
  39
  40 #include <plat/dma.h>
  41 #include <plat/clock.h>
  42 #include <plat/mcspi.h>
  43
  44 #define OMAP2_MCSPI_MAX_FREQ            48000000
  45
  46 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
  47 #define OMAP2_MCSPI_MAX_CTRL            4
  48
  49 #define OMAP2_MCSPI_REVISION            0x00
  50 #define OMAP2_MCSPI_SYSSTATUS           0x14
  51 #define OMAP2_MCSPI_IRQSTATUS           0x18
  52 #define OMAP2_MCSPI_IRQENABLE           0x1c
  53 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  54 #define OMAP2_MCSPI_SYST                0x24
  55 #define OMAP2_MCSPI_MODULCTRL           0x28
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65
  66 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  67 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  68 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  69
  70 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  71 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  73 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  74 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  77 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  78 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  79 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  80 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  81 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  82 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  83 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  84 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  85
  86 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  87 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  88 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  89
  90 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  91
  92 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  93
  94 /* We have 2 DMA channels per CS, one for RX and one for TX */
  95 struct omap2_mcspi_dma {
  96         int dma_tx_channel;
  97         int dma_rx_channel;
  98
  99         int dma_tx_sync_dev;
 100         int dma_rx_sync_dev;
 101
 102         struct completion dma_tx_completion;
 103         struct completion dma_rx_completion;
 104 };
 105
 106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 107  * cache operations; better heuristics consider wordsize and bitrate.
 108  */
 109 #define DMA_MIN_BYTES                   160
 110
 111
 112 struct omap2_mcspi {
 113         struct work_struct      work;
 114         /* lock protects queue and registers */
 115         spinlock_t              lock;
 116         struct list_head        msg_queue;
 117         struct spi_master       *master;
 118         /* Virtual base address of the controller */
 119         void __iomem            *base;
 120         unsigned long           phys;
 121         /* SPI1 has 4 channels, while SPI2 has 2 */
 122         struct omap2_mcspi_dma  *dma_channels;
 123         struct  device          *dev;
 124 };
 125
 126 struct omap2_mcspi_cs {
 127         void __iomem            *base;
 128         unsigned long           phys;
 129         int                     word_len;
 130         struct list_head        node;
 131         /* Context save and restore shadow register */
 132         u32                     chconf0;
 133 };
 134
 135 /* used for context save and restore, structure members to be updated whenever
 136  * corresponding registers are modified.
 137  */
 138 struct omap2_mcspi_regs {
 139         u32 modulctrl;
 140         u32 wakeupenable;
 141         struct list_head cs;
 142 };
 143
 144 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
 145
 146 static struct workqueue_struct *omap2_mcspi_wq;
 147
 148 #define MOD_REG_BIT(val, mask, set) do { \
 149         if (set) \
 150                 val |= mask; \
 151         else \
 152                 val &= ~mask; \
 153 } while (0)
 154
 155 static inline void mcspi_write_reg(struct spi_master *master,
 156                 int idx, u32 val)
 157 {
 158         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 159
 160         __raw_writel(val, mcspi->base + idx);
 161 }
 162
 163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 164 {
 165         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 166
 167         return __raw_readl(mcspi->base + idx);
 168 }
 169
 170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 171                 int idx, u32 val)
 172 {
 173         struct omap2_mcspi_cs   *cs = spi->controller_state;
 174
 175         __raw_writel(val, cs->base +  idx);
 176 }
 177
 178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 179 {
 180         struct omap2_mcspi_cs   *cs = spi->controller_state;
 181
 182         return __raw_readl(cs->base + idx);
 183 }
 184
 185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 186 {
 187         struct omap2_mcspi_cs *cs = spi->controller_state;
 188
 189         return cs->chconf0;
 190 }
 191
 192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 193 {
 194         struct omap2_mcspi_cs *cs = spi->controller_state;
 195
 196         cs->chconf0 = val;
 197         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 198         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 199 }
 200
 201 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 202                 int is_read, int enable)
 203 {
 204         u32 l, rw;
 205
 206         l = mcspi_cached_chconf0(spi);
 207
 208         if (is_read) /* 1 is read, 0 write */
 209                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 210         else
 211                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 212
 213         MOD_REG_BIT(l, rw, enable);
 214         mcspi_write_chconf0(spi, l);
 215 }
 216
 217 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 218 {
 219         u32 l;
 220
 221         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 222         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 223         /* Flash post-writes */
 224         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 225 }
 226
 227 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 228 {
 229         u32 l;
 230
 231         l = mcspi_cached_chconf0(spi);
 232         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 233         mcspi_write_chconf0(spi, l);
 234 }
 235
 236 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 237 {
 238         u32 l;
 239
 240         /* setup when switching from (reset default) slave mode
 241          * to single-channel master mode
 242          */
 243         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 244         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 245         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 246         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 247         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 248
 249         omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
 250 }
 251
 252 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 253 {
 254         struct spi_master *spi_cntrl;
 255         struct omap2_mcspi_cs *cs;
 256         spi_cntrl = mcspi->master;
 257
 258         /* McSPI: context restore */
 259         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
 260                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
 261
 262         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
 263                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
 264
 265         list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
 266                         node)
 267                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 268 }
 269 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 270 {
 271         pm_runtime_put_sync(mcspi->dev);
 272 }
 273
 274 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 275 {
 276         return pm_runtime_get_sync(mcspi->dev);
 277 }
 278
 279 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 280 {
 281         unsigned long timeout;
 282
 283         timeout = jiffies + msecs_to_jiffies(1000);
 284         while (!(__raw_readl(reg) & bit)) {
 285                 if (time_after(jiffies, timeout))
 286                         return -1;
 287                 cpu_relax();
 288         }
 289         return 0;
 290 }
 291
 292 static unsigned
 293 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 294 {
 295         struct omap2_mcspi      *mcspi;
 296         struct omap2_mcspi_cs   *cs = spi->controller_state;
 297         struct omap2_mcspi_dma  *mcspi_dma;
 298         unsigned int            count, c;
 299         unsigned long           base, tx_reg, rx_reg;
 300         int                     word_len, data_type, element_count;
 301         int                     elements;
 302         u32                     l;
 303         u8                      * rx;
 304         const u8                * tx;
 305         void __iomem            *chstat_reg;
 306
 307         mcspi = spi_master_get_devdata(spi->master);
 308         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 309         l = mcspi_cached_chconf0(spi);
 310
 311         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 312
 313         count = xfer->len;
 314         c = count;
 315         word_len = cs->word_len;
 316
 317         base = cs->phys;
 318         tx_reg = base + OMAP2_MCSPI_TX0;
 319         rx_reg = base + OMAP2_MCSPI_RX0;
 320         rx = xfer->rx_buf;
 321         tx = xfer->tx_buf;
 322
 323         if (word_len <= 8) {
 324                 data_type = OMAP_DMA_DATA_TYPE_S8;
 325                 element_count = count;
 326         } else if (word_len <= 16) {
 327                 data_type = OMAP_DMA_DATA_TYPE_S16;
 328                 element_count = count >> 1;
 329         } else /* word_len <= 32 */ {
 330                 data_type = OMAP_DMA_DATA_TYPE_S32;
 331                 element_count = count >> 2;
 332         }
 333
 334         if (tx != NULL) {
 335                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 336                                 data_type, element_count, 1,
 337                                 OMAP_DMA_SYNC_ELEMENT,
 338                                 mcspi_dma->dma_tx_sync_dev, 0);
 339
 340                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 341                                 OMAP_DMA_AMODE_CONSTANT,
 342                                 tx_reg, 0, 0);
 343
 344                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 345                                 OMAP_DMA_AMODE_POST_INC,
 346                                 xfer->tx_dma, 0, 0);
 347         }
 348
 349         if (rx != NULL) {
 350                 elements = element_count - 1;
 351                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
 352                         elements--;
 353
 354                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 355                                 data_type, elements, 1,
 356                                 OMAP_DMA_SYNC_ELEMENT,
 357                                 mcspi_dma->dma_rx_sync_dev, 1);
 358
 359                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 360                                 OMAP_DMA_AMODE_CONSTANT,
 361                                 rx_reg, 0, 0);
 362
 363                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 364                                 OMAP_DMA_AMODE_POST_INC,
 365                                 xfer->rx_dma, 0, 0);
 366         }
 367
 368         if (tx != NULL) {
 369                 omap_start_dma(mcspi_dma->dma_tx_channel);
 370                 omap2_mcspi_set_dma_req(spi, 0, 1);
 371         }
 372
 373         if (rx != NULL) {
 374                 omap_start_dma(mcspi_dma->dma_rx_channel);
 375                 omap2_mcspi_set_dma_req(spi, 1, 1);
 376         }
 377
 378         if (tx != NULL) {
 379                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 380                 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
 381
 382                 /* for TX_ONLY mode, be sure all words have shifted out */
 383                 if (rx == NULL) {
 384                         if (mcspi_wait_for_reg_bit(chstat_reg,
 385                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0)
 386                                 dev_err(&spi->dev, "TXS timed out\n");
 387                         else if (mcspi_wait_for_reg_bit(chstat_reg,
 388                                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 389                                 dev_err(&spi->dev, "EOT timed out\n");
 390                 }
 391         }
 392
 393         if (rx != NULL) {
 394                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 395                 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
 396                 omap2_mcspi_set_enable(spi, 0);
 397
 398                 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 399
 400                         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 401                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 402                                 u32 w;
 403
 404                                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 405                                 if (word_len <= 8)
 406                                         ((u8 *)xfer->rx_buf)[elements++] = w;
 407                                 else if (word_len <= 16)
 408                                         ((u16 *)xfer->rx_buf)[elements++] = w;
 409                                 else /* word_len <= 32 */
 410                                         ((u32 *)xfer->rx_buf)[elements++] = w;
 411                         } else {
 412                                 dev_err(&spi->dev,
 413                                         "DMA RX penultimate word empty");
 414                                 count -= (word_len <= 8)  ? 2 :
 415                                         (word_len <= 16) ? 4 :
 416                                         /* word_len <= 32 */ 8;
 417                                 omap2_mcspi_set_enable(spi, 1);
 418                                 return count;
 419                         }
 420                 }
 421
 422                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 423                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 424                         u32 w;
 425
 426                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 427                         if (word_len <= 8)
 428                                 ((u8 *)xfer->rx_buf)[elements] = w;
 429                         else if (word_len <= 16)
 430                                 ((u16 *)xfer->rx_buf)[elements] = w;
 431                         else /* word_len <= 32 */
 432                                 ((u32 *)xfer->rx_buf)[elements] = w;
 433                 } else {
 434                         dev_err(&spi->dev, "DMA RX last word empty");
 435                         count -= (word_len <= 8)  ? 1 :
 436                                  (word_len <= 16) ? 2 :
 437                                /* word_len <= 32 */ 4;
 438                 }
 439                 omap2_mcspi_set_enable(spi, 1);
 440         }
 441         return count;
 442 }
 443
 444 static unsigned
 445 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 446 {
 447         struct omap2_mcspi      *mcspi;
 448         struct omap2_mcspi_cs   *cs = spi->controller_state;
 449         unsigned int            count, c;
 450         u32                     l;
 451         void __iomem            *base = cs->base;
 452         void __iomem            *tx_reg;
 453         void __iomem            *rx_reg;
 454         void __iomem            *chstat_reg;
 455         int                     word_len;
 456
 457         mcspi = spi_master_get_devdata(spi->master);
 458         count = xfer->len;
 459         c = count;
 460         word_len = cs->word_len;
 461
 462         l = mcspi_cached_chconf0(spi);
 463
 464         /* We store the pre-calculated register addresses on stack to speed
 465          * up the transfer loop. */
 466         tx_reg          = base + OMAP2_MCSPI_TX0;
 467         rx_reg          = base + OMAP2_MCSPI_RX0;
 468         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 469
 470         if (word_len <= 8) {
 471                 u8              *rx;
 472                 const u8        *tx;
 473
 474                 rx = xfer->rx_buf;
 475                 tx = xfer->tx_buf;
 476
 477                 do {
 478                         c -= 1;
 479                         if (tx != NULL) {
 480                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 481                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 482                                         dev_err(&spi->dev, "TXS timed out\n");
 483                                         goto out;
 484                                 }
 485                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 486                                                 word_len, *tx);
 487                                 __raw_writel(*tx++, tx_reg);
 488                         }
 489                         if (rx != NULL) {
 490                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 491                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 492                                         dev_err(&spi->dev, "RXS timed out\n");
 493                                         goto out;
 494                                 }
 495
 496                                 if (c == 1 && tx == NULL &&
 497                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 498                                         omap2_mcspi_set_enable(spi, 0);
 499                                         *rx++ = __raw_readl(rx_reg);
 500                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 501                                                     word_len, *(rx - 1));
 502                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 503                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 504                                                 dev_err(&spi->dev,
 505                                                         "RXS timed out\n");
 506                                                 goto out;
 507                                         }
 508                                         c = 0;
 509                                 } else if (c == 0 && tx == NULL) {
 510                                         omap2_mcspi_set_enable(spi, 0);
 511                                 }
 512
 513                                 *rx++ = __raw_readl(rx_reg);
 514                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 515                                                 word_len, *(rx - 1));
 516                         }
 517                 } while (c);
 518         } else if (word_len <= 16) {
 519                 u16             *rx;
 520                 const u16       *tx;
 521
 522                 rx = xfer->rx_buf;
 523                 tx = xfer->tx_buf;
 524                 do {
 525                         c -= 2;
 526                         if (tx != NULL) {
 527                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 528                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 529                                         dev_err(&spi->dev, "TXS timed out\n");
 530                                         goto out;
 531                                 }
 532                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 533                                                 word_len, *tx);
 534                                 __raw_writel(*tx++, tx_reg);
 535                         }
 536                         if (rx != NULL) {
 537                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 538                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 539                                         dev_err(&spi->dev, "RXS timed out\n");
 540                                         goto out;
 541                                 }
 542
 543                                 if (c == 2 && tx == NULL &&
 544                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 545                                         omap2_mcspi_set_enable(spi, 0);
 546                                         *rx++ = __raw_readl(rx_reg);
 547                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 548                                                     word_len, *(rx - 1));
 549                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 550                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 551                                                 dev_err(&spi->dev,
 552                                                         "RXS timed out\n");
 553                                                 goto out;
 554                                         }
 555                                         c = 0;
 556                                 } else if (c == 0 && tx == NULL) {
 557                                         omap2_mcspi_set_enable(spi, 0);
 558                                 }
 559
 560                                 *rx++ = __raw_readl(rx_reg);
 561                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 562                                                 word_len, *(rx - 1));
 563                         }
 564                 } while (c);
 565         } else if (word_len <= 32) {
 566                 u32             *rx;
 567                 const u32       *tx;
 568
 569                 rx = xfer->rx_buf;
 570                 tx = xfer->tx_buf;
 571                 do {
 572                         c -= 4;
 573                         if (tx != NULL) {
 574                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 575                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 576                                         dev_err(&spi->dev, "TXS timed out\n");
 577                                         goto out;
 578                                 }
 579                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 580                                                 word_len, *tx);
 581                                 __raw_writel(*tx++, tx_reg);
 582                         }
 583                         if (rx != NULL) {
 584                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 585                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 586                                         dev_err(&spi->dev, "RXS timed out\n");
 587                                         goto out;
 588                                 }
 589
 590                                 if (c == 4 && tx == NULL &&
 591                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 592                                         omap2_mcspi_set_enable(spi, 0);
 593                                         *rx++ = __raw_readl(rx_reg);
 594                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 595                                                     word_len, *(rx - 1));
 596                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 597                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 598                                                 dev_err(&spi->dev,
 599                                                         "RXS timed out\n");
 600                                                 goto out;
 601                                         }
 602                                         c = 0;
 603                                 } else if (c == 0 && tx == NULL) {
 604                                         omap2_mcspi_set_enable(spi, 0);
 605                                 }
 606
 607                                 *rx++ = __raw_readl(rx_reg);
 608                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 609                                                 word_len, *(rx - 1));
 610                         }
 611                 } while (c);
 612         }
 613
 614         /* for TX_ONLY mode, be sure all words have shifted out */
 615         if (xfer->rx_buf == NULL) {
 616                 if (mcspi_wait_for_reg_bit(chstat_reg,
 617                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 618                         dev_err(&spi->dev, "TXS timed out\n");
 619                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 620                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 621                         dev_err(&spi->dev, "EOT timed out\n");
 622
 623                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 624                  * otherwise these rx datas will affect the direct following
 625                  * RX_ONLY transfer.
 626                  */
 627                 omap2_mcspi_set_enable(spi, 0);
 628         }
 629 out:
 630         omap2_mcspi_set_enable(spi, 1);
 631         return count - c;
 632 }
 633
 634 /* called only when no transfer is active to this device */
 635 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 636                 struct spi_transfer *t)
 637 {
 638         struct omap2_mcspi_cs *cs = spi->controller_state;
 639         struct omap2_mcspi *mcspi;
 640         struct spi_master *spi_cntrl;
 641         u32 l = 0, div = 0;
 642         u8 word_len = spi->bits_per_word;
 643         u32 speed_hz = spi->max_speed_hz;
 644
 645         mcspi = spi_master_get_devdata(spi->master);
 646         spi_cntrl = mcspi->master;
 647
 648         if (t != NULL && t->bits_per_word)
 649                 word_len = t->bits_per_word;
 650
 651         cs->word_len = word_len;
 652
 653         if (t && t->speed_hz)
 654                 speed_hz = t->speed_hz;
 655
 656         if (speed_hz) {
 657                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 658                                         > speed_hz)
 659                         div++;
 660         } else
 661                 div = 15;
 662
 663         l = mcspi_cached_chconf0(spi);
 664
 665         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 666          * REVISIT: this controller could support SPI_3WIRE mode.
 667          */
 668         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 669         l |= OMAP2_MCSPI_CHCONF_DPE0;
 670
 671         /* wordlength */
 672         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 673         l |= (word_len - 1) << 7;
 674
 675         /* set chipselect polarity; manage with FORCE */
 676         if (!(spi->mode & SPI_CS_HIGH))
 677                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 678         else
 679                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 680
 681         /* set clock divisor */
 682         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 683         l |= div << 2;
 684
 685         /* set SPI mode 0..3 */
 686         if (spi->mode & SPI_CPOL)
 687                 l |= OMAP2_MCSPI_CHCONF_POL;
 688         else
 689                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 690         if (spi->mode & SPI_CPHA)
 691                 l |= OMAP2_MCSPI_CHCONF_PHA;
 692         else
 693                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 694
 695         mcspi_write_chconf0(spi, l);
 696
 697         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 698                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 699                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 700                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 701
 702         return 0;
 703 }
 704
 705 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 706 {
 707         struct spi_device       *spi = data;
 708         struct omap2_mcspi      *mcspi;
 709         struct omap2_mcspi_dma  *mcspi_dma;
 710
 711         mcspi = spi_master_get_devdata(spi->master);
 712         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 713
 714         complete(&mcspi_dma->dma_rx_completion);
 715
 716         /* We must disable the DMA RX request */
 717         omap2_mcspi_set_dma_req(spi, 1, 0);
 718 }
 719
 720 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 721 {
 722         struct spi_device       *spi = data;
 723         struct omap2_mcspi      *mcspi;
 724         struct omap2_mcspi_dma  *mcspi_dma;
 725
 726         mcspi = spi_master_get_devdata(spi->master);
 727         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 728
 729         complete(&mcspi_dma->dma_tx_completion);
 730
 731         /* We must disable the DMA TX request */
 732         omap2_mcspi_set_dma_req(spi, 0, 0);
 733 }
 734
 735 static int omap2_mcspi_request_dma(struct spi_device *spi)
 736 {
 737         struct spi_master       *master = spi->master;
 738         struct omap2_mcspi      *mcspi;
 739         struct omap2_mcspi_dma  *mcspi_dma;
 740
 741         mcspi = spi_master_get_devdata(master);
 742         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 743
 744         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 745                         omap2_mcspi_dma_rx_callback, spi,
 746                         &mcspi_dma->dma_rx_channel)) {
 747                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 748                 return -EAGAIN;
 749         }
 750
 751         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 752                         omap2_mcspi_dma_tx_callback, spi,
 753                         &mcspi_dma->dma_tx_channel)) {
 754                 omap_free_dma(mcspi_dma->dma_rx_channel);
 755                 mcspi_dma->dma_rx_channel = -1;
 756                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 757                 return -EAGAIN;
 758         }
 759
 760         init_completion(&mcspi_dma->dma_rx_completion);
 761         init_completion(&mcspi_dma->dma_tx_completion);
 762
 763         return 0;
 764 }
 765
 766 static int omap2_mcspi_setup(struct spi_device *spi)
 767 {
 768         int                     ret;
 769         struct omap2_mcspi      *mcspi;
 770         struct omap2_mcspi_dma  *mcspi_dma;
 771         struct omap2_mcspi_cs   *cs = spi->controller_state;
 772
 773         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 774                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 775                         spi->bits_per_word);
 776                 return -EINVAL;
 777         }
 778
 779         mcspi = spi_master_get_devdata(spi->master);
 780         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 781
 782         if (!cs) {
 783                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 784                 if (!cs)
 785                         return -ENOMEM;
 786                 cs->base = mcspi->base + spi->chip_select * 0x14;
 787                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 788                 cs->chconf0 = 0;
 789                 spi->controller_state = cs;
 790                 /* Link this to context save list */
 791                 list_add_tail(&cs->node,
 792                         &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
 793         }
 794
 795         if (mcspi_dma->dma_rx_channel == -1
 796                         || mcspi_dma->dma_tx_channel == -1) {
 797                 ret = omap2_mcspi_request_dma(spi);
 798                 if (ret < 0)
 799                         return ret;
 800         }
 801
 802         ret = omap2_mcspi_enable_clocks(mcspi);
 803         if (ret < 0)
 804                 return ret;
 805
 806         ret = omap2_mcspi_setup_transfer(spi, NULL);
 807         omap2_mcspi_disable_clocks(mcspi);
 808
 809         return ret;
 810 }
 811
 812 static void omap2_mcspi_cleanup(struct spi_device *spi)
 813 {
 814         struct omap2_mcspi      *mcspi;
 815         struct omap2_mcspi_dma  *mcspi_dma;
 816         struct omap2_mcspi_cs   *cs;
 817
 818         mcspi = spi_master_get_devdata(spi->master);
 819
 820         if (spi->controller_state) {
 821                 /* Unlink controller state from context save list */
 822                 cs = spi->controller_state;
 823                 list_del(&cs->node);
 824
 825                 kfree(spi->controller_state);
 826         }
 827
 828         if (spi->chip_select < spi->master->num_chipselect) {
 829                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 830
 831                 if (mcspi_dma->dma_rx_channel != -1) {
 832                         omap_free_dma(mcspi_dma->dma_rx_channel);
 833                         mcspi_dma->dma_rx_channel = -1;
 834                 }
 835                 if (mcspi_dma->dma_tx_channel != -1) {
 836                         omap_free_dma(mcspi_dma->dma_tx_channel);
 837                         mcspi_dma->dma_tx_channel = -1;
 838                 }
 839         }
 840 }
 841
 842 static void omap2_mcspi_work(struct work_struct *work)
 843 {
 844         struct omap2_mcspi      *mcspi;
 845
 846         mcspi = container_of(work, struct omap2_mcspi, work);
 847
 848         if (omap2_mcspi_enable_clocks(mcspi) < 0)
 849                 return;
 850
 851         spin_lock_irq(&mcspi->lock);
 852
 853         /* We only enable one channel at a time -- the one whose message is
 854          * at the head of the queue -- although this controller would gladly
 855          * arbitrate among multiple channels.  This corresponds to "single
 856          * channel" master mode.  As a side effect, we need to manage the
 857          * chipselect with the FORCE bit ... CS != channel enable.
 858          */
 859         while (!list_empty(&mcspi->msg_queue)) {
 860                 struct spi_message              *m;
 861                 struct spi_device               *spi;
 862                 struct spi_transfer             *t = NULL;
 863                 int                             cs_active = 0;
 864                 struct omap2_mcspi_cs           *cs;
 865                 struct omap2_mcspi_device_config *cd;
 866                 int                             par_override = 0;
 867                 int                             status = 0;
 868                 u32                             chconf;
 869
 870                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 871                                  queue);
 872
 873                 list_del_init(&m->queue);
 874                 spin_unlock_irq(&mcspi->lock);
 875
 876                 spi = m->spi;
 877                 cs = spi->controller_state;
 878                 cd = spi->controller_data;
 879
 880                 omap2_mcspi_set_enable(spi, 1);
 881                 list_for_each_entry(t, &m->transfers, transfer_list) {
 882                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 883                                 status = -EINVAL;
 884                                 break;
 885                         }
 886                         if (par_override || t->speed_hz || t->bits_per_word) {
 887                                 par_override = 1;
 888                                 status = omap2_mcspi_setup_transfer(spi, t);
 889                                 if (status < 0)
 890                                         break;
 891                                 if (!t->speed_hz && !t->bits_per_word)
 892                                         par_override = 0;
 893                         }
 894
 895                         if (!cs_active) {
 896                                 omap2_mcspi_force_cs(spi, 1);
 897                                 cs_active = 1;
 898                         }
 899
 900                         chconf = mcspi_cached_chconf0(spi);
 901                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 902                         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 903
 904                         if (t->tx_buf == NULL)
 905                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 906                         else if (t->rx_buf == NULL)
 907                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 908
 909                         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 910                                 /* Turbo mode is for more than one word */
 911                                 if (t->len > ((cs->word_len + 7) >> 3))
 912                                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 913                         }
 914
 915                         mcspi_write_chconf0(spi, chconf);
 916
 917                         if (t->len) {
 918                                 unsigned        count;
 919
 920                                 /* RX_ONLY mode needs dummy data in TX reg */
 921                                 if (t->tx_buf == NULL)
 922                                         __raw_writel(0, cs->base
 923                                                         + OMAP2_MCSPI_TX0);
 924
 925                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 926                                         count = omap2_mcspi_txrx_dma(spi, t);
 927                                 else
 928                                         count = omap2_mcspi_txrx_pio(spi, t);
 929                                 m->actual_length += count;
 930
 931                                 if (count != t->len) {
 932                                         status = -EIO;
 933                                         break;
 934                                 }
 935                         }
 936
 937                         if (t->delay_usecs)
 938                                 udelay(t->delay_usecs);
 939
 940                         /* ignore the "leave it on after last xfer" hint */
 941                         if (t->cs_change) {
 942                                 omap2_mcspi_force_cs(spi, 0);
 943                                 cs_active = 0;
 944                         }
 945                 }
 946
 947                 /* Restore defaults if they were overriden */
 948                 if (par_override) {
 949                         par_override = 0;
 950                         status = omap2_mcspi_setup_transfer(spi, NULL);
 951                 }
 952
 953                 if (cs_active)
 954                         omap2_mcspi_force_cs(spi, 0);
 955
 956                 omap2_mcspi_set_enable(spi, 0);
 957
 958                 m->status = status;
 959                 m->complete(m->context);
 960
 961                 spin_lock_irq(&mcspi->lock);
 962         }
 963
 964         spin_unlock_irq(&mcspi->lock);
 965
 966         omap2_mcspi_disable_clocks(mcspi);
 967 }
 968
 969 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 970 {
 971         struct omap2_mcspi      *mcspi;
 972         unsigned long           flags;
 973         struct spi_transfer     *t;
 974
 975         m->actual_length = 0;
 976         m->status = 0;
 977
 978         /* reject invalid messages and transfers */
 979         if (list_empty(&m->transfers) || !m->complete)
 980                 return -EINVAL;
 981         list_for_each_entry(t, &m->transfers, transfer_list) {
 982                 const void      *tx_buf = t->tx_buf;
 983                 void            *rx_buf = t->rx_buf;
 984                 unsigned        len = t->len;
 985
 986                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 987                                 || (len && !(rx_buf || tx_buf))
 988                                 || (t->bits_per_word &&
 989                                         (  t->bits_per_word < 4
 990                                         || t->bits_per_word > 32))) {
 991                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 992                                         t->speed_hz,
 993                                         len,
 994                                         tx_buf ? "tx" : "",
 995                                         rx_buf ? "rx" : "",
 996                                         t->bits_per_word);
 997                         return -EINVAL;
 998                 }
 999                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
1000                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
1001                                         t->speed_hz,
1002                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
1003                         return -EINVAL;
1004                 }
1005
1006                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1007                         continue;
1008
1009                 if (tx_buf != NULL) {
1010                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
1011                                         len, DMA_TO_DEVICE);
1012                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
1013                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1014                                                 'T', len);
1015                                 return -EINVAL;
1016                         }
1017                 }
1018                 if (rx_buf != NULL) {
1019                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
1020                                         DMA_FROM_DEVICE);
1021                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
1022                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1023                                                 'R', len);
1024                                 if (tx_buf != NULL)
1025                                         dma_unmap_single(&spi->dev, t->tx_dma,
1026                                                         len, DMA_TO_DEVICE);
1027                                 return -EINVAL;
1028                         }
1029                 }
1030         }
1031
1032         mcspi = spi_master_get_devdata(spi->master);
1033
1034         spin_lock_irqsave(&mcspi->lock, flags);
1035         list_add_tail(&m->queue, &mcspi->msg_queue);
1036         queue_work(omap2_mcspi_wq, &mcspi->work);
1037         spin_unlock_irqrestore(&mcspi->lock, flags);
1038
1039         return 0;
1040 }
1041
1042 static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1043 {
1044         struct spi_master       *master = mcspi->master;
1045         u32                     tmp;
1046         int ret = 0;
1047
1048         ret = omap2_mcspi_enable_clocks(mcspi);
1049         if (ret < 0)
1050                 return ret;
1051
1052         tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1053         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1054         omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
1055
1056         omap2_mcspi_set_master_mode(master);
1057         omap2_mcspi_disable_clocks(mcspi);
1058         return 0;
1059 }
1060
1061 static int omap_mcspi_runtime_resume(struct device *dev)
1062 {
1063         struct omap2_mcspi      *mcspi;
1064         struct spi_master       *master;
1065
1066         master = dev_get_drvdata(dev);
1067         mcspi = spi_master_get_devdata(master);
1068         omap2_mcspi_restore_ctx(mcspi);
1069
1070         return 0;
1071 }
1072
1073
1074 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1075 {
1076         struct spi_master       *master;
1077         struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
1078         struct omap2_mcspi      *mcspi;
1079         struct resource         *r;
1080         int                     status = 0, i;
1081
1082         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1083         if (master == NULL) {
1084                 dev_dbg(&pdev->dev, "master allocation failed\n");
1085                 return -ENOMEM;
1086         }
1087
1088         /* the spi->mode bits understood by this driver: */
1089         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1090
1091         if (pdev->id != -1)
1092                 master->bus_num = pdev->id;
1093
1094         master->setup = omap2_mcspi_setup;
1095         master->transfer = omap2_mcspi_transfer;
1096         master->cleanup = omap2_mcspi_cleanup;
1097         master->num_chipselect = pdata->num_cs;
1098
1099         dev_set_drvdata(&pdev->dev, master);
1100
1101         mcspi = spi_master_get_devdata(master);
1102         mcspi->master = master;
1103
1104         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105         if (r == NULL) {
1106                 status = -ENODEV;
1107                 goto err1;
1108         }
1109         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1110                         dev_name(&pdev->dev))) {
1111                 status = -EBUSY;
1112                 goto err1;
1113         }
1114
1115         r->start += pdata->regs_offset;
1116         r->end += pdata->regs_offset;
1117         mcspi->phys = r->start;
1118         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1119         if (!mcspi->base) {
1120                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1121                 status = -ENOMEM;
1122                 goto err2;
1123         }
1124
1125         mcspi->dev = &pdev->dev;
1126         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1127
1128         spin_lock_init(&mcspi->lock);
1129         INIT_LIST_HEAD(&mcspi->msg_queue);
1130         INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1131
1132         mcspi->dma_channels = kcalloc(master->num_chipselect,
1133                         sizeof(struct omap2_mcspi_dma),
1134                         GFP_KERNEL);
1135
1136         if (mcspi->dma_channels == NULL)
1137                 goto err2;
1138
1139         for (i = 0; i < master->num_chipselect; i++) {
1140                 char dma_ch_name[14];
1141                 struct resource *dma_res;
1142
1143                 sprintf(dma_ch_name, "rx%d", i);
1144                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1145                                                         dma_ch_name);
1146                 if (!dma_res) {
1147                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1148                         status = -ENODEV;
1149                         break;
1150                 }
1151
1152                 mcspi->dma_channels[i].dma_rx_channel = -1;
1153                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1154                 sprintf(dma_ch_name, "tx%d", i);
1155                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1156                                                         dma_ch_name);
1157                 if (!dma_res) {
1158                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1159                         status = -ENODEV;
1160                         break;
1161                 }
1162
1163                 mcspi->dma_channels[i].dma_tx_channel = -1;
1164                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1165         }
1166
1167         pm_runtime_enable(&pdev->dev);
1168
1169         if (status || omap2_mcspi_master_setup(mcspi) < 0)
1170                 goto err3;
1171
1172         status = spi_register_master(master);
1173         if (status < 0)
1174                 goto err4;
1175
1176         return status;
1177
1178 err4:
1179         spi_master_put(master);
1180 err3:
1181         kfree(mcspi->dma_channels);
1182 err2:
1183         release_mem_region(r->start, (r->end - r->start) + 1);
1184         iounmap(mcspi->base);
1185 err1:
1186         return status;
1187 }
1188
1189 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1190 {
1191         struct spi_master       *master;
1192         struct omap2_mcspi      *mcspi;
1193         struct omap2_mcspi_dma  *dma_channels;
1194         struct resource         *r;
1195         void __iomem *base;
1196
1197         master = dev_get_drvdata(&pdev->dev);
1198         mcspi = spi_master_get_devdata(master);
1199         dma_channels = mcspi->dma_channels;
1200
1201         omap2_mcspi_disable_clocks(mcspi);
1202         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203         release_mem_region(r->start, (r->end - r->start) + 1);
1204
1205         base = mcspi->base;
1206         spi_unregister_master(master);
1207         iounmap(base);
1208         kfree(dma_channels);
1209
1210         return 0;
1211 }
1212
1213 /* work with hotplug and coldplug */
1214 MODULE_ALIAS("platform:omap2_mcspi");
1215
1216 #ifdef  CONFIG_SUSPEND
1217 /*
1218  * When SPI wake up from off-mode, CS is in activate state. If it was in
1219  * unactive state when driver was suspend, then force it to unactive state at
1220  * wake up.
1221  */
1222 static int omap2_mcspi_resume(struct device *dev)
1223 {
1224         struct spi_master       *master = dev_get_drvdata(dev);
1225         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1226         struct omap2_mcspi_cs *cs;
1227
1228         omap2_mcspi_enable_clocks(mcspi);
1229         list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
1230                             node) {
1231                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1232
1233                         /*
1234                          * We need to toggle CS state for OMAP take this
1235                          * change in account.
1236                          */
1237                         MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1238                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1239                         MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1240                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1241                 }
1242         }
1243         omap2_mcspi_disable_clocks(mcspi);
1244         return 0;
1245 }
1246 #else
1247 #define omap2_mcspi_resume      NULL
1248 #endif
1249
1250 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1251         .resume = omap2_mcspi_resume,
1252         .runtime_resume = omap_mcspi_runtime_resume,
1253 };
1254
1255 static struct platform_driver omap2_mcspi_driver = {
1256         .driver = {
1257                 .name =         "omap2_mcspi",
1258                 .owner =        THIS_MODULE,
1259                 .pm =           &omap2_mcspi_pm_ops
1260         },
1261         .remove =       __exit_p(omap2_mcspi_remove),
1262 };
1263
1264
1265 static int __init omap2_mcspi_init(void)
1266 {
1267         omap2_mcspi_wq = create_singlethread_workqueue(
1268                                 omap2_mcspi_driver.driver.name);
1269         if (omap2_mcspi_wq == NULL)
1270                 return -1;
1271         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1272 }
1273 subsys_initcall(omap2_mcspi_init);
1274
1275 static void __exit omap2_mcspi_exit(void)
1276 {
1277         platform_driver_unregister(&omap2_mcspi_driver);
1278
1279         destroy_workqueue(omap2_mcspi_wq);
1280 }
1281 module_exit(omap2_mcspi_exit);
1282
1283 MODULE_LICENSE("GPL");