2 * Copyright (C) 2009 Texas Instruments.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/interrupt.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/slab.h>
33 #include <mach/edma.h>
35 #define SPI_NO_RESOURCE ((resource_size_t)-1)
37 #define SPI_MAX_CHIPSELECT 2
39 #define CS_DEFAULT 0xFF
41 #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
43 #define SPIFMT_PHASE_MASK BIT(16)
44 #define SPIFMT_POLARITY_MASK BIT(17)
45 #define SPIFMT_DISTIMER_MASK BIT(18)
46 #define SPIFMT_SHIFTDIR_MASK BIT(20)
47 #define SPIFMT_WAITENA_MASK BIT(21)
48 #define SPIFMT_PARITYENA_MASK BIT(22)
49 #define SPIFMT_ODD_PARITY_MASK BIT(23)
50 #define SPIFMT_WDELAY_MASK 0x3f000000u
51 #define SPIFMT_WDELAY_SHIFT 24
52 #define SPIFMT_PRESCALE_SHIFT 8
56 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
57 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
59 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
61 #define SPIINT_MASKALL 0x0101035F
62 #define SPIINT_MASKINT 0x0000015F
63 #define SPI_INTLVL_1 0x000001FF
64 #define SPI_INTLVL_0 0x00000000
66 /* SPIDAT1 (upper 16 bit defines) */
67 #define SPIDAT1_CSHOLD_MASK BIT(12)
70 #define SPIGCR1_CLKMOD_MASK BIT(1)
71 #define SPIGCR1_MASTER_MASK BIT(0)
72 #define SPIGCR1_LOOPBACK_MASK BIT(16)
73 #define SPIGCR1_SPIENA_MASK BIT(24)
76 #define SPIBUF_TXFULL_MASK BIT(29)
77 #define SPIBUF_RXEMPTY_MASK BIT(31)
80 #define SPIDELAY_C2TDELAY_SHIFT 24
81 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
82 #define SPIDELAY_T2CDELAY_SHIFT 16
83 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
84 #define SPIDELAY_T2EDELAY_SHIFT 8
85 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
86 #define SPIDELAY_C2EDELAY_SHIFT 0
87 #define SPIDELAY_C2EDELAY_MASK 0xFF
90 #define SPIFLG_DLEN_ERR_MASK BIT(0)
91 #define SPIFLG_TIMEOUT_MASK BIT(1)
92 #define SPIFLG_PARERR_MASK BIT(2)
93 #define SPIFLG_DESYNC_MASK BIT(3)
94 #define SPIFLG_BITERR_MASK BIT(4)
95 #define SPIFLG_OVRRUN_MASK BIT(6)
96 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
97 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
98 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
99 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100 | SPIFLG_OVRRUN_MASK)
102 #define SPIINT_DMA_REQ_EN BIT(16)
104 /* SPI Controller registers */
113 #define SPIDELAY 0x48
117 /* We have 2 DMA channels per CS, one for RX and one for TX */
118 struct davinci_spi_dma {
123 enum dma_event_q eventq;
125 struct completion dma_tx_completion;
126 struct completion dma_rx_completion;
129 /* SPI Controller driver's private data. */
131 struct spi_bitbang bitbang;
135 resource_size_t pbase;
139 struct completion done;
146 struct davinci_spi_dma *dma_channels;
147 struct davinci_spi_platform_data *pdata;
149 void (*get_rx)(u32 rx_data, struct davinci_spi *);
150 u32 (*get_tx)(struct davinci_spi *);
152 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
155 static struct davinci_spi_config davinci_spi_default_cfg;
157 static unsigned use_dma;
159 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
161 if (davinci_spi->rx) {
162 u8 *rx = davinci_spi->rx;
164 davinci_spi->rx = rx;
168 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
170 if (davinci_spi->rx) {
171 u16 *rx = davinci_spi->rx;
173 davinci_spi->rx = rx;
177 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
180 if (davinci_spi->tx) {
181 const u8 *tx = davinci_spi->tx;
183 davinci_spi->tx = tx;
188 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
191 if (davinci_spi->tx) {
192 const u16 *tx = davinci_spi->tx;
194 davinci_spi->tx = tx;
199 static inline void set_io_bits(void __iomem *addr, u32 bits)
201 u32 v = ioread32(addr);
207 static inline void clear_io_bits(void __iomem *addr, u32 bits)
209 u32 v = ioread32(addr);
215 static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
217 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
220 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
222 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
226 * Interface to control the chip select signal
228 static void davinci_spi_chipselect(struct spi_device *spi, int value)
230 struct davinci_spi *davinci_spi;
231 struct davinci_spi_platform_data *pdata;
232 u8 chip_sel = spi->chip_select;
233 u16 spidat1_cfg = CS_DEFAULT;
234 bool gpio_chipsel = false;
236 davinci_spi = spi_master_get_devdata(spi->master);
237 pdata = davinci_spi->pdata;
239 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
240 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
244 * Board specific chip select logic decides the polarity and cs
245 * line for the controller
248 if (value == BITBANG_CS_ACTIVE)
249 gpio_set_value(pdata->chip_sel[chip_sel], 0);
251 gpio_set_value(pdata->chip_sel[chip_sel], 1);
253 if (value == BITBANG_CS_ACTIVE) {
254 spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
255 spidat1_cfg &= ~(0x1 << chip_sel);
258 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
263 * davinci_spi_get_prescale - Calculates the correct prescale value
264 * @maxspeed_hz: the maximum rate the SPI clock can run at
266 * This function calculates the prescale value that generates a clock rate
267 * less than or equal to the specified maximum.
269 * Returns: calculated prescale - 1 for easy programming into SPI registers
270 * or negative error number if valid prescalar cannot be updated.
272 static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
277 ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
279 if (ret < 3 || ret > 256)
286 * davinci_spi_setup_transfer - This functions will determine transfer method
287 * @spi: spi device on which data transfer to be done
288 * @t: spi transfer in which transfer info is filled
290 * This function determines data transfer method (8/16/32 bit transfer).
291 * It will also set the SPI Clock Control register according to
292 * SPI slave device freq.
294 static int davinci_spi_setup_transfer(struct spi_device *spi,
295 struct spi_transfer *t)
298 struct davinci_spi *davinci_spi;
299 struct davinci_spi_config *spicfg;
300 u8 bits_per_word = 0;
301 u32 hz = 0, spifmt = 0, prescale = 0;
303 davinci_spi = spi_master_get_devdata(spi->master);
304 spicfg = (struct davinci_spi_config *)spi->controller_data;
306 spicfg = &davinci_spi_default_cfg;
309 bits_per_word = t->bits_per_word;
313 /* if bits_per_word is not set then set it default */
315 bits_per_word = spi->bits_per_word;
318 * Assign function pointer to appropriate transfer method
319 * 8bit, 16bit or 32bit transfer
321 if (bits_per_word <= 8 && bits_per_word >= 2) {
322 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
323 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
324 davinci_spi->bytes_per_word[spi->chip_select] = 1;
325 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
326 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
327 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
328 davinci_spi->bytes_per_word[spi->chip_select] = 2;
333 hz = spi->max_speed_hz;
335 /* Set up SPIFMTn register, unique to this chipselect. */
337 prescale = davinci_spi_get_prescale(davinci_spi, hz);
341 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
343 if (spi->mode & SPI_LSB_FIRST)
344 spifmt |= SPIFMT_SHIFTDIR_MASK;
346 if (spi->mode & SPI_CPOL)
347 spifmt |= SPIFMT_POLARITY_MASK;
349 if (!(spi->mode & SPI_CPHA))
350 spifmt |= SPIFMT_PHASE_MASK;
353 * Version 1 hardware supports two basic SPI modes:
354 * - Standard SPI mode uses 4 pins, with chipselect
355 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
356 * (distinct from SPI_3WIRE, with just one data wire;
357 * or similar variants without MOSI or without MISO)
359 * Version 2 hardware supports an optional handshaking signal,
360 * so it can support two more modes:
361 * - 5 pin SPI variant is standard SPI plus SPI_READY
362 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
365 if (davinci_spi->version == SPI_VERSION_2) {
369 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
370 & SPIFMT_WDELAY_MASK);
372 if (spicfg->odd_parity)
373 spifmt |= SPIFMT_ODD_PARITY_MASK;
375 if (spicfg->parity_enable)
376 spifmt |= SPIFMT_PARITYENA_MASK;
378 if (spicfg->timer_disable) {
379 spifmt |= SPIFMT_DISTIMER_MASK;
381 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
382 & SPIDELAY_C2TDELAY_MASK;
383 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
384 & SPIDELAY_T2CDELAY_MASK;
387 if (spi->mode & SPI_READY) {
388 spifmt |= SPIFMT_WAITENA_MASK;
389 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
390 & SPIDELAY_T2EDELAY_MASK;
391 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
392 & SPIDELAY_C2EDELAY_MASK;
395 iowrite32(delay, davinci_spi->base + SPIDELAY);
398 iowrite32(spifmt, davinci_spi->base + SPIFMT0);
403 static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
405 struct spi_device *spi = (struct spi_device *)data;
406 struct davinci_spi *davinci_spi;
407 struct davinci_spi_dma *davinci_spi_dma;
409 davinci_spi = spi_master_get_devdata(spi->master);
410 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
412 if (ch_status == DMA_COMPLETE)
413 edma_stop(davinci_spi_dma->dma_rx_channel);
415 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
417 complete(&davinci_spi_dma->dma_rx_completion);
418 /* We must disable the DMA RX request */
419 davinci_spi_set_dma_req(spi, 0);
422 static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
424 struct spi_device *spi = (struct spi_device *)data;
425 struct davinci_spi *davinci_spi;
426 struct davinci_spi_dma *davinci_spi_dma;
428 davinci_spi = spi_master_get_devdata(spi->master);
429 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
431 if (ch_status == DMA_COMPLETE)
432 edma_stop(davinci_spi_dma->dma_tx_channel);
434 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
436 complete(&davinci_spi_dma->dma_tx_completion);
437 /* We must disable the DMA TX request */
438 davinci_spi_set_dma_req(spi, 0);
441 static int davinci_spi_request_dma(struct spi_device *spi)
443 struct davinci_spi *davinci_spi;
444 struct davinci_spi_dma *davinci_spi_dma;
448 davinci_spi = spi_master_get_devdata(spi->master);
449 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
450 sdev = davinci_spi->bitbang.master->dev.parent;
452 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
453 davinci_spi_dma_rx_callback, spi,
454 davinci_spi_dma->eventq);
456 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
459 davinci_spi_dma->dma_rx_channel = r;
460 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
461 davinci_spi_dma_tx_callback, spi,
462 davinci_spi_dma->eventq);
464 edma_free_channel(davinci_spi_dma->dma_rx_channel);
465 davinci_spi_dma->dma_rx_channel = -1;
466 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
469 davinci_spi_dma->dma_tx_channel = r;
475 * davinci_spi_setup - This functions will set default transfer method
476 * @spi: spi device on which data transfer to be done
478 * This functions sets the default transfer method.
480 static int davinci_spi_setup(struct spi_device *spi)
483 struct davinci_spi *davinci_spi;
484 struct davinci_spi_dma *davinci_spi_dma;
485 struct davinci_spi_platform_data *pdata;
487 davinci_spi = spi_master_get_devdata(spi->master);
488 pdata = davinci_spi->pdata;
490 /* if bits per word length is zero then set it default 8 */
491 if (!spi->bits_per_word)
492 spi->bits_per_word = 8;
494 if (!(spi->mode & SPI_NO_CS)) {
495 if ((pdata->chip_sel == NULL) ||
496 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
497 set_io_bits(davinci_spi->base + SPIPC0,
498 1 << spi->chip_select);
502 if (spi->mode & SPI_READY)
503 set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK);
505 if (spi->mode & SPI_LOOP)
506 set_io_bits(davinci_spi->base + SPIGCR1,
507 SPIGCR1_LOOPBACK_MASK);
509 clear_io_bits(davinci_spi->base + SPIGCR1,
510 SPIGCR1_LOOPBACK_MASK);
512 if (use_dma && davinci_spi->dma_channels) {
513 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
515 if ((davinci_spi_dma->dma_rx_channel == -1)
516 || (davinci_spi_dma->dma_tx_channel == -1)) {
517 retval = davinci_spi_request_dma(spi);
523 retval = davinci_spi_setup_transfer(spi, NULL);
528 static void davinci_spi_cleanup(struct spi_device *spi)
530 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
531 struct davinci_spi_dma *davinci_spi_dma;
533 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
535 if (use_dma && davinci_spi->dma_channels) {
536 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
538 if ((davinci_spi_dma->dma_rx_channel != -1)
539 && (davinci_spi_dma->dma_tx_channel != -1)) {
540 edma_free_channel(davinci_spi_dma->dma_tx_channel);
541 edma_free_channel(davinci_spi_dma->dma_rx_channel);
546 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
549 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
551 if (int_status & SPIFLG_TIMEOUT_MASK) {
552 dev_dbg(sdev, "SPI Time-out Error\n");
555 if (int_status & SPIFLG_DESYNC_MASK) {
556 dev_dbg(sdev, "SPI Desynchronization Error\n");
559 if (int_status & SPIFLG_BITERR_MASK) {
560 dev_dbg(sdev, "SPI Bit error\n");
564 if (davinci_spi->version == SPI_VERSION_2) {
565 if (int_status & SPIFLG_DLEN_ERR_MASK) {
566 dev_dbg(sdev, "SPI Data Length Error\n");
569 if (int_status & SPIFLG_PARERR_MASK) {
570 dev_dbg(sdev, "SPI Parity Error\n");
573 if (int_status & SPIFLG_OVRRUN_MASK) {
574 dev_dbg(sdev, "SPI Data Overrun error\n");
577 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
578 dev_dbg(sdev, "SPI Buffer Init Active\n");
587 * davinci_spi_process_events - check for and handle any SPI controller events
588 * @davinci_spi: the controller data
590 * This function will check the SPIFLG register and handle any events that are
593 static int davinci_spi_process_events(struct davinci_spi *davinci_spi)
595 u32 buf, status, errors = 0, data1_reg_val;
597 buf = ioread32(davinci_spi->base + SPIBUF);
599 if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
600 davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
601 davinci_spi->rcount--;
604 status = ioread32(davinci_spi->base + SPIFLG);
606 if (unlikely(status & SPIFLG_ERROR_MASK)) {
607 errors = status & SPIFLG_ERROR_MASK;
611 if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
612 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
613 davinci_spi->wcount--;
614 data1_reg_val &= ~0xFFFF;
615 data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi);
616 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
624 * davinci_spi_bufs - functions which will handle transfer data
625 * @spi: spi device on which data transfer to be done
626 * @t: spi transfer in which transfer info is filled
628 * This function will put data to be transferred into data register
629 * of SPI controller and then wait until the completion will be marked
630 * by the IRQ Handler.
632 static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
634 struct davinci_spi *davinci_spi;
636 u32 tx_data, data1_reg_val;
638 struct davinci_spi_config *spicfg;
639 struct davinci_spi_platform_data *pdata;
641 davinci_spi = spi_master_get_devdata(spi->master);
642 pdata = davinci_spi->pdata;
643 spicfg = (struct davinci_spi_config *)spi->controller_data;
645 spicfg = &davinci_spi_default_cfg;
647 davinci_spi->tx = t->tx_buf;
648 davinci_spi->rx = t->rx_buf;
649 davinci_spi->wcount = t->len /
650 davinci_spi->bytes_per_word[spi->chip_select];
651 davinci_spi->rcount = davinci_spi->wcount;
653 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
656 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
658 if (spicfg->io_type == SPI_IO_TYPE_INTR) {
659 set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
660 INIT_COMPLETION(davinci_spi->done);
663 /* start the transfer */
664 davinci_spi->wcount--;
665 tx_data = davinci_spi->get_tx(davinci_spi);
666 data1_reg_val &= 0xFFFF0000;
667 data1_reg_val |= tx_data & 0xFFFF;
668 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
670 /* Wait for the transfer to complete */
671 if (spicfg->io_type == SPI_IO_TYPE_INTR) {
672 wait_for_completion_interruptible(&(davinci_spi->done));
674 while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
675 errors = davinci_spi_process_events(davinci_spi);
682 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
685 * Check for bit error, desync error,parity error,timeout error and
686 * receive overflow errors
689 ret = davinci_spi_check_error(davinci_spi, errors);
690 WARN(!ret, "%s: error reported but no error found!\n",
691 dev_name(&spi->dev));
699 * davinci_spi_irq - Interrupt handler for SPI Master Controller
700 * @irq: IRQ number for this SPI Master
701 * @context_data: structure for SPI Master controller davinci_spi
703 * ISR will determine that interrupt arrives either for READ or WRITE command.
704 * According to command it will do the appropriate action. It will check
705 * transfer length and if it is not zero then dispatch transfer command again.
706 * If transfer length is zero then it will indicate the COMPLETION so that
707 * davinci_spi_bufs function can go ahead.
709 static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
711 struct davinci_spi *davinci_spi = context_data;
714 status = davinci_spi_process_events(davinci_spi);
715 if (unlikely(status != 0))
716 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
718 if ((!davinci_spi->rcount && !davinci_spi->wcount) || status)
719 complete(&davinci_spi->done);
724 static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
726 struct davinci_spi *davinci_spi;
728 int count, temp_count;
730 struct davinci_spi_dma *davinci_spi_dma;
732 unsigned long tx_reg, rx_reg;
735 davinci_spi = spi_master_get_devdata(spi->master);
736 sdev = davinci_spi->bitbang.master->dev.parent;
738 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
740 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
741 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
743 davinci_spi->tx = t->tx_buf;
744 davinci_spi->rx = t->rx_buf;
746 /* convert len to words based on bits_per_word */
747 data_type = davinci_spi->bytes_per_word[spi->chip_select];
749 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
751 init_completion(&davinci_spi_dma->dma_rx_completion);
752 init_completion(&davinci_spi_dma->dma_tx_completion);
754 count = t->len / data_type; /* the number of elements */
756 /* disable all interrupts for dma transfers */
757 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
759 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
762 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
764 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
765 dev_dbg(sdev, "Unable to DMA map a %d bytes"
766 " TX buffer\n", count);
771 /* We need TX clocking for RX transaction */
772 t->tx_dma = dma_map_single(&spi->dev,
773 (void *)davinci_spi->tmp_buf, count + 1,
775 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
776 dev_dbg(sdev, "Unable to DMA map a %d bytes"
777 " TX tmp buffer\n", count);
780 temp_count = count + 1;
783 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
784 data_type, temp_count, 1, 0, ASYNC);
785 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
786 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
787 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
788 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
791 /* initiate transaction */
792 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
794 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
796 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
797 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
799 if (t->tx_buf != NULL)
800 dma_unmap_single(NULL, t->tx_dma,
801 count, DMA_TO_DEVICE);
804 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
805 data_type, count, 1, 0, ASYNC);
806 edma_set_src(davinci_spi_dma->dma_rx_channel,
807 rx_reg, INCR, W8BIT);
808 edma_set_dest(davinci_spi_dma->dma_rx_channel,
809 t->rx_dma, INCR, W8BIT);
810 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
811 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
815 if ((t->tx_buf) || (t->rx_buf))
816 edma_start(davinci_spi_dma->dma_tx_channel);
819 edma_start(davinci_spi_dma->dma_rx_channel);
821 if ((t->rx_buf) || (t->tx_buf))
822 davinci_spi_set_dma_req(spi, 1);
825 wait_for_completion_interruptible(
826 &davinci_spi_dma->dma_tx_completion);
829 wait_for_completion_interruptible(
830 &davinci_spi_dma->dma_rx_completion);
832 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
835 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
838 * Check for bit error, desync error,parity error,timeout error and
839 * receive overflow errors
841 int_status = ioread32(davinci_spi->base + SPIFLG);
843 ret = davinci_spi_check_error(davinci_spi, int_status);
851 * davinci_spi_probe - probe function for SPI Master Controller
852 * @pdev: platform_device structure which contains plateform specific data
854 static int davinci_spi_probe(struct platform_device *pdev)
856 struct spi_master *master;
857 struct davinci_spi *davinci_spi;
858 struct davinci_spi_platform_data *pdata;
859 struct resource *r, *mem;
860 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
861 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
862 resource_size_t dma_eventq = SPI_NO_RESOURCE;
866 pdata = pdev->dev.platform_data;
872 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
873 if (master == NULL) {
878 dev_set_drvdata(&pdev->dev, master);
880 davinci_spi = spi_master_get_devdata(master);
881 if (davinci_spi == NULL) {
886 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
892 davinci_spi->pbase = r->start;
893 davinci_spi->region_size = resource_size(r);
894 davinci_spi->pdata = pdata;
896 mem = request_mem_region(r->start, davinci_spi->region_size,
903 davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
904 if (davinci_spi->base == NULL) {
909 davinci_spi->irq = platform_get_irq(pdev, 0);
910 if (davinci_spi->irq <= 0) {
915 ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0,
916 dev_name(&pdev->dev), davinci_spi);
920 /* Allocate tmp_buf for tx_buf */
921 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
922 if (davinci_spi->tmp_buf == NULL) {
927 davinci_spi->bitbang.master = spi_master_get(master);
928 if (davinci_spi->bitbang.master == NULL) {
933 davinci_spi->clk = clk_get(&pdev->dev, NULL);
934 if (IS_ERR(davinci_spi->clk)) {
938 clk_enable(davinci_spi->clk);
940 master->bus_num = pdev->id;
941 master->num_chipselect = pdata->num_chipselect;
942 master->setup = davinci_spi_setup;
943 master->cleanup = davinci_spi_cleanup;
945 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
946 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
948 davinci_spi->version = pdata->version;
949 use_dma = pdata->use_dma;
951 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
952 if (davinci_spi->version == SPI_VERSION_2)
953 davinci_spi->bitbang.flags |= SPI_READY;
956 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
958 dma_rx_chan = r->start;
959 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
961 dma_tx_chan = r->start;
962 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
964 dma_eventq = r->start;
968 dma_rx_chan == SPI_NO_RESOURCE ||
969 dma_tx_chan == SPI_NO_RESOURCE ||
970 dma_eventq == SPI_NO_RESOURCE) {
971 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
974 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
975 davinci_spi->dma_channels = kzalloc(master->num_chipselect
976 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
977 if (davinci_spi->dma_channels == NULL) {
982 for (i = 0; i < master->num_chipselect; i++) {
983 davinci_spi->dma_channels[i].dma_rx_channel = -1;
984 davinci_spi->dma_channels[i].dma_rx_sync_dev =
986 davinci_spi->dma_channels[i].dma_tx_channel = -1;
987 davinci_spi->dma_channels[i].dma_tx_sync_dev =
989 davinci_spi->dma_channels[i].eventq = dma_eventq;
991 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
992 "Using RX channel = %d , TX channel = %d and "
993 "event queue = %d", dma_rx_chan, dma_tx_chan,
997 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
998 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1000 init_completion(&davinci_spi->done);
1002 /* Reset In/OUT SPI module */
1003 iowrite32(0, davinci_spi->base + SPIGCR0);
1005 iowrite32(1, davinci_spi->base + SPIGCR0);
1007 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1008 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1009 iowrite32(spipc0, davinci_spi->base + SPIPC0);
1011 /* initialize chip selects */
1012 if (pdata->chip_sel) {
1013 for (i = 0; i < pdata->num_chipselect; i++) {
1014 if (pdata->chip_sel[i] != SPI_INTERN_CS)
1015 gpio_direction_output(pdata->chip_sel[i], 1);
1019 /* Clock internal */
1020 if (davinci_spi->pdata->clk_internal)
1021 set_io_bits(davinci_spi->base + SPIGCR1,
1022 SPIGCR1_CLKMOD_MASK);
1024 clear_io_bits(davinci_spi->base + SPIGCR1,
1025 SPIGCR1_CLKMOD_MASK);
1027 if (pdata->intr_line)
1028 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1030 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1032 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1034 /* master mode default */
1035 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1037 ret = spi_bitbang_start(&davinci_spi->bitbang);
1041 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
1046 clk_disable(davinci_spi->clk);
1047 clk_put(davinci_spi->clk);
1049 spi_master_put(master);
1051 kfree(davinci_spi->tmp_buf);
1053 free_irq(davinci_spi->irq, davinci_spi);
1055 iounmap(davinci_spi->base);
1057 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1065 * davinci_spi_remove - remove function for SPI Master Controller
1066 * @pdev: platform_device structure which contains plateform specific data
1068 * This function will do the reverse action of davinci_spi_probe function
1069 * It will free the IRQ and SPI controller's memory region.
1070 * It will also call spi_bitbang_stop to destroy the work queue which was
1071 * created by spi_bitbang_start.
1073 static int __exit davinci_spi_remove(struct platform_device *pdev)
1075 struct davinci_spi *davinci_spi;
1076 struct spi_master *master;
1078 master = dev_get_drvdata(&pdev->dev);
1079 davinci_spi = spi_master_get_devdata(master);
1081 spi_bitbang_stop(&davinci_spi->bitbang);
1083 clk_disable(davinci_spi->clk);
1084 clk_put(davinci_spi->clk);
1085 spi_master_put(master);
1086 kfree(davinci_spi->tmp_buf);
1087 free_irq(davinci_spi->irq, davinci_spi);
1088 iounmap(davinci_spi->base);
1089 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1094 static struct platform_driver davinci_spi_driver = {
1095 .driver.name = "spi_davinci",
1096 .remove = __exit_p(davinci_spi_remove),
1099 static int __init davinci_spi_init(void)
1101 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1103 module_init(davinci_spi_init);
1105 static void __exit davinci_spi_exit(void)
1107 platform_driver_unregister(&davinci_spi_driver);
1109 module_exit(davinci_spi_exit);
1111 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1112 MODULE_LICENSE("GPL");