drivers/spi/atmel_spi.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/arch/board.h>
  24 #include <asm/arch/gpio.h>
  25
  26 #include "atmel_spi.h"
  27
  28 /*
  29  * The core SPI transfer engine just talks to a register bank to set up
  30  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
  31  * framework provides the base clock, subdivided for each spi_device.
  32  *
  33  * Newer controllers, marked with "new_1" flag, have:
  34  *  - CR.LASTXFER
  35  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  36  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  37  *  - SPI_CSRx.CSAAT
  38  *  - SPI_CSRx.SBCR allows faster clocking
  39  */
  40 struct atmel_spi {
  41         spinlock_t              lock;
  42
  43         void __iomem            *regs;
  44         int                     irq;
  45         struct clk              *clk;
  46         struct platform_device  *pdev;
  47         unsigned                new_1:1;
  48
  49         u8                      stopping;
  50         struct list_head        queue;
  51         struct spi_transfer     *current_transfer;
  52         unsigned long           remaining_bytes;
  53
  54         void                    *buffer;
  55         dma_addr_t              buffer_dma;
  56 };
  57
  58 #define BUFFER_SIZE             PAGE_SIZE
  59 #define INVALID_DMA_ADDRESS     0xffffffff
  60
  61 /*
  62  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  63  * they assume that spi slave device state will not change on deselect, so
  64  * that automagic deselection is OK.  Not so!  Workaround uses nCSx pins
  65  * as GPIOs; or newer controllers have CSAAT and friends.
  66  *
  67  * Since the CSAAT functionality is a bit weird on newer controllers
  68  * as well, we use GPIO to control nCSx pins on all controllers.
  69  */
  70
  71 static inline void cs_activate(struct spi_device *spi)
  72 {
  73         unsigned gpio = (unsigned) spi->controller_data;
  74         unsigned active = spi->mode & SPI_CS_HIGH;
  75
  76         dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : "");
  77         gpio_set_value(gpio, active);
  78 }
  79
  80 static inline void cs_deactivate(struct spi_device *spi)
  81 {
  82         unsigned gpio = (unsigned) spi->controller_data;
  83         unsigned active = spi->mode & SPI_CS_HIGH;
  84
  85         dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
  86         gpio_set_value(gpio, !active);
  87 }
  88
  89 /*
  90  * Submit next transfer for DMA.
  91  * lock is held, spi irq is blocked
  92  */
  93 static void atmel_spi_next_xfer(struct spi_master *master,
  94                                 struct spi_message *msg)
  95 {
  96         struct atmel_spi        *as = spi_master_get_devdata(master);
  97         struct spi_transfer     *xfer;
  98         u32                     len;
  99         dma_addr_t              tx_dma, rx_dma;
 100
 101         xfer = as->current_transfer;
 102         if (!xfer || as->remaining_bytes == 0) {
 103                 if (xfer)
 104                         xfer = list_entry(xfer->transfer_list.next,
 105                                         struct spi_transfer, transfer_list);
 106                 else
 107                         xfer = list_entry(msg->transfers.next,
 108                                         struct spi_transfer, transfer_list);
 109                 as->remaining_bytes = xfer->len;
 110                 as->current_transfer = xfer;
 111         }
 112
 113         len = as->remaining_bytes;
 114
 115         tx_dma = xfer->tx_dma;
 116         rx_dma = xfer->rx_dma;
 117
 118         /* use scratch buffer only when rx or tx data is unspecified */
 119         if (rx_dma == INVALID_DMA_ADDRESS) {
 120                 rx_dma = as->buffer_dma;
 121                 if (len > BUFFER_SIZE)
 122                         len = BUFFER_SIZE;
 123         }
 124         if (tx_dma == INVALID_DMA_ADDRESS) {
 125                 tx_dma = as->buffer_dma;
 126                 if (len > BUFFER_SIZE)
 127                         len = BUFFER_SIZE;
 128                 memset(as->buffer, 0, len);
 129                 dma_sync_single_for_device(&as->pdev->dev,
 130                                 as->buffer_dma, len, DMA_TO_DEVICE);
 131         }
 132
 133         spi_writel(as, RPR, rx_dma);
 134         spi_writel(as, TPR, tx_dma);
 135
 136         as->remaining_bytes -= len;
 137         if (msg->spi->bits_per_word > 8)
 138                 len >>= 1;
 139
 140         /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
 141          * mechanism might help avoid the IRQ latency between transfers
 142          *
 143          * We're also waiting for ENDRX before we start the next
 144          * transfer because we need to handle some difficult timing
 145          * issues otherwise. If we wait for ENDTX in one transfer and
 146          * then starts waiting for ENDRX in the next, it's difficult
 147          * to tell the difference between the ENDRX interrupt we're
 148          * actually waiting for and the ENDRX interrupt of the
 149          * previous transfer.
 150          *
 151          * It should be doable, though. Just not now...
 152          */
 153         spi_writel(as, TNCR, 0);
 154         spi_writel(as, RNCR, 0);
 155         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 156
 157         dev_dbg(&msg->spi->dev,
 158                 "  start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
 159                 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 160                 xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
 161
 162         spi_writel(as, TCR, len);
 163         spi_writel(as, RCR, len);
 164         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 165 }
 166
 167 static void atmel_spi_next_message(struct spi_master *master)
 168 {
 169         struct atmel_spi        *as = spi_master_get_devdata(master);
 170         struct spi_message      *msg;
 171         u32                     mr;
 172
 173         BUG_ON(as->current_transfer);
 174
 175         msg = list_entry(as->queue.next, struct spi_message, queue);
 176
 177         /* Select the chip */
 178         mr = spi_readl(as, MR);
 179         mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
 180         spi_writel(as, MR, mr);
 181         cs_activate(msg->spi);
 182
 183         atmel_spi_next_xfer(master, msg);
 184 }
 185
 186 static void
 187 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 188 {
 189         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 190         if (xfer->tx_buf)
 191                 xfer->tx_dma = dma_map_single(&as->pdev->dev,
 192                                 (void *) xfer->tx_buf, xfer->len,
 193                                 DMA_TO_DEVICE);
 194         if (xfer->rx_buf)
 195                 xfer->rx_dma = dma_map_single(&as->pdev->dev,
 196                                 xfer->rx_buf, xfer->len,
 197                                 DMA_FROM_DEVICE);
 198 }
 199
 200 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 201                                      struct spi_transfer *xfer)
 202 {
 203         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 204                 dma_unmap_single(master->cdev.dev, xfer->tx_dma,
 205                                  xfer->len, DMA_TO_DEVICE);
 206         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 207                 dma_unmap_single(master->cdev.dev, xfer->rx_dma,
 208                                  xfer->len, DMA_FROM_DEVICE);
 209 }
 210
 211 static void
 212 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 213                    struct spi_message *msg, int status)
 214 {
 215         cs_deactivate(msg->spi);
 216         list_del(&msg->queue);
 217         msg->status = status;
 218
 219         dev_dbg(master->cdev.dev,
 220                 "xfer complete: %u bytes transferred\n",
 221                 msg->actual_length);
 222
 223         spin_unlock(&as->lock);
 224         msg->complete(msg->context);
 225         spin_lock(&as->lock);
 226
 227         as->current_transfer = NULL;
 228
 229         /* continue if needed */
 230         if (list_empty(&as->queue) || as->stopping)
 231                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 232         else
 233                 atmel_spi_next_message(master);
 234 }
 235
 236 static irqreturn_t
 237 atmel_spi_interrupt(int irq, void *dev_id)
 238 {
 239         struct spi_master       *master = dev_id;
 240         struct atmel_spi        *as = spi_master_get_devdata(master);
 241         struct spi_message      *msg;
 242         struct spi_transfer     *xfer;
 243         u32                     status, pending, imr;
 244         int                     ret = IRQ_NONE;
 245
 246         spin_lock(&as->lock);
 247
 248         xfer = as->current_transfer;
 249         msg = list_entry(as->queue.next, struct spi_message, queue);
 250
 251         imr = spi_readl(as, IMR);
 252         status = spi_readl(as, SR);
 253         pending = status & imr;
 254
 255         if (pending & SPI_BIT(OVRES)) {
 256                 int timeout;
 257
 258                 ret = IRQ_HANDLED;
 259
 260                 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
 261                                      | SPI_BIT(OVRES)));
 262
 263                 /*
 264                  * When we get an overrun, we disregard the current
 265                  * transfer. Data will not be copied back from any
 266                  * bounce buffer and msg->actual_len will not be
 267                  * updated with the last xfer.
 268                  *
 269                  * We will also not process any remaning transfers in
 270                  * the message.
 271                  *
 272                  * First, stop the transfer and unmap the DMA buffers.
 273                  */
 274                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 275                 if (!msg->is_dma_mapped)
 276                         atmel_spi_dma_unmap_xfer(master, xfer);
 277
 278                 /* REVISIT: udelay in irq is unfriendly */
 279                 if (xfer->delay_usecs)
 280                         udelay(xfer->delay_usecs);
 281
 282                 dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n",
 283                          spi_readl(as, TCR), spi_readl(as, RCR));
 284
 285                 /*
 286                  * Clean up DMA registers and make sure the data
 287                  * registers are empty.
 288                  */
 289                 spi_writel(as, RNCR, 0);
 290                 spi_writel(as, TNCR, 0);
 291                 spi_writel(as, RCR, 0);
 292                 spi_writel(as, TCR, 0);
 293                 for (timeout = 1000; timeout; timeout--)
 294                         if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
 295                                 break;
 296                 if (!timeout)
 297                         dev_warn(master->cdev.dev,
 298                                  "timeout waiting for TXEMPTY");
 299                 while (spi_readl(as, SR) & SPI_BIT(RDRF))
 300                         spi_readl(as, RDR);
 301
 302                 /* Clear any overrun happening while cleaning up */
 303                 spi_readl(as, SR);
 304
 305                 atmel_spi_msg_done(master, as, msg, -EIO);
 306         } else if (pending & SPI_BIT(ENDRX)) {
 307                 ret = IRQ_HANDLED;
 308
 309                 spi_writel(as, IDR, pending);
 310
 311                 if (as->remaining_bytes == 0) {
 312                         msg->actual_length += xfer->len;
 313
 314                         if (!msg->is_dma_mapped)
 315                                 atmel_spi_dma_unmap_xfer(master, xfer);
 316
 317                         /* REVISIT: udelay in irq is unfriendly */
 318                         if (xfer->delay_usecs)
 319                                 udelay(xfer->delay_usecs);
 320
 321                         if (msg->transfers.prev == &xfer->transfer_list) {
 322                                 /* report completed message */
 323                                 atmel_spi_msg_done(master, as, msg, 0);
 324                         } else {
 325                                 if (xfer->cs_change) {
 326                                         cs_deactivate(msg->spi);
 327                                         udelay(1);
 328                                         cs_activate(msg->spi);
 329                                 }
 330
 331                                 /*
 332                                  * Not done yet. Submit the next transfer.
 333                                  *
 334                                  * FIXME handle protocol options for xfer
 335                                  */
 336                                 atmel_spi_next_xfer(master, msg);
 337                         }
 338                 } else {
 339                         /*
 340                          * Keep going, we still have data to send in
 341                          * the current transfer.
 342                          */
 343                         atmel_spi_next_xfer(master, msg);
 344                 }
 345         }
 346
 347         spin_unlock(&as->lock);
 348
 349         return ret;
 350 }
 351
 352 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 353
 354 static int atmel_spi_setup(struct spi_device *spi)
 355 {
 356         struct atmel_spi        *as;
 357         u32                     scbr, csr;
 358         unsigned int            bits = spi->bits_per_word;
 359         unsigned long           bus_hz, sck_hz;
 360         unsigned int            npcs_pin;
 361         int                     ret;
 362
 363         as = spi_master_get_devdata(spi->master);
 364
 365         if (as->stopping)
 366                 return -ESHUTDOWN;
 367
 368         if (spi->chip_select > spi->master->num_chipselect) {
 369                 dev_dbg(&spi->dev,
 370                                 "setup: invalid chipselect %u (%u defined)\n",
 371                                 spi->chip_select, spi->master->num_chipselect);
 372                 return -EINVAL;
 373         }
 374
 375         if (bits == 0)
 376                 bits = 8;
 377         if (bits < 8 || bits > 16) {
 378                 dev_dbg(&spi->dev,
 379                                 "setup: invalid bits_per_word %u (8 to 16)\n",
 380                                 bits);
 381                 return -EINVAL;
 382         }
 383
 384         if (spi->mode & ~MODEBITS) {
 385                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 386                         spi->mode & ~MODEBITS);
 387                 return -EINVAL;
 388         }
 389
 390         /* speed zero convention is used by some upper layers */
 391         bus_hz = clk_get_rate(as->clk);
 392         if (spi->max_speed_hz) {
 393                 /* assume div32/fdiv/mbz == 0 */
 394                 if (!as->new_1)
 395                         bus_hz /= 2;
 396                 scbr = ((bus_hz + spi->max_speed_hz - 1)
 397                         / spi->max_speed_hz);
 398                 if (scbr >= (1 << SPI_SCBR_SIZE)) {
 399                         dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
 400                                         spi->max_speed_hz, scbr);
 401                         return -EINVAL;
 402                 }
 403         } else
 404                 scbr = 0xff;
 405         sck_hz = bus_hz / scbr;
 406
 407         csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
 408         if (spi->mode & SPI_CPOL)
 409                 csr |= SPI_BIT(CPOL);
 410         if (!(spi->mode & SPI_CPHA))
 411                 csr |= SPI_BIT(NCPHA);
 412
 413         /* TODO: DLYBS and DLYBCT */
 414         csr |= SPI_BF(DLYBS, 10);
 415         csr |= SPI_BF(DLYBCT, 10);
 416
 417         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
 418         npcs_pin = (unsigned int)spi->controller_data;
 419         if (!spi->controller_state) {
 420                 ret = gpio_request(npcs_pin, "spi_npcs");
 421                 if (ret)
 422                         return ret;
 423                 spi->controller_state = (void *)npcs_pin;
 424                 gpio_direction_output(npcs_pin);
 425         }
 426
 427         dev_dbg(&spi->dev,
 428                 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 429                 sck_hz, bits, spi->mode, spi->chip_select, csr);
 430
 431         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 432
 433         return 0;
 434 }
 435
 436 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 437 {
 438         struct atmel_spi        *as;
 439         struct spi_transfer     *xfer;
 440         unsigned long           flags;
 441         struct device           *controller = spi->master->cdev.dev;
 442
 443         as = spi_master_get_devdata(spi->master);
 444
 445         dev_dbg(controller, "new message %p submitted for %s\n",
 446                         msg, spi->dev.bus_id);
 447
 448         if (unlikely(list_empty(&msg->transfers)
 449                         || !spi->max_speed_hz))
 450                 return -EINVAL;
 451
 452         if (as->stopping)
 453                 return -ESHUTDOWN;
 454
 455         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 456                 if (!(xfer->tx_buf || xfer->rx_buf)) {
 457                         dev_dbg(&spi->dev, "missing rx or tx buf\n");
 458                         return -EINVAL;
 459                 }
 460
 461                 /* FIXME implement these protocol options!! */
 462                 if (xfer->bits_per_word || xfer->speed_hz) {
 463                         dev_dbg(&spi->dev, "no protocol options yet\n");
 464                         return -ENOPROTOOPT;
 465                 }
 466         }
 467
 468         /* scrub dcache "early" */
 469         if (!msg->is_dma_mapped) {
 470                 list_for_each_entry(xfer, &msg->transfers, transfer_list)
 471                         atmel_spi_dma_map_xfer(as, xfer);
 472         }
 473
 474         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 475                 dev_dbg(controller,
 476                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 477                         xfer, xfer->len,
 478                         xfer->tx_buf, xfer->tx_dma,
 479                         xfer->rx_buf, xfer->rx_dma);
 480         }
 481
 482         msg->status = -EINPROGRESS;
 483         msg->actual_length = 0;
 484
 485         spin_lock_irqsave(&as->lock, flags);
 486         list_add_tail(&msg->queue, &as->queue);
 487         if (!as->current_transfer)
 488                 atmel_spi_next_message(spi->master);
 489         spin_unlock_irqrestore(&as->lock, flags);
 490
 491         return 0;
 492 }
 493
 494 static void atmel_spi_cleanup(const struct spi_device *spi)
 495 {
 496         if (spi->controller_state)
 497                 gpio_free((unsigned int)spi->controller_data);
 498 }
 499
 500 /*-------------------------------------------------------------------------*/
 501
 502 static int __init atmel_spi_probe(struct platform_device *pdev)
 503 {
 504         struct resource         *regs;
 505         int                     irq;
 506         struct clk              *clk;
 507         int                     ret;
 508         struct spi_master       *master;
 509         struct atmel_spi        *as;
 510
 511         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 512         if (!regs)
 513                 return -ENXIO;
 514
 515         irq = platform_get_irq(pdev, 0);
 516         if (irq < 0)
 517                 return irq;
 518
 519         clk = clk_get(&pdev->dev, "spi_clk");
 520         if (IS_ERR(clk))
 521                 return PTR_ERR(clk);
 522
 523         /* setup spi core then atmel-specific driver state */
 524         ret = -ENOMEM;
 525         master = spi_alloc_master(&pdev->dev, sizeof *as);
 526         if (!master)
 527                 goto out_free;
 528
 529         master->bus_num = pdev->id;
 530         master->num_chipselect = 4;
 531         master->setup = atmel_spi_setup;
 532         master->transfer = atmel_spi_transfer;
 533         master->cleanup = atmel_spi_cleanup;
 534         platform_set_drvdata(pdev, master);
 535
 536         as = spi_master_get_devdata(master);
 537
 538         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 539                                         &as->buffer_dma, GFP_KERNEL);
 540         if (!as->buffer)
 541                 goto out_free;
 542
 543         spin_lock_init(&as->lock);
 544         INIT_LIST_HEAD(&as->queue);
 545         as->pdev = pdev;
 546         as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 547         if (!as->regs)
 548                 goto out_free_buffer;
 549         as->irq = irq;
 550         as->clk = clk;
 551 #ifdef CONFIG_ARCH_AT91
 552         if (!cpu_is_at91rm9200())
 553                 as->new_1 = 1;
 554 #endif
 555
 556         ret = request_irq(irq, atmel_spi_interrupt, 0,
 557                         pdev->dev.bus_id, master);
 558         if (ret)
 559                 goto out_unmap_regs;
 560
 561         /* Initialize the hardware */
 562         clk_enable(clk);
 563         spi_writel(as, CR, SPI_BIT(SWRST));
 564         spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 565         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 566         spi_writel(as, CR, SPI_BIT(SPIEN));
 567
 568         /* go! */
 569         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 570                         (unsigned long)regs->start, irq);
 571
 572         ret = spi_register_master(master);
 573         if (ret)
 574                 goto out_reset_hw;
 575
 576         return 0;
 577
 578 out_reset_hw:
 579         spi_writel(as, CR, SPI_BIT(SWRST));
 580         clk_disable(clk);
 581         free_irq(irq, master);
 582 out_unmap_regs:
 583         iounmap(as->regs);
 584 out_free_buffer:
 585         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 586                         as->buffer_dma);
 587 out_free:
 588         clk_put(clk);
 589         spi_master_put(master);
 590         return ret;
 591 }
 592
 593 static int __exit atmel_spi_remove(struct platform_device *pdev)
 594 {
 595         struct spi_master       *master = platform_get_drvdata(pdev);
 596         struct atmel_spi        *as = spi_master_get_devdata(master);
 597         struct spi_message      *msg;
 598
 599         /* reset the hardware and block queue progress */
 600         spin_lock_irq(&as->lock);
 601         as->stopping = 1;
 602         spi_writel(as, CR, SPI_BIT(SWRST));
 603         spi_readl(as, SR);
 604         spin_unlock_irq(&as->lock);
 605
 606         /* Terminate remaining queued transfers */
 607         list_for_each_entry(msg, &as->queue, queue) {
 608                 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
 609                  * but we shouldn't depend on that...
 610                  */
 611                 msg->status = -ESHUTDOWN;
 612                 msg->complete(msg->context);
 613         }
 614
 615         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 616                         as->buffer_dma);
 617
 618         clk_disable(as->clk);
 619         clk_put(as->clk);
 620         free_irq(as->irq, master);
 621         iounmap(as->regs);
 622
 623         spi_unregister_master(master);
 624
 625         return 0;
 626 }
 627
 628 #ifdef  CONFIG_PM
 629
 630 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 631 {
 632         struct spi_master       *master = platform_get_drvdata(pdev);
 633         struct atmel_spi        *as = spi_master_get_devdata(master);
 634
 635         clk_disable(as->clk);
 636         return 0;
 637 }
 638
 639 static int atmel_spi_resume(struct platform_device *pdev)
 640 {
 641         struct spi_master       *master = platform_get_drvdata(pdev);
 642         struct atmel_spi        *as = spi_master_get_devdata(master);
 643
 644         clk_enable(as->clk);
 645         return 0;
 646 }
 647
 648 #else
 649 #define atmel_spi_suspend       NULL
 650 #define atmel_spi_resume        NULL
 651 #endif
 652
 653
 654 static struct platform_driver atmel_spi_driver = {
 655         .driver         = {
 656                 .name   = "atmel_spi",
 657                 .owner  = THIS_MODULE,
 658         },
 659         .suspend        = atmel_spi_suspend,
 660         .resume         = atmel_spi_resume,
 661         .remove         = __exit_p(atmel_spi_remove),
 662 };
 663
 664 static int __init atmel_spi_init(void)
 665 {
 666         return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
 667 }
 668 module_init(atmel_spi_init);
 669
 670 static void __exit atmel_spi_exit(void)
 671 {
 672         platform_driver_unregister(&atmel_spi_driver);
 673 }
 674 module_exit(atmel_spi_exit);
 675
 676 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
 677 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 678 MODULE_LICENSE("GPL");