drivers/spi/atmel_spi.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/arch/board.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/cpu.h>
  26
  27 #include "atmel_spi.h"
  28
  29 /*
  30  * The core SPI transfer engine just talks to a register bank to set up
  31  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
  32  * framework provides the base clock, subdivided for each spi_device.
  33  *
  34  * Newer controllers, marked with "new_1" flag, have:
  35  *  - CR.LASTXFER
  36  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  37  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  38  *  - SPI_CSRx.CSAAT
  39  *  - SPI_CSRx.SBCR allows faster clocking
  40  */
  41 struct atmel_spi {
  42         spinlock_t              lock;
  43
  44         void __iomem            *regs;
  45         int                     irq;
  46         struct clk              *clk;
  47         struct platform_device  *pdev;
  48         unsigned                new_1:1;
  49         struct spi_device       *stay;
  50
  51         u8                      stopping;
  52         struct list_head        queue;
  53         struct spi_transfer     *current_transfer;
  54         unsigned long           current_remaining_bytes;
  55         struct spi_transfer     *next_transfer;
  56         unsigned long           next_remaining_bytes;
  57
  58         void                    *buffer;
  59         dma_addr_t              buffer_dma;
  60 };
  61
  62 #define BUFFER_SIZE             PAGE_SIZE
  63 #define INVALID_DMA_ADDRESS     0xffffffff
  64
  65 /*
  66  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  67  * they assume that spi slave device state will not change on deselect, so
  68  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
  69  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
  70  * controllers have CSAAT and friends.
  71  *
  72  * Since the CSAAT functionality is a bit weird on newer controllers as
  73  * well, we use GPIO to control nCSx pins on all controllers, updating
  74  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
  75  * support active-high chipselects despite the controller's belief that
  76  * only active-low devices/systems exists.
  77  *
  78  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
  79  * right when driven with GPIO.  ("Mode Fault does not allow more than one
  80  * Master on Chip Select 0.")  No workaround exists for that ... so for
  81  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
  82  * and (c) will trigger that first erratum in some cases.
  83  */
  84
  85 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
  86 {
  87         unsigned gpio = (unsigned) spi->controller_data;
  88         unsigned active = spi->mode & SPI_CS_HIGH;
  89         u32 mr;
  90
  91         mr = spi_readl(as, MR);
  92         mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
  93
  94         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
  95                         gpio, active ? " (high)" : "",
  96                         mr);
  97
  98         if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
  99                 gpio_set_value(gpio, active);
 100         spi_writel(as, MR, mr);
 101 }
 102
 103 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 104 {
 105         unsigned gpio = (unsigned) spi->controller_data;
 106         unsigned active = spi->mode & SPI_CS_HIGH;
 107         u32 mr;
 108
 109         /* only deactivate *this* device; sometimes transfers to
 110          * another device may be active when this routine is called.
 111          */
 112         mr = spi_readl(as, MR);
 113         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 114                 mr = SPI_BFINS(PCS, 0xf, mr);
 115                 spi_writel(as, MR, mr);
 116         }
 117
 118         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 119                         gpio, active ? " (low)" : "",
 120                         mr);
 121
 122         if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
 123                 gpio_set_value(gpio, !active);
 124 }
 125
 126 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 127                                         struct spi_transfer *xfer)
 128 {
 129         return msg->transfers.prev == &xfer->transfer_list;
 130 }
 131
 132 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 133 {
 134         return xfer->delay_usecs == 0 && !xfer->cs_change;
 135 }
 136
 137 static void atmel_spi_next_xfer_data(struct spi_master *master,
 138                                 struct spi_transfer *xfer,
 139                                 dma_addr_t *tx_dma,
 140                                 dma_addr_t *rx_dma,
 141                                 u32 *plen)
 142 {
 143         struct atmel_spi        *as = spi_master_get_devdata(master);
 144         u32                     len = *plen;
 145
 146         /* use scratch buffer only when rx or tx data is unspecified */
 147         if (xfer->rx_buf)
 148                 *rx_dma = xfer->rx_dma + xfer->len - len;
 149         else {
 150                 *rx_dma = as->buffer_dma;
 151                 if (len > BUFFER_SIZE)
 152                         len = BUFFER_SIZE;
 153         }
 154         if (xfer->tx_buf)
 155                 *tx_dma = xfer->tx_dma + xfer->len - len;
 156         else {
 157                 *tx_dma = as->buffer_dma;
 158                 if (len > BUFFER_SIZE)
 159                         len = BUFFER_SIZE;
 160                 memset(as->buffer, 0, len);
 161                 dma_sync_single_for_device(&as->pdev->dev,
 162                                 as->buffer_dma, len, DMA_TO_DEVICE);
 163         }
 164
 165         *plen = len;
 166 }
 167
 168 /*
 169  * Submit next transfer for DMA.
 170  * lock is held, spi irq is blocked
 171  */
 172 static void atmel_spi_next_xfer(struct spi_master *master,
 173                                 struct spi_message *msg)
 174 {
 175         struct atmel_spi        *as = spi_master_get_devdata(master);
 176         struct spi_transfer     *xfer;
 177         u32                     len, remaining, total;
 178         dma_addr_t              tx_dma, rx_dma;
 179
 180         if (!as->current_transfer)
 181                 xfer = list_entry(msg->transfers.next,
 182                                 struct spi_transfer, transfer_list);
 183         else if (!as->next_transfer)
 184                 xfer = list_entry(as->current_transfer->transfer_list.next,
 185                                 struct spi_transfer, transfer_list);
 186         else
 187                 xfer = NULL;
 188
 189         if (xfer) {
 190                 len = xfer->len;
 191                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 192                 remaining = xfer->len - len;
 193
 194                 spi_writel(as, RPR, rx_dma);
 195                 spi_writel(as, TPR, tx_dma);
 196
 197                 if (msg->spi->bits_per_word > 8)
 198                         len >>= 1;
 199                 spi_writel(as, RCR, len);
 200                 spi_writel(as, TCR, len);
 201
 202                 dev_dbg(&msg->spi->dev,
 203                         "  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 204                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 205                         xfer->rx_buf, xfer->rx_dma);
 206         } else {
 207                 xfer = as->next_transfer;
 208                 remaining = as->next_remaining_bytes;
 209         }
 210
 211         as->current_transfer = xfer;
 212         as->current_remaining_bytes = remaining;
 213
 214         if (remaining > 0)
 215                 len = remaining;
 216         else if (!atmel_spi_xfer_is_last(msg, xfer)
 217                         && atmel_spi_xfer_can_be_chained(xfer)) {
 218                 xfer = list_entry(xfer->transfer_list.next,
 219                                 struct spi_transfer, transfer_list);
 220                 len = xfer->len;
 221         } else
 222                 xfer = NULL;
 223
 224         as->next_transfer = xfer;
 225
 226         if (xfer) {
 227                 total = len;
 228                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 229                 as->next_remaining_bytes = total - len;
 230
 231                 spi_writel(as, RNPR, rx_dma);
 232                 spi_writel(as, TNPR, tx_dma);
 233
 234                 if (msg->spi->bits_per_word > 8)
 235                         len >>= 1;
 236                 spi_writel(as, RNCR, len);
 237                 spi_writel(as, TNCR, len);
 238
 239                 dev_dbg(&msg->spi->dev,
 240                         "  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 241                         xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 242                         xfer->rx_buf, xfer->rx_dma);
 243         } else {
 244                 spi_writel(as, RNCR, 0);
 245                 spi_writel(as, TNCR, 0);
 246         }
 247
 248         /* REVISIT: We're waiting for ENDRX before we start the next
 249          * transfer because we need to handle some difficult timing
 250          * issues otherwise. If we wait for ENDTX in one transfer and
 251          * then starts waiting for ENDRX in the next, it's difficult
 252          * to tell the difference between the ENDRX interrupt we're
 253          * actually waiting for and the ENDRX interrupt of the
 254          * previous transfer.
 255          *
 256          * It should be doable, though. Just not now...
 257          */
 258         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 259         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 260 }
 261
 262 static void atmel_spi_next_message(struct spi_master *master)
 263 {
 264         struct atmel_spi        *as = spi_master_get_devdata(master);
 265         struct spi_message      *msg;
 266         struct spi_device       *spi;
 267
 268         BUG_ON(as->current_transfer);
 269
 270         msg = list_entry(as->queue.next, struct spi_message, queue);
 271         spi = msg->spi;
 272
 273         dev_dbg(master->dev.parent, "start message %p for %s\n",
 274                         msg, spi->dev.bus_id);
 275
 276         /* select chip if it's not still active */
 277         if (as->stay) {
 278                 if (as->stay != spi) {
 279                         cs_deactivate(as, as->stay);
 280                         cs_activate(as, spi);
 281                 }
 282                 as->stay = NULL;
 283         } else
 284                 cs_activate(as, spi);
 285
 286         atmel_spi_next_xfer(master, msg);
 287 }
 288
 289 /*
 290  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 291  *  - The buffer is either valid for CPU access, else NULL
 292  *  - If the buffer is valid, so is its DMA addresss
 293  *
 294  * This driver manages the dma addresss unless message->is_dma_mapped.
 295  */
 296 static int
 297 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 298 {
 299         struct device   *dev = &as->pdev->dev;
 300
 301         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 302         if (xfer->tx_buf) {
 303                 xfer->tx_dma = dma_map_single(dev,
 304                                 (void *) xfer->tx_buf, xfer->len,
 305                                 DMA_TO_DEVICE);
 306                 if (dma_mapping_error(xfer->tx_dma))
 307                         return -ENOMEM;
 308         }
 309         if (xfer->rx_buf) {
 310                 xfer->rx_dma = dma_map_single(dev,
 311                                 xfer->rx_buf, xfer->len,
 312                                 DMA_FROM_DEVICE);
 313                 if (dma_mapping_error(xfer->rx_dma)) {
 314                         if (xfer->tx_buf)
 315                                 dma_unmap_single(dev,
 316                                                 xfer->tx_dma, xfer->len,
 317                                                 DMA_TO_DEVICE);
 318                         return -ENOMEM;
 319                 }
 320         }
 321         return 0;
 322 }
 323
 324 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 325                                      struct spi_transfer *xfer)
 326 {
 327         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 328                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 329                                  xfer->len, DMA_TO_DEVICE);
 330         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 331                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 332                                  xfer->len, DMA_FROM_DEVICE);
 333 }
 334
 335 static void
 336 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 337                 struct spi_message *msg, int status, int stay)
 338 {
 339         if (!stay || status < 0)
 340                 cs_deactivate(as, msg->spi);
 341         else
 342                 as->stay = msg->spi;
 343
 344         list_del(&msg->queue);
 345         msg->status = status;
 346
 347         dev_dbg(master->dev.parent,
 348                 "xfer complete: %u bytes transferred\n",
 349                 msg->actual_length);
 350
 351         spin_unlock(&as->lock);
 352         msg->complete(msg->context);
 353         spin_lock(&as->lock);
 354
 355         as->current_transfer = NULL;
 356         as->next_transfer = NULL;
 357
 358         /* continue if needed */
 359         if (list_empty(&as->queue) || as->stopping)
 360                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 361         else
 362                 atmel_spi_next_message(master);
 363 }
 364
 365 static irqreturn_t
 366 atmel_spi_interrupt(int irq, void *dev_id)
 367 {
 368         struct spi_master       *master = dev_id;
 369         struct atmel_spi        *as = spi_master_get_devdata(master);
 370         struct spi_message      *msg;
 371         struct spi_transfer     *xfer;
 372         u32                     status, pending, imr;
 373         int                     ret = IRQ_NONE;
 374
 375         spin_lock(&as->lock);
 376
 377         xfer = as->current_transfer;
 378         msg = list_entry(as->queue.next, struct spi_message, queue);
 379
 380         imr = spi_readl(as, IMR);
 381         status = spi_readl(as, SR);
 382         pending = status & imr;
 383
 384         if (pending & SPI_BIT(OVRES)) {
 385                 int timeout;
 386
 387                 ret = IRQ_HANDLED;
 388
 389                 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
 390                                      | SPI_BIT(OVRES)));
 391
 392                 /*
 393                  * When we get an overrun, we disregard the current
 394                  * transfer. Data will not be copied back from any
 395                  * bounce buffer and msg->actual_len will not be
 396                  * updated with the last xfer.
 397                  *
 398                  * We will also not process any remaning transfers in
 399                  * the message.
 400                  *
 401                  * First, stop the transfer and unmap the DMA buffers.
 402                  */
 403                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 404                 if (!msg->is_dma_mapped)
 405                         atmel_spi_dma_unmap_xfer(master, xfer);
 406
 407                 /* REVISIT: udelay in irq is unfriendly */
 408                 if (xfer->delay_usecs)
 409                         udelay(xfer->delay_usecs);
 410
 411                 dev_warn(master->dev.parent, "fifo overrun (%u/%u remaining)\n",
 412                          spi_readl(as, TCR), spi_readl(as, RCR));
 413
 414                 /*
 415                  * Clean up DMA registers and make sure the data
 416                  * registers are empty.
 417                  */
 418                 spi_writel(as, RNCR, 0);
 419                 spi_writel(as, TNCR, 0);
 420                 spi_writel(as, RCR, 0);
 421                 spi_writel(as, TCR, 0);
 422                 for (timeout = 1000; timeout; timeout--)
 423                         if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
 424                                 break;
 425                 if (!timeout)
 426                         dev_warn(master->dev.parent,
 427                                  "timeout waiting for TXEMPTY");
 428                 while (spi_readl(as, SR) & SPI_BIT(RDRF))
 429                         spi_readl(as, RDR);
 430
 431                 /* Clear any overrun happening while cleaning up */
 432                 spi_readl(as, SR);
 433
 434                 atmel_spi_msg_done(master, as, msg, -EIO, 0);
 435         } else if (pending & SPI_BIT(ENDRX)) {
 436                 ret = IRQ_HANDLED;
 437
 438                 spi_writel(as, IDR, pending);
 439
 440                 if (as->current_remaining_bytes == 0) {
 441                         msg->actual_length += xfer->len;
 442
 443                         if (!msg->is_dma_mapped)
 444                                 atmel_spi_dma_unmap_xfer(master, xfer);
 445
 446                         /* REVISIT: udelay in irq is unfriendly */
 447                         if (xfer->delay_usecs)
 448                                 udelay(xfer->delay_usecs);
 449
 450                         if (atmel_spi_xfer_is_last(msg, xfer)) {
 451                                 /* report completed message */
 452                                 atmel_spi_msg_done(master, as, msg, 0,
 453                                                 xfer->cs_change);
 454                         } else {
 455                                 if (xfer->cs_change) {
 456                                         cs_deactivate(as, msg->spi);
 457                                         udelay(1);
 458                                         cs_activate(as, msg->spi);
 459                                 }
 460
 461                                 /*
 462                                  * Not done yet. Submit the next transfer.
 463                                  *
 464                                  * FIXME handle protocol options for xfer
 465                                  */
 466                                 atmel_spi_next_xfer(master, msg);
 467                         }
 468                 } else {
 469                         /*
 470                          * Keep going, we still have data to send in
 471                          * the current transfer.
 472                          */
 473                         atmel_spi_next_xfer(master, msg);
 474                 }
 475         }
 476
 477         spin_unlock(&as->lock);
 478
 479         return ret;
 480 }
 481
 482 /* the spi->mode bits understood by this driver: */
 483 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 484
 485 static int atmel_spi_setup(struct spi_device *spi)
 486 {
 487         struct atmel_spi        *as;
 488         u32                     scbr, csr;
 489         unsigned int            bits = spi->bits_per_word;
 490         unsigned long           bus_hz, sck_hz;
 491         unsigned int            npcs_pin;
 492         int                     ret;
 493
 494         as = spi_master_get_devdata(spi->master);
 495
 496         if (as->stopping)
 497                 return -ESHUTDOWN;
 498
 499         if (spi->chip_select > spi->master->num_chipselect) {
 500                 dev_dbg(&spi->dev,
 501                                 "setup: invalid chipselect %u (%u defined)\n",
 502                                 spi->chip_select, spi->master->num_chipselect);
 503                 return -EINVAL;
 504         }
 505
 506         if (bits == 0)
 507                 bits = 8;
 508         if (bits < 8 || bits > 16) {
 509                 dev_dbg(&spi->dev,
 510                                 "setup: invalid bits_per_word %u (8 to 16)\n",
 511                                 bits);
 512                 return -EINVAL;
 513         }
 514
 515         if (spi->mode & ~MODEBITS) {
 516                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 517                         spi->mode & ~MODEBITS);
 518                 return -EINVAL;
 519         }
 520
 521         /* see notes above re chipselect */
 522         if (cpu_is_at91rm9200()
 523                         && spi->chip_select == 0
 524                         && (spi->mode & SPI_CS_HIGH)) {
 525                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 526                 return -EINVAL;
 527         }
 528
 529         /* speed zero convention is used by some upper layers */
 530         bus_hz = clk_get_rate(as->clk);
 531         if (spi->max_speed_hz) {
 532                 /* assume div32/fdiv/mbz == 0 */
 533                 if (!as->new_1)
 534                         bus_hz /= 2;
 535                 scbr = ((bus_hz + spi->max_speed_hz - 1)
 536                         / spi->max_speed_hz);
 537                 if (scbr >= (1 << SPI_SCBR_SIZE)) {
 538                         dev_dbg(&spi->dev,
 539                                 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 540                                 spi->max_speed_hz, scbr, bus_hz/255);
 541                         return -EINVAL;
 542                 }
 543         } else
 544                 scbr = 0xff;
 545         sck_hz = bus_hz / scbr;
 546
 547         csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
 548         if (spi->mode & SPI_CPOL)
 549                 csr |= SPI_BIT(CPOL);
 550         if (!(spi->mode & SPI_CPHA))
 551                 csr |= SPI_BIT(NCPHA);
 552
 553         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
 554          *
 555          * DLYBCT would add delays between words, slowing down transfers.
 556          * It could potentially be useful to cope with DMA bottlenecks, but
 557          * in those cases it's probably best to just use a lower bitrate.
 558          */
 559         csr |= SPI_BF(DLYBS, 0);
 560         csr |= SPI_BF(DLYBCT, 0);
 561
 562         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
 563         npcs_pin = (unsigned int)spi->controller_data;
 564         if (!spi->controller_state) {
 565                 ret = gpio_request(npcs_pin, spi->dev.bus_id);
 566                 if (ret)
 567                         return ret;
 568                 spi->controller_state = (void *)npcs_pin;
 569                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 570         } else {
 571                 unsigned long           flags;
 572
 573                 spin_lock_irqsave(&as->lock, flags);
 574                 if (as->stay == spi)
 575                         as->stay = NULL;
 576                 cs_deactivate(as, spi);
 577                 spin_unlock_irqrestore(&as->lock, flags);
 578         }
 579
 580         dev_dbg(&spi->dev,
 581                 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 582                 sck_hz, bits, spi->mode, spi->chip_select, csr);
 583
 584         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 585
 586         return 0;
 587 }
 588
 589 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 590 {
 591         struct atmel_spi        *as;
 592         struct spi_transfer     *xfer;
 593         unsigned long           flags;
 594         struct device           *controller = spi->master->dev.parent;
 595
 596         as = spi_master_get_devdata(spi->master);
 597
 598         dev_dbg(controller, "new message %p submitted for %s\n",
 599                         msg, spi->dev.bus_id);
 600
 601         if (unlikely(list_empty(&msg->transfers)
 602                         || !spi->max_speed_hz))
 603                 return -EINVAL;
 604
 605         if (as->stopping)
 606                 return -ESHUTDOWN;
 607
 608         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 609                 if (!(xfer->tx_buf || xfer->rx_buf)) {
 610                         dev_dbg(&spi->dev, "missing rx or tx buf\n");
 611                         return -EINVAL;
 612                 }
 613
 614                 /* FIXME implement these protocol options!! */
 615                 if (xfer->bits_per_word || xfer->speed_hz) {
 616                         dev_dbg(&spi->dev, "no protocol options yet\n");
 617                         return -ENOPROTOOPT;
 618                 }
 619
 620                 /*
 621                  * DMA map early, for performance (empties dcache ASAP) and
 622                  * better fault reporting.  This is a DMA-only driver.
 623                  *
 624                  * NOTE that if dma_unmap_single() ever starts to do work on
 625                  * platforms supported by this driver, we would need to clean
 626                  * up mappings for previously-mapped transfers.
 627                  */
 628                 if (!msg->is_dma_mapped) {
 629                         if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 630                                 return -ENOMEM;
 631                 }
 632         }
 633
 634 #ifdef VERBOSE
 635         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 636                 dev_dbg(controller,
 637                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 638                         xfer, xfer->len,
 639                         xfer->tx_buf, xfer->tx_dma,
 640                         xfer->rx_buf, xfer->rx_dma);
 641         }
 642 #endif
 643
 644         msg->status = -EINPROGRESS;
 645         msg->actual_length = 0;
 646
 647         spin_lock_irqsave(&as->lock, flags);
 648         list_add_tail(&msg->queue, &as->queue);
 649         if (!as->current_transfer)
 650                 atmel_spi_next_message(spi->master);
 651         spin_unlock_irqrestore(&as->lock, flags);
 652
 653         return 0;
 654 }
 655
 656 static void atmel_spi_cleanup(struct spi_device *spi)
 657 {
 658         struct atmel_spi        *as = spi_master_get_devdata(spi->master);
 659         unsigned                gpio = (unsigned) spi->controller_data;
 660         unsigned long           flags;
 661
 662         if (!spi->controller_state)
 663                 return;
 664
 665         spin_lock_irqsave(&as->lock, flags);
 666         if (as->stay == spi) {
 667                 as->stay = NULL;
 668                 cs_deactivate(as, spi);
 669         }
 670         spin_unlock_irqrestore(&as->lock, flags);
 671
 672         gpio_free(gpio);
 673 }
 674
 675 /*-------------------------------------------------------------------------*/
 676
 677 static int __init atmel_spi_probe(struct platform_device *pdev)
 678 {
 679         struct resource         *regs;
 680         int                     irq;
 681         struct clk              *clk;
 682         int                     ret;
 683         struct spi_master       *master;
 684         struct atmel_spi        *as;
 685
 686         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 687         if (!regs)
 688                 return -ENXIO;
 689
 690         irq = platform_get_irq(pdev, 0);
 691         if (irq < 0)
 692                 return irq;
 693
 694         clk = clk_get(&pdev->dev, "spi_clk");
 695         if (IS_ERR(clk))
 696                 return PTR_ERR(clk);
 697
 698         /* setup spi core then atmel-specific driver state */
 699         ret = -ENOMEM;
 700         master = spi_alloc_master(&pdev->dev, sizeof *as);
 701         if (!master)
 702                 goto out_free;
 703
 704         master->bus_num = pdev->id;
 705         master->num_chipselect = 4;
 706         master->setup = atmel_spi_setup;
 707         master->transfer = atmel_spi_transfer;
 708         master->cleanup = atmel_spi_cleanup;
 709         platform_set_drvdata(pdev, master);
 710
 711         as = spi_master_get_devdata(master);
 712
 713         /*
 714          * Scratch buffer is used for throwaway rx and tx data.
 715          * It's coherent to minimize dcache pollution.
 716          */
 717         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 718                                         &as->buffer_dma, GFP_KERNEL);
 719         if (!as->buffer)
 720                 goto out_free;
 721
 722         spin_lock_init(&as->lock);
 723         INIT_LIST_HEAD(&as->queue);
 724         as->pdev = pdev;
 725         as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 726         if (!as->regs)
 727                 goto out_free_buffer;
 728         as->irq = irq;
 729         as->clk = clk;
 730         if (!cpu_is_at91rm9200())
 731                 as->new_1 = 1;
 732
 733         ret = request_irq(irq, atmel_spi_interrupt, 0,
 734                         pdev->dev.bus_id, master);
 735         if (ret)
 736                 goto out_unmap_regs;
 737
 738         /* Initialize the hardware */
 739         clk_enable(clk);
 740         spi_writel(as, CR, SPI_BIT(SWRST));
 741         spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 742         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 743         spi_writel(as, CR, SPI_BIT(SPIEN));
 744
 745         /* go! */
 746         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 747                         (unsigned long)regs->start, irq);
 748
 749         ret = spi_register_master(master);
 750         if (ret)
 751                 goto out_reset_hw;
 752
 753         return 0;
 754
 755 out_reset_hw:
 756         spi_writel(as, CR, SPI_BIT(SWRST));
 757         clk_disable(clk);
 758         free_irq(irq, master);
 759 out_unmap_regs:
 760         iounmap(as->regs);
 761 out_free_buffer:
 762         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 763                         as->buffer_dma);
 764 out_free:
 765         clk_put(clk);
 766         spi_master_put(master);
 767         return ret;
 768 }
 769
 770 static int __exit atmel_spi_remove(struct platform_device *pdev)
 771 {
 772         struct spi_master       *master = platform_get_drvdata(pdev);
 773         struct atmel_spi        *as = spi_master_get_devdata(master);
 774         struct spi_message      *msg;
 775
 776         /* reset the hardware and block queue progress */
 777         spin_lock_irq(&as->lock);
 778         as->stopping = 1;
 779         spi_writel(as, CR, SPI_BIT(SWRST));
 780         spi_readl(as, SR);
 781         spin_unlock_irq(&as->lock);
 782
 783         /* Terminate remaining queued transfers */
 784         list_for_each_entry(msg, &as->queue, queue) {
 785                 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
 786                  * but we shouldn't depend on that...
 787                  */
 788                 msg->status = -ESHUTDOWN;
 789                 msg->complete(msg->context);
 790         }
 791
 792         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 793                         as->buffer_dma);
 794
 795         clk_disable(as->clk);
 796         clk_put(as->clk);
 797         free_irq(as->irq, master);
 798         iounmap(as->regs);
 799
 800         spi_unregister_master(master);
 801
 802         return 0;
 803 }
 804
 805 #ifdef  CONFIG_PM
 806
 807 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 808 {
 809         struct spi_master       *master = platform_get_drvdata(pdev);
 810         struct atmel_spi        *as = spi_master_get_devdata(master);
 811
 812         clk_disable(as->clk);
 813         return 0;
 814 }
 815
 816 static int atmel_spi_resume(struct platform_device *pdev)
 817 {
 818         struct spi_master       *master = platform_get_drvdata(pdev);
 819         struct atmel_spi        *as = spi_master_get_devdata(master);
 820
 821         clk_enable(as->clk);
 822         return 0;
 823 }
 824
 825 #else
 826 #define atmel_spi_suspend       NULL
 827 #define atmel_spi_resume        NULL
 828 #endif
 829
 830
 831 static struct platform_driver atmel_spi_driver = {
 832         .driver         = {
 833                 .name   = "atmel_spi",
 834                 .owner  = THIS_MODULE,
 835         },
 836         .suspend        = atmel_spi_suspend,
 837         .resume         = atmel_spi_resume,
 838         .remove         = __exit_p(atmel_spi_remove),
 839 };
 840
 841 static int __init atmel_spi_init(void)
 842 {
 843         return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
 844 }
 845 module_init(atmel_spi_init);
 846
 847 static void __exit atmel_spi_exit(void)
 848 {
 849         platform_driver_unregister(&atmel_spi_driver);
 850 }
 851 module_exit(atmel_spi_exit);
 852
 853 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
 854 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 855 MODULE_LICENSE("GPL");