1 /* linux/drivers/serial/s3c2410.c
3 * Driver for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 /* Note on 2440 fclk clock source handling
15 * Whilst it is possible to use the fclk as clock source, the method
16 * of properly switching too/from this is currently un-implemented, so
17 * whichever way is configured at startup is the one that will be used.
20 /* Hote on 2410 error handling
22 * The s3c2410 manual has a love/hate affair with the contents of the
23 * UERSTAT register in the UART blocks, and keeps marking some of the
24 * error bits as reserved. Having checked with the s3c2410x01,
25 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
26 * feature from the latter versions of the manual.
28 * If it becomes aparrent that latter versions of the 2410 remove these
29 * bits, then action will have to be taken to differentiate the versions
30 * and change the policy on BREAK
36 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/platform_device.h>
43 #include <linux/init.h>
44 #include <linux/sysrq.h>
45 #include <linux/console.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50 #include <linux/delay.h>
51 #include <linux/clk.h>
56 #include <asm/hardware.h>
58 #include <asm/plat-s3c/regs-serial.h>
59 #include <asm/arch/regs-gpio.h>
63 struct s3c24xx_uart_info {
66 unsigned int fifosize;
67 unsigned long rx_fifomask;
68 unsigned long rx_fifoshift;
69 unsigned long rx_fifofull;
70 unsigned long tx_fifomask;
71 unsigned long tx_fifoshift;
72 unsigned long tx_fifofull;
74 /* clock source control */
76 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
77 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
80 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
83 struct s3c24xx_uart_port {
84 unsigned char rx_claimed;
85 unsigned char tx_claimed;
87 struct s3c24xx_uart_info *info;
88 struct s3c24xx_uart_clksrc *clksrc;
91 struct uart_port port;
95 /* configuration defines */
99 /* send debug to the low-level output routines */
101 extern void printascii(const char *);
104 s3c24xx_serial_dbg(const char *fmt, ...)
110 vsprintf(buff, fmt, va);
116 #define dbg(x...) s3c24xx_serial_dbg(x)
119 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
122 #define dbg(x...) do {} while(0)
125 /* UART name and device definitions */
127 #define S3C24XX_SERIAL_NAME "ttySAC"
128 #define S3C24XX_SERIAL_MAJOR 204
129 #define S3C24XX_SERIAL_MINOR 64
132 /* conversion functions */
134 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
135 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
137 /* we can support 3 uarts, but not always use them */
139 #ifdef CONFIG_CPU_S3C2400
145 /* port irq numbers */
147 #define TX_IRQ(port) ((port)->irq + 1)
148 #define RX_IRQ(port) ((port)->irq)
150 /* register access controls */
152 #define portaddr(port, reg) ((port)->membase + (reg))
154 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
155 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
157 #define wr_regb(port, reg, val) \
158 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
160 #define wr_regl(port, reg, val) \
161 do { __raw_writel(val, portaddr(port, reg)); } while(0)
163 /* macros to change one thing to another */
165 #define tx_enabled(port) ((port)->unused[0])
166 #define rx_enabled(port) ((port)->unused[1])
168 /* flag to ignore all characters comming in */
169 #define RXSTAT_DUMMY_READ (0x10000000)
171 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
173 return container_of(port, struct s3c24xx_uart_port, port);
176 /* translate a port to the device name */
178 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
180 return to_platform_device(port->dev)->name;
183 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
185 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
188 static void s3c24xx_serial_rx_enable(struct uart_port *port)
191 unsigned int ucon, ufcon;
194 spin_lock_irqsave(&port->lock, flags);
196 while (--count && !s3c24xx_serial_txempty_nofifo(port))
199 ufcon = rd_regl(port, S3C2410_UFCON);
200 ufcon |= S3C2410_UFCON_RESETRX;
201 wr_regl(port, S3C2410_UFCON, ufcon);
203 ucon = rd_regl(port, S3C2410_UCON);
204 ucon |= S3C2410_UCON_RXIRQMODE;
205 wr_regl(port, S3C2410_UCON, ucon);
207 rx_enabled(port) = 1;
208 spin_unlock_irqrestore(&port->lock, flags);
211 static void s3c24xx_serial_rx_disable(struct uart_port *port)
216 spin_lock_irqsave(&port->lock, flags);
218 ucon = rd_regl(port, S3C2410_UCON);
219 ucon &= ~S3C2410_UCON_RXIRQMODE;
220 wr_regl(port, S3C2410_UCON, ucon);
222 rx_enabled(port) = 0;
223 spin_unlock_irqrestore(&port->lock, flags);
226 static void s3c24xx_serial_stop_tx(struct uart_port *port)
228 if (tx_enabled(port)) {
229 disable_irq(TX_IRQ(port));
230 tx_enabled(port) = 0;
231 if (port->flags & UPF_CONS_FLOW)
232 s3c24xx_serial_rx_enable(port);
236 static void s3c24xx_serial_start_tx(struct uart_port *port)
238 if (!tx_enabled(port)) {
239 if (port->flags & UPF_CONS_FLOW)
240 s3c24xx_serial_rx_disable(port);
242 enable_irq(TX_IRQ(port));
243 tx_enabled(port) = 1;
248 static void s3c24xx_serial_stop_rx(struct uart_port *port)
250 if (rx_enabled(port)) {
251 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
252 disable_irq(RX_IRQ(port));
253 rx_enabled(port) = 0;
257 static void s3c24xx_serial_enable_ms(struct uart_port *port)
261 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
263 return to_ourport(port)->info;
266 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
268 if (port->dev == NULL)
271 return (struct s3c2410_uartcfg *)port->dev->platform_data;
274 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
275 unsigned long ufstat)
277 struct s3c24xx_uart_info *info = ourport->info;
279 if (ufstat & info->rx_fifofull)
280 return info->fifosize;
282 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
286 /* ? - where has parity gone?? */
287 #define S3C2410_UERSTAT_PARITY (0x1000)
290 s3c24xx_serial_rx_chars(int irq, void *dev_id)
292 struct s3c24xx_uart_port *ourport = dev_id;
293 struct uart_port *port = &ourport->port;
294 struct tty_struct *tty = port->info->tty;
295 unsigned int ufcon, ch, flag, ufstat, uerstat;
298 while (max_count-- > 0) {
299 ufcon = rd_regl(port, S3C2410_UFCON);
300 ufstat = rd_regl(port, S3C2410_UFSTAT);
302 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
305 uerstat = rd_regl(port, S3C2410_UERSTAT);
306 ch = rd_regb(port, S3C2410_URXH);
308 if (port->flags & UPF_CONS_FLOW) {
309 int txe = s3c24xx_serial_txempty_nofifo(port);
311 if (rx_enabled(port)) {
313 rx_enabled(port) = 0;
318 ufcon |= S3C2410_UFCON_RESETRX;
319 wr_regl(port, S3C2410_UFCON, ufcon);
320 rx_enabled(port) = 1;
327 /* insert the character into the buffer */
332 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
333 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
336 /* check for break */
337 if (uerstat & S3C2410_UERSTAT_BREAK) {
340 if (uart_handle_break(port))
344 if (uerstat & S3C2410_UERSTAT_FRAME)
345 port->icount.frame++;
346 if (uerstat & S3C2410_UERSTAT_OVERRUN)
347 port->icount.overrun++;
349 uerstat &= port->read_status_mask;
351 if (uerstat & S3C2410_UERSTAT_BREAK)
353 else if (uerstat & S3C2410_UERSTAT_PARITY)
355 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
359 if (uart_handle_sysrq_char(port, ch))
362 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
367 tty_flip_buffer_push(tty);
373 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
375 struct s3c24xx_uart_port *ourport = id;
376 struct uart_port *port = &ourport->port;
377 struct circ_buf *xmit = &port->info->xmit;
381 wr_regb(port, S3C2410_UTXH, port->x_char);
387 /* if there isnt anything more to transmit, or the uart is now
388 * stopped, disable the uart and exit
391 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
392 s3c24xx_serial_stop_tx(port);
396 /* try and drain the buffer... */
398 while (!uart_circ_empty(xmit) && count-- > 0) {
399 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
402 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
403 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
408 uart_write_wakeup(port);
410 if (uart_circ_empty(xmit))
411 s3c24xx_serial_stop_tx(port);
417 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
419 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
420 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
421 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
423 if (ufcon & S3C2410_UFCON_FIFOMODE) {
424 if ((ufstat & info->tx_fifomask) != 0 ||
425 (ufstat & info->tx_fifofull))
431 return s3c24xx_serial_txempty_nofifo(port);
434 /* no modem control lines */
435 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
437 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
439 if (umstat & S3C2410_UMSTAT_CTS)
440 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
442 return TIOCM_CAR | TIOCM_DSR;
445 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
447 /* todo - possibly remove AFC and do manual CTS */
450 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
455 spin_lock_irqsave(&port->lock, flags);
457 ucon = rd_regl(port, S3C2410_UCON);
460 ucon |= S3C2410_UCON_SBREAK;
462 ucon &= ~S3C2410_UCON_SBREAK;
464 wr_regl(port, S3C2410_UCON, ucon);
466 spin_unlock_irqrestore(&port->lock, flags);
469 static void s3c24xx_serial_shutdown(struct uart_port *port)
471 struct s3c24xx_uart_port *ourport = to_ourport(port);
473 if (ourport->tx_claimed) {
474 free_irq(TX_IRQ(port), ourport);
475 tx_enabled(port) = 0;
476 ourport->tx_claimed = 0;
479 if (ourport->rx_claimed) {
480 free_irq(RX_IRQ(port), ourport);
481 ourport->rx_claimed = 0;
482 rx_enabled(port) = 0;
487 static int s3c24xx_serial_startup(struct uart_port *port)
489 struct s3c24xx_uart_port *ourport = to_ourport(port);
492 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
493 port->mapbase, port->membase);
495 rx_enabled(port) = 1;
497 ret = request_irq(RX_IRQ(port),
498 s3c24xx_serial_rx_chars, 0,
499 s3c24xx_serial_portname(port), ourport);
502 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
506 ourport->rx_claimed = 1;
508 dbg("requesting tx irq...\n");
510 tx_enabled(port) = 1;
512 ret = request_irq(TX_IRQ(port),
513 s3c24xx_serial_tx_chars, 0,
514 s3c24xx_serial_portname(port), ourport);
517 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
521 ourport->tx_claimed = 1;
523 dbg("s3c24xx_serial_startup ok\n");
525 /* the port reset code should have done the correct
526 * register setup for the port controls */
531 s3c24xx_serial_shutdown(port);
535 /* power power management control */
537 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
540 struct s3c24xx_uart_port *ourport = to_ourport(port);
544 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
545 clk_disable(ourport->baudclk);
547 clk_disable(ourport->clk);
551 clk_enable(ourport->clk);
553 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
554 clk_enable(ourport->baudclk);
558 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
562 /* baud rate calculation
564 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
565 * of different sources, including the peripheral clock ("pclk") and an
566 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
567 * with a programmable extra divisor.
569 * The following code goes through the clock sources, and calculates the
570 * baud clocks (and the resultant actual baud rates) and then tries to
571 * pick the closest one and select that.
578 static struct s3c24xx_uart_clksrc tmp_clksrc = {
586 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
588 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
590 return (info->get_clksrc)(port, c);
594 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
596 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
598 return (info->set_clksrc)(port, c);
602 struct s3c24xx_uart_clksrc *clksrc;
608 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
609 struct uart_port *port,
610 struct s3c24xx_uart_clksrc *clksrc,
615 calc->src = clk_get(port->dev, clksrc->name);
616 if (calc->src == NULL || IS_ERR(calc->src))
619 rate = clk_get_rate(calc->src);
620 rate /= clksrc->divisor;
622 calc->clksrc = clksrc;
623 calc->quot = (rate + (8 * baud)) / (16 * baud);
624 calc->calc = (rate / (calc->quot * 16));
630 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
631 struct s3c24xx_uart_clksrc **clksrc,
635 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
636 struct s3c24xx_uart_clksrc *clkp;
637 struct baud_calc res[MAX_CLKS];
638 struct baud_calc *resptr, *best, *sptr;
644 if (cfg->clocks_size < 2) {
645 if (cfg->clocks_size == 0)
648 /* check to see if we're sourcing fclk, and if so we're
649 * going to have to update the clock source
652 if (strcmp(clkp->name, "fclk") == 0) {
653 struct s3c24xx_uart_clksrc src;
655 s3c24xx_serial_getsource(port, &src);
657 /* check that the port already using fclk, and if
658 * not, then re-select fclk
661 if (strcmp(src.name, clkp->name) == 0) {
662 s3c24xx_serial_setsource(port, clkp);
663 s3c24xx_serial_getsource(port, &src);
666 clkp->divisor = src.divisor;
669 s3c24xx_serial_calcbaud(res, port, clkp, baud);
675 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
676 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
681 /* ok, we now need to select the best clock we found */
684 unsigned int deviation = (1<<30)|((1<<30)-1);
687 for (sptr = res; sptr < resptr; sptr++) {
688 calc_deviation = baud - sptr->calc;
689 if (calc_deviation < 0)
690 calc_deviation = -calc_deviation;
692 if (calc_deviation < deviation) {
694 deviation = calc_deviation;
699 /* store results to pass back */
701 *clksrc = best->clksrc;
707 static void s3c24xx_serial_set_termios(struct uart_port *port,
708 struct ktermios *termios,
709 struct ktermios *old)
711 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
712 struct s3c24xx_uart_port *ourport = to_ourport(port);
713 struct s3c24xx_uart_clksrc *clksrc = NULL;
714 struct clk *clk = NULL;
716 unsigned int baud, quot;
721 * We don't support modem control lines.
723 termios->c_cflag &= ~(HUPCL | CMSPAR);
724 termios->c_cflag |= CLOCAL;
727 * Ask the core to calculate the divisor for us.
730 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
732 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
733 quot = port->custom_divisor;
735 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
737 /* check to see if we need to change clock source */
739 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
740 s3c24xx_serial_setsource(port, clksrc);
742 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
743 clk_disable(ourport->baudclk);
744 ourport->baudclk = NULL;
749 ourport->clksrc = clksrc;
750 ourport->baudclk = clk;
753 switch (termios->c_cflag & CSIZE) {
755 dbg("config: 5bits/char\n");
756 ulcon = S3C2410_LCON_CS5;
759 dbg("config: 6bits/char\n");
760 ulcon = S3C2410_LCON_CS6;
763 dbg("config: 7bits/char\n");
764 ulcon = S3C2410_LCON_CS7;
768 dbg("config: 8bits/char\n");
769 ulcon = S3C2410_LCON_CS8;
773 /* preserve original lcon IR settings */
774 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
776 if (termios->c_cflag & CSTOPB)
777 ulcon |= S3C2410_LCON_STOPB;
779 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
781 if (termios->c_cflag & PARENB) {
782 if (termios->c_cflag & PARODD)
783 ulcon |= S3C2410_LCON_PODD;
785 ulcon |= S3C2410_LCON_PEVEN;
787 ulcon |= S3C2410_LCON_PNONE;
790 spin_lock_irqsave(&port->lock, flags);
792 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
794 wr_regl(port, S3C2410_ULCON, ulcon);
795 wr_regl(port, S3C2410_UBRDIV, quot);
796 wr_regl(port, S3C2410_UMCON, umcon);
798 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
799 rd_regl(port, S3C2410_ULCON),
800 rd_regl(port, S3C2410_UCON),
801 rd_regl(port, S3C2410_UFCON));
804 * Update the per-port timeout.
806 uart_update_timeout(port, termios->c_cflag, baud);
809 * Which character status flags are we interested in?
811 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
812 if (termios->c_iflag & INPCK)
813 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
816 * Which character status flags should we ignore?
818 port->ignore_status_mask = 0;
819 if (termios->c_iflag & IGNPAR)
820 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
821 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
822 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
825 * Ignore all characters if CREAD is not set.
827 if ((termios->c_cflag & CREAD) == 0)
828 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
830 spin_unlock_irqrestore(&port->lock, flags);
833 static const char *s3c24xx_serial_type(struct uart_port *port)
835 switch (port->type) {
847 #define MAP_SIZE (0x100)
849 static void s3c24xx_serial_release_port(struct uart_port *port)
851 release_mem_region(port->mapbase, MAP_SIZE);
854 static int s3c24xx_serial_request_port(struct uart_port *port)
856 const char *name = s3c24xx_serial_portname(port);
857 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
860 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
862 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
864 if (flags & UART_CONFIG_TYPE &&
865 s3c24xx_serial_request_port(port) == 0)
866 port->type = info->type;
870 * verify the new serial_struct (for TIOCSSERIAL).
873 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
875 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
877 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
884 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
886 static struct console s3c24xx_serial_console;
888 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
890 #define S3C24XX_SERIAL_CONSOLE NULL
893 static struct uart_ops s3c24xx_serial_ops = {
894 .pm = s3c24xx_serial_pm,
895 .tx_empty = s3c24xx_serial_tx_empty,
896 .get_mctrl = s3c24xx_serial_get_mctrl,
897 .set_mctrl = s3c24xx_serial_set_mctrl,
898 .stop_tx = s3c24xx_serial_stop_tx,
899 .start_tx = s3c24xx_serial_start_tx,
900 .stop_rx = s3c24xx_serial_stop_rx,
901 .enable_ms = s3c24xx_serial_enable_ms,
902 .break_ctl = s3c24xx_serial_break_ctl,
903 .startup = s3c24xx_serial_startup,
904 .shutdown = s3c24xx_serial_shutdown,
905 .set_termios = s3c24xx_serial_set_termios,
906 .type = s3c24xx_serial_type,
907 .release_port = s3c24xx_serial_release_port,
908 .request_port = s3c24xx_serial_request_port,
909 .config_port = s3c24xx_serial_config_port,
910 .verify_port = s3c24xx_serial_verify_port,
914 static struct uart_driver s3c24xx_uart_drv = {
915 .owner = THIS_MODULE,
916 .dev_name = "s3c2410_serial",
918 .cons = S3C24XX_SERIAL_CONSOLE,
919 .driver_name = S3C24XX_SERIAL_NAME,
920 .major = S3C24XX_SERIAL_MAJOR,
921 .minor = S3C24XX_SERIAL_MINOR,
924 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
927 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
929 .irq = IRQ_S3CUART_RX0,
932 .ops = &s3c24xx_serial_ops,
933 .flags = UPF_BOOT_AUTOCONF,
939 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
941 .irq = IRQ_S3CUART_RX1,
944 .ops = &s3c24xx_serial_ops,
945 .flags = UPF_BOOT_AUTOCONF,
953 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
955 .irq = IRQ_S3CUART_RX2,
958 .ops = &s3c24xx_serial_ops,
959 .flags = UPF_BOOT_AUTOCONF,
966 /* s3c24xx_serial_resetport
968 * wrapper to call the specific reset for this port (reset the fifos
972 static inline int s3c24xx_serial_resetport(struct uart_port * port,
973 struct s3c2410_uartcfg *cfg)
975 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
977 return (info->reset_port)(port, cfg);
980 /* s3c24xx_serial_init_port
982 * initialise a single serial port from the platform device given
985 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
986 struct s3c24xx_uart_info *info,
987 struct platform_device *platdev)
989 struct uart_port *port = &ourport->port;
990 struct s3c2410_uartcfg *cfg;
991 struct resource *res;
994 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
999 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1001 if (port->mapbase != 0)
1004 if (cfg->hwport > 3)
1007 /* setup info for port */
1008 port->dev = &platdev->dev;
1009 ourport->info = info;
1011 /* copy the info in from provided structure */
1012 ourport->port.fifosize = info->fifosize;
1014 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1018 if (cfg->uart_flags & UPF_CONS_FLOW) {
1019 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1020 port->flags |= UPF_CONS_FLOW;
1023 /* sort our the physical and virtual addresses for each UART */
1025 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1027 printk(KERN_ERR "failed to find memory resource for uart\n");
1031 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1033 port->mapbase = res->start;
1034 port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
1035 ret = platform_get_irq(platdev, 0);
1041 ourport->clk = clk_get(&platdev->dev, "uart");
1043 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1044 port->mapbase, port->membase, port->irq, port->uartclk);
1046 /* reset the fifos (and setup the uart) */
1047 s3c24xx_serial_resetport(port, cfg);
1051 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1052 struct device_attribute *attr,
1055 struct uart_port *port = s3c24xx_dev_to_port(dev);
1056 struct s3c24xx_uart_port *ourport = to_ourport(port);
1058 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1061 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1063 /* Device driver serial port probe */
1065 static int probe_index = 0;
1067 static int s3c24xx_serial_probe(struct platform_device *dev,
1068 struct s3c24xx_uart_info *info)
1070 struct s3c24xx_uart_port *ourport;
1073 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1075 ourport = &s3c24xx_serial_ports[probe_index];
1078 dbg("%s: initialising port %p...\n", __func__, ourport);
1080 ret = s3c24xx_serial_init_port(ourport, info, dev);
1084 dbg("%s: adding port\n", __func__);
1085 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1086 platform_set_drvdata(dev, &ourport->port);
1088 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1090 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1099 static int s3c24xx_serial_remove(struct platform_device *dev)
1101 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1104 device_remove_file(&dev->dev, &dev_attr_clock_source);
1105 uart_remove_one_port(&s3c24xx_uart_drv, port);
1111 /* UART power management code */
1115 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1117 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1120 uart_suspend_port(&s3c24xx_uart_drv, port);
1125 static int s3c24xx_serial_resume(struct platform_device *dev)
1127 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1128 struct s3c24xx_uart_port *ourport = to_ourport(port);
1131 clk_enable(ourport->clk);
1132 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1133 clk_disable(ourport->clk);
1135 uart_resume_port(&s3c24xx_uart_drv, port);
1142 #define s3c24xx_serial_suspend NULL
1143 #define s3c24xx_serial_resume NULL
1146 static int s3c24xx_serial_init(struct platform_driver *drv,
1147 struct s3c24xx_uart_info *info)
1149 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1150 return platform_driver_register(drv);
1154 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1158 /* cpu specific variations on the serial port support */
1160 #ifdef CONFIG_CPU_S3C2400
1162 static int s3c2400_serial_getsource(struct uart_port *port,
1163 struct s3c24xx_uart_clksrc *clk)
1171 static int s3c2400_serial_setsource(struct uart_port *port,
1172 struct s3c24xx_uart_clksrc *clk)
1177 static int s3c2400_serial_resetport(struct uart_port *port,
1178 struct s3c2410_uartcfg *cfg)
1180 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1181 port, port->mapbase, cfg);
1183 wr_regl(port, S3C2410_UCON, cfg->ucon);
1184 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1186 /* reset both fifos */
1188 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1189 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1194 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1195 .name = "Samsung S3C2400 UART",
1196 .type = PORT_S3C2400,
1198 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1199 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1200 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1201 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1202 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1203 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1204 .get_clksrc = s3c2400_serial_getsource,
1205 .set_clksrc = s3c2400_serial_setsource,
1206 .reset_port = s3c2400_serial_resetport,
1209 static int s3c2400_serial_probe(struct platform_device *dev)
1211 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1214 static struct platform_driver s3c2400_serial_drv = {
1215 .probe = s3c2400_serial_probe,
1216 .remove = s3c24xx_serial_remove,
1217 .suspend = s3c24xx_serial_suspend,
1218 .resume = s3c24xx_serial_resume,
1220 .name = "s3c2400-uart",
1221 .owner = THIS_MODULE,
1225 static inline int s3c2400_serial_init(void)
1227 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1230 static inline void s3c2400_serial_exit(void)
1232 platform_driver_unregister(&s3c2400_serial_drv);
1235 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1238 static inline int s3c2400_serial_init(void)
1243 static inline void s3c2400_serial_exit(void)
1247 #define s3c2400_uart_inf_at NULL
1249 #endif /* CONFIG_CPU_S3C2400 */
1251 /* S3C2410 support */
1253 #ifdef CONFIG_CPU_S3C2410
1255 static int s3c2410_serial_setsource(struct uart_port *port,
1256 struct s3c24xx_uart_clksrc *clk)
1258 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1260 if (strcmp(clk->name, "uclk") == 0)
1261 ucon |= S3C2410_UCON_UCLK;
1263 ucon &= ~S3C2410_UCON_UCLK;
1265 wr_regl(port, S3C2410_UCON, ucon);
1269 static int s3c2410_serial_getsource(struct uart_port *port,
1270 struct s3c24xx_uart_clksrc *clk)
1272 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1275 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1280 static int s3c2410_serial_resetport(struct uart_port *port,
1281 struct s3c2410_uartcfg *cfg)
1283 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1284 port, port->mapbase, cfg);
1286 wr_regl(port, S3C2410_UCON, cfg->ucon);
1287 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1289 /* reset both fifos */
1291 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1292 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1297 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1298 .name = "Samsung S3C2410 UART",
1299 .type = PORT_S3C2410,
1301 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1302 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1303 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1304 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1305 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1306 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1307 .get_clksrc = s3c2410_serial_getsource,
1308 .set_clksrc = s3c2410_serial_setsource,
1309 .reset_port = s3c2410_serial_resetport,
1312 /* device management */
1314 static int s3c2410_serial_probe(struct platform_device *dev)
1316 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1319 static struct platform_driver s3c2410_serial_drv = {
1320 .probe = s3c2410_serial_probe,
1321 .remove = s3c24xx_serial_remove,
1322 .suspend = s3c24xx_serial_suspend,
1323 .resume = s3c24xx_serial_resume,
1325 .name = "s3c2410-uart",
1326 .owner = THIS_MODULE,
1330 static inline int s3c2410_serial_init(void)
1332 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1335 static inline void s3c2410_serial_exit(void)
1337 platform_driver_unregister(&s3c2410_serial_drv);
1340 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1343 static inline int s3c2410_serial_init(void)
1348 static inline void s3c2410_serial_exit(void)
1352 #define s3c2410_uart_inf_at NULL
1354 #endif /* CONFIG_CPU_S3C2410 */
1356 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1358 static int s3c2440_serial_setsource(struct uart_port *port,
1359 struct s3c24xx_uart_clksrc *clk)
1361 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1363 // todo - proper fclk<>nonfclk switch //
1365 ucon &= ~S3C2440_UCON_CLKMASK;
1367 if (strcmp(clk->name, "uclk") == 0)
1368 ucon |= S3C2440_UCON_UCLK;
1369 else if (strcmp(clk->name, "pclk") == 0)
1370 ucon |= S3C2440_UCON_PCLK;
1371 else if (strcmp(clk->name, "fclk") == 0)
1372 ucon |= S3C2440_UCON_FCLK;
1374 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1378 wr_regl(port, S3C2410_UCON, ucon);
1383 static int s3c2440_serial_getsource(struct uart_port *port,
1384 struct s3c24xx_uart_clksrc *clk)
1386 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1387 unsigned long ucon0, ucon1, ucon2;
1389 switch (ucon & S3C2440_UCON_CLKMASK) {
1390 case S3C2440_UCON_UCLK:
1395 case S3C2440_UCON_PCLK:
1396 case S3C2440_UCON_PCLK2:
1401 case S3C2440_UCON_FCLK:
1402 /* the fun of calculating the uart divisors on
1405 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1406 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1407 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1409 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1411 ucon0 &= S3C2440_UCON0_DIVMASK;
1412 ucon1 &= S3C2440_UCON1_DIVMASK;
1413 ucon2 &= S3C2440_UCON2_DIVMASK;
1416 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1418 } else if (ucon1 != 0) {
1419 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1421 } else if (ucon2 != 0) {
1422 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1425 /* manual calims 44, seems to be 9 */
1436 static int s3c2440_serial_resetport(struct uart_port *port,
1437 struct s3c2410_uartcfg *cfg)
1439 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1441 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1442 port, port->mapbase, cfg);
1444 /* ensure we don't change the clock settings... */
1446 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1448 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1449 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1451 /* reset both fifos */
1453 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1454 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1459 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1460 .name = "Samsung S3C2440 UART",
1461 .type = PORT_S3C2440,
1463 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1464 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1465 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1466 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1467 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1468 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1469 .get_clksrc = s3c2440_serial_getsource,
1470 .set_clksrc = s3c2440_serial_setsource,
1471 .reset_port = s3c2440_serial_resetport,
1474 /* device management */
1476 static int s3c2440_serial_probe(struct platform_device *dev)
1478 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1479 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1482 static struct platform_driver s3c2440_serial_drv = {
1483 .probe = s3c2440_serial_probe,
1484 .remove = s3c24xx_serial_remove,
1485 .suspend = s3c24xx_serial_suspend,
1486 .resume = s3c24xx_serial_resume,
1488 .name = "s3c2440-uart",
1489 .owner = THIS_MODULE,
1494 static inline int s3c2440_serial_init(void)
1496 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1499 static inline void s3c2440_serial_exit(void)
1501 platform_driver_unregister(&s3c2440_serial_drv);
1504 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1507 static inline int s3c2440_serial_init(void)
1512 static inline void s3c2440_serial_exit(void)
1516 #define s3c2440_uart_inf_at NULL
1517 #endif /* CONFIG_CPU_S3C2440 */
1519 #if defined(CONFIG_CPU_S3C2412)
1521 static int s3c2412_serial_setsource(struct uart_port *port,
1522 struct s3c24xx_uart_clksrc *clk)
1524 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1526 ucon &= ~S3C2412_UCON_CLKMASK;
1528 if (strcmp(clk->name, "uclk") == 0)
1529 ucon |= S3C2440_UCON_UCLK;
1530 else if (strcmp(clk->name, "pclk") == 0)
1531 ucon |= S3C2440_UCON_PCLK;
1532 else if (strcmp(clk->name, "usysclk") == 0)
1533 ucon |= S3C2412_UCON_USYSCLK;
1535 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1539 wr_regl(port, S3C2410_UCON, ucon);
1544 static int s3c2412_serial_getsource(struct uart_port *port,
1545 struct s3c24xx_uart_clksrc *clk)
1547 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1549 switch (ucon & S3C2412_UCON_CLKMASK) {
1550 case S3C2412_UCON_UCLK:
1555 case S3C2412_UCON_PCLK:
1556 case S3C2412_UCON_PCLK2:
1561 case S3C2412_UCON_USYSCLK:
1563 clk->name = "usysclk";
1570 static int s3c2412_serial_resetport(struct uart_port *port,
1571 struct s3c2410_uartcfg *cfg)
1573 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1575 dbg("%s: port=%p (%08lx), cfg=%p\n",
1576 __func__, port, port->mapbase, cfg);
1578 /* ensure we don't change the clock settings... */
1580 ucon &= S3C2412_UCON_CLKMASK;
1582 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1583 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1585 /* reset both fifos */
1587 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1588 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1593 static struct s3c24xx_uart_info s3c2412_uart_inf = {
1594 .name = "Samsung S3C2412 UART",
1595 .type = PORT_S3C2412,
1597 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1598 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1599 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1600 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1601 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1602 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1603 .get_clksrc = s3c2412_serial_getsource,
1604 .set_clksrc = s3c2412_serial_setsource,
1605 .reset_port = s3c2412_serial_resetport,
1608 /* device management */
1610 static int s3c2412_serial_probe(struct platform_device *dev)
1612 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1613 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
1616 static struct platform_driver s3c2412_serial_drv = {
1617 .probe = s3c2412_serial_probe,
1618 .remove = s3c24xx_serial_remove,
1619 .suspend = s3c24xx_serial_suspend,
1620 .resume = s3c24xx_serial_resume,
1622 .name = "s3c2412-uart",
1623 .owner = THIS_MODULE,
1628 static inline int s3c2412_serial_init(void)
1630 return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
1633 static inline void s3c2412_serial_exit(void)
1635 platform_driver_unregister(&s3c2412_serial_drv);
1638 #define s3c2412_uart_inf_at &s3c2412_uart_inf
1641 static inline int s3c2412_serial_init(void)
1646 static inline void s3c2412_serial_exit(void)
1650 #define s3c2412_uart_inf_at NULL
1651 #endif /* CONFIG_CPU_S3C2440 */
1654 /* module initialisation code */
1656 static int __init s3c24xx_serial_modinit(void)
1660 ret = uart_register_driver(&s3c24xx_uart_drv);
1662 printk(KERN_ERR "failed to register UART driver\n");
1666 s3c2400_serial_init();
1667 s3c2410_serial_init();
1668 s3c2412_serial_init();
1669 s3c2440_serial_init();
1674 static void __exit s3c24xx_serial_modexit(void)
1676 s3c2400_serial_exit();
1677 s3c2410_serial_exit();
1678 s3c2412_serial_exit();
1679 s3c2440_serial_exit();
1681 uart_unregister_driver(&s3c24xx_uart_drv);
1685 module_init(s3c24xx_serial_modinit);
1686 module_exit(s3c24xx_serial_modexit);
1690 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1692 static struct uart_port *cons_uart;
1695 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1697 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1698 unsigned long ufstat, utrstat;
1700 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1701 /* fifo mode - check ammount of data in fifo registers... */
1703 ufstat = rd_regl(port, S3C2410_UFSTAT);
1704 return (ufstat & info->tx_fifofull) ? 0 : 1;
1707 /* in non-fifo mode, we go and use the tx buffer empty */
1709 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1710 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1714 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1716 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1717 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1719 wr_regb(cons_uart, S3C2410_UTXH, ch);
1723 s3c24xx_serial_console_write(struct console *co, const char *s,
1726 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1730 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1731 int *parity, int *bits)
1733 struct s3c24xx_uart_clksrc clksrc;
1737 unsigned int ubrdiv;
1740 ulcon = rd_regl(port, S3C2410_ULCON);
1741 ucon = rd_regl(port, S3C2410_UCON);
1742 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1744 dbg("s3c24xx_serial_get_options: port=%p\n"
1745 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1746 port, ulcon, ucon, ubrdiv);
1748 if ((ucon & 0xf) != 0) {
1749 /* consider the serial port configured if the tx/rx mode set */
1751 switch (ulcon & S3C2410_LCON_CSMASK) {
1752 case S3C2410_LCON_CS5:
1755 case S3C2410_LCON_CS6:
1758 case S3C2410_LCON_CS7:
1762 case S3C2410_LCON_CS8:
1767 switch (ulcon & S3C2410_LCON_PMASK) {
1768 case S3C2410_LCON_PEVEN:
1772 case S3C2410_LCON_PODD:
1776 case S3C2410_LCON_PNONE:
1781 /* now calculate the baud rate */
1783 s3c24xx_serial_getsource(port, &clksrc);
1785 clk = clk_get(port->dev, clksrc.name);
1786 if (!IS_ERR(clk) && clk != NULL)
1787 rate = clk_get_rate(clk) / clksrc.divisor;
1792 *baud = rate / ( 16 * (ubrdiv + 1));
1793 dbg("calculated baud %d\n", *baud);
1798 /* s3c24xx_serial_init_ports
1800 * initialise the serial ports from the machine provided initialisation
1804 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1806 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1807 struct platform_device **platdev_ptr;
1810 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1812 platdev_ptr = s3c24xx_uart_devs;
1814 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1815 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1822 s3c24xx_serial_console_setup(struct console *co, char *options)
1824 struct uart_port *port;
1830 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1831 co, co->index, options);
1833 /* is this a valid port */
1835 if (co->index == -1 || co->index >= NR_PORTS)
1838 port = &s3c24xx_serial_ports[co->index].port;
1840 /* is the port configured? */
1842 if (port->mapbase == 0x0) {
1844 port = &s3c24xx_serial_ports[co->index].port;
1849 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1852 * Check whether an invalid uart number has been specified, and
1853 * if so, search for the first available port that does have
1857 uart_parse_options(options, &baud, &parity, &bits, &flow);
1859 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1861 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1863 return uart_set_options(port, co, baud, parity, bits, flow);
1866 /* s3c24xx_serial_initconsole
1868 * initialise the console from one of the uart drivers
1871 static struct console s3c24xx_serial_console =
1873 .name = S3C24XX_SERIAL_NAME,
1874 .device = uart_console_device,
1875 .flags = CON_PRINTBUFFER,
1877 .write = s3c24xx_serial_console_write,
1878 .setup = s3c24xx_serial_console_setup
1881 static int s3c24xx_serial_initconsole(void)
1883 struct s3c24xx_uart_info *info;
1884 struct platform_device *dev = s3c24xx_uart_devs[0];
1886 dbg("s3c24xx_serial_initconsole\n");
1888 /* select driver based on the cpu */
1891 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1895 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1896 info = s3c2400_uart_inf_at;
1897 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1898 info = s3c2410_uart_inf_at;
1899 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1900 info = s3c2440_uart_inf_at;
1901 } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
1902 info = s3c2412_uart_inf_at;
1904 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1909 printk(KERN_ERR "s3c24xx: no driver for console\n");
1913 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1914 s3c24xx_serial_init_ports(info);
1916 register_console(&s3c24xx_serial_console);
1920 console_initcall(s3c24xx_serial_initconsole);
1922 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1924 MODULE_LICENSE("GPL v2");
1925 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1926 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
1927 MODULE_ALIAS("platform:s3c2400-uart");
1928 MODULE_ALIAS("platform:s3c2410-uart");
1929 MODULE_ALIAS("platform:s3c2412-uart");
1930 MODULE_ALIAS("platform:s3c2440-uart");