drivers/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. In A0 stepping, UART will not support TX half empty flag
  20  *
  21  * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  22  *    asserted, only when the HW is reset the DDCD and DDSR will
  23  *    be triggered
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/console.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include <linux/serial_reg.h>
  32 #include <linux/circ_buf.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/tty.h>
  36 #include <linux/tty_flip.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/serial_mfd.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/pci.h>
  41 #include <linux/io.h>
  42 #include <linux/debugfs.h>
  43
  44 #define  MFD_HSU_A0_STEPPING    1
  45
  46 #define HSU_DMA_BUF_SIZE        2048
  47
  48 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  49 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  50
  51 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  52 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  53
  54 #define HSU_DMA_TIMEOUT_CHECK_FREQ      (HZ/10)
  55
  56 struct hsu_dma_buffer {
  57         u8              *buf;
  58         dma_addr_t      dma_addr;
  59         u32             dma_size;
  60         u32             ofs;
  61 };
  62
  63 struct hsu_dma_chan {
  64         u32     id;
  65         enum dma_data_direction dirt;
  66         struct uart_hsu_port    *uport;
  67         void __iomem            *reg;
  68         struct timer_list       rx_timer; /* only needed by RX channel */
  69 };
  70
  71 struct uart_hsu_port {
  72         struct uart_port        port;
  73         unsigned char           ier;
  74         unsigned char           lcr;
  75         unsigned char           mcr;
  76         unsigned int            lsr_break_flag;
  77         char                    name[12];
  78         int                     index;
  79         struct device           *dev;
  80
  81         struct hsu_dma_chan     *txc;
  82         struct hsu_dma_chan     *rxc;
  83         struct hsu_dma_buffer   txbuf;
  84         struct hsu_dma_buffer   rxbuf;
  85         int                     use_dma;        /* flag for DMA/PIO */
  86         int                     running;
  87         int                     dma_tx_on;
  88 };
  89
  90 /* Top level data structure of HSU */
  91 struct hsu_port {
  92         void __iomem    *reg;
  93         unsigned long   paddr;
  94         unsigned long   iolen;
  95         u32             irq;
  96
  97         struct uart_hsu_port    port[3];
  98         struct hsu_dma_chan     chans[10];
  99
 100         struct dentry *debugfs;
 101 };
 102
 103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 104 {
 105         unsigned int val;
 106
 107         if (offset > UART_MSR) {
 108                 offset <<= 2;
 109                 val = readl(up->port.membase + offset);
 110         } else
 111                 val = (unsigned int)readb(up->port.membase + offset);
 112
 113         return val;
 114 }
 115
 116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 117 {
 118         if (offset > UART_MSR) {
 119                 offset <<= 2;
 120                 writel(value, up->port.membase + offset);
 121         } else {
 122                 unsigned char val = value & 0xff;
 123                 writeb(val, up->port.membase + offset);
 124         }
 125 }
 126
 127 #ifdef CONFIG_DEBUG_FS
 128
 129 #define HSU_REGS_BUFSIZE        1024
 130
 131 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 132 {
 133         file->private_data = inode->i_private;
 134         return 0;
 135 }
 136
 137 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 138                                 size_t count, loff_t *ppos)
 139 {
 140         struct uart_hsu_port *up = file->private_data;
 141         char *buf;
 142         u32 len = 0;
 143         ssize_t ret;
 144
 145         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 146         if (!buf)
 147                 return 0;
 148
 149         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 150                         "MFD HSU port[%d] regs:\n", up->index);
 151
 152         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 153                         "=================================\n");
 154         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 155                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 156         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 157                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 158         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 159                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 160         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 161                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 162         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 163                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 164         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 165                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 166         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 167                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 168         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 169                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 170         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 171                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 172         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 173                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 174
 175         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 176         kfree(buf);
 177         return ret;
 178 }
 179
 180 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 181                                 size_t count, loff_t *ppos)
 182 {
 183         struct hsu_dma_chan *chan = file->private_data;
 184         char *buf;
 185         u32 len = 0;
 186         ssize_t ret;
 187
 188         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 189         if (!buf)
 190                 return 0;
 191
 192         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 193                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 194
 195         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 196                         "=================================\n");
 197         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 198                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 199         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 200                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 201         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 202                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 203         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 204                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 205         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 206                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 207         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 208                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 209         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 210                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 211         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 212                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 213         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 214                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 215         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 216                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 217         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 218                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 219         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 220                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 221
 222         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 223         kfree(buf);
 224         return ret;
 225 }
 226
 227 static const struct file_operations port_regs_ops = {
 228         .owner          = THIS_MODULE,
 229         .open           = hsu_show_regs_open,
 230         .read           = port_show_regs,
 231 };
 232
 233 static const struct file_operations dma_regs_ops = {
 234         .owner          = THIS_MODULE,
 235         .open           = hsu_show_regs_open,
 236         .read           = dma_show_regs,
 237 };
 238
 239 static int hsu_debugfs_init(struct hsu_port *hsu)
 240 {
 241         int i;
 242         char name[32];
 243
 244         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 245         if (!hsu->debugfs)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < 3; i++) {
 249                 snprintf(name, sizeof(name), "port_%d_regs", i);
 250                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 251                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 252         }
 253
 254         for (i = 0; i < 6; i++) {
 255                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 256                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 257                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 258         }
 259
 260         return 0;
 261 }
 262
 263 static void hsu_debugfs_remove(struct hsu_port *hsu)
 264 {
 265         if (hsu->debugfs)
 266                 debugfs_remove_recursive(hsu->debugfs);
 267 }
 268
 269 #else
 270 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 271 {
 272         return 0;
 273 }
 274
 275 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 276 {
 277 }
 278 #endif /* CONFIG_DEBUG_FS */
 279
 280 static void serial_hsu_enable_ms(struct uart_port *port)
 281 {
 282         struct uart_hsu_port *up =
 283                 container_of(port, struct uart_hsu_port, port);
 284
 285         up->ier |= UART_IER_MSI;
 286         serial_out(up, UART_IER, up->ier);
 287 }
 288
 289 void hsu_dma_tx(struct uart_hsu_port *up)
 290 {
 291         struct circ_buf *xmit = &up->port.state->xmit;
 292         struct hsu_dma_buffer *dbuf = &up->txbuf;
 293         int count;
 294
 295         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 296         if (up->dma_tx_on)
 297                 return;
 298
 299         /* Update the circ buf info */
 300         xmit->tail += dbuf->ofs;
 301         xmit->tail &= UART_XMIT_SIZE - 1;
 302
 303         up->port.icount.tx += dbuf->ofs;
 304         dbuf->ofs = 0;
 305
 306         /* Disable the channel */
 307         chan_writel(up->txc, HSU_CH_CR, 0x0);
 308
 309         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 310                 dma_sync_single_for_device(up->port.dev,
 311                                            dbuf->dma_addr,
 312                                            dbuf->dma_size,
 313                                            DMA_TO_DEVICE);
 314
 315                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 316                 dbuf->ofs = count;
 317
 318                 /* Reprogram the channel */
 319                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 320                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 321
 322                 /* Reenable the channel */
 323                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 324                                                  | (0x1 << 8)
 325                                                  | (0x1 << 16)
 326                                                  | (0x1 << 24));
 327                 up->dma_tx_on = 1;
 328                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 329         }
 330
 331         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 332                 uart_write_wakeup(&up->port);
 333 }
 334
 335 /* The buffer is already cache coherent */
 336 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 337 {
 338         dbuf->ofs = 0;
 339
 340         chan_writel(rxc, HSU_CH_BSR, 32);
 341         chan_writel(rxc, HSU_CH_MOTSR, 4);
 342
 343         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 344         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 345         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 346                                          | (0x1 << 16)
 347                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 348                                          );
 349         chan_writel(rxc, HSU_CH_CR, 0x3);
 350
 351         mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
 352 }
 353
 354 /* Protected by spin_lock_irqsave(port->lock) */
 355 static void serial_hsu_start_tx(struct uart_port *port)
 356 {
 357         struct uart_hsu_port *up =
 358                 container_of(port, struct uart_hsu_port, port);
 359
 360         if (up->use_dma) {
 361                 hsu_dma_tx(up);
 362         } else if (!(up->ier & UART_IER_THRI)) {
 363                 up->ier |= UART_IER_THRI;
 364                 serial_out(up, UART_IER, up->ier);
 365         }
 366 }
 367
 368 static void serial_hsu_stop_tx(struct uart_port *port)
 369 {
 370         struct uart_hsu_port *up =
 371                 container_of(port, struct uart_hsu_port, port);
 372         struct hsu_dma_chan *txc = up->txc;
 373
 374         if (up->use_dma)
 375                 chan_writel(txc, HSU_CH_CR, 0x0);
 376         else if (up->ier & UART_IER_THRI) {
 377                 up->ier &= ~UART_IER_THRI;
 378                 serial_out(up, UART_IER, up->ier);
 379         }
 380 }
 381
 382 /* This is always called in spinlock protected mode, so
 383  * modify timeout timer is safe here */
 384 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 385 {
 386         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 387         struct hsu_dma_chan *chan = up->rxc;
 388         struct uart_port *port = &up->port;
 389         struct tty_struct *tty = port->state->port.tty;
 390         int count;
 391
 392         if (!tty)
 393                 return;
 394
 395         /*
 396          * First need to know how many is already transferred,
 397          * then check if its a timeout DMA irq, and return
 398          * the trail bytes out, push them up and reenable the
 399          * channel
 400          */
 401
 402         /* Timeout IRQ, need wait some time, see Errata 2 */
 403         if (int_sts & 0xf00)
 404                 udelay(2);
 405
 406         /* Stop the channel */
 407         chan_writel(chan, HSU_CH_CR, 0x0);
 408
 409         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 410         if (!count) {
 411                 /* Restart the channel before we leave */
 412                 chan_writel(chan, HSU_CH_CR, 0x3);
 413                 return;
 414         }
 415         del_timer(&chan->rx_timer);
 416
 417         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 418                         dbuf->dma_size, DMA_FROM_DEVICE);
 419
 420         /*
 421          * Head will only wrap around when we recycle
 422          * the DMA buffer, and when that happens, we
 423          * explicitly set tail to 0. So head will
 424          * always be greater than tail.
 425          */
 426         tty_insert_flip_string(tty, dbuf->buf, count);
 427         port->icount.rx += count;
 428
 429         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 430                         dbuf->dma_size, DMA_FROM_DEVICE);
 431
 432         /* Reprogram the channel */
 433         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 434         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 435         chan_writel(chan, HSU_CH_DCR, 0x1
 436                                          | (0x1 << 8)
 437                                          | (0x1 << 16)
 438                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 439                                          );
 440         tty_flip_buffer_push(tty);
 441
 442         chan_writel(chan, HSU_CH_CR, 0x3);
 443         chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
 444         add_timer(&chan->rx_timer);
 445
 446 }
 447
 448 static void serial_hsu_stop_rx(struct uart_port *port)
 449 {
 450         struct uart_hsu_port *up =
 451                 container_of(port, struct uart_hsu_port, port);
 452         struct hsu_dma_chan *chan = up->rxc;
 453
 454         if (up->use_dma)
 455                 chan_writel(chan, HSU_CH_CR, 0x2);
 456         else {
 457                 up->ier &= ~UART_IER_RLSI;
 458                 up->port.read_status_mask &= ~UART_LSR_DR;
 459                 serial_out(up, UART_IER, up->ier);
 460         }
 461 }
 462
 463 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 464 {
 465         struct tty_struct *tty = up->port.state->port.tty;
 466         unsigned int ch, flag;
 467         unsigned int max_count = 256;
 468
 469         if (!tty)
 470                 return;
 471
 472         do {
 473                 ch = serial_in(up, UART_RX);
 474                 flag = TTY_NORMAL;
 475                 up->port.icount.rx++;
 476
 477                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 478                                        UART_LSR_FE | UART_LSR_OE))) {
 479
 480                         dev_warn(up->dev, "We really rush into ERR/BI case"
 481                                 "status = 0x%02x", *status);
 482                         /* For statistics only */
 483                         if (*status & UART_LSR_BI) {
 484                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 485                                 up->port.icount.brk++;
 486                                 /*
 487                                  * We do the SysRQ and SAK checking
 488                                  * here because otherwise the break
 489                                  * may get masked by ignore_status_mask
 490                                  * or read_status_mask.
 491                                  */
 492                                 if (uart_handle_break(&up->port))
 493                                         goto ignore_char;
 494                         } else if (*status & UART_LSR_PE)
 495                                 up->port.icount.parity++;
 496                         else if (*status & UART_LSR_FE)
 497                                 up->port.icount.frame++;
 498                         if (*status & UART_LSR_OE)
 499                                 up->port.icount.overrun++;
 500
 501                         /* Mask off conditions which should be ignored. */
 502                         *status &= up->port.read_status_mask;
 503
 504 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 505                         if (up->port.cons &&
 506                                 up->port.cons->index == up->port.line) {
 507                                 /* Recover the break flag from console xmit */
 508                                 *status |= up->lsr_break_flag;
 509                                 up->lsr_break_flag = 0;
 510                         }
 511 #endif
 512                         if (*status & UART_LSR_BI) {
 513                                 flag = TTY_BREAK;
 514                         } else if (*status & UART_LSR_PE)
 515                                 flag = TTY_PARITY;
 516                         else if (*status & UART_LSR_FE)
 517                                 flag = TTY_FRAME;
 518                 }
 519
 520                 if (uart_handle_sysrq_char(&up->port, ch))
 521                         goto ignore_char;
 522
 523                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 524         ignore_char:
 525                 *status = serial_in(up, UART_LSR);
 526         } while ((*status & UART_LSR_DR) && max_count--);
 527         tty_flip_buffer_push(tty);
 528 }
 529
 530 static void transmit_chars(struct uart_hsu_port *up)
 531 {
 532         struct circ_buf *xmit = &up->port.state->xmit;
 533         int count;
 534
 535         if (up->port.x_char) {
 536                 serial_out(up, UART_TX, up->port.x_char);
 537                 up->port.icount.tx++;
 538                 up->port.x_char = 0;
 539                 return;
 540         }
 541         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 542                 serial_hsu_stop_tx(&up->port);
 543                 return;
 544         }
 545
 546 #ifndef MFD_HSU_A0_STEPPING
 547         count = up->port.fifosize / 2;
 548 #else
 549         /*
 550          * A0 only supports fully empty IRQ, and the first char written
 551          * into it won't clear the EMPT bit, so we may need be cautious
 552          * by useing a shorter buffer
 553          */
 554         count = up->port.fifosize - 4;
 555 #endif
 556         do {
 557                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 558                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 559
 560                 up->port.icount.tx++;
 561                 if (uart_circ_empty(xmit))
 562                         break;
 563         } while (--count > 0);
 564
 565         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 566                 uart_write_wakeup(&up->port);
 567
 568         if (uart_circ_empty(xmit))
 569                 serial_hsu_stop_tx(&up->port);
 570 }
 571
 572 static inline void check_modem_status(struct uart_hsu_port *up)
 573 {
 574         int status;
 575
 576         status = serial_in(up, UART_MSR);
 577
 578         if ((status & UART_MSR_ANY_DELTA) == 0)
 579                 return;
 580
 581         if (status & UART_MSR_TERI)
 582                 up->port.icount.rng++;
 583         if (status & UART_MSR_DDSR)
 584                 up->port.icount.dsr++;
 585         /* We may only get DDCD when HW init and reset */
 586         if (status & UART_MSR_DDCD)
 587                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 588         /* Will start/stop_tx accordingly */
 589         if (status & UART_MSR_DCTS)
 590                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 591
 592         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 593 }
 594
 595 /*
 596  * This handles the interrupt from one port.
 597  */
 598 static irqreturn_t port_irq(int irq, void *dev_id)
 599 {
 600         struct uart_hsu_port *up = dev_id;
 601         unsigned int iir, lsr;
 602         unsigned long flags;
 603
 604         if (unlikely(!up->running))
 605                 return IRQ_NONE;
 606
 607         spin_lock_irqsave(&up->port.lock, flags);
 608         if (up->use_dma) {
 609                 lsr = serial_in(up, UART_LSR);
 610                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 611                                        UART_LSR_FE | UART_LSR_OE)))
 612                         dev_warn(up->dev,
 613                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 614                                 lsr);
 615                 check_modem_status(up);
 616                 spin_unlock_irqrestore(&up->port.lock, flags);
 617                 return IRQ_HANDLED;
 618         }
 619
 620         iir = serial_in(up, UART_IIR);
 621         if (iir & UART_IIR_NO_INT) {
 622                 spin_unlock_irqrestore(&up->port.lock, flags);
 623                 return IRQ_NONE;
 624         }
 625
 626         lsr = serial_in(up, UART_LSR);
 627         if (lsr & UART_LSR_DR)
 628                 receive_chars(up, &lsr);
 629         check_modem_status(up);
 630
 631         /* lsr will be renewed during the receive_chars */
 632         if (lsr & UART_LSR_THRE)
 633                 transmit_chars(up);
 634
 635         spin_unlock_irqrestore(&up->port.lock, flags);
 636         return IRQ_HANDLED;
 637 }
 638
 639 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 640 {
 641         struct uart_hsu_port *up = chan->uport;
 642         unsigned long flags;
 643         u32 int_sts;
 644
 645         spin_lock_irqsave(&up->port.lock, flags);
 646
 647         if (!up->use_dma || !up->running)
 648                 goto exit;
 649
 650         /*
 651          * No matter what situation, need read clear the IRQ status
 652          * There is a bug, see Errata 5, HSD 2900918
 653          */
 654         int_sts = chan_readl(chan, HSU_CH_SR);
 655
 656         /* Rx channel */
 657         if (chan->dirt == DMA_FROM_DEVICE)
 658                 hsu_dma_rx(up, int_sts);
 659
 660         /* Tx channel */
 661         if (chan->dirt == DMA_TO_DEVICE) {
 662                 chan_writel(chan, HSU_CH_CR, 0x0);
 663                 up->dma_tx_on = 0;
 664                 hsu_dma_tx(up);
 665         }
 666
 667 exit:
 668         spin_unlock_irqrestore(&up->port.lock, flags);
 669         return;
 670 }
 671
 672 static irqreturn_t dma_irq(int irq, void *dev_id)
 673 {
 674         struct hsu_port *hsu = dev_id;
 675         u32 int_sts, i;
 676
 677         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 678
 679         /* Currently we only have 6 channels may be used */
 680         for (i = 0; i < 6; i++) {
 681                 if (int_sts & 0x1)
 682                         dma_chan_irq(&hsu->chans[i]);
 683                 int_sts >>= 1;
 684         }
 685
 686         return IRQ_HANDLED;
 687 }
 688
 689 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 690 {
 691         struct uart_hsu_port *up =
 692                 container_of(port, struct uart_hsu_port, port);
 693         unsigned long flags;
 694         unsigned int ret;
 695
 696         spin_lock_irqsave(&up->port.lock, flags);
 697         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 698         spin_unlock_irqrestore(&up->port.lock, flags);
 699
 700         return ret;
 701 }
 702
 703 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 704 {
 705         struct uart_hsu_port *up =
 706                 container_of(port, struct uart_hsu_port, port);
 707         unsigned char status;
 708         unsigned int ret;
 709
 710         status = serial_in(up, UART_MSR);
 711
 712         ret = 0;
 713         if (status & UART_MSR_DCD)
 714                 ret |= TIOCM_CAR;
 715         if (status & UART_MSR_RI)
 716                 ret |= TIOCM_RNG;
 717         if (status & UART_MSR_DSR)
 718                 ret |= TIOCM_DSR;
 719         if (status & UART_MSR_CTS)
 720                 ret |= TIOCM_CTS;
 721         return ret;
 722 }
 723
 724 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 725 {
 726         struct uart_hsu_port *up =
 727                 container_of(port, struct uart_hsu_port, port);
 728         unsigned char mcr = 0;
 729
 730         if (mctrl & TIOCM_RTS)
 731                 mcr |= UART_MCR_RTS;
 732         if (mctrl & TIOCM_DTR)
 733                 mcr |= UART_MCR_DTR;
 734         if (mctrl & TIOCM_OUT1)
 735                 mcr |= UART_MCR_OUT1;
 736         if (mctrl & TIOCM_OUT2)
 737                 mcr |= UART_MCR_OUT2;
 738         if (mctrl & TIOCM_LOOP)
 739                 mcr |= UART_MCR_LOOP;
 740
 741         mcr |= up->mcr;
 742
 743         serial_out(up, UART_MCR, mcr);
 744 }
 745
 746 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 747 {
 748         struct uart_hsu_port *up =
 749                 container_of(port, struct uart_hsu_port, port);
 750         unsigned long flags;
 751
 752         spin_lock_irqsave(&up->port.lock, flags);
 753         if (break_state == -1)
 754                 up->lcr |= UART_LCR_SBC;
 755         else
 756                 up->lcr &= ~UART_LCR_SBC;
 757         serial_out(up, UART_LCR, up->lcr);
 758         spin_unlock_irqrestore(&up->port.lock, flags);
 759 }
 760
 761 /*
 762  * What special to do:
 763  * 1. chose the 64B fifo mode
 764  * 2. make sure not to select half empty mode for A0 stepping
 765  * 3. start dma or pio depends on configuration
 766  * 4. we only allocate dma memory when needed
 767  */
 768 static int serial_hsu_startup(struct uart_port *port)
 769 {
 770         struct uart_hsu_port *up =
 771                 container_of(port, struct uart_hsu_port, port);
 772         unsigned long flags;
 773
 774         /*
 775          * Clear the FIFO buffers and disable them.
 776          * (they will be reenabled in set_termios())
 777          */
 778         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 779         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 780                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 781         serial_out(up, UART_FCR, 0);
 782
 783         /* Clear the interrupt registers. */
 784         (void) serial_in(up, UART_LSR);
 785         (void) serial_in(up, UART_RX);
 786         (void) serial_in(up, UART_IIR);
 787         (void) serial_in(up, UART_MSR);
 788
 789         /* Now, initialize the UART, default is 8n1 */
 790         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 791
 792         spin_lock_irqsave(&up->port.lock, flags);
 793
 794         up->port.mctrl |= TIOCM_OUT2;
 795         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 796
 797         /*
 798          * Finally, enable interrupts.  Note: Modem status interrupts
 799          * are set via set_termios(), which will be occurring imminently
 800          * anyway, so we don't enable them here.
 801          */
 802         if (!up->use_dma)
 803                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 804         else
 805                 up->ier = 0;
 806         serial_out(up, UART_IER, up->ier);
 807
 808         spin_unlock_irqrestore(&up->port.lock, flags);
 809
 810         /* DMA init */
 811         if (up->use_dma) {
 812                 struct hsu_dma_buffer *dbuf;
 813                 struct circ_buf *xmit = &port->state->xmit;
 814
 815                 up->dma_tx_on = 0;
 816
 817                 /* First allocate the RX buffer */
 818                 dbuf = &up->rxbuf;
 819                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 820                 if (!dbuf->buf) {
 821                         up->use_dma = 0;
 822                         goto exit;
 823                 }
 824                 dbuf->dma_addr = dma_map_single(port->dev,
 825                                                 dbuf->buf,
 826                                                 HSU_DMA_BUF_SIZE,
 827                                                 DMA_FROM_DEVICE);
 828                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 829
 830                 /* Start the RX channel right now */
 831                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 832
 833                 /* Next init the TX DMA */
 834                 dbuf = &up->txbuf;
 835                 dbuf->buf = xmit->buf;
 836                 dbuf->dma_addr = dma_map_single(port->dev,
 837                                                dbuf->buf,
 838                                                UART_XMIT_SIZE,
 839                                                DMA_TO_DEVICE);
 840                 dbuf->dma_size = UART_XMIT_SIZE;
 841
 842                 /* This should not be changed all around */
 843                 chan_writel(up->txc, HSU_CH_BSR, 32);
 844                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 845                 dbuf->ofs = 0;
 846         }
 847
 848 exit:
 849          /* And clear the interrupt registers again for luck. */
 850         (void) serial_in(up, UART_LSR);
 851         (void) serial_in(up, UART_RX);
 852         (void) serial_in(up, UART_IIR);
 853         (void) serial_in(up, UART_MSR);
 854
 855         up->running = 1;
 856         return 0;
 857 }
 858
 859 static void serial_hsu_shutdown(struct uart_port *port)
 860 {
 861         struct uart_hsu_port *up =
 862                 container_of(port, struct uart_hsu_port, port);
 863         unsigned long flags;
 864
 865         del_timer_sync(&up->rxc->rx_timer);
 866
 867         /* Disable interrupts from this port */
 868         up->ier = 0;
 869         serial_out(up, UART_IER, 0);
 870         up->running = 0;
 871
 872         spin_lock_irqsave(&up->port.lock, flags);
 873         up->port.mctrl &= ~TIOCM_OUT2;
 874         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 875         spin_unlock_irqrestore(&up->port.lock, flags);
 876
 877         /* Disable break condition and FIFOs */
 878         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 879         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 880                                   UART_FCR_CLEAR_RCVR |
 881                                   UART_FCR_CLEAR_XMIT);
 882         serial_out(up, UART_FCR, 0);
 883 }
 884
 885 static void
 886 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 887                        struct ktermios *old)
 888 {
 889         struct uart_hsu_port *up =
 890                         container_of(port, struct uart_hsu_port, port);
 891         struct tty_struct *tty = port->state->port.tty;
 892         unsigned char cval, fcr = 0;
 893         unsigned long flags;
 894         unsigned int baud, quot;
 895         u32 mul = 0x3600;
 896         u32 ps = 0x10;
 897
 898         switch (termios->c_cflag & CSIZE) {
 899         case CS5:
 900                 cval = UART_LCR_WLEN5;
 901                 break;
 902         case CS6:
 903                 cval = UART_LCR_WLEN6;
 904                 break;
 905         case CS7:
 906                 cval = UART_LCR_WLEN7;
 907                 break;
 908         default:
 909         case CS8:
 910                 cval = UART_LCR_WLEN8;
 911                 break;
 912         }
 913
 914         /* CMSPAR isn't supported by this driver */
 915         if (tty)
 916                 tty->termios->c_cflag &= ~CMSPAR;
 917
 918         if (termios->c_cflag & CSTOPB)
 919                 cval |= UART_LCR_STOP;
 920         if (termios->c_cflag & PARENB)
 921                 cval |= UART_LCR_PARITY;
 922         if (!(termios->c_cflag & PARODD))
 923                 cval |= UART_LCR_EPAR;
 924
 925         /*
 926          * For those basic low baud rate we can get the direct
 927          * scalar from 2746800, like 115200 = 2746800/24, for those
 928          * higher baud rate, we have to handle them case by case,
 929          * but DIV reg is never touched as its default value 0x3d09
 930          */
 931         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 932         quot = uart_get_divisor(port, baud);
 933
 934         switch (baud) {
 935         case 3500000:
 936                 mul = 0x3345;
 937                 ps = 0xC;
 938                 quot = 1;
 939                 break;
 940         case 2500000:
 941                 mul = 0x2710;
 942                 ps = 0x10;
 943                 quot = 1;
 944                 break;
 945         case 18432000:
 946                 mul = 0x2400;
 947                 ps = 0x10;
 948                 quot = 1;
 949                 break;
 950         case 1500000:
 951                 mul = 0x1D4C;
 952                 ps = 0xc;
 953                 quot = 1;
 954                 break;
 955         default:
 956                 ;
 957         }
 958
 959         if ((up->port.uartclk / quot) < (2400 * 16))
 960                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 961         else if ((up->port.uartclk / quot) < (230400 * 16))
 962                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 963         else
 964                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 965
 966         fcr |= UART_FCR_HSU_64B_FIFO;
 967 #ifdef MFD_HSU_A0_STEPPING
 968         /* A0 doesn't support half empty IRQ */
 969         fcr |= UART_FCR_FULL_EMPT_TXI;
 970 #endif
 971
 972         /*
 973          * Ok, we're now changing the port state.  Do it with
 974          * interrupts disabled.
 975          */
 976         spin_lock_irqsave(&up->port.lock, flags);
 977
 978         /* Update the per-port timeout */
 979         uart_update_timeout(port, termios->c_cflag, baud);
 980
 981         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 982         if (termios->c_iflag & INPCK)
 983                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 984         if (termios->c_iflag & (BRKINT | PARMRK))
 985                 up->port.read_status_mask |= UART_LSR_BI;
 986
 987         /* Characters to ignore */
 988         up->port.ignore_status_mask = 0;
 989         if (termios->c_iflag & IGNPAR)
 990                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 991         if (termios->c_iflag & IGNBRK) {
 992                 up->port.ignore_status_mask |= UART_LSR_BI;
 993                 /*
 994                  * If we're ignoring parity and break indicators,
 995                  * ignore overruns too (for real raw support).
 996                  */
 997                 if (termios->c_iflag & IGNPAR)
 998                         up->port.ignore_status_mask |= UART_LSR_OE;
 999         }
1000
1001         /* Ignore all characters if CREAD is not set */
1002         if ((termios->c_cflag & CREAD) == 0)
1003                 up->port.ignore_status_mask |= UART_LSR_DR;
1004
1005         /*
1006          * CTS flow control flag and modem status interrupts, disable
1007          * MSI by default
1008          */
1009         up->ier &= ~UART_IER_MSI;
1010         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1011                 up->ier |= UART_IER_MSI;
1012
1013         serial_out(up, UART_IER, up->ier);
1014
1015         if (termios->c_cflag & CRTSCTS)
1016                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1017         else
1018                 up->mcr &= ~UART_MCR_AFE;
1019
1020         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1021         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1022         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1023         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1024         serial_out(up, UART_MUL, mul);                  /* set MUL */
1025         serial_out(up, UART_PS, ps);                    /* set PS */
1026         up->lcr = cval;                                 /* Save LCR */
1027         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1028         serial_out(up, UART_FCR, fcr);
1029         spin_unlock_irqrestore(&up->port.lock, flags);
1030 }
1031
1032 static void
1033 serial_hsu_pm(struct uart_port *port, unsigned int state,
1034               unsigned int oldstate)
1035 {
1036 }
1037
1038 static void serial_hsu_release_port(struct uart_port *port)
1039 {
1040 }
1041
1042 static int serial_hsu_request_port(struct uart_port *port)
1043 {
1044         return 0;
1045 }
1046
1047 static void serial_hsu_config_port(struct uart_port *port, int flags)
1048 {
1049         struct uart_hsu_port *up =
1050                 container_of(port, struct uart_hsu_port, port);
1051         up->port.type = PORT_MFD;
1052 }
1053
1054 static int
1055 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1056 {
1057         /* We don't want the core code to modify any port params */
1058         return -EINVAL;
1059 }
1060
1061 static const char *
1062 serial_hsu_type(struct uart_port *port)
1063 {
1064         struct uart_hsu_port *up =
1065                 container_of(port, struct uart_hsu_port, port);
1066         return up->name;
1067 }
1068
1069 /* Mainly for uart console use */
1070 static struct uart_hsu_port *serial_hsu_ports[3];
1071 static struct uart_driver serial_hsu_reg;
1072
1073 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1074
1075 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1076
1077 /* Wait for transmitter & holding register to empty */
1078 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1079 {
1080         unsigned int status, tmout = 1000;
1081
1082         /* Wait up to 1ms for the character to be sent. */
1083         do {
1084                 status = serial_in(up, UART_LSR);
1085
1086                 if (status & UART_LSR_BI)
1087                         up->lsr_break_flag = UART_LSR_BI;
1088
1089                 if (--tmout == 0)
1090                         break;
1091                 udelay(1);
1092         } while (!(status & BOTH_EMPTY));
1093
1094         /* Wait up to 1s for flow control if necessary */
1095         if (up->port.flags & UPF_CONS_FLOW) {
1096                 tmout = 1000000;
1097                 while (--tmout &&
1098                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1099                         udelay(1);
1100         }
1101 }
1102
1103 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1104 {
1105         struct uart_hsu_port *up =
1106                 container_of(port, struct uart_hsu_port, port);
1107
1108         wait_for_xmitr(up);
1109         serial_out(up, UART_TX, ch);
1110 }
1111
1112 /*
1113  * Print a string to the serial port trying not to disturb
1114  * any possible real use of the port...
1115  *
1116  *      The console_lock must be held when we get here.
1117  */
1118 static void
1119 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1120 {
1121         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1122         unsigned long flags;
1123         unsigned int ier;
1124         int locked = 1;
1125
1126         local_irq_save(flags);
1127         if (up->port.sysrq)
1128                 locked = 0;
1129         else if (oops_in_progress) {
1130                 locked = spin_trylock(&up->port.lock);
1131         } else
1132                 spin_lock(&up->port.lock);
1133
1134         /* First save the IER then disable the interrupts */
1135         ier = serial_in(up, UART_IER);
1136         serial_out(up, UART_IER, 0);
1137
1138         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1139
1140         /*
1141          * Finally, wait for transmitter to become empty
1142          * and restore the IER
1143          */
1144         wait_for_xmitr(up);
1145         serial_out(up, UART_IER, ier);
1146
1147         if (locked)
1148                 spin_unlock(&up->port.lock);
1149         local_irq_restore(flags);
1150 }
1151
1152 static struct console serial_hsu_console;
1153
1154 static int __init
1155 serial_hsu_console_setup(struct console *co, char *options)
1156 {
1157         struct uart_hsu_port *up;
1158         int baud = 115200;
1159         int bits = 8;
1160         int parity = 'n';
1161         int flow = 'n';
1162         int ret;
1163
1164         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1165                 co->index = 0;
1166         up = serial_hsu_ports[co->index];
1167         if (!up)
1168                 return -ENODEV;
1169
1170         if (options)
1171                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1172
1173         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1174
1175         return ret;
1176 }
1177
1178 static struct console serial_hsu_console = {
1179         .name           = "ttyMFD",
1180         .write          = serial_hsu_console_write,
1181         .device         = uart_console_device,
1182         .setup          = serial_hsu_console_setup,
1183         .flags          = CON_PRINTBUFFER,
1184         .index          = 2,
1185         .data           = &serial_hsu_reg,
1186 };
1187 #endif
1188
1189 struct uart_ops serial_hsu_pops = {
1190         .tx_empty       = serial_hsu_tx_empty,
1191         .set_mctrl      = serial_hsu_set_mctrl,
1192         .get_mctrl      = serial_hsu_get_mctrl,
1193         .stop_tx        = serial_hsu_stop_tx,
1194         .start_tx       = serial_hsu_start_tx,
1195         .stop_rx        = serial_hsu_stop_rx,
1196         .enable_ms      = serial_hsu_enable_ms,
1197         .break_ctl      = serial_hsu_break_ctl,
1198         .startup        = serial_hsu_startup,
1199         .shutdown       = serial_hsu_shutdown,
1200         .set_termios    = serial_hsu_set_termios,
1201         .pm             = serial_hsu_pm,
1202         .type           = serial_hsu_type,
1203         .release_port   = serial_hsu_release_port,
1204         .request_port   = serial_hsu_request_port,
1205         .config_port    = serial_hsu_config_port,
1206         .verify_port    = serial_hsu_verify_port,
1207 };
1208
1209 static struct uart_driver serial_hsu_reg = {
1210         .owner          = THIS_MODULE,
1211         .driver_name    = "MFD serial",
1212         .dev_name       = "ttyMFD",
1213         .major          = TTY_MAJOR,
1214         .minor          = 128,
1215         .nr             = 3,
1216 };
1217
1218 #ifdef CONFIG_PM
1219 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1220 {
1221         void *priv = pci_get_drvdata(pdev);
1222         struct uart_hsu_port *up;
1223
1224         /* Make sure this is not the internal dma controller */
1225         if (priv && (pdev->device != 0x081E)) {
1226                 up = priv;
1227                 uart_suspend_port(&serial_hsu_reg, &up->port);
1228         }
1229
1230         pci_save_state(pdev);
1231         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1232         return 0;
1233 }
1234
1235 static int serial_hsu_resume(struct pci_dev *pdev)
1236 {
1237         void *priv = pci_get_drvdata(pdev);
1238         struct uart_hsu_port *up;
1239         int ret;
1240
1241         pci_set_power_state(pdev, PCI_D0);
1242         pci_restore_state(pdev);
1243
1244         ret = pci_enable_device(pdev);
1245         if (ret)
1246                 dev_warn(&pdev->dev,
1247                         "HSU: can't re-enable device, try to continue\n");
1248
1249         if (priv && (pdev->device != 0x081E)) {
1250                 up = priv;
1251                 uart_resume_port(&serial_hsu_reg, &up->port);
1252         }
1253         return 0;
1254 }
1255 #else
1256 #define serial_hsu_suspend      NULL
1257 #define serial_hsu_resume       NULL
1258 #endif
1259
1260 /* temp global pointer before we settle down on using one or four PCI dev */
1261 static struct hsu_port *phsu;
1262
1263 static int serial_hsu_probe(struct pci_dev *pdev,
1264                                 const struct pci_device_id *ent)
1265 {
1266         struct uart_hsu_port *uport;
1267         int index, ret;
1268
1269         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1270                 pdev->vendor, pdev->device);
1271
1272         switch (pdev->device) {
1273         case 0x081B:
1274                 index = 0;
1275                 break;
1276         case 0x081C:
1277                 index = 1;
1278                 break;
1279         case 0x081D:
1280                 index = 2;
1281                 break;
1282         case 0x081E:
1283                 /* internal DMA controller */
1284                 index = 3;
1285                 break;
1286         default:
1287                 dev_err(&pdev->dev, "HSU: out of index!");
1288                 return -ENODEV;
1289         }
1290
1291         ret = pci_enable_device(pdev);
1292         if (ret)
1293                 return ret;
1294
1295         if (index == 3) {
1296                 /* DMA controller */
1297                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1298                 if (ret) {
1299                         dev_err(&pdev->dev, "can not get IRQ\n");
1300                         goto err_disable;
1301                 }
1302                 pci_set_drvdata(pdev, phsu);
1303         } else {
1304                 /* UART port 0~2 */
1305                 uport = &phsu->port[index];
1306                 uport->port.irq = pdev->irq;
1307                 uport->port.dev = &pdev->dev;
1308                 uport->dev = &pdev->dev;
1309
1310                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1311                 if (ret) {
1312                         dev_err(&pdev->dev, "can not get IRQ\n");
1313                         goto err_disable;
1314                 }
1315                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1316
1317 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1318                 if (index == 2) {
1319                         register_console(&serial_hsu_console);
1320                         uport->port.cons = &serial_hsu_console;
1321                 }
1322 #endif
1323                 pci_set_drvdata(pdev, uport);
1324         }
1325
1326         return 0;
1327
1328 err_disable:
1329         pci_disable_device(pdev);
1330         return ret;
1331 }
1332
1333 static void hsu_dma_rx_timeout(unsigned long data)
1334 {
1335         struct hsu_dma_chan *chan = (void *)data;
1336         struct uart_hsu_port *up = chan->uport;
1337         struct hsu_dma_buffer *dbuf = &up->rxbuf;
1338         int count = 0;
1339         unsigned long flags;
1340
1341         spin_lock_irqsave(&up->port.lock, flags);
1342
1343         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1344
1345         if (!count) {
1346                 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1347                 goto exit;
1348         }
1349
1350         hsu_dma_rx(up, 0);
1351 exit:
1352         spin_unlock_irqrestore(&up->port.lock, flags);
1353 }
1354
1355 static void hsu_global_init(void)
1356 {
1357         struct hsu_port *hsu;
1358         struct uart_hsu_port *uport;
1359         struct hsu_dma_chan *dchan;
1360         int i, ret;
1361
1362         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1363         if (!hsu)
1364                 return;
1365
1366         /* Get basic io resource and map it */
1367         hsu->paddr = 0xffa28000;
1368         hsu->iolen = 0x1000;
1369
1370         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1371                 pr_warning("HSU: error in request mem region\n");
1372
1373         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1374         if (!hsu->reg) {
1375                 pr_err("HSU: error in ioremap\n");
1376                 ret = -ENOMEM;
1377                 goto err_free_region;
1378         }
1379
1380         /* Initialise the 3 UART ports */
1381         uport = hsu->port;
1382         for (i = 0; i < 3; i++) {
1383                 uport->port.type = PORT_MFD;
1384                 uport->port.iotype = UPIO_MEM;
1385                 uport->port.mapbase = (resource_size_t)hsu->paddr
1386                                         + HSU_PORT_REG_OFFSET
1387                                         + i * HSU_PORT_REG_LENGTH;
1388                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1389                                         + i * HSU_PORT_REG_LENGTH;
1390
1391                 sprintf(uport->name, "hsu_port%d", i);
1392                 uport->port.fifosize = 64;
1393                 uport->port.ops = &serial_hsu_pops;
1394                 uport->port.line = i;
1395                 uport->port.flags = UPF_IOREMAP;
1396                 /* set the scalable maxim support rate to 2746800 bps */
1397                 uport->port.uartclk = 115200 * 24 * 16;
1398
1399                 uport->running = 0;
1400                 uport->txc = &hsu->chans[i * 2];
1401                 uport->rxc = &hsu->chans[i * 2 + 1];
1402
1403                 serial_hsu_ports[i] = uport;
1404                 uport->index = i;
1405                 uport++;
1406         }
1407
1408         /* Initialise 6 dma channels */
1409         dchan = hsu->chans;
1410         for (i = 0; i < 6; i++) {
1411                 dchan->id = i;
1412                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1413                 dchan->uport = &hsu->port[i/2];
1414                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1415                                 i * HSU_DMA_CHANS_REG_LENGTH;
1416
1417                 /* Work around for RX */
1418                 if (dchan->dirt == DMA_FROM_DEVICE) {
1419                         init_timer(&dchan->rx_timer);
1420                         dchan->rx_timer.function = hsu_dma_rx_timeout;
1421                         dchan->rx_timer.data = (unsigned long)dchan;
1422                 }
1423                 dchan++;
1424         }
1425
1426         phsu = hsu;
1427         hsu_debugfs_init(hsu);
1428         return;
1429
1430 err_free_region:
1431         release_mem_region(hsu->paddr, hsu->iolen);
1432         kfree(hsu);
1433         return;
1434 }
1435
1436 static void serial_hsu_remove(struct pci_dev *pdev)
1437 {
1438         void *priv = pci_get_drvdata(pdev);
1439         struct uart_hsu_port *up;
1440
1441         if (!priv)
1442                 return;
1443
1444         /* For port 0/1/2, priv is the address of uart_hsu_port */
1445         if (pdev->device != 0x081E) {
1446                 up = priv;
1447                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1448         }
1449
1450         pci_set_drvdata(pdev, NULL);
1451         free_irq(pdev->irq, priv);
1452         pci_disable_device(pdev);
1453 }
1454
1455 /* First 3 are UART ports, and the 4th is the DMA */
1456 static const struct pci_device_id pci_ids[] __devinitdata = {
1457         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1458         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1459         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1460         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1461         {},
1462 };
1463
1464 static struct pci_driver hsu_pci_driver = {
1465         .name =         "HSU serial",
1466         .id_table =     pci_ids,
1467         .probe =        serial_hsu_probe,
1468         .remove =       __devexit_p(serial_hsu_remove),
1469         .suspend =      serial_hsu_suspend,
1470         .resume =       serial_hsu_resume,
1471 };
1472
1473 static int __init hsu_pci_init(void)
1474 {
1475         int ret;
1476
1477         hsu_global_init();
1478
1479         ret = uart_register_driver(&serial_hsu_reg);
1480         if (ret)
1481                 return ret;
1482
1483         return pci_register_driver(&hsu_pci_driver);
1484 }
1485
1486 static void __exit hsu_pci_exit(void)
1487 {
1488         pci_unregister_driver(&hsu_pci_driver);
1489         uart_unregister_driver(&serial_hsu_reg);
1490
1491         hsu_debugfs_remove(phsu);
1492
1493         kfree(phsu);
1494 }
1495
1496 module_init(hsu_pci_init);
1497 module_exit(hsu_pci_exit);
1498
1499 MODULE_LICENSE("GPL v2");
1500 MODULE_ALIAS("platform:medfield-hsu");