drivers/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. In A0 stepping, UART will not support TX half empty flag
  20  *
  21  * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  22  *    asserted, only when the HW is reset the DDCD and DDSR will
  23  *    be triggered
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/console.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include <linux/serial_reg.h>
  32 #include <linux/circ_buf.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/tty.h>
  36 #include <linux/tty_flip.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/serial_mfd.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/pci.h>
  41 #include <linux/io.h>
  42 #include <linux/debugfs.h>
  43
  44 #define  MFD_HSU_A0_STEPPING    1
  45
  46 #define HSU_DMA_BUF_SIZE        2048
  47
  48 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  49 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  50
  51 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  52 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  53
  54 #define HSU_DMA_TIMEOUT_CHECK_FREQ      (HZ/10)
  55
  56 struct hsu_dma_buffer {
  57         u8              *buf;
  58         dma_addr_t      dma_addr;
  59         u32             dma_size;
  60         u32             ofs;
  61 };
  62
  63 struct hsu_dma_chan {
  64         u32     id;
  65         enum dma_data_direction dirt;
  66         struct uart_hsu_port    *uport;
  67         void __iomem            *reg;
  68         struct timer_list       rx_timer; /* only needed by RX channel */
  69 };
  70
  71 struct uart_hsu_port {
  72         struct uart_port        port;
  73         unsigned char           ier;
  74         unsigned char           lcr;
  75         unsigned char           mcr;
  76         unsigned int            lsr_break_flag;
  77         char                    name[12];
  78         int                     index;
  79         struct device           *dev;
  80
  81         struct hsu_dma_chan     *txc;
  82         struct hsu_dma_chan     *rxc;
  83         struct hsu_dma_buffer   txbuf;
  84         struct hsu_dma_buffer   rxbuf;
  85         int                     use_dma;        /* flag for DMA/PIO */
  86         int                     running;
  87         int                     dma_tx_on;
  88 };
  89
  90 /* Top level data structure of HSU */
  91 struct hsu_port {
  92         void __iomem    *reg;
  93         unsigned long   paddr;
  94         unsigned long   iolen;
  95         u32             irq;
  96
  97         struct uart_hsu_port    port[3];
  98         struct hsu_dma_chan     chans[10];
  99
 100         struct dentry *debugfs;
 101 };
 102
 103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 104 {
 105         unsigned int val;
 106
 107         if (offset > UART_MSR) {
 108                 offset <<= 2;
 109                 val = readl(up->port.membase + offset);
 110         } else
 111                 val = (unsigned int)readb(up->port.membase + offset);
 112
 113         return val;
 114 }
 115
 116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 117 {
 118         if (offset > UART_MSR) {
 119                 offset <<= 2;
 120                 writel(value, up->port.membase + offset);
 121         } else {
 122                 unsigned char val = value & 0xff;
 123                 writeb(val, up->port.membase + offset);
 124         }
 125 }
 126
 127 #ifdef CONFIG_DEBUG_FS
 128
 129 #define HSU_REGS_BUFSIZE        1024
 130
 131 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 132 {
 133         file->private_data = inode->i_private;
 134         return 0;
 135 }
 136
 137 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 138                                 size_t count, loff_t *ppos)
 139 {
 140         struct uart_hsu_port *up = file->private_data;
 141         char *buf;
 142         u32 len = 0;
 143         ssize_t ret;
 144
 145         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 146         if (!buf)
 147                 return 0;
 148
 149         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 150                         "MFD HSU port[%d] regs:\n", up->index);
 151
 152         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 153                         "=================================\n");
 154         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 155                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 156         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 157                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 158         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 159                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 160         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 161                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 162         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 163                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 164         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 165                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 166         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 167                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 168         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 169                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 170         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 171                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 172         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 173                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 174
 175         if (len > HSU_REGS_BUFSIZE)
 176                 len = HSU_REGS_BUFSIZE;
 177
 178         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 179         kfree(buf);
 180         return ret;
 181 }
 182
 183 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 184                                 size_t count, loff_t *ppos)
 185 {
 186         struct hsu_dma_chan *chan = file->private_data;
 187         char *buf;
 188         u32 len = 0;
 189         ssize_t ret;
 190
 191         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 192         if (!buf)
 193                 return 0;
 194
 195         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 196                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 197
 198         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 199                         "=================================\n");
 200         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 201                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 202         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 203                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 204         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 205                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 206         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 207                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 208         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 209                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 210         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 211                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 212         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 213                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 214         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 215                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 216         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 217                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 218         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 219                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 220         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 221                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 222         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 223                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 224
 225         if (len > HSU_REGS_BUFSIZE)
 226                 len = HSU_REGS_BUFSIZE;
 227
 228         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 229         kfree(buf);
 230         return ret;
 231 }
 232
 233 static const struct file_operations port_regs_ops = {
 234         .owner          = THIS_MODULE,
 235         .open           = hsu_show_regs_open,
 236         .read           = port_show_regs,
 237 };
 238
 239 static const struct file_operations dma_regs_ops = {
 240         .owner          = THIS_MODULE,
 241         .open           = hsu_show_regs_open,
 242         .read           = dma_show_regs,
 243 };
 244
 245 static int hsu_debugfs_init(struct hsu_port *hsu)
 246 {
 247         int i;
 248         char name[32];
 249
 250         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 251         if (!hsu->debugfs)
 252                 return -ENOMEM;
 253
 254         for (i = 0; i < 3; i++) {
 255                 snprintf(name, sizeof(name), "port_%d_regs", i);
 256                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 257                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 258         }
 259
 260         for (i = 0; i < 6; i++) {
 261                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 262                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 263                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void hsu_debugfs_remove(struct hsu_port *hsu)
 270 {
 271         if (hsu->debugfs)
 272                 debugfs_remove_recursive(hsu->debugfs);
 273 }
 274
 275 #else
 276 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 277 {
 278         return 0;
 279 }
 280
 281 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 282 {
 283 }
 284 #endif /* CONFIG_DEBUG_FS */
 285
 286 static void serial_hsu_enable_ms(struct uart_port *port)
 287 {
 288         struct uart_hsu_port *up =
 289                 container_of(port, struct uart_hsu_port, port);
 290
 291         up->ier |= UART_IER_MSI;
 292         serial_out(up, UART_IER, up->ier);
 293 }
 294
 295 void hsu_dma_tx(struct uart_hsu_port *up)
 296 {
 297         struct circ_buf *xmit = &up->port.state->xmit;
 298         struct hsu_dma_buffer *dbuf = &up->txbuf;
 299         int count;
 300
 301         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 302         if (up->dma_tx_on)
 303                 return;
 304
 305         /* Update the circ buf info */
 306         xmit->tail += dbuf->ofs;
 307         xmit->tail &= UART_XMIT_SIZE - 1;
 308
 309         up->port.icount.tx += dbuf->ofs;
 310         dbuf->ofs = 0;
 311
 312         /* Disable the channel */
 313         chan_writel(up->txc, HSU_CH_CR, 0x0);
 314
 315         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 316                 dma_sync_single_for_device(up->port.dev,
 317                                            dbuf->dma_addr,
 318                                            dbuf->dma_size,
 319                                            DMA_TO_DEVICE);
 320
 321                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 322                 dbuf->ofs = count;
 323
 324                 /* Reprogram the channel */
 325                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 326                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 327
 328                 /* Reenable the channel */
 329                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 330                                                  | (0x1 << 8)
 331                                                  | (0x1 << 16)
 332                                                  | (0x1 << 24));
 333                 up->dma_tx_on = 1;
 334                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 335         }
 336
 337         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 338                 uart_write_wakeup(&up->port);
 339 }
 340
 341 /* The buffer is already cache coherent */
 342 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 343 {
 344         dbuf->ofs = 0;
 345
 346         chan_writel(rxc, HSU_CH_BSR, 32);
 347         chan_writel(rxc, HSU_CH_MOTSR, 4);
 348
 349         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 350         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 351         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 352                                          | (0x1 << 16)
 353                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 354                                          );
 355         chan_writel(rxc, HSU_CH_CR, 0x3);
 356
 357         mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
 358 }
 359
 360 /* Protected by spin_lock_irqsave(port->lock) */
 361 static void serial_hsu_start_tx(struct uart_port *port)
 362 {
 363         struct uart_hsu_port *up =
 364                 container_of(port, struct uart_hsu_port, port);
 365
 366         if (up->use_dma) {
 367                 hsu_dma_tx(up);
 368         } else if (!(up->ier & UART_IER_THRI)) {
 369                 up->ier |= UART_IER_THRI;
 370                 serial_out(up, UART_IER, up->ier);
 371         }
 372 }
 373
 374 static void serial_hsu_stop_tx(struct uart_port *port)
 375 {
 376         struct uart_hsu_port *up =
 377                 container_of(port, struct uart_hsu_port, port);
 378         struct hsu_dma_chan *txc = up->txc;
 379
 380         if (up->use_dma)
 381                 chan_writel(txc, HSU_CH_CR, 0x0);
 382         else if (up->ier & UART_IER_THRI) {
 383                 up->ier &= ~UART_IER_THRI;
 384                 serial_out(up, UART_IER, up->ier);
 385         }
 386 }
 387
 388 /* This is always called in spinlock protected mode, so
 389  * modify timeout timer is safe here */
 390 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 391 {
 392         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 393         struct hsu_dma_chan *chan = up->rxc;
 394         struct uart_port *port = &up->port;
 395         struct tty_struct *tty = port->state->port.tty;
 396         int count;
 397
 398         if (!tty)
 399                 return;
 400
 401         /*
 402          * First need to know how many is already transferred,
 403          * then check if its a timeout DMA irq, and return
 404          * the trail bytes out, push them up and reenable the
 405          * channel
 406          */
 407
 408         /* Timeout IRQ, need wait some time, see Errata 2 */
 409         if (int_sts & 0xf00)
 410                 udelay(2);
 411
 412         /* Stop the channel */
 413         chan_writel(chan, HSU_CH_CR, 0x0);
 414
 415         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 416         if (!count) {
 417                 /* Restart the channel before we leave */
 418                 chan_writel(chan, HSU_CH_CR, 0x3);
 419                 return;
 420         }
 421         del_timer(&chan->rx_timer);
 422
 423         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 424                         dbuf->dma_size, DMA_FROM_DEVICE);
 425
 426         /*
 427          * Head will only wrap around when we recycle
 428          * the DMA buffer, and when that happens, we
 429          * explicitly set tail to 0. So head will
 430          * always be greater than tail.
 431          */
 432         tty_insert_flip_string(tty, dbuf->buf, count);
 433         port->icount.rx += count;
 434
 435         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 436                         dbuf->dma_size, DMA_FROM_DEVICE);
 437
 438         /* Reprogram the channel */
 439         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 440         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 441         chan_writel(chan, HSU_CH_DCR, 0x1
 442                                          | (0x1 << 8)
 443                                          | (0x1 << 16)
 444                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 445                                          );
 446         tty_flip_buffer_push(tty);
 447
 448         chan_writel(chan, HSU_CH_CR, 0x3);
 449         chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
 450         add_timer(&chan->rx_timer);
 451
 452 }
 453
 454 static void serial_hsu_stop_rx(struct uart_port *port)
 455 {
 456         struct uart_hsu_port *up =
 457                 container_of(port, struct uart_hsu_port, port);
 458         struct hsu_dma_chan *chan = up->rxc;
 459
 460         if (up->use_dma)
 461                 chan_writel(chan, HSU_CH_CR, 0x2);
 462         else {
 463                 up->ier &= ~UART_IER_RLSI;
 464                 up->port.read_status_mask &= ~UART_LSR_DR;
 465                 serial_out(up, UART_IER, up->ier);
 466         }
 467 }
 468
 469 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 470 {
 471         struct tty_struct *tty = up->port.state->port.tty;
 472         unsigned int ch, flag;
 473         unsigned int max_count = 256;
 474
 475         if (!tty)
 476                 return;
 477
 478         do {
 479                 ch = serial_in(up, UART_RX);
 480                 flag = TTY_NORMAL;
 481                 up->port.icount.rx++;
 482
 483                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 484                                        UART_LSR_FE | UART_LSR_OE))) {
 485
 486                         dev_warn(up->dev, "We really rush into ERR/BI case"
 487                                 "status = 0x%02x", *status);
 488                         /* For statistics only */
 489                         if (*status & UART_LSR_BI) {
 490                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 491                                 up->port.icount.brk++;
 492                                 /*
 493                                  * We do the SysRQ and SAK checking
 494                                  * here because otherwise the break
 495                                  * may get masked by ignore_status_mask
 496                                  * or read_status_mask.
 497                                  */
 498                                 if (uart_handle_break(&up->port))
 499                                         goto ignore_char;
 500                         } else if (*status & UART_LSR_PE)
 501                                 up->port.icount.parity++;
 502                         else if (*status & UART_LSR_FE)
 503                                 up->port.icount.frame++;
 504                         if (*status & UART_LSR_OE)
 505                                 up->port.icount.overrun++;
 506
 507                         /* Mask off conditions which should be ignored. */
 508                         *status &= up->port.read_status_mask;
 509
 510 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 511                         if (up->port.cons &&
 512                                 up->port.cons->index == up->port.line) {
 513                                 /* Recover the break flag from console xmit */
 514                                 *status |= up->lsr_break_flag;
 515                                 up->lsr_break_flag = 0;
 516                         }
 517 #endif
 518                         if (*status & UART_LSR_BI) {
 519                                 flag = TTY_BREAK;
 520                         } else if (*status & UART_LSR_PE)
 521                                 flag = TTY_PARITY;
 522                         else if (*status & UART_LSR_FE)
 523                                 flag = TTY_FRAME;
 524                 }
 525
 526                 if (uart_handle_sysrq_char(&up->port, ch))
 527                         goto ignore_char;
 528
 529                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 530         ignore_char:
 531                 *status = serial_in(up, UART_LSR);
 532         } while ((*status & UART_LSR_DR) && max_count--);
 533         tty_flip_buffer_push(tty);
 534 }
 535
 536 static void transmit_chars(struct uart_hsu_port *up)
 537 {
 538         struct circ_buf *xmit = &up->port.state->xmit;
 539         int count;
 540
 541         if (up->port.x_char) {
 542                 serial_out(up, UART_TX, up->port.x_char);
 543                 up->port.icount.tx++;
 544                 up->port.x_char = 0;
 545                 return;
 546         }
 547         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 548                 serial_hsu_stop_tx(&up->port);
 549                 return;
 550         }
 551
 552 #ifndef MFD_HSU_A0_STEPPING
 553         count = up->port.fifosize / 2;
 554 #else
 555         /*
 556          * A0 only supports fully empty IRQ, and the first char written
 557          * into it won't clear the EMPT bit, so we may need be cautious
 558          * by useing a shorter buffer
 559          */
 560         count = up->port.fifosize - 4;
 561 #endif
 562         do {
 563                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 564                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 565
 566                 up->port.icount.tx++;
 567                 if (uart_circ_empty(xmit))
 568                         break;
 569         } while (--count > 0);
 570
 571         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 572                 uart_write_wakeup(&up->port);
 573
 574         if (uart_circ_empty(xmit))
 575                 serial_hsu_stop_tx(&up->port);
 576 }
 577
 578 static inline void check_modem_status(struct uart_hsu_port *up)
 579 {
 580         int status;
 581
 582         status = serial_in(up, UART_MSR);
 583
 584         if ((status & UART_MSR_ANY_DELTA) == 0)
 585                 return;
 586
 587         if (status & UART_MSR_TERI)
 588                 up->port.icount.rng++;
 589         if (status & UART_MSR_DDSR)
 590                 up->port.icount.dsr++;
 591         /* We may only get DDCD when HW init and reset */
 592         if (status & UART_MSR_DDCD)
 593                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 594         /* Will start/stop_tx accordingly */
 595         if (status & UART_MSR_DCTS)
 596                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 597
 598         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 599 }
 600
 601 /*
 602  * This handles the interrupt from one port.
 603  */
 604 static irqreturn_t port_irq(int irq, void *dev_id)
 605 {
 606         struct uart_hsu_port *up = dev_id;
 607         unsigned int iir, lsr;
 608         unsigned long flags;
 609
 610         if (unlikely(!up->running))
 611                 return IRQ_NONE;
 612
 613         spin_lock_irqsave(&up->port.lock, flags);
 614         if (up->use_dma) {
 615                 lsr = serial_in(up, UART_LSR);
 616                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 617                                        UART_LSR_FE | UART_LSR_OE)))
 618                         dev_warn(up->dev,
 619                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 620                                 lsr);
 621                 check_modem_status(up);
 622                 spin_unlock_irqrestore(&up->port.lock, flags);
 623                 return IRQ_HANDLED;
 624         }
 625
 626         iir = serial_in(up, UART_IIR);
 627         if (iir & UART_IIR_NO_INT) {
 628                 spin_unlock_irqrestore(&up->port.lock, flags);
 629                 return IRQ_NONE;
 630         }
 631
 632         lsr = serial_in(up, UART_LSR);
 633         if (lsr & UART_LSR_DR)
 634                 receive_chars(up, &lsr);
 635         check_modem_status(up);
 636
 637         /* lsr will be renewed during the receive_chars */
 638         if (lsr & UART_LSR_THRE)
 639                 transmit_chars(up);
 640
 641         spin_unlock_irqrestore(&up->port.lock, flags);
 642         return IRQ_HANDLED;
 643 }
 644
 645 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 646 {
 647         struct uart_hsu_port *up = chan->uport;
 648         unsigned long flags;
 649         u32 int_sts;
 650
 651         spin_lock_irqsave(&up->port.lock, flags);
 652
 653         if (!up->use_dma || !up->running)
 654                 goto exit;
 655
 656         /*
 657          * No matter what situation, need read clear the IRQ status
 658          * There is a bug, see Errata 5, HSD 2900918
 659          */
 660         int_sts = chan_readl(chan, HSU_CH_SR);
 661
 662         /* Rx channel */
 663         if (chan->dirt == DMA_FROM_DEVICE)
 664                 hsu_dma_rx(up, int_sts);
 665
 666         /* Tx channel */
 667         if (chan->dirt == DMA_TO_DEVICE) {
 668                 chan_writel(chan, HSU_CH_CR, 0x0);
 669                 up->dma_tx_on = 0;
 670                 hsu_dma_tx(up);
 671         }
 672
 673 exit:
 674         spin_unlock_irqrestore(&up->port.lock, flags);
 675         return;
 676 }
 677
 678 static irqreturn_t dma_irq(int irq, void *dev_id)
 679 {
 680         struct hsu_port *hsu = dev_id;
 681         u32 int_sts, i;
 682
 683         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 684
 685         /* Currently we only have 6 channels may be used */
 686         for (i = 0; i < 6; i++) {
 687                 if (int_sts & 0x1)
 688                         dma_chan_irq(&hsu->chans[i]);
 689                 int_sts >>= 1;
 690         }
 691
 692         return IRQ_HANDLED;
 693 }
 694
 695 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 696 {
 697         struct uart_hsu_port *up =
 698                 container_of(port, struct uart_hsu_port, port);
 699         unsigned long flags;
 700         unsigned int ret;
 701
 702         spin_lock_irqsave(&up->port.lock, flags);
 703         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 704         spin_unlock_irqrestore(&up->port.lock, flags);
 705
 706         return ret;
 707 }
 708
 709 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 710 {
 711         struct uart_hsu_port *up =
 712                 container_of(port, struct uart_hsu_port, port);
 713         unsigned char status;
 714         unsigned int ret;
 715
 716         status = serial_in(up, UART_MSR);
 717
 718         ret = 0;
 719         if (status & UART_MSR_DCD)
 720                 ret |= TIOCM_CAR;
 721         if (status & UART_MSR_RI)
 722                 ret |= TIOCM_RNG;
 723         if (status & UART_MSR_DSR)
 724                 ret |= TIOCM_DSR;
 725         if (status & UART_MSR_CTS)
 726                 ret |= TIOCM_CTS;
 727         return ret;
 728 }
 729
 730 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 731 {
 732         struct uart_hsu_port *up =
 733                 container_of(port, struct uart_hsu_port, port);
 734         unsigned char mcr = 0;
 735
 736         if (mctrl & TIOCM_RTS)
 737                 mcr |= UART_MCR_RTS;
 738         if (mctrl & TIOCM_DTR)
 739                 mcr |= UART_MCR_DTR;
 740         if (mctrl & TIOCM_OUT1)
 741                 mcr |= UART_MCR_OUT1;
 742         if (mctrl & TIOCM_OUT2)
 743                 mcr |= UART_MCR_OUT2;
 744         if (mctrl & TIOCM_LOOP)
 745                 mcr |= UART_MCR_LOOP;
 746
 747         mcr |= up->mcr;
 748
 749         serial_out(up, UART_MCR, mcr);
 750 }
 751
 752 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 753 {
 754         struct uart_hsu_port *up =
 755                 container_of(port, struct uart_hsu_port, port);
 756         unsigned long flags;
 757
 758         spin_lock_irqsave(&up->port.lock, flags);
 759         if (break_state == -1)
 760                 up->lcr |= UART_LCR_SBC;
 761         else
 762                 up->lcr &= ~UART_LCR_SBC;
 763         serial_out(up, UART_LCR, up->lcr);
 764         spin_unlock_irqrestore(&up->port.lock, flags);
 765 }
 766
 767 /*
 768  * What special to do:
 769  * 1. chose the 64B fifo mode
 770  * 2. make sure not to select half empty mode for A0 stepping
 771  * 3. start dma or pio depends on configuration
 772  * 4. we only allocate dma memory when needed
 773  */
 774 static int serial_hsu_startup(struct uart_port *port)
 775 {
 776         struct uart_hsu_port *up =
 777                 container_of(port, struct uart_hsu_port, port);
 778         unsigned long flags;
 779
 780         /*
 781          * Clear the FIFO buffers and disable them.
 782          * (they will be reenabled in set_termios())
 783          */
 784         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 785         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 786                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 787         serial_out(up, UART_FCR, 0);
 788
 789         /* Clear the interrupt registers. */
 790         (void) serial_in(up, UART_LSR);
 791         (void) serial_in(up, UART_RX);
 792         (void) serial_in(up, UART_IIR);
 793         (void) serial_in(up, UART_MSR);
 794
 795         /* Now, initialize the UART, default is 8n1 */
 796         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 797
 798         spin_lock_irqsave(&up->port.lock, flags);
 799
 800         up->port.mctrl |= TIOCM_OUT2;
 801         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 802
 803         /*
 804          * Finally, enable interrupts.  Note: Modem status interrupts
 805          * are set via set_termios(), which will be occurring imminently
 806          * anyway, so we don't enable them here.
 807          */
 808         if (!up->use_dma)
 809                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 810         else
 811                 up->ier = 0;
 812         serial_out(up, UART_IER, up->ier);
 813
 814         spin_unlock_irqrestore(&up->port.lock, flags);
 815
 816         /* DMA init */
 817         if (up->use_dma) {
 818                 struct hsu_dma_buffer *dbuf;
 819                 struct circ_buf *xmit = &port->state->xmit;
 820
 821                 up->dma_tx_on = 0;
 822
 823                 /* First allocate the RX buffer */
 824                 dbuf = &up->rxbuf;
 825                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 826                 if (!dbuf->buf) {
 827                         up->use_dma = 0;
 828                         goto exit;
 829                 }
 830                 dbuf->dma_addr = dma_map_single(port->dev,
 831                                                 dbuf->buf,
 832                                                 HSU_DMA_BUF_SIZE,
 833                                                 DMA_FROM_DEVICE);
 834                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 835
 836                 /* Start the RX channel right now */
 837                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 838
 839                 /* Next init the TX DMA */
 840                 dbuf = &up->txbuf;
 841                 dbuf->buf = xmit->buf;
 842                 dbuf->dma_addr = dma_map_single(port->dev,
 843                                                dbuf->buf,
 844                                                UART_XMIT_SIZE,
 845                                                DMA_TO_DEVICE);
 846                 dbuf->dma_size = UART_XMIT_SIZE;
 847
 848                 /* This should not be changed all around */
 849                 chan_writel(up->txc, HSU_CH_BSR, 32);
 850                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 851                 dbuf->ofs = 0;
 852         }
 853
 854 exit:
 855          /* And clear the interrupt registers again for luck. */
 856         (void) serial_in(up, UART_LSR);
 857         (void) serial_in(up, UART_RX);
 858         (void) serial_in(up, UART_IIR);
 859         (void) serial_in(up, UART_MSR);
 860
 861         up->running = 1;
 862         return 0;
 863 }
 864
 865 static void serial_hsu_shutdown(struct uart_port *port)
 866 {
 867         struct uart_hsu_port *up =
 868                 container_of(port, struct uart_hsu_port, port);
 869         unsigned long flags;
 870
 871         del_timer_sync(&up->rxc->rx_timer);
 872
 873         /* Disable interrupts from this port */
 874         up->ier = 0;
 875         serial_out(up, UART_IER, 0);
 876         up->running = 0;
 877
 878         spin_lock_irqsave(&up->port.lock, flags);
 879         up->port.mctrl &= ~TIOCM_OUT2;
 880         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 881         spin_unlock_irqrestore(&up->port.lock, flags);
 882
 883         /* Disable break condition and FIFOs */
 884         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 885         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 886                                   UART_FCR_CLEAR_RCVR |
 887                                   UART_FCR_CLEAR_XMIT);
 888         serial_out(up, UART_FCR, 0);
 889 }
 890
 891 static void
 892 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 893                        struct ktermios *old)
 894 {
 895         struct uart_hsu_port *up =
 896                         container_of(port, struct uart_hsu_port, port);
 897         struct tty_struct *tty = port->state->port.tty;
 898         unsigned char cval, fcr = 0;
 899         unsigned long flags;
 900         unsigned int baud, quot;
 901         u32 mul = 0x3600;
 902         u32 ps = 0x10;
 903
 904         switch (termios->c_cflag & CSIZE) {
 905         case CS5:
 906                 cval = UART_LCR_WLEN5;
 907                 break;
 908         case CS6:
 909                 cval = UART_LCR_WLEN6;
 910                 break;
 911         case CS7:
 912                 cval = UART_LCR_WLEN7;
 913                 break;
 914         default:
 915         case CS8:
 916                 cval = UART_LCR_WLEN8;
 917                 break;
 918         }
 919
 920         /* CMSPAR isn't supported by this driver */
 921         if (tty)
 922                 tty->termios->c_cflag &= ~CMSPAR;
 923
 924         if (termios->c_cflag & CSTOPB)
 925                 cval |= UART_LCR_STOP;
 926         if (termios->c_cflag & PARENB)
 927                 cval |= UART_LCR_PARITY;
 928         if (!(termios->c_cflag & PARODD))
 929                 cval |= UART_LCR_EPAR;
 930
 931         /*
 932          * The base clk is 50Mhz, and the baud rate come from:
 933          *      baud = 50M * MUL / (DIV * PS * DLAB)
 934          *
 935          * For those basic low baud rate we can get the direct
 936          * scalar from 2746800, like 115200 = 2746800/24. For those
 937          * higher baud rate, we handle them case by case, mainly by
 938          * adjusting the MUL/PS registers, and DIV register is kept
 939          * as default value 0x3d09 to make things simple
 940          */
 941         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 942
 943         quot = 1;
 944         switch (baud) {
 945         case 3500000:
 946                 mul = 0x3345;
 947                 ps = 0xC;
 948                 break;
 949         case 3000000:
 950                 mul = 0x2EE0;
 951                 break;
 952         case 2500000:
 953                 mul = 0x2710;
 954                 break;
 955         case 2000000:
 956                 mul = 0x1F40;
 957                 break;
 958         case 1843200:
 959                 mul = 0x2400;
 960                 break;
 961         case 1500000:
 962                 mul = 0x1770;
 963                 break;
 964         case 1000000:
 965                 mul = 0xFA0;
 966                 break;
 967         case 500000:
 968                 mul = 0x7D0;
 969                 break;
 970         default:
 971                 /* Use uart_get_divisor to get quot for other baud rates */
 972                 quot = 0;
 973         }
 974
 975         if (!quot)
 976                 quot = uart_get_divisor(port, baud);
 977
 978         if ((up->port.uartclk / quot) < (2400 * 16))
 979                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 980         else if ((up->port.uartclk / quot) < (230400 * 16))
 981                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 982         else
 983                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 984
 985         fcr |= UART_FCR_HSU_64B_FIFO;
 986 #ifdef MFD_HSU_A0_STEPPING
 987         /* A0 doesn't support half empty IRQ */
 988         fcr |= UART_FCR_FULL_EMPT_TXI;
 989 #endif
 990
 991         /*
 992          * Ok, we're now changing the port state.  Do it with
 993          * interrupts disabled.
 994          */
 995         spin_lock_irqsave(&up->port.lock, flags);
 996
 997         /* Update the per-port timeout */
 998         uart_update_timeout(port, termios->c_cflag, baud);
 999
1000         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1001         if (termios->c_iflag & INPCK)
1002                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1003         if (termios->c_iflag & (BRKINT | PARMRK))
1004                 up->port.read_status_mask |= UART_LSR_BI;
1005
1006         /* Characters to ignore */
1007         up->port.ignore_status_mask = 0;
1008         if (termios->c_iflag & IGNPAR)
1009                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1010         if (termios->c_iflag & IGNBRK) {
1011                 up->port.ignore_status_mask |= UART_LSR_BI;
1012                 /*
1013                  * If we're ignoring parity and break indicators,
1014                  * ignore overruns too (for real raw support).
1015                  */
1016                 if (termios->c_iflag & IGNPAR)
1017                         up->port.ignore_status_mask |= UART_LSR_OE;
1018         }
1019
1020         /* Ignore all characters if CREAD is not set */
1021         if ((termios->c_cflag & CREAD) == 0)
1022                 up->port.ignore_status_mask |= UART_LSR_DR;
1023
1024         /*
1025          * CTS flow control flag and modem status interrupts, disable
1026          * MSI by default
1027          */
1028         up->ier &= ~UART_IER_MSI;
1029         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1030                 up->ier |= UART_IER_MSI;
1031
1032         serial_out(up, UART_IER, up->ier);
1033
1034         if (termios->c_cflag & CRTSCTS)
1035                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1036         else
1037                 up->mcr &= ~UART_MCR_AFE;
1038
1039         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1040         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1041         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1042         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1043         serial_out(up, UART_MUL, mul);                  /* set MUL */
1044         serial_out(up, UART_PS, ps);                    /* set PS */
1045         up->lcr = cval;                                 /* Save LCR */
1046         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1047         serial_out(up, UART_FCR, fcr);
1048         spin_unlock_irqrestore(&up->port.lock, flags);
1049 }
1050
1051 static void
1052 serial_hsu_pm(struct uart_port *port, unsigned int state,
1053               unsigned int oldstate)
1054 {
1055 }
1056
1057 static void serial_hsu_release_port(struct uart_port *port)
1058 {
1059 }
1060
1061 static int serial_hsu_request_port(struct uart_port *port)
1062 {
1063         return 0;
1064 }
1065
1066 static void serial_hsu_config_port(struct uart_port *port, int flags)
1067 {
1068         struct uart_hsu_port *up =
1069                 container_of(port, struct uart_hsu_port, port);
1070         up->port.type = PORT_MFD;
1071 }
1072
1073 static int
1074 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1075 {
1076         /* We don't want the core code to modify any port params */
1077         return -EINVAL;
1078 }
1079
1080 static const char *
1081 serial_hsu_type(struct uart_port *port)
1082 {
1083         struct uart_hsu_port *up =
1084                 container_of(port, struct uart_hsu_port, port);
1085         return up->name;
1086 }
1087
1088 /* Mainly for uart console use */
1089 static struct uart_hsu_port *serial_hsu_ports[3];
1090 static struct uart_driver serial_hsu_reg;
1091
1092 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1093
1094 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1095
1096 /* Wait for transmitter & holding register to empty */
1097 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1098 {
1099         unsigned int status, tmout = 1000;
1100
1101         /* Wait up to 1ms for the character to be sent. */
1102         do {
1103                 status = serial_in(up, UART_LSR);
1104
1105                 if (status & UART_LSR_BI)
1106                         up->lsr_break_flag = UART_LSR_BI;
1107
1108                 if (--tmout == 0)
1109                         break;
1110                 udelay(1);
1111         } while (!(status & BOTH_EMPTY));
1112
1113         /* Wait up to 1s for flow control if necessary */
1114         if (up->port.flags & UPF_CONS_FLOW) {
1115                 tmout = 1000000;
1116                 while (--tmout &&
1117                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1118                         udelay(1);
1119         }
1120 }
1121
1122 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1123 {
1124         struct uart_hsu_port *up =
1125                 container_of(port, struct uart_hsu_port, port);
1126
1127         wait_for_xmitr(up);
1128         serial_out(up, UART_TX, ch);
1129 }
1130
1131 /*
1132  * Print a string to the serial port trying not to disturb
1133  * any possible real use of the port...
1134  *
1135  *      The console_lock must be held when we get here.
1136  */
1137 static void
1138 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1139 {
1140         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1141         unsigned long flags;
1142         unsigned int ier;
1143         int locked = 1;
1144
1145         local_irq_save(flags);
1146         if (up->port.sysrq)
1147                 locked = 0;
1148         else if (oops_in_progress) {
1149                 locked = spin_trylock(&up->port.lock);
1150         } else
1151                 spin_lock(&up->port.lock);
1152
1153         /* First save the IER then disable the interrupts */
1154         ier = serial_in(up, UART_IER);
1155         serial_out(up, UART_IER, 0);
1156
1157         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1158
1159         /*
1160          * Finally, wait for transmitter to become empty
1161          * and restore the IER
1162          */
1163         wait_for_xmitr(up);
1164         serial_out(up, UART_IER, ier);
1165
1166         if (locked)
1167                 spin_unlock(&up->port.lock);
1168         local_irq_restore(flags);
1169 }
1170
1171 static struct console serial_hsu_console;
1172
1173 static int __init
1174 serial_hsu_console_setup(struct console *co, char *options)
1175 {
1176         struct uart_hsu_port *up;
1177         int baud = 115200;
1178         int bits = 8;
1179         int parity = 'n';
1180         int flow = 'n';
1181         int ret;
1182
1183         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1184                 co->index = 0;
1185         up = serial_hsu_ports[co->index];
1186         if (!up)
1187                 return -ENODEV;
1188
1189         if (options)
1190                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1191
1192         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1193
1194         return ret;
1195 }
1196
1197 static struct console serial_hsu_console = {
1198         .name           = "ttyMFD",
1199         .write          = serial_hsu_console_write,
1200         .device         = uart_console_device,
1201         .setup          = serial_hsu_console_setup,
1202         .flags          = CON_PRINTBUFFER,
1203         .index          = 2,
1204         .data           = &serial_hsu_reg,
1205 };
1206 #endif
1207
1208 struct uart_ops serial_hsu_pops = {
1209         .tx_empty       = serial_hsu_tx_empty,
1210         .set_mctrl      = serial_hsu_set_mctrl,
1211         .get_mctrl      = serial_hsu_get_mctrl,
1212         .stop_tx        = serial_hsu_stop_tx,
1213         .start_tx       = serial_hsu_start_tx,
1214         .stop_rx        = serial_hsu_stop_rx,
1215         .enable_ms      = serial_hsu_enable_ms,
1216         .break_ctl      = serial_hsu_break_ctl,
1217         .startup        = serial_hsu_startup,
1218         .shutdown       = serial_hsu_shutdown,
1219         .set_termios    = serial_hsu_set_termios,
1220         .pm             = serial_hsu_pm,
1221         .type           = serial_hsu_type,
1222         .release_port   = serial_hsu_release_port,
1223         .request_port   = serial_hsu_request_port,
1224         .config_port    = serial_hsu_config_port,
1225         .verify_port    = serial_hsu_verify_port,
1226 };
1227
1228 static struct uart_driver serial_hsu_reg = {
1229         .owner          = THIS_MODULE,
1230         .driver_name    = "MFD serial",
1231         .dev_name       = "ttyMFD",
1232         .major          = TTY_MAJOR,
1233         .minor          = 128,
1234         .nr             = 3,
1235 };
1236
1237 #ifdef CONFIG_PM
1238 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1239 {
1240         void *priv = pci_get_drvdata(pdev);
1241         struct uart_hsu_port *up;
1242
1243         /* Make sure this is not the internal dma controller */
1244         if (priv && (pdev->device != 0x081E)) {
1245                 up = priv;
1246                 uart_suspend_port(&serial_hsu_reg, &up->port);
1247         }
1248
1249         pci_save_state(pdev);
1250         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1251         return 0;
1252 }
1253
1254 static int serial_hsu_resume(struct pci_dev *pdev)
1255 {
1256         void *priv = pci_get_drvdata(pdev);
1257         struct uart_hsu_port *up;
1258         int ret;
1259
1260         pci_set_power_state(pdev, PCI_D0);
1261         pci_restore_state(pdev);
1262
1263         ret = pci_enable_device(pdev);
1264         if (ret)
1265                 dev_warn(&pdev->dev,
1266                         "HSU: can't re-enable device, try to continue\n");
1267
1268         if (priv && (pdev->device != 0x081E)) {
1269                 up = priv;
1270                 uart_resume_port(&serial_hsu_reg, &up->port);
1271         }
1272         return 0;
1273 }
1274 #else
1275 #define serial_hsu_suspend      NULL
1276 #define serial_hsu_resume       NULL
1277 #endif
1278
1279 /* temp global pointer before we settle down on using one or four PCI dev */
1280 static struct hsu_port *phsu;
1281
1282 static int serial_hsu_probe(struct pci_dev *pdev,
1283                                 const struct pci_device_id *ent)
1284 {
1285         struct uart_hsu_port *uport;
1286         int index, ret;
1287
1288         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1289                 pdev->vendor, pdev->device);
1290
1291         switch (pdev->device) {
1292         case 0x081B:
1293                 index = 0;
1294                 break;
1295         case 0x081C:
1296                 index = 1;
1297                 break;
1298         case 0x081D:
1299                 index = 2;
1300                 break;
1301         case 0x081E:
1302                 /* internal DMA controller */
1303                 index = 3;
1304                 break;
1305         default:
1306                 dev_err(&pdev->dev, "HSU: out of index!");
1307                 return -ENODEV;
1308         }
1309
1310         ret = pci_enable_device(pdev);
1311         if (ret)
1312                 return ret;
1313
1314         if (index == 3) {
1315                 /* DMA controller */
1316                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1317                 if (ret) {
1318                         dev_err(&pdev->dev, "can not get IRQ\n");
1319                         goto err_disable;
1320                 }
1321                 pci_set_drvdata(pdev, phsu);
1322         } else {
1323                 /* UART port 0~2 */
1324                 uport = &phsu->port[index];
1325                 uport->port.irq = pdev->irq;
1326                 uport->port.dev = &pdev->dev;
1327                 uport->dev = &pdev->dev;
1328
1329                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1330                 if (ret) {
1331                         dev_err(&pdev->dev, "can not get IRQ\n");
1332                         goto err_disable;
1333                 }
1334                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1335
1336 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1337                 if (index == 2) {
1338                         register_console(&serial_hsu_console);
1339                         uport->port.cons = &serial_hsu_console;
1340                 }
1341 #endif
1342                 pci_set_drvdata(pdev, uport);
1343         }
1344
1345         return 0;
1346
1347 err_disable:
1348         pci_disable_device(pdev);
1349         return ret;
1350 }
1351
1352 static void hsu_dma_rx_timeout(unsigned long data)
1353 {
1354         struct hsu_dma_chan *chan = (void *)data;
1355         struct uart_hsu_port *up = chan->uport;
1356         struct hsu_dma_buffer *dbuf = &up->rxbuf;
1357         int count = 0;
1358         unsigned long flags;
1359
1360         spin_lock_irqsave(&up->port.lock, flags);
1361
1362         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1363
1364         if (!count) {
1365                 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1366                 goto exit;
1367         }
1368
1369         hsu_dma_rx(up, 0);
1370 exit:
1371         spin_unlock_irqrestore(&up->port.lock, flags);
1372 }
1373
1374 static void hsu_global_init(void)
1375 {
1376         struct hsu_port *hsu;
1377         struct uart_hsu_port *uport;
1378         struct hsu_dma_chan *dchan;
1379         int i, ret;
1380
1381         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1382         if (!hsu)
1383                 return;
1384
1385         /* Get basic io resource and map it */
1386         hsu->paddr = 0xffa28000;
1387         hsu->iolen = 0x1000;
1388
1389         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1390                 pr_warning("HSU: error in request mem region\n");
1391
1392         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1393         if (!hsu->reg) {
1394                 pr_err("HSU: error in ioremap\n");
1395                 ret = -ENOMEM;
1396                 goto err_free_region;
1397         }
1398
1399         /* Initialise the 3 UART ports */
1400         uport = hsu->port;
1401         for (i = 0; i < 3; i++) {
1402                 uport->port.type = PORT_MFD;
1403                 uport->port.iotype = UPIO_MEM;
1404                 uport->port.mapbase = (resource_size_t)hsu->paddr
1405                                         + HSU_PORT_REG_OFFSET
1406                                         + i * HSU_PORT_REG_LENGTH;
1407                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1408                                         + i * HSU_PORT_REG_LENGTH;
1409
1410                 sprintf(uport->name, "hsu_port%d", i);
1411                 uport->port.fifosize = 64;
1412                 uport->port.ops = &serial_hsu_pops;
1413                 uport->port.line = i;
1414                 uport->port.flags = UPF_IOREMAP;
1415                 /* set the scalable maxim support rate to 2746800 bps */
1416                 uport->port.uartclk = 115200 * 24 * 16;
1417
1418                 uport->running = 0;
1419                 uport->txc = &hsu->chans[i * 2];
1420                 uport->rxc = &hsu->chans[i * 2 + 1];
1421
1422                 serial_hsu_ports[i] = uport;
1423                 uport->index = i;
1424                 uport++;
1425         }
1426
1427         /* Initialise 6 dma channels */
1428         dchan = hsu->chans;
1429         for (i = 0; i < 6; i++) {
1430                 dchan->id = i;
1431                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1432                 dchan->uport = &hsu->port[i/2];
1433                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1434                                 i * HSU_DMA_CHANS_REG_LENGTH;
1435
1436                 /* Work around for RX */
1437                 if (dchan->dirt == DMA_FROM_DEVICE) {
1438                         init_timer(&dchan->rx_timer);
1439                         dchan->rx_timer.function = hsu_dma_rx_timeout;
1440                         dchan->rx_timer.data = (unsigned long)dchan;
1441                 }
1442                 dchan++;
1443         }
1444
1445         phsu = hsu;
1446         hsu_debugfs_init(hsu);
1447         return;
1448
1449 err_free_region:
1450         release_mem_region(hsu->paddr, hsu->iolen);
1451         kfree(hsu);
1452         return;
1453 }
1454
1455 static void serial_hsu_remove(struct pci_dev *pdev)
1456 {
1457         void *priv = pci_get_drvdata(pdev);
1458         struct uart_hsu_port *up;
1459
1460         if (!priv)
1461                 return;
1462
1463         /* For port 0/1/2, priv is the address of uart_hsu_port */
1464         if (pdev->device != 0x081E) {
1465                 up = priv;
1466                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1467         }
1468
1469         pci_set_drvdata(pdev, NULL);
1470         free_irq(pdev->irq, priv);
1471         pci_disable_device(pdev);
1472 }
1473
1474 /* First 3 are UART ports, and the 4th is the DMA */
1475 static const struct pci_device_id pci_ids[] __devinitdata = {
1476         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1477         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1478         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1479         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1480         {},
1481 };
1482
1483 static struct pci_driver hsu_pci_driver = {
1484         .name =         "HSU serial",
1485         .id_table =     pci_ids,
1486         .probe =        serial_hsu_probe,
1487         .remove =       __devexit_p(serial_hsu_remove),
1488         .suspend =      serial_hsu_suspend,
1489         .resume =       serial_hsu_resume,
1490 };
1491
1492 static int __init hsu_pci_init(void)
1493 {
1494         int ret;
1495
1496         hsu_global_init();
1497
1498         ret = uart_register_driver(&serial_hsu_reg);
1499         if (ret)
1500                 return ret;
1501
1502         return pci_register_driver(&hsu_pci_driver);
1503 }
1504
1505 static void __exit hsu_pci_exit(void)
1506 {
1507         pci_unregister_driver(&hsu_pci_driver);
1508         uart_unregister_driver(&serial_hsu_reg);
1509
1510         hsu_debugfs_remove(phsu);
1511
1512         kfree(phsu);
1513 }
1514
1515 module_init(hsu_pci_init);
1516 module_exit(hsu_pci_exit);
1517
1518 MODULE_LICENSE("GPL v2");
1519 MODULE_ALIAS("platform:medfield-hsu");