2 * linux/drivers/serial/imx.c
4 * Driver for Motorola IMX serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/clk.h>
44 #include <linux/rational.h>
48 #include <mach/hardware.h>
49 #include <mach/imx-uart.h>
51 /* Register definitions */
52 #define URXD0 0x0 /* Receiver Register */
53 #define URTX0 0x40 /* Transmitter Register */
54 #define UCR1 0x80 /* Control Register 1 */
55 #define UCR2 0x84 /* Control Register 2 */
56 #define UCR3 0x88 /* Control Register 3 */
57 #define UCR4 0x8c /* Control Register 4 */
58 #define UFCR 0x90 /* FIFO Control Register */
59 #define USR1 0x94 /* Status Register 1 */
60 #define USR2 0x98 /* Status Register 2 */
61 #define UESC 0x9c /* Escape Character Register */
62 #define UTIM 0xa0 /* Escape Timer Register */
63 #define UBIR 0xa4 /* BRM Incremental Register */
64 #define UBMR 0xa8 /* BRM Modulator Register */
65 #define UBRC 0xac /* Baud Rate Count Register */
66 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
67 #define ONEMS 0xb0 /* One Millisecond register */
68 #define UTS 0xb4 /* UART Test Register */
70 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
71 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
72 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
73 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
74 #define BIPR4 0xbc /* Incremental Preset Register 4 */
75 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
76 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
77 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
78 #define BMPR4 0xcc /* BRM Modulator Register 4 */
79 #define UTS 0xd0 /* UART Test Register */
82 /* UART Control Register Bit Fields.*/
83 #define URXD_CHARRDY (1<<15)
84 #define URXD_ERR (1<<14)
85 #define URXD_OVRRUN (1<<13)
86 #define URXD_FRMERR (1<<12)
87 #define URXD_BRK (1<<11)
88 #define URXD_PRERR (1<<10)
89 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
90 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
91 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
92 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
93 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
94 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
95 #define UCR1_IREN (1<<7) /* Infrared interface enable */
96 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
97 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
98 #define UCR1_SNDBRK (1<<4) /* Send break */
99 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
100 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
101 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
103 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
104 #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
106 #define UCR1_DOZE (1<<1) /* Doze */
107 #define UCR1_UARTEN (1<<0) /* UART enabled */
108 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
109 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
110 #define UCR2_CTSC (1<<13) /* CTS pin control */
111 #define UCR2_CTS (1<<12) /* Clear to send */
112 #define UCR2_ESCEN (1<<11) /* Escape enable */
113 #define UCR2_PREN (1<<8) /* Parity enable */
114 #define UCR2_PROE (1<<7) /* Parity odd/even */
115 #define UCR2_STPB (1<<6) /* Stop */
116 #define UCR2_WS (1<<5) /* Word size */
117 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
118 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
119 #define UCR2_RXEN (1<<1) /* Receiver enabled */
120 #define UCR2_SRST (1<<0) /* SW reset */
121 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
122 #define UCR3_PARERREN (1<<12) /* Parity enable */
123 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
124 #define UCR3_DSR (1<<10) /* Data set ready */
125 #define UCR3_DCD (1<<9) /* Data carrier detect */
126 #define UCR3_RI (1<<8) /* Ring indicator */
127 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
128 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
129 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
130 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
131 #ifdef CONFIG_ARCH_IMX
132 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
133 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
135 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
136 #define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
138 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
139 #define UCR3_BPEN (1<<0) /* Preset registers enable */
140 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
141 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
142 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
143 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
144 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
145 #define UCR4_IRSC (1<<5) /* IR special case */
146 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
147 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
148 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
149 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
150 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
151 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
152 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
153 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
154 #define USR1_RTSS (1<<14) /* RTS pin status */
155 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
156 #define USR1_RTSD (1<<12) /* RTS delta */
157 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
158 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
159 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
160 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
161 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
162 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
163 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
164 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
165 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
166 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
167 #define USR2_IDLE (1<<12) /* Idle condition */
168 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
169 #define USR2_WAKE (1<<7) /* Wake */
170 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
171 #define USR2_TXDC (1<<3) /* Transmitter complete */
172 #define USR2_BRCD (1<<2) /* Break condition */
173 #define USR2_ORE (1<<1) /* Overrun error */
174 #define USR2_RDR (1<<0) /* Recv data ready */
175 #define UTS_FRCPERR (1<<13) /* Force parity error */
176 #define UTS_LOOP (1<<12) /* Loop tx and rx */
177 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
178 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
179 #define UTS_TXFULL (1<<4) /* TxFIFO full */
180 #define UTS_RXFULL (1<<3) /* RxFIFO full */
181 #define UTS_SOFTRST (1<<0) /* Software reset */
183 /* We've been assigned a range on the "Low-density serial ports" major */
184 #ifdef CONFIG_ARCH_IMX
185 #define SERIAL_IMX_MAJOR 204
186 #define MINOR_START 41
187 #define DEV_NAME "ttySMX"
188 #define MAX_INTERNAL_IRQ IMX_IRQS
191 #ifdef CONFIG_ARCH_MXC
192 #define SERIAL_IMX_MAJOR 207
193 #define MINOR_START 16
194 #define DEV_NAME "ttymxc"
195 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
199 * This determines how often we check the modem status signals
200 * for any change. They generally aren't connected to an IRQ
201 * so we have to poll them. We also check immediately before
202 * filling the TX fifo incase CTS has been dropped.
204 #define MCTRL_TIMEOUT (250*HZ/1000)
206 #define DRIVER_NAME "IMX-uart"
211 struct uart_port port;
212 struct timer_list timer;
213 unsigned int old_status;
214 int txirq,rxirq,rtsirq;
215 unsigned int have_rtscts:1;
220 * Handle any change of modem status signal since we were last called.
222 static void imx_mctrl_check(struct imx_port *sport)
224 unsigned int status, changed;
226 status = sport->port.ops->get_mctrl(&sport->port);
227 changed = status ^ sport->old_status;
232 sport->old_status = status;
234 if (changed & TIOCM_RI)
235 sport->port.icount.rng++;
236 if (changed & TIOCM_DSR)
237 sport->port.icount.dsr++;
238 if (changed & TIOCM_CAR)
239 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
240 if (changed & TIOCM_CTS)
241 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
243 wake_up_interruptible(&sport->port.info->delta_msr_wait);
247 * This is our per-port timeout handler, for checking the
248 * modem status signals.
250 static void imx_timeout(unsigned long data)
252 struct imx_port *sport = (struct imx_port *)data;
255 if (sport->port.info) {
256 spin_lock_irqsave(&sport->port.lock, flags);
257 imx_mctrl_check(sport);
258 spin_unlock_irqrestore(&sport->port.lock, flags);
260 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
265 * interrupts disabled on entry
267 static void imx_stop_tx(struct uart_port *port)
269 struct imx_port *sport = (struct imx_port *)port;
272 temp = readl(sport->port.membase + UCR1);
273 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
277 * interrupts disabled on entry
279 static void imx_stop_rx(struct uart_port *port)
281 struct imx_port *sport = (struct imx_port *)port;
284 temp = readl(sport->port.membase + UCR2);
285 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
289 * Set the modem control timer to fire immediately.
291 static void imx_enable_ms(struct uart_port *port)
293 struct imx_port *sport = (struct imx_port *)port;
295 mod_timer(&sport->timer, jiffies);
298 static inline void imx_transmit_buffer(struct imx_port *sport)
300 struct circ_buf *xmit = &sport->port.info->xmit;
302 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
303 /* send xmit->buf[xmit->tail]
304 * out the port here */
305 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
306 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
307 sport->port.icount.tx++;
308 if (uart_circ_empty(xmit))
312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
313 uart_write_wakeup(&sport->port);
315 if (uart_circ_empty(xmit))
316 imx_stop_tx(&sport->port);
320 * interrupts disabled on entry
322 static void imx_start_tx(struct uart_port *port)
324 struct imx_port *sport = (struct imx_port *)port;
327 temp = readl(sport->port.membase + UCR1);
328 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
330 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
331 imx_transmit_buffer(sport);
334 static irqreturn_t imx_rtsint(int irq, void *dev_id)
336 struct imx_port *sport = dev_id;
337 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
340 spin_lock_irqsave(&sport->port.lock, flags);
342 writel(USR1_RTSD, sport->port.membase + USR1);
343 uart_handle_cts_change(&sport->port, !!val);
344 wake_up_interruptible(&sport->port.info->delta_msr_wait);
346 spin_unlock_irqrestore(&sport->port.lock, flags);
350 static irqreturn_t imx_txint(int irq, void *dev_id)
352 struct imx_port *sport = dev_id;
353 struct circ_buf *xmit = &sport->port.info->xmit;
356 spin_lock_irqsave(&sport->port.lock,flags);
357 if (sport->port.x_char)
360 writel(sport->port.x_char, sport->port.membase + URTX0);
364 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
365 imx_stop_tx(&sport->port);
369 imx_transmit_buffer(sport);
371 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
372 uart_write_wakeup(&sport->port);
375 spin_unlock_irqrestore(&sport->port.lock,flags);
379 static irqreturn_t imx_rxint(int irq, void *dev_id)
381 struct imx_port *sport = dev_id;
382 unsigned int rx,flg,ignored = 0;
383 struct tty_struct *tty = sport->port.info->port.tty;
384 unsigned long flags, temp;
386 spin_lock_irqsave(&sport->port.lock,flags);
388 while (readl(sport->port.membase + USR2) & USR2_RDR) {
390 sport->port.icount.rx++;
392 rx = readl(sport->port.membase + URXD0);
394 temp = readl(sport->port.membase + USR2);
395 if (temp & USR2_BRCD) {
396 writel(temp | USR2_BRCD, sport->port.membase + USR2);
397 if (uart_handle_break(&sport->port))
401 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
404 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
406 sport->port.icount.parity++;
407 else if (rx & URXD_FRMERR)
408 sport->port.icount.frame++;
409 if (rx & URXD_OVRRUN)
410 sport->port.icount.overrun++;
412 if (rx & sport->port.ignore_status_mask) {
418 rx &= sport->port.read_status_mask;
422 else if (rx & URXD_FRMERR)
424 if (rx & URXD_OVRRUN)
428 sport->port.sysrq = 0;
432 tty_insert_flip_char(tty, rx, flg);
436 spin_unlock_irqrestore(&sport->port.lock,flags);
437 tty_flip_buffer_push(tty);
441 static irqreturn_t imx_int(int irq, void *dev_id)
443 struct imx_port *sport = dev_id;
446 sts = readl(sport->port.membase + USR1);
449 imx_rxint(irq, dev_id);
451 if (sts & USR1_TRDY &&
452 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
453 imx_txint(irq, dev_id);
456 imx_rtsint(irq, dev_id);
462 * Return TIOCSER_TEMT when transmitter is not busy.
464 static unsigned int imx_tx_empty(struct uart_port *port)
466 struct imx_port *sport = (struct imx_port *)port;
468 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
472 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
474 static unsigned int imx_get_mctrl(struct uart_port *port)
476 struct imx_port *sport = (struct imx_port *)port;
477 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
479 if (readl(sport->port.membase + USR1) & USR1_RTSS)
482 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
488 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
490 struct imx_port *sport = (struct imx_port *)port;
493 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
495 if (mctrl & TIOCM_RTS)
498 writel(temp, sport->port.membase + UCR2);
502 * Interrupts always disabled.
504 static void imx_break_ctl(struct uart_port *port, int break_state)
506 struct imx_port *sport = (struct imx_port *)port;
507 unsigned long flags, temp;
509 spin_lock_irqsave(&sport->port.lock, flags);
511 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
513 if ( break_state != 0 )
516 writel(temp, sport->port.membase + UCR1);
518 spin_unlock_irqrestore(&sport->port.lock, flags);
521 #define TXTL 2 /* reset default */
522 #define RXTL 1 /* reset default */
524 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
527 unsigned int ufcr_rfdiv;
529 /* set receiver / transmitter trigger level.
530 * RFDIV is set such way to satisfy requested uartclk value
532 val = TXTL << 10 | RXTL;
533 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
534 / sport->port.uartclk;
542 ufcr_rfdiv = 6 - ufcr_rfdiv;
544 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
546 writel(val, sport->port.membase + UFCR);
551 static int imx_startup(struct uart_port *port)
553 struct imx_port *sport = (struct imx_port *)port;
555 unsigned long flags, temp;
557 imx_setup_ufcr(sport, 0);
559 /* disable the DREN bit (Data Ready interrupt enable) before
562 temp = readl(sport->port.membase + UCR4);
563 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
566 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
567 * chips only have one interrupt.
569 if (sport->txirq > 0) {
570 retval = request_irq(sport->rxirq, imx_rxint, 0,
575 retval = request_irq(sport->txirq, imx_txint, 0,
580 retval = request_irq(sport->rtsirq, imx_rtsint,
581 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
582 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
587 retval = request_irq(sport->port.irq, imx_int, 0,
590 free_irq(sport->port.irq, sport);
596 * Finally, clear and enable interrupts
598 writel(USR1_RTSD, sport->port.membase + USR1);
600 temp = readl(sport->port.membase + UCR1);
601 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
602 writel(temp, sport->port.membase + UCR1);
604 temp = readl(sport->port.membase + UCR2);
605 temp |= (UCR2_RXEN | UCR2_TXEN);
606 writel(temp, sport->port.membase + UCR2);
608 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
609 temp = readl(sport->port.membase + UCR3);
610 temp |= UCR3_RXDMUXSEL;
611 writel(temp, sport->port.membase + UCR3);
615 * Enable modem status interrupts
617 spin_lock_irqsave(&sport->port.lock,flags);
618 imx_enable_ms(&sport->port);
619 spin_unlock_irqrestore(&sport->port.lock,flags);
625 free_irq(sport->txirq, sport);
628 free_irq(sport->rxirq, sport);
633 static void imx_shutdown(struct uart_port *port)
635 struct imx_port *sport = (struct imx_port *)port;
638 temp = readl(sport->port.membase + UCR2);
639 temp &= ~(UCR2_TXEN);
640 writel(temp, sport->port.membase + UCR2);
645 del_timer_sync(&sport->timer);
648 * Free the interrupts
650 if (sport->txirq > 0) {
651 free_irq(sport->rtsirq, sport);
652 free_irq(sport->txirq, sport);
653 free_irq(sport->rxirq, sport);
655 free_irq(sport->port.irq, sport);
658 * Disable all interrupts, port and break condition.
661 temp = readl(sport->port.membase + UCR1);
662 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
663 writel(temp, sport->port.membase + UCR1);
667 imx_set_termios(struct uart_port *port, struct ktermios *termios,
668 struct ktermios *old)
670 struct imx_port *sport = (struct imx_port *)port;
672 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
673 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
674 unsigned int div, ufcr;
675 unsigned long num, denom;
678 * If we don't support modem control lines, don't allow
682 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
683 termios->c_cflag |= CLOCAL;
687 * We only support CS7 and CS8.
689 while ((termios->c_cflag & CSIZE) != CS7 &&
690 (termios->c_cflag & CSIZE) != CS8) {
691 termios->c_cflag &= ~CSIZE;
692 termios->c_cflag |= old_csize;
696 if ((termios->c_cflag & CSIZE) == CS8)
697 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
699 ucr2 = UCR2_SRST | UCR2_IRTS;
701 if (termios->c_cflag & CRTSCTS) {
702 if( sport->have_rtscts ) {
706 termios->c_cflag &= ~CRTSCTS;
710 if (termios->c_cflag & CSTOPB)
712 if (termios->c_cflag & PARENB) {
714 if (termios->c_cflag & PARODD)
719 * Ask the core to calculate the divisor for us.
721 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
722 quot = uart_get_divisor(port, baud);
724 spin_lock_irqsave(&sport->port.lock, flags);
726 sport->port.read_status_mask = 0;
727 if (termios->c_iflag & INPCK)
728 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
729 if (termios->c_iflag & (BRKINT | PARMRK))
730 sport->port.read_status_mask |= URXD_BRK;
733 * Characters to ignore
735 sport->port.ignore_status_mask = 0;
736 if (termios->c_iflag & IGNPAR)
737 sport->port.ignore_status_mask |= URXD_PRERR;
738 if (termios->c_iflag & IGNBRK) {
739 sport->port.ignore_status_mask |= URXD_BRK;
741 * If we're ignoring parity and break indicators,
742 * ignore overruns too (for real raw support).
744 if (termios->c_iflag & IGNPAR)
745 sport->port.ignore_status_mask |= URXD_OVRRUN;
748 del_timer_sync(&sport->timer);
751 * Update the per-port timeout.
753 uart_update_timeout(port, termios->c_cflag, baud);
756 * disable interrupts and drain transmitter
758 old_ucr1 = readl(sport->port.membase + UCR1);
759 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
760 sport->port.membase + UCR1);
762 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
765 /* then, disable everything */
766 old_txrxen = readl(sport->port.membase + UCR2);
767 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
768 sport->port.membase + UCR2);
769 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
771 div = sport->port.uartclk / (baud * 16);
777 rational_best_approximation(16 * div * baud, sport->port.uartclk,
778 1 << 16, 1 << 16, &num, &denom);
783 ufcr = readl(sport->port.membase + UFCR);
784 ufcr = (ufcr & (~UFCR_RFDIV)) |
786 writel(ufcr, sport->port.membase + UFCR);
788 writel(num, sport->port.membase + UBIR);
789 writel(denom, sport->port.membase + UBMR);
792 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
795 writel(old_ucr1, sport->port.membase + UCR1);
797 /* set the parity, stop bits and data size */
798 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
800 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
801 imx_enable_ms(&sport->port);
803 spin_unlock_irqrestore(&sport->port.lock, flags);
806 static const char *imx_type(struct uart_port *port)
808 struct imx_port *sport = (struct imx_port *)port;
810 return sport->port.type == PORT_IMX ? "IMX" : NULL;
814 * Release the memory region(s) being used by 'port'.
816 static void imx_release_port(struct uart_port *port)
818 struct platform_device *pdev = to_platform_device(port->dev);
819 struct resource *mmres;
821 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
822 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
826 * Request the memory region(s) being used by 'port'.
828 static int imx_request_port(struct uart_port *port)
830 struct platform_device *pdev = to_platform_device(port->dev);
831 struct resource *mmres;
834 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
838 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
841 return ret ? 0 : -EBUSY;
845 * Configure/autoconfigure the port.
847 static void imx_config_port(struct uart_port *port, int flags)
849 struct imx_port *sport = (struct imx_port *)port;
851 if (flags & UART_CONFIG_TYPE &&
852 imx_request_port(&sport->port) == 0)
853 sport->port.type = PORT_IMX;
857 * Verify the new serial_struct (for TIOCSSERIAL).
858 * The only change we allow are to the flags and type, and
859 * even then only between PORT_IMX and PORT_UNKNOWN
862 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
864 struct imx_port *sport = (struct imx_port *)port;
867 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
869 if (sport->port.irq != ser->irq)
871 if (ser->io_type != UPIO_MEM)
873 if (sport->port.uartclk / 16 != ser->baud_base)
875 if ((void *)sport->port.mapbase != ser->iomem_base)
877 if (sport->port.iobase != ser->port)
884 static struct uart_ops imx_pops = {
885 .tx_empty = imx_tx_empty,
886 .set_mctrl = imx_set_mctrl,
887 .get_mctrl = imx_get_mctrl,
888 .stop_tx = imx_stop_tx,
889 .start_tx = imx_start_tx,
890 .stop_rx = imx_stop_rx,
891 .enable_ms = imx_enable_ms,
892 .break_ctl = imx_break_ctl,
893 .startup = imx_startup,
894 .shutdown = imx_shutdown,
895 .set_termios = imx_set_termios,
897 .release_port = imx_release_port,
898 .request_port = imx_request_port,
899 .config_port = imx_config_port,
900 .verify_port = imx_verify_port,
903 static struct imx_port *imx_ports[UART_NR];
905 #ifdef CONFIG_SERIAL_IMX_CONSOLE
906 static void imx_console_putchar(struct uart_port *port, int ch)
908 struct imx_port *sport = (struct imx_port *)port;
910 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
913 writel(ch, sport->port.membase + URTX0);
917 * Interrupts are disabled on entering
920 imx_console_write(struct console *co, const char *s, unsigned int count)
922 struct imx_port *sport = imx_ports[co->index];
923 unsigned int old_ucr1, old_ucr2;
926 * First, save UCR1/2 and then disable interrupts
928 old_ucr1 = readl(sport->port.membase + UCR1);
929 old_ucr2 = readl(sport->port.membase + UCR2);
931 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
932 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
933 sport->port.membase + UCR1);
935 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
937 uart_console_write(&sport->port, s, count, imx_console_putchar);
940 * Finally, wait for transmitter to become empty
943 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
945 writel(old_ucr1, sport->port.membase + UCR1);
946 writel(old_ucr2, sport->port.membase + UCR2);
950 * If the port was already initialised (eg, by a boot loader),
951 * try to determine the current setup.
954 imx_console_get_options(struct imx_port *sport, int *baud,
955 int *parity, int *bits)
958 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
959 /* ok, the port was enabled */
960 unsigned int ucr2, ubir,ubmr, uartclk;
961 unsigned int baud_raw;
962 unsigned int ucfr_rfdiv;
964 ucr2 = readl(sport->port.membase + UCR2);
967 if (ucr2 & UCR2_PREN) {
968 if (ucr2 & UCR2_PROE)
979 ubir = readl(sport->port.membase + UBIR) & 0xffff;
980 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
982 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
986 ucfr_rfdiv = 6 - ucfr_rfdiv;
988 uartclk = clk_get_rate(sport->clk);
989 uartclk /= ucfr_rfdiv;
992 * The next code provides exact computation of
993 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
994 * without need of float support or long long division,
995 * which would be required to prevent 32bit arithmetic overflow
997 unsigned int mul = ubir + 1;
998 unsigned int div = 16 * (ubmr + 1);
999 unsigned int rem = uartclk % div;
1001 baud_raw = (uartclk / div) * mul;
1002 baud_raw += (rem * mul + div / 2) / div;
1003 *baud = (baud_raw + 50) / 100 * 100;
1006 if(*baud != baud_raw)
1007 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1013 imx_console_setup(struct console *co, char *options)
1015 struct imx_port *sport;
1022 * Check whether an invalid uart number has been specified, and
1023 * if so, search for the first available port that does have
1026 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1028 sport = imx_ports[co->index];
1033 uart_parse_options(options, &baud, &parity, &bits, &flow);
1035 imx_console_get_options(sport, &baud, &parity, &bits);
1037 imx_setup_ufcr(sport, 0);
1039 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1042 static struct uart_driver imx_reg;
1043 static struct console imx_console = {
1045 .write = imx_console_write,
1046 .device = uart_console_device,
1047 .setup = imx_console_setup,
1048 .flags = CON_PRINTBUFFER,
1053 #define IMX_CONSOLE &imx_console
1055 #define IMX_CONSOLE NULL
1058 static struct uart_driver imx_reg = {
1059 .owner = THIS_MODULE,
1060 .driver_name = DRIVER_NAME,
1061 .dev_name = DEV_NAME,
1062 .major = SERIAL_IMX_MAJOR,
1063 .minor = MINOR_START,
1064 .nr = ARRAY_SIZE(imx_ports),
1065 .cons = IMX_CONSOLE,
1068 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1070 struct imx_port *sport = platform_get_drvdata(dev);
1073 uart_suspend_port(&imx_reg, &sport->port);
1078 static int serial_imx_resume(struct platform_device *dev)
1080 struct imx_port *sport = platform_get_drvdata(dev);
1083 uart_resume_port(&imx_reg, &sport->port);
1088 static int serial_imx_probe(struct platform_device *pdev)
1090 struct imx_port *sport;
1091 struct imxuart_platform_data *pdata;
1094 struct resource *res;
1096 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1100 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106 base = ioremap(res->start, PAGE_SIZE);
1112 sport->port.dev = &pdev->dev;
1113 sport->port.mapbase = res->start;
1114 sport->port.membase = base;
1115 sport->port.type = PORT_IMX,
1116 sport->port.iotype = UPIO_MEM;
1117 sport->port.irq = platform_get_irq(pdev, 0);
1118 sport->rxirq = platform_get_irq(pdev, 0);
1119 sport->txirq = platform_get_irq(pdev, 1);
1120 sport->rtsirq = platform_get_irq(pdev, 2);
1121 sport->port.fifosize = 32;
1122 sport->port.ops = &imx_pops;
1123 sport->port.flags = UPF_BOOT_AUTOCONF;
1124 sport->port.line = pdev->id;
1125 init_timer(&sport->timer);
1126 sport->timer.function = imx_timeout;
1127 sport->timer.data = (unsigned long)sport;
1129 sport->clk = clk_get(&pdev->dev, "uart");
1130 if (IS_ERR(sport->clk)) {
1131 ret = PTR_ERR(sport->clk);
1134 clk_enable(sport->clk);
1136 sport->port.uartclk = clk_get_rate(sport->clk);
1138 imx_ports[pdev->id] = sport;
1140 pdata = pdev->dev.platform_data;
1141 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1142 sport->have_rtscts = 1;
1145 ret = pdata->init(pdev);
1150 ret = uart_add_one_port(&imx_reg, &sport->port);
1153 platform_set_drvdata(pdev, &sport->port);
1160 clk_put(sport->clk);
1161 clk_disable(sport->clk);
1163 iounmap(sport->port.membase);
1170 static int serial_imx_remove(struct platform_device *pdev)
1172 struct imxuart_platform_data *pdata;
1173 struct imx_port *sport = platform_get_drvdata(pdev);
1175 pdata = pdev->dev.platform_data;
1177 platform_set_drvdata(pdev, NULL);
1180 uart_remove_one_port(&imx_reg, &sport->port);
1181 clk_put(sport->clk);
1184 clk_disable(sport->clk);
1189 iounmap(sport->port.membase);
1195 static struct platform_driver serial_imx_driver = {
1196 .probe = serial_imx_probe,
1197 .remove = serial_imx_remove,
1199 .suspend = serial_imx_suspend,
1200 .resume = serial_imx_resume,
1203 .owner = THIS_MODULE,
1207 static int __init imx_serial_init(void)
1211 printk(KERN_INFO "Serial: IMX driver\n");
1213 ret = uart_register_driver(&imx_reg);
1217 ret = platform_driver_register(&serial_imx_driver);
1219 uart_unregister_driver(&imx_reg);
1224 static void __exit imx_serial_exit(void)
1226 platform_driver_unregister(&serial_imx_driver);
1227 uart_unregister_driver(&imx_reg);
1230 module_init(imx_serial_init);
1231 module_exit(imx_serial_exit);
1233 MODULE_AUTHOR("Sascha Hauer");
1234 MODULE_DESCRIPTION("IMX generic serial port driver");
1235 MODULE_LICENSE("GPL");
1236 MODULE_ALIAS("platform:imx-uart");