2 * linux/drivers/serial/imx.c
4 * Driver for Motorola IMX serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/clk.h>
47 #include <mach/hardware.h>
48 #include <mach/imx-uart.h>
50 /* Register definitions */
51 #define URXD0 0x0 /* Receiver Register */
52 #define URTX0 0x40 /* Transmitter Register */
53 #define UCR1 0x80 /* Control Register 1 */
54 #define UCR2 0x84 /* Control Register 2 */
55 #define UCR3 0x88 /* Control Register 3 */
56 #define UCR4 0x8c /* Control Register 4 */
57 #define UFCR 0x90 /* FIFO Control Register */
58 #define USR1 0x94 /* Status Register 1 */
59 #define USR2 0x98 /* Status Register 2 */
60 #define UESC 0x9c /* Escape Character Register */
61 #define UTIM 0xa0 /* Escape Timer Register */
62 #define UBIR 0xa4 /* BRM Incremental Register */
63 #define UBMR 0xa8 /* BRM Modulator Register */
64 #define UBRC 0xac /* Baud Rate Count Register */
65 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
66 #define ONEMS 0xb0 /* One Millisecond register */
67 #define UTS 0xb4 /* UART Test Register */
69 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
70 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
71 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
72 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
73 #define BIPR4 0xbc /* Incremental Preset Register 4 */
74 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
75 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
76 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
77 #define BMPR4 0xcc /* BRM Modulator Register 4 */
78 #define UTS 0xd0 /* UART Test Register */
81 /* UART Control Register Bit Fields.*/
82 #define URXD_CHARRDY (1<<15)
83 #define URXD_ERR (1<<14)
84 #define URXD_OVRRUN (1<<13)
85 #define URXD_FRMERR (1<<12)
86 #define URXD_BRK (1<<11)
87 #define URXD_PRERR (1<<10)
88 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
89 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
90 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
91 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
92 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
93 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
94 #define UCR1_IREN (1<<7) /* Infrared interface enable */
95 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
96 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
97 #define UCR1_SNDBRK (1<<4) /* Send break */
98 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
99 #if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
100 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
102 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
103 #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
105 #define UCR1_DOZE (1<<1) /* Doze */
106 #define UCR1_UARTEN (1<<0) /* UART enabled */
107 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
108 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
109 #define UCR2_CTSC (1<<13) /* CTS pin control */
110 #define UCR2_CTS (1<<12) /* Clear to send */
111 #define UCR2_ESCEN (1<<11) /* Escape enable */
112 #define UCR2_PREN (1<<8) /* Parity enable */
113 #define UCR2_PROE (1<<7) /* Parity odd/even */
114 #define UCR2_STPB (1<<6) /* Stop */
115 #define UCR2_WS (1<<5) /* Word size */
116 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
117 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
118 #define UCR2_RXEN (1<<1) /* Receiver enabled */
119 #define UCR2_SRST (1<<0) /* SW reset */
120 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
121 #define UCR3_PARERREN (1<<12) /* Parity enable */
122 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
123 #define UCR3_DSR (1<<10) /* Data set ready */
124 #define UCR3_DCD (1<<9) /* Data carrier detect */
125 #define UCR3_RI (1<<8) /* Ring indicator */
126 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
127 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
128 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
129 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
130 #ifdef CONFIG_ARCH_IMX
131 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
132 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
134 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
135 #define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
137 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
138 #define UCR3_BPEN (1<<0) /* Preset registers enable */
139 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
140 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
141 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
142 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
143 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
144 #define UCR4_IRSC (1<<5) /* IR special case */
145 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
146 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
147 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
148 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
149 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
150 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
151 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
152 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
153 #define USR1_RTSS (1<<14) /* RTS pin status */
154 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
155 #define USR1_RTSD (1<<12) /* RTS delta */
156 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
157 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
158 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
159 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
160 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
161 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
162 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
163 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
164 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
165 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
166 #define USR2_IDLE (1<<12) /* Idle condition */
167 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
168 #define USR2_WAKE (1<<7) /* Wake */
169 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
170 #define USR2_TXDC (1<<3) /* Transmitter complete */
171 #define USR2_BRCD (1<<2) /* Break condition */
172 #define USR2_ORE (1<<1) /* Overrun error */
173 #define USR2_RDR (1<<0) /* Recv data ready */
174 #define UTS_FRCPERR (1<<13) /* Force parity error */
175 #define UTS_LOOP (1<<12) /* Loop tx and rx */
176 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
177 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
178 #define UTS_TXFULL (1<<4) /* TxFIFO full */
179 #define UTS_RXFULL (1<<3) /* RxFIFO full */
180 #define UTS_SOFTRST (1<<0) /* Software reset */
182 /* We've been assigned a range on the "Low-density serial ports" major */
183 #ifdef CONFIG_ARCH_IMX
184 #define SERIAL_IMX_MAJOR 204
185 #define MINOR_START 41
186 #define DEV_NAME "ttySMX"
187 #define MAX_INTERNAL_IRQ IMX_IRQS
190 #ifdef CONFIG_ARCH_MXC
191 #define SERIAL_IMX_MAJOR 207
192 #define MINOR_START 16
193 #define DEV_NAME "ttymxc"
194 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
198 * This determines how often we check the modem status signals
199 * for any change. They generally aren't connected to an IRQ
200 * so we have to poll them. We also check immediately before
201 * filling the TX fifo incase CTS has been dropped.
203 #define MCTRL_TIMEOUT (250*HZ/1000)
205 #define DRIVER_NAME "IMX-uart"
210 struct uart_port port;
211 struct timer_list timer;
212 unsigned int old_status;
213 int txirq,rxirq,rtsirq;
214 unsigned int have_rtscts:1;
219 * Handle any change of modem status signal since we were last called.
221 static void imx_mctrl_check(struct imx_port *sport)
223 unsigned int status, changed;
225 status = sport->port.ops->get_mctrl(&sport->port);
226 changed = status ^ sport->old_status;
231 sport->old_status = status;
233 if (changed & TIOCM_RI)
234 sport->port.icount.rng++;
235 if (changed & TIOCM_DSR)
236 sport->port.icount.dsr++;
237 if (changed & TIOCM_CAR)
238 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
239 if (changed & TIOCM_CTS)
240 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
242 wake_up_interruptible(&sport->port.info->delta_msr_wait);
246 * This is our per-port timeout handler, for checking the
247 * modem status signals.
249 static void imx_timeout(unsigned long data)
251 struct imx_port *sport = (struct imx_port *)data;
254 if (sport->port.info) {
255 spin_lock_irqsave(&sport->port.lock, flags);
256 imx_mctrl_check(sport);
257 spin_unlock_irqrestore(&sport->port.lock, flags);
259 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
264 * interrupts disabled on entry
266 static void imx_stop_tx(struct uart_port *port)
268 struct imx_port *sport = (struct imx_port *)port;
271 temp = readl(sport->port.membase + UCR1);
272 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
276 * interrupts disabled on entry
278 static void imx_stop_rx(struct uart_port *port)
280 struct imx_port *sport = (struct imx_port *)port;
283 temp = readl(sport->port.membase + UCR2);
284 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
288 * Set the modem control timer to fire immediately.
290 static void imx_enable_ms(struct uart_port *port)
292 struct imx_port *sport = (struct imx_port *)port;
294 mod_timer(&sport->timer, jiffies);
297 static inline void imx_transmit_buffer(struct imx_port *sport)
299 struct circ_buf *xmit = &sport->port.info->xmit;
301 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
302 /* send xmit->buf[xmit->tail]
303 * out the port here */
304 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
305 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
306 sport->port.icount.tx++;
307 if (uart_circ_empty(xmit))
311 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312 uart_write_wakeup(&sport->port);
314 if (uart_circ_empty(xmit))
315 imx_stop_tx(&sport->port);
319 * interrupts disabled on entry
321 static void imx_start_tx(struct uart_port *port)
323 struct imx_port *sport = (struct imx_port *)port;
326 temp = readl(sport->port.membase + UCR1);
327 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
329 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
330 imx_transmit_buffer(sport);
333 static irqreturn_t imx_rtsint(int irq, void *dev_id)
335 struct imx_port *sport = dev_id;
336 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
339 spin_lock_irqsave(&sport->port.lock, flags);
341 writel(USR1_RTSD, sport->port.membase + USR1);
342 uart_handle_cts_change(&sport->port, !!val);
343 wake_up_interruptible(&sport->port.info->delta_msr_wait);
345 spin_unlock_irqrestore(&sport->port.lock, flags);
349 static irqreturn_t imx_txint(int irq, void *dev_id)
351 struct imx_port *sport = dev_id;
352 struct circ_buf *xmit = &sport->port.info->xmit;
355 spin_lock_irqsave(&sport->port.lock,flags);
356 if (sport->port.x_char)
359 writel(sport->port.x_char, sport->port.membase + URTX0);
363 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
364 imx_stop_tx(&sport->port);
368 imx_transmit_buffer(sport);
370 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
371 uart_write_wakeup(&sport->port);
374 spin_unlock_irqrestore(&sport->port.lock,flags);
378 static irqreturn_t imx_rxint(int irq, void *dev_id)
380 struct imx_port *sport = dev_id;
381 unsigned int rx,flg,ignored = 0;
382 struct tty_struct *tty = sport->port.info->port.tty;
383 unsigned long flags, temp;
385 spin_lock_irqsave(&sport->port.lock,flags);
387 while (readl(sport->port.membase + USR2) & USR2_RDR) {
389 sport->port.icount.rx++;
391 rx = readl(sport->port.membase + URXD0);
393 temp = readl(sport->port.membase + USR2);
394 if (temp & USR2_BRCD) {
395 writel(temp | USR2_BRCD, sport->port.membase + USR2);
396 if (uart_handle_break(&sport->port))
400 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
403 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
405 sport->port.icount.parity++;
406 else if (rx & URXD_FRMERR)
407 sport->port.icount.frame++;
408 if (rx & URXD_OVRRUN)
409 sport->port.icount.overrun++;
411 if (rx & sport->port.ignore_status_mask) {
417 rx &= sport->port.read_status_mask;
421 else if (rx & URXD_FRMERR)
423 if (rx & URXD_OVRRUN)
427 sport->port.sysrq = 0;
431 tty_insert_flip_char(tty, rx, flg);
435 spin_unlock_irqrestore(&sport->port.lock,flags);
436 tty_flip_buffer_push(tty);
440 static irqreturn_t imx_int(int irq, void *dev_id)
442 struct imx_port *sport = dev_id;
445 sts = readl(sport->port.membase + USR1);
448 imx_rxint(irq, dev_id);
450 if (sts & USR1_TRDY &&
451 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
452 imx_txint(irq, dev_id);
455 imx_rtsint(irq, dev_id);
461 * Return TIOCSER_TEMT when transmitter is not busy.
463 static unsigned int imx_tx_empty(struct uart_port *port)
465 struct imx_port *sport = (struct imx_port *)port;
467 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
471 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
473 static unsigned int imx_get_mctrl(struct uart_port *port)
475 struct imx_port *sport = (struct imx_port *)port;
476 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
478 if (readl(sport->port.membase + USR1) & USR1_RTSS)
481 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
487 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
489 struct imx_port *sport = (struct imx_port *)port;
492 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
494 if (mctrl & TIOCM_RTS)
497 writel(temp, sport->port.membase + UCR2);
501 * Interrupts always disabled.
503 static void imx_break_ctl(struct uart_port *port, int break_state)
505 struct imx_port *sport = (struct imx_port *)port;
506 unsigned long flags, temp;
508 spin_lock_irqsave(&sport->port.lock, flags);
510 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
512 if ( break_state != 0 )
515 writel(temp, sport->port.membase + UCR1);
517 spin_unlock_irqrestore(&sport->port.lock, flags);
520 #define TXTL 2 /* reset default */
521 #define RXTL 1 /* reset default */
523 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
526 unsigned int ufcr_rfdiv;
528 /* set receiver / transmitter trigger level.
529 * RFDIV is set such way to satisfy requested uartclk value
531 val = TXTL << 10 | RXTL;
532 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
533 / sport->port.uartclk;
541 ufcr_rfdiv = 6 - ufcr_rfdiv;
543 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
545 writel(val, sport->port.membase + UFCR);
550 static int imx_startup(struct uart_port *port)
552 struct imx_port *sport = (struct imx_port *)port;
554 unsigned long flags, temp;
556 imx_setup_ufcr(sport, 0);
558 /* disable the DREN bit (Data Ready interrupt enable) before
561 temp = readl(sport->port.membase + UCR4);
562 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
565 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
566 * chips only have one interrupt.
568 if (sport->txirq > 0) {
569 retval = request_irq(sport->rxirq, imx_rxint, 0,
574 retval = request_irq(sport->txirq, imx_txint, 0,
579 retval = request_irq(sport->rtsirq, imx_rtsint,
580 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
581 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
586 retval = request_irq(sport->port.irq, imx_int, 0,
589 free_irq(sport->port.irq, sport);
595 * Finally, clear and enable interrupts
597 writel(USR1_RTSD, sport->port.membase + USR1);
599 temp = readl(sport->port.membase + UCR1);
600 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
601 writel(temp, sport->port.membase + UCR1);
603 temp = readl(sport->port.membase + UCR2);
604 temp |= (UCR2_RXEN | UCR2_TXEN);
605 writel(temp, sport->port.membase + UCR2);
607 #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
608 temp = readl(sport->port.membase + UCR3);
609 temp |= UCR3_RXDMUXSEL;
610 writel(temp, sport->port.membase + UCR3);
614 * Enable modem status interrupts
616 spin_lock_irqsave(&sport->port.lock,flags);
617 imx_enable_ms(&sport->port);
618 spin_unlock_irqrestore(&sport->port.lock,flags);
624 free_irq(sport->txirq, sport);
627 free_irq(sport->rxirq, sport);
632 static void imx_shutdown(struct uart_port *port)
634 struct imx_port *sport = (struct imx_port *)port;
637 temp = readl(sport->port.membase + UCR2);
638 temp &= ~(UCR2_TXEN);
639 writel(temp, sport->port.membase + UCR2);
644 del_timer_sync(&sport->timer);
647 * Free the interrupts
649 if (sport->txirq > 0) {
650 free_irq(sport->rtsirq, sport);
651 free_irq(sport->txirq, sport);
652 free_irq(sport->rxirq, sport);
654 free_irq(sport->port.irq, sport);
657 * Disable all interrupts, port and break condition.
660 temp = readl(sport->port.membase + UCR1);
661 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
662 writel(temp, sport->port.membase + UCR1);
666 imx_set_termios(struct uart_port *port, struct ktermios *termios,
667 struct ktermios *old)
669 struct imx_port *sport = (struct imx_port *)port;
671 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
672 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
673 unsigned int div, num, denom, ufcr;
676 * If we don't support modem control lines, don't allow
680 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
681 termios->c_cflag |= CLOCAL;
685 * We only support CS7 and CS8.
687 while ((termios->c_cflag & CSIZE) != CS7 &&
688 (termios->c_cflag & CSIZE) != CS8) {
689 termios->c_cflag &= ~CSIZE;
690 termios->c_cflag |= old_csize;
694 if ((termios->c_cflag & CSIZE) == CS8)
695 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
697 ucr2 = UCR2_SRST | UCR2_IRTS;
699 if (termios->c_cflag & CRTSCTS) {
700 if( sport->have_rtscts ) {
704 termios->c_cflag &= ~CRTSCTS;
708 if (termios->c_cflag & CSTOPB)
710 if (termios->c_cflag & PARENB) {
712 if (termios->c_cflag & PARODD)
717 * Ask the core to calculate the divisor for us.
719 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
720 quot = uart_get_divisor(port, baud);
722 spin_lock_irqsave(&sport->port.lock, flags);
724 sport->port.read_status_mask = 0;
725 if (termios->c_iflag & INPCK)
726 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
727 if (termios->c_iflag & (BRKINT | PARMRK))
728 sport->port.read_status_mask |= URXD_BRK;
731 * Characters to ignore
733 sport->port.ignore_status_mask = 0;
734 if (termios->c_iflag & IGNPAR)
735 sport->port.ignore_status_mask |= URXD_PRERR;
736 if (termios->c_iflag & IGNBRK) {
737 sport->port.ignore_status_mask |= URXD_BRK;
739 * If we're ignoring parity and break indicators,
740 * ignore overruns too (for real raw support).
742 if (termios->c_iflag & IGNPAR)
743 sport->port.ignore_status_mask |= URXD_OVRRUN;
746 del_timer_sync(&sport->timer);
749 * Update the per-port timeout.
751 uart_update_timeout(port, termios->c_cflag, baud);
754 * disable interrupts and drain transmitter
756 old_ucr1 = readl(sport->port.membase + UCR1);
757 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
758 sport->port.membase + UCR1);
760 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
763 /* then, disable everything */
764 old_txrxen = readl(sport->port.membase + UCR2);
765 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
766 sport->port.membase + UCR2);
767 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
769 div = sport->port.uartclk / (baud * 16);
776 denom = port->uartclk / div / 16;
778 /* shift num and denom right until they fit into 16 bits */
779 while (num > 0x10000 || denom > 0x10000) {
788 writel(num, sport->port.membase + UBIR);
789 writel(denom, sport->port.membase + UBMR);
792 div = 6; /* 6 in RFDIV means divide by 7 */
796 ufcr = readl(sport->port.membase + UFCR);
797 ufcr = (ufcr & (~UFCR_RFDIV)) |
799 writel(ufcr, sport->port.membase + UFCR);
802 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
805 writel(old_ucr1, sport->port.membase + UCR1);
807 /* set the parity, stop bits and data size */
808 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
810 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
811 imx_enable_ms(&sport->port);
813 spin_unlock_irqrestore(&sport->port.lock, flags);
816 static const char *imx_type(struct uart_port *port)
818 struct imx_port *sport = (struct imx_port *)port;
820 return sport->port.type == PORT_IMX ? "IMX" : NULL;
824 * Release the memory region(s) being used by 'port'.
826 static void imx_release_port(struct uart_port *port)
828 struct platform_device *pdev = to_platform_device(port->dev);
829 struct resource *mmres;
831 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
836 * Request the memory region(s) being used by 'port'.
838 static int imx_request_port(struct uart_port *port)
840 struct platform_device *pdev = to_platform_device(port->dev);
841 struct resource *mmres;
844 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
851 return ret ? 0 : -EBUSY;
855 * Configure/autoconfigure the port.
857 static void imx_config_port(struct uart_port *port, int flags)
859 struct imx_port *sport = (struct imx_port *)port;
861 if (flags & UART_CONFIG_TYPE &&
862 imx_request_port(&sport->port) == 0)
863 sport->port.type = PORT_IMX;
867 * Verify the new serial_struct (for TIOCSSERIAL).
868 * The only change we allow are to the flags and type, and
869 * even then only between PORT_IMX and PORT_UNKNOWN
872 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
874 struct imx_port *sport = (struct imx_port *)port;
877 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
879 if (sport->port.irq != ser->irq)
881 if (ser->io_type != UPIO_MEM)
883 if (sport->port.uartclk / 16 != ser->baud_base)
885 if ((void *)sport->port.mapbase != ser->iomem_base)
887 if (sport->port.iobase != ser->port)
894 static struct uart_ops imx_pops = {
895 .tx_empty = imx_tx_empty,
896 .set_mctrl = imx_set_mctrl,
897 .get_mctrl = imx_get_mctrl,
898 .stop_tx = imx_stop_tx,
899 .start_tx = imx_start_tx,
900 .stop_rx = imx_stop_rx,
901 .enable_ms = imx_enable_ms,
902 .break_ctl = imx_break_ctl,
903 .startup = imx_startup,
904 .shutdown = imx_shutdown,
905 .set_termios = imx_set_termios,
907 .release_port = imx_release_port,
908 .request_port = imx_request_port,
909 .config_port = imx_config_port,
910 .verify_port = imx_verify_port,
913 static struct imx_port *imx_ports[UART_NR];
915 #ifdef CONFIG_SERIAL_IMX_CONSOLE
916 static void imx_console_putchar(struct uart_port *port, int ch)
918 struct imx_port *sport = (struct imx_port *)port;
920 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
923 writel(ch, sport->port.membase + URTX0);
927 * Interrupts are disabled on entering
930 imx_console_write(struct console *co, const char *s, unsigned int count)
932 struct imx_port *sport = imx_ports[co->index];
933 unsigned int old_ucr1, old_ucr2;
936 * First, save UCR1/2 and then disable interrupts
938 old_ucr1 = readl(sport->port.membase + UCR1);
939 old_ucr2 = readl(sport->port.membase + UCR2);
941 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
942 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
943 sport->port.membase + UCR1);
945 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
947 uart_console_write(&sport->port, s, count, imx_console_putchar);
950 * Finally, wait for transmitter to become empty
953 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
955 writel(old_ucr1, sport->port.membase + UCR1);
956 writel(old_ucr2, sport->port.membase + UCR2);
960 * If the port was already initialised (eg, by a boot loader),
961 * try to determine the current setup.
964 imx_console_get_options(struct imx_port *sport, int *baud,
965 int *parity, int *bits)
968 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
969 /* ok, the port was enabled */
970 unsigned int ucr2, ubir,ubmr, uartclk;
971 unsigned int baud_raw;
972 unsigned int ucfr_rfdiv;
974 ucr2 = readl(sport->port.membase + UCR2);
977 if (ucr2 & UCR2_PREN) {
978 if (ucr2 & UCR2_PROE)
989 ubir = readl(sport->port.membase + UBIR) & 0xffff;
990 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
992 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
996 ucfr_rfdiv = 6 - ucfr_rfdiv;
998 uartclk = clk_get_rate(sport->clk);
999 uartclk /= ucfr_rfdiv;
1002 * The next code provides exact computation of
1003 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1004 * without need of float support or long long division,
1005 * which would be required to prevent 32bit arithmetic overflow
1007 unsigned int mul = ubir + 1;
1008 unsigned int div = 16 * (ubmr + 1);
1009 unsigned int rem = uartclk % div;
1011 baud_raw = (uartclk / div) * mul;
1012 baud_raw += (rem * mul + div / 2) / div;
1013 *baud = (baud_raw + 50) / 100 * 100;
1016 if(*baud != baud_raw)
1017 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1023 imx_console_setup(struct console *co, char *options)
1025 struct imx_port *sport;
1032 * Check whether an invalid uart number has been specified, and
1033 * if so, search for the first available port that does have
1036 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1038 sport = imx_ports[co->index];
1043 uart_parse_options(options, &baud, &parity, &bits, &flow);
1045 imx_console_get_options(sport, &baud, &parity, &bits);
1047 imx_setup_ufcr(sport, 0);
1049 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1052 static struct uart_driver imx_reg;
1053 static struct console imx_console = {
1055 .write = imx_console_write,
1056 .device = uart_console_device,
1057 .setup = imx_console_setup,
1058 .flags = CON_PRINTBUFFER,
1063 #define IMX_CONSOLE &imx_console
1065 #define IMX_CONSOLE NULL
1068 static struct uart_driver imx_reg = {
1069 .owner = THIS_MODULE,
1070 .driver_name = DRIVER_NAME,
1071 .dev_name = DEV_NAME,
1072 .major = SERIAL_IMX_MAJOR,
1073 .minor = MINOR_START,
1074 .nr = ARRAY_SIZE(imx_ports),
1075 .cons = IMX_CONSOLE,
1078 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1080 struct imx_port *sport = platform_get_drvdata(dev);
1083 uart_suspend_port(&imx_reg, &sport->port);
1088 static int serial_imx_resume(struct platform_device *dev)
1090 struct imx_port *sport = platform_get_drvdata(dev);
1093 uart_resume_port(&imx_reg, &sport->port);
1098 static int serial_imx_probe(struct platform_device *pdev)
1100 struct imx_port *sport;
1101 struct imxuart_platform_data *pdata;
1104 struct resource *res;
1106 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1110 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116 base = ioremap(res->start, PAGE_SIZE);
1122 sport->port.dev = &pdev->dev;
1123 sport->port.mapbase = res->start;
1124 sport->port.membase = base;
1125 sport->port.type = PORT_IMX,
1126 sport->port.iotype = UPIO_MEM;
1127 sport->port.irq = platform_get_irq(pdev, 0);
1128 sport->rxirq = platform_get_irq(pdev, 0);
1129 sport->txirq = platform_get_irq(pdev, 1);
1130 sport->rtsirq = platform_get_irq(pdev, 2);
1131 sport->port.fifosize = 32;
1132 sport->port.ops = &imx_pops;
1133 sport->port.flags = UPF_BOOT_AUTOCONF;
1134 sport->port.line = pdev->id;
1135 init_timer(&sport->timer);
1136 sport->timer.function = imx_timeout;
1137 sport->timer.data = (unsigned long)sport;
1139 sport->clk = clk_get(&pdev->dev, "uart");
1140 if (IS_ERR(sport->clk)) {
1141 ret = PTR_ERR(sport->clk);
1144 clk_enable(sport->clk);
1146 sport->port.uartclk = clk_get_rate(sport->clk);
1148 imx_ports[pdev->id] = sport;
1150 pdata = pdev->dev.platform_data;
1151 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1152 sport->have_rtscts = 1;
1155 ret = pdata->init(pdev);
1160 ret = uart_add_one_port(&imx_reg, &sport->port);
1163 platform_set_drvdata(pdev, &sport->port);
1170 clk_put(sport->clk);
1171 clk_disable(sport->clk);
1173 iounmap(sport->port.membase);
1180 static int serial_imx_remove(struct platform_device *pdev)
1182 struct imxuart_platform_data *pdata;
1183 struct imx_port *sport = platform_get_drvdata(pdev);
1185 pdata = pdev->dev.platform_data;
1187 platform_set_drvdata(pdev, NULL);
1190 uart_remove_one_port(&imx_reg, &sport->port);
1191 clk_put(sport->clk);
1194 clk_disable(sport->clk);
1199 iounmap(sport->port.membase);
1205 static struct platform_driver serial_imx_driver = {
1206 .probe = serial_imx_probe,
1207 .remove = serial_imx_remove,
1209 .suspend = serial_imx_suspend,
1210 .resume = serial_imx_resume,
1213 .owner = THIS_MODULE,
1217 static int __init imx_serial_init(void)
1221 printk(KERN_INFO "Serial: IMX driver\n");
1223 ret = uart_register_driver(&imx_reg);
1227 ret = platform_driver_register(&serial_imx_driver);
1229 uart_unregister_driver(&imx_reg);
1234 static void __exit imx_serial_exit(void)
1236 platform_driver_unregister(&serial_imx_driver);
1237 uart_unregister_driver(&imx_reg);
1240 module_init(imx_serial_init);
1241 module_exit(imx_serial_exit);
1243 MODULE_AUTHOR("Sascha Hauer");
1244 MODULE_DESCRIPTION("IMX generic serial port driver");
1245 MODULE_LICENSE("GPL");
1246 MODULE_ALIAS("platform:imx-uart");