drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * init function returns:
  38  *  > 0 - number of ports
  39  *  = 0 - use board->num_ports
  40  *  < 0 - error
  41  */
  42 struct pci_serial_quirk {
  43         u32     vendor;
  44         u32     device;
  45         u32     subvendor;
  46         u32     subdevice;
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *, struct pciserial_board *,
  49                          struct uart_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING "%s: %s\n"
  66                KERN_WARNING "Please send the output of lspci -vv, this\n"
  67                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                KERN_WARNING "manufacturer and name of serial board or\n"
  69                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * AFAVLAB uses a different mixture of BARs and offsets
 111  * Not that ugly ;) -- HW
 112  */
 113 static int
 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 115               struct uart_port *port, int idx)
 116 {
 117         unsigned int bar, offset = board->first_offset;
 118
 119         bar = FL_GET_BASE(board->flags);
 120         if (idx < 4)
 121                 bar += idx;
 122         else {
 123                 bar = 4;
 124                 offset += (idx - 4) * board->uart_offset;
 125         }
 126
 127         return setup_port(priv, port, bar, offset, board->reg_shift);
 128 }
 129
 130 /*
 131  * HP's Remote Management Console.  The Diva chip came in several
 132  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 133  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 134  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 135  * one Diva chip, but it has been expanded to 5 UARTs.
 136  */
 137 static int pci_hp_diva_init(struct pci_dev *dev)
 138 {
 139         int rc = 0;
 140
 141         switch (dev->subsystem_device) {
 142         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 143         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 144         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 145         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 146                 rc = 3;
 147                 break;
 148         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 149                 rc = 2;
 150                 break;
 151         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 152                 rc = 4;
 153                 break;
 154         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 155         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 156                 rc = 1;
 157                 break;
 158         }
 159
 160         return rc;
 161 }
 162
 163 /*
 164  * HP's Diva chip puts the 4th/5th serial port further out, and
 165  * some serial ports are supposed to be hidden on certain models.
 166  */
 167 static int
 168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 169               struct uart_port *port, int idx)
 170 {
 171         unsigned int offset = board->first_offset;
 172         unsigned int bar = FL_GET_BASE(board->flags);
 173
 174         switch (priv->dev->subsystem_device) {
 175         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 176                 if (idx == 3)
 177                         idx++;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 180                 if (idx > 0)
 181                         idx++;
 182                 if (idx > 2)
 183                         idx++;
 184                 break;
 185         }
 186         if (idx > 2)
 187                 offset = 0x18;
 188
 189         offset += idx * board->uart_offset;
 190
 191         return setup_port(priv, port, bar, offset, board->reg_shift);
 192 }
 193
 194 /*
 195  * Added for EKF Intel i960 serial boards
 196  */
 197 static int pci_inteli960ni_init(struct pci_dev *dev)
 198 {
 199         unsigned long oldval;
 200
 201         if (!(dev->subsystem_device & 0x1000))
 202                 return -ENODEV;
 203
 204         /* is firmware started? */
 205         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 206         if (oldval == 0x00001000L) { /* RESET value */
 207                 printk(KERN_DEBUG "Local i960 firmware missing");
 208                 return -ENODEV;
 209         }
 210         return 0;
 211 }
 212
 213 /*
 214  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 215  * that the card interrupt be explicitly enabled or disabled.  This
 216  * seems to be mainly needed on card using the PLX which also use I/O
 217  * mapped memory.
 218  */
 219 static int pci_plx9050_init(struct pci_dev *dev)
 220 {
 221         u8 irq_config;
 222         void __iomem *p;
 223
 224         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 225                 moan_device("no memory in bar 0", dev);
 226                 return 0;
 227         }
 228
 229         irq_config = 0x41;
 230         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 231             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 232                 irq_config = 0x43;
 233         }
 234         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 235             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 236                 /*
 237                  * As the megawolf cards have the int pins active
 238                  * high, and have 2 UART chips, both ints must be
 239                  * enabled on the 9050. Also, the UARTS are set in
 240                  * 16450 mode by default, so we have to enable the
 241                  * 16C950 'enhanced' mode so that we can use the
 242                  * deep FIFOs
 243                  */
 244                 irq_config = 0x5b;
 245         }
 246
 247         /*
 248          * enable/disable interrupts
 249          */
 250         p = ioremap(pci_resource_start(dev, 0), 0x80);
 251         if (p == NULL)
 252                 return -ENOMEM;
 253         writel(irq_config, p + 0x4c);
 254
 255         /*
 256          * Read the register back to ensure that it took effect.
 257          */
 258         readl(p + 0x4c);
 259         iounmap(p);
 260
 261         return 0;
 262 }
 263
 264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 265 {
 266         u8 __iomem *p;
 267
 268         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 269                 return;
 270
 271         /*
 272          * disable interrupts
 273          */
 274         p = ioremap(pci_resource_start(dev, 0), 0x80);
 275         if (p != NULL) {
 276                 writel(0, p + 0x4c);
 277
 278                 /*
 279                  * Read the register back to ensure that it took effect.
 280                  */
 281                 readl(p + 0x4c);
 282                 iounmap(p);
 283         }
 284 }
 285
 286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 287 static int
 288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 289                 struct uart_port *port, int idx)
 290 {
 291         unsigned int bar, offset = board->first_offset;
 292
 293         bar = 0;
 294
 295         if (idx < 4) {
 296                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 297                 offset += idx * board->uart_offset;
 298         } else if (idx < 8) {
 299                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 300                 offset += idx * board->uart_offset + 0xC00;
 301         } else /* we have only 8 ports on PMC-OCTALPRO */
 302                 return 1;
 303
 304         return setup_port(priv, port, bar, offset, board->reg_shift);
 305 }
 306
 307 /*
 308 * This does initialization for PMC OCTALPRO cards:
 309 * maps the device memory, resets the UARTs (needed, bc
 310 * if the module is removed and inserted again, the card
 311 * is in the sleep mode) and enables global interrupt.
 312 */
 313
 314 /* global control register offset for SBS PMC-OctalPro */
 315 #define OCT_REG_CR_OFF          0x500
 316
 317 static int sbs_init(struct pci_dev *dev)
 318 {
 319         u8 __iomem *p;
 320
 321         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 322
 323         if (p == NULL)
 324                 return -ENOMEM;
 325         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 326         writeb(0x10,p + OCT_REG_CR_OFF);
 327         udelay(50);
 328         writeb(0x0,p + OCT_REG_CR_OFF);
 329
 330         /* Set bit-2 (INTENABLE) of Control Register */
 331         writeb(0x4, p + OCT_REG_CR_OFF);
 332         iounmap(p);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Disables the global interrupt of PMC-OctalPro
 339  */
 340
 341 static void __devexit sbs_exit(struct pci_dev *dev)
 342 {
 343         u8 __iomem *p;
 344
 345         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 346         if (p != NULL) {
 347                 writeb(0, p + OCT_REG_CR_OFF);
 348         }
 349         iounmap(p);
 350 }
 351
 352 /*
 353  * SIIG serial cards have an PCI interface chip which also controls
 354  * the UART clocking frequency. Each UART can be clocked independently
 355  * (except cards equiped with 4 UARTs) and initial clocking settings
 356  * are stored in the EEPROM chip. It can cause problems because this
 357  * version of serial driver doesn't support differently clocked UART's
 358  * on single PCI card. To prevent this, initialization functions set
 359  * high frequency clocking for all UART's on given card. It is safe (I
 360  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 361  * with other OSes (like M$ DOS).
 362  *
 363  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 364  *
 365  * There is two family of SIIG serial cards with different PCI
 366  * interface chip and different configuration methods:
 367  *     - 10x cards have control registers in IO and/or memory space;
 368  *     - 20x cards have control registers in standard PCI configuration space.
 369  *
 370  * Note: all 10x cards have PCI device ids 0x10..
 371  *       all 20x cards have PCI device ids 0x20..
 372  *
 373  * There are also Quartet Serial cards which use Oxford Semiconductor
 374  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 375  *
 376  * Note: some SIIG cards are probed by the parport_serial object.
 377  */
 378
 379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 381
 382 static int pci_siig10x_init(struct pci_dev *dev)
 383 {
 384         u16 data;
 385         void __iomem *p;
 386
 387         switch (dev->device & 0xfff8) {
 388         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 389                 data = 0xffdf;
 390                 break;
 391         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 392                 data = 0xf7ff;
 393                 break;
 394         default:                        /* 1S1P, 4S */
 395                 data = 0xfffb;
 396                 break;
 397         }
 398
 399         p = ioremap(pci_resource_start(dev, 0), 0x80);
 400         if (p == NULL)
 401                 return -ENOMEM;
 402
 403         writew(readw(p + 0x28) & data, p + 0x28);
 404         readw(p + 0x28);
 405         iounmap(p);
 406         return 0;
 407 }
 408
 409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 411
 412 static int pci_siig20x_init(struct pci_dev *dev)
 413 {
 414         u8 data;
 415
 416         /* Change clock frequency for the first UART. */
 417         pci_read_config_byte(dev, 0x6f, &data);
 418         pci_write_config_byte(dev, 0x6f, data & 0xef);
 419
 420         /* If this card has 2 UART, we have to do the same with second UART. */
 421         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 422             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 423                 pci_read_config_byte(dev, 0x73, &data);
 424                 pci_write_config_byte(dev, 0x73, data & 0xef);
 425         }
 426         return 0;
 427 }
 428
 429 static int pci_siig_init(struct pci_dev *dev)
 430 {
 431         unsigned int type = dev->device & 0xff00;
 432
 433         if (type == 0x1000)
 434                 return pci_siig10x_init(dev);
 435         else if (type == 0x2000)
 436                 return pci_siig20x_init(dev);
 437
 438         moan_device("Unknown SIIG card", dev);
 439         return -ENODEV;
 440 }
 441
 442 static int pci_siig_setup(struct serial_private *priv,
 443                           struct pciserial_board *board,
 444                           struct uart_port *port, int idx)
 445 {
 446         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 447
 448         if (idx > 3) {
 449                 bar = 4;
 450                 offset = (idx - 4) * 8;
 451         }
 452
 453         return setup_port(priv, port, bar, offset, 0);
 454 }
 455
 456 /*
 457  * Timedia has an explosion of boards, and to avoid the PCI table from
 458  * growing *huge*, we use this function to collapse some 70 entries
 459  * in the PCI table into one, for sanity's and compactness's sake.
 460  */
 461 static const unsigned short timedia_single_port[] = {
 462         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 463 };
 464
 465 static const unsigned short timedia_dual_port[] = {
 466         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 467         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 468         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 469         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 470         0xD079, 0
 471 };
 472
 473 static const unsigned short timedia_quad_port[] = {
 474         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 475         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 476         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 477         0xB157, 0
 478 };
 479
 480 static const unsigned short timedia_eight_port[] = {
 481         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 482         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 483 };
 484
 485 static const struct timedia_struct {
 486         int num;
 487         const unsigned short *ids;
 488 } timedia_data[] = {
 489         { 1, timedia_single_port },
 490         { 2, timedia_dual_port },
 491         { 4, timedia_quad_port },
 492         { 8, timedia_eight_port }
 493 };
 494
 495 static int pci_timedia_init(struct pci_dev *dev)
 496 {
 497         const unsigned short *ids;
 498         int i, j;
 499
 500         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 501                 ids = timedia_data[i].ids;
 502                 for (j = 0; ids[j]; j++)
 503                         if (dev->subsystem_device == ids[j])
 504                                 return timedia_data[i].num;
 505         }
 506         return 0;
 507 }
 508
 509 /*
 510  * Timedia/SUNIX uses a mixture of BARs and offsets
 511  * Ugh, this is ugly as all hell --- TYT
 512  */
 513 static int
 514 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 515                   struct uart_port *port, int idx)
 516 {
 517         unsigned int bar = 0, offset = board->first_offset;
 518
 519         switch (idx) {
 520         case 0:
 521                 bar = 0;
 522                 break;
 523         case 1:
 524                 offset = board->uart_offset;
 525                 bar = 0;
 526                 break;
 527         case 2:
 528                 bar = 1;
 529                 break;
 530         case 3:
 531                 offset = board->uart_offset;
 532                 /* FALLTHROUGH */
 533         case 4: /* BAR 2 */
 534         case 5: /* BAR 3 */
 535         case 6: /* BAR 4 */
 536         case 7: /* BAR 5 */
 537                 bar = idx - 2;
 538         }
 539
 540         return setup_port(priv, port, bar, offset, board->reg_shift);
 541 }
 542
 543 /*
 544  * Some Titan cards are also a little weird
 545  */
 546 static int
 547 titan_400l_800l_setup(struct serial_private *priv,
 548                       struct pciserial_board *board,
 549                       struct uart_port *port, int idx)
 550 {
 551         unsigned int bar, offset = board->first_offset;
 552
 553         switch (idx) {
 554         case 0:
 555                 bar = 1;
 556                 break;
 557         case 1:
 558                 bar = 2;
 559                 break;
 560         default:
 561                 bar = 4;
 562                 offset = (idx - 2) * board->uart_offset;
 563         }
 564
 565         return setup_port(priv, port, bar, offset, board->reg_shift);
 566 }
 567
 568 static int pci_xircom_init(struct pci_dev *dev)
 569 {
 570         msleep(100);
 571         return 0;
 572 }
 573
 574 static int pci_netmos_init(struct pci_dev *dev)
 575 {
 576         /* subdevice 0x00PS means <P> parallel, <S> serial */
 577         unsigned int num_serial = dev->subsystem_device & 0xf;
 578
 579         if (num_serial == 0)
 580                 return -ENODEV;
 581         return num_serial;
 582 }
 583
 584 static int
 585 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 586                   struct uart_port *port, int idx)
 587 {
 588         unsigned int bar, offset = board->first_offset, maxnr;
 589
 590         bar = FL_GET_BASE(board->flags);
 591         if (board->flags & FL_BASE_BARS)
 592                 bar += idx;
 593         else
 594                 offset += idx * board->uart_offset;
 595
 596         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 597                 (board->reg_shift + 3);
 598
 599         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 600                 return 1;
 601
 602         return setup_port(priv, port, bar, offset, board->reg_shift);
 603 }
 604
 605 /* This should be in linux/pci_ids.h */
 606 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 607 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 608 #define PCI_DEVICE_ID_OCTPRO            0x0001
 609 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 610 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 611 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 612 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 613
 614 /*
 615  * Master list of serial port init/setup/exit quirks.
 616  * This does not describe the general nature of the port.
 617  * (ie, baud base, number and location of ports, etc)
 618  *
 619  * This list is ordered alphabetically by vendor then device.
 620  * Specific entries must come before more generic entries.
 621  */
 622 static struct pci_serial_quirk pci_serial_quirks[] = {
 623         /*
 624          * AFAVLAB cards - these may be called via parport_serial
 625          *  It is not clear whether this applies to all products.
 626          */
 627         {
 628                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 629                 .device         = PCI_ANY_ID,
 630                 .subvendor      = PCI_ANY_ID,
 631                 .subdevice      = PCI_ANY_ID,
 632                 .setup          = afavlab_setup,
 633         },
 634         /*
 635          * HP Diva
 636          */
 637         {
 638                 .vendor         = PCI_VENDOR_ID_HP,
 639                 .device         = PCI_DEVICE_ID_HP_DIVA,
 640                 .subvendor      = PCI_ANY_ID,
 641                 .subdevice      = PCI_ANY_ID,
 642                 .init           = pci_hp_diva_init,
 643                 .setup          = pci_hp_diva_setup,
 644         },
 645         /*
 646          * Intel
 647          */
 648         {
 649                 .vendor         = PCI_VENDOR_ID_INTEL,
 650                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 651                 .subvendor      = 0xe4bf,
 652                 .subdevice      = PCI_ANY_ID,
 653                 .init           = pci_inteli960ni_init,
 654                 .setup          = pci_default_setup,
 655         },
 656         /*
 657          * Panacom
 658          */
 659         {
 660                 .vendor         = PCI_VENDOR_ID_PANACOM,
 661                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 662                 .subvendor      = PCI_ANY_ID,
 663                 .subdevice      = PCI_ANY_ID,
 664                 .init           = pci_plx9050_init,
 665                 .setup          = pci_default_setup,
 666                 .exit           = __devexit_p(pci_plx9050_exit),
 667         },
 668         {
 669                 .vendor         = PCI_VENDOR_ID_PANACOM,
 670                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 671                 .subvendor      = PCI_ANY_ID,
 672                 .subdevice      = PCI_ANY_ID,
 673                 .init           = pci_plx9050_init,
 674                 .setup          = pci_default_setup,
 675                 .exit           = __devexit_p(pci_plx9050_exit),
 676         },
 677         /*
 678          * PLX
 679          */
 680         {
 681                 .vendor         = PCI_VENDOR_ID_PLX,
 682                 .device         = PCI_DEVICE_ID_PLX_9030,
 683                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 684                 .subdevice      = PCI_ANY_ID,
 685                 .setup          = pci_default_setup,
 686         },
 687         {
 688                 .vendor         = PCI_VENDOR_ID_PLX,
 689                 .device         = PCI_DEVICE_ID_PLX_9050,
 690                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 691                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 692                 .init           = pci_plx9050_init,
 693                 .setup          = pci_default_setup,
 694                 .exit           = __devexit_p(pci_plx9050_exit),
 695         },
 696         {
 697                 .vendor         = PCI_VENDOR_ID_PLX,
 698                 .device         = PCI_DEVICE_ID_PLX_9050,
 699                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 700                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 701                 .init           = pci_plx9050_init,
 702                 .setup          = pci_default_setup,
 703                 .exit           = __devexit_p(pci_plx9050_exit),
 704         },
 705         {
 706                 .vendor         = PCI_VENDOR_ID_PLX,
 707                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 708                 .subvendor      = PCI_VENDOR_ID_PLX,
 709                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 710                 .init           = pci_plx9050_init,
 711                 .setup          = pci_default_setup,
 712                 .exit           = __devexit_p(pci_plx9050_exit),
 713         },
 714         /*
 715          * SBS Technologies, Inc., PMC-OCTALPRO 232
 716          */
 717         {
 718                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 719                 .device         = PCI_DEVICE_ID_OCTPRO,
 720                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 721                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 722                 .init           = sbs_init,
 723                 .setup          = sbs_setup,
 724                 .exit           = __devexit_p(sbs_exit),
 725         },
 726         /*
 727          * SBS Technologies, Inc., PMC-OCTALPRO 422
 728          */
 729         {
 730                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 731                 .device         = PCI_DEVICE_ID_OCTPRO,
 732                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 733                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 734                 .init           = sbs_init,
 735                 .setup          = sbs_setup,
 736                 .exit           = __devexit_p(sbs_exit),
 737         },
 738         /*
 739          * SBS Technologies, Inc., P-Octal 232
 740          */
 741         {
 742                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 743                 .device         = PCI_DEVICE_ID_OCTPRO,
 744                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 745                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 746                 .init           = sbs_init,
 747                 .setup          = sbs_setup,
 748                 .exit           = __devexit_p(sbs_exit),
 749         },
 750         /*
 751          * SBS Technologies, Inc., P-Octal 422
 752          */
 753         {
 754                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 755                 .device         = PCI_DEVICE_ID_OCTPRO,
 756                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 757                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 758                 .init           = sbs_init,
 759                 .setup          = sbs_setup,
 760                 .exit           = __devexit_p(sbs_exit),
 761         },
 762         /*
 763          * SIIG cards - these may be called via parport_serial
 764          */
 765         {
 766                 .vendor         = PCI_VENDOR_ID_SIIG,
 767                 .device         = PCI_ANY_ID,
 768                 .subvendor      = PCI_ANY_ID,
 769                 .subdevice      = PCI_ANY_ID,
 770                 .init           = pci_siig_init,
 771                 .setup          = pci_siig_setup,
 772         },
 773         /*
 774          * Titan cards
 775          */
 776         {
 777                 .vendor         = PCI_VENDOR_ID_TITAN,
 778                 .device         = PCI_DEVICE_ID_TITAN_400L,
 779                 .subvendor      = PCI_ANY_ID,
 780                 .subdevice      = PCI_ANY_ID,
 781                 .setup          = titan_400l_800l_setup,
 782         },
 783         {
 784                 .vendor         = PCI_VENDOR_ID_TITAN,
 785                 .device         = PCI_DEVICE_ID_TITAN_800L,
 786                 .subvendor      = PCI_ANY_ID,
 787                 .subdevice      = PCI_ANY_ID,
 788                 .setup          = titan_400l_800l_setup,
 789         },
 790         /*
 791          * Timedia cards
 792          */
 793         {
 794                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 795                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 796                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 797                 .subdevice      = PCI_ANY_ID,
 798                 .init           = pci_timedia_init,
 799                 .setup          = pci_timedia_setup,
 800         },
 801         {
 802                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 803                 .device         = PCI_ANY_ID,
 804                 .subvendor      = PCI_ANY_ID,
 805                 .subdevice      = PCI_ANY_ID,
 806                 .setup          = pci_timedia_setup,
 807         },
 808         /*
 809          * Xircom cards
 810          */
 811         {
 812                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 813                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 814                 .subvendor      = PCI_ANY_ID,
 815                 .subdevice      = PCI_ANY_ID,
 816                 .init           = pci_xircom_init,
 817                 .setup          = pci_default_setup,
 818         },
 819         /*
 820          * Netmos cards - these may be called via parport_serial
 821          */
 822         {
 823                 .vendor         = PCI_VENDOR_ID_NETMOS,
 824                 .device         = PCI_ANY_ID,
 825                 .subvendor      = PCI_ANY_ID,
 826                 .subdevice      = PCI_ANY_ID,
 827                 .init           = pci_netmos_init,
 828                 .setup          = pci_default_setup,
 829         },
 830         /*
 831          * Default "match everything" terminator entry
 832          */
 833         {
 834                 .vendor         = PCI_ANY_ID,
 835                 .device         = PCI_ANY_ID,
 836                 .subvendor      = PCI_ANY_ID,
 837                 .subdevice      = PCI_ANY_ID,
 838                 .setup          = pci_default_setup,
 839         }
 840 };
 841
 842 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 843 {
 844         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 845 }
 846
 847 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 848 {
 849         struct pci_serial_quirk *quirk;
 850
 851         for (quirk = pci_serial_quirks; ; quirk++)
 852                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 853                     quirk_id_matches(quirk->device, dev->device) &&
 854                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 855                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 856                         break;
 857         return quirk;
 858 }
 859
 860 static inline int get_pci_irq(struct pci_dev *dev,
 861                                 struct pciserial_board *board)
 862 {
 863         if (board->flags & FL_NOIRQ)
 864                 return 0;
 865         else
 866                 return dev->irq;
 867 }
 868
 869 /*
 870  * This is the configuration table for all of the PCI serial boards
 871  * which we support.  It is directly indexed by the pci_board_num_t enum
 872  * value, which is encoded in the pci_device_id PCI probe table's
 873  * driver_data member.
 874  *
 875  * The makeup of these names are:
 876  *  pbn_bn{_bt}_n_baud{_offsetinhex}
 877  *
 878  *  bn          = PCI BAR number
 879  *  bt          = Index using PCI BARs
 880  *  n           = number of serial ports
 881  *  baud        = baud rate
 882  *  offsetinhex = offset for each sequential port (in hex)
 883  *
 884  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
 885  *
 886  * Please note: in theory if n = 1, _bt infix should make no difference.
 887  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 888  */
 889 enum pci_board_num_t {
 890         pbn_default = 0,
 891
 892         pbn_b0_1_115200,
 893         pbn_b0_2_115200,
 894         pbn_b0_4_115200,
 895         pbn_b0_5_115200,
 896
 897         pbn_b0_1_921600,
 898         pbn_b0_2_921600,
 899         pbn_b0_4_921600,
 900
 901         pbn_b0_2_1130000,
 902
 903         pbn_b0_4_1152000,
 904
 905         pbn_b0_2_1843200,
 906         pbn_b0_4_1843200,
 907
 908         pbn_b0_2_1843200_200,
 909         pbn_b0_4_1843200_200,
 910         pbn_b0_8_1843200_200,
 911
 912         pbn_b0_bt_1_115200,
 913         pbn_b0_bt_2_115200,
 914         pbn_b0_bt_8_115200,
 915
 916         pbn_b0_bt_1_460800,
 917         pbn_b0_bt_2_460800,
 918         pbn_b0_bt_4_460800,
 919
 920         pbn_b0_bt_1_921600,
 921         pbn_b0_bt_2_921600,
 922         pbn_b0_bt_4_921600,
 923         pbn_b0_bt_8_921600,
 924
 925         pbn_b1_1_115200,
 926         pbn_b1_2_115200,
 927         pbn_b1_4_115200,
 928         pbn_b1_8_115200,
 929
 930         pbn_b1_1_921600,
 931         pbn_b1_2_921600,
 932         pbn_b1_4_921600,
 933         pbn_b1_8_921600,
 934
 935         pbn_b1_2_1250000,
 936
 937         pbn_b1_bt_2_921600,
 938
 939         pbn_b1_1_1382400,
 940         pbn_b1_2_1382400,
 941         pbn_b1_4_1382400,
 942         pbn_b1_8_1382400,
 943
 944         pbn_b2_1_115200,
 945         pbn_b2_2_115200,
 946         pbn_b2_4_115200,
 947         pbn_b2_8_115200,
 948
 949         pbn_b2_1_460800,
 950         pbn_b2_4_460800,
 951         pbn_b2_8_460800,
 952         pbn_b2_16_460800,
 953
 954         pbn_b2_1_921600,
 955         pbn_b2_4_921600,
 956         pbn_b2_8_921600,
 957
 958         pbn_b2_bt_1_115200,
 959         pbn_b2_bt_2_115200,
 960         pbn_b2_bt_4_115200,
 961
 962         pbn_b2_bt_2_921600,
 963         pbn_b2_bt_4_921600,
 964
 965         pbn_b3_2_115200,
 966         pbn_b3_4_115200,
 967         pbn_b3_8_115200,
 968
 969         /*
 970          * Board-specific versions.
 971          */
 972         pbn_panacom,
 973         pbn_panacom2,
 974         pbn_panacom4,
 975         pbn_exsys_4055,
 976         pbn_plx_romulus,
 977         pbn_oxsemi,
 978         pbn_intel_i960,
 979         pbn_sgi_ioc3,
 980         pbn_nec_nile4,
 981         pbn_computone_4,
 982         pbn_computone_6,
 983         pbn_computone_8,
 984         pbn_sbsxrsio,
 985         pbn_exar_XR17C152,
 986         pbn_exar_XR17C154,
 987         pbn_exar_XR17C158,
 988 };
 989
 990 /*
 991  * uart_offset - the space between channels
 992  * reg_shift   - describes how the UART registers are mapped
 993  *               to PCI memory by the card.
 994  * For example IER register on SBS, Inc. PMC-OctPro is located at
 995  * offset 0x10 from the UART base, while UART_IER is defined as 1
 996  * in include/linux/serial_reg.h,
 997  * see first lines of serial_in() and serial_out() in 8250.c
 998 */
 999
1000 static struct pciserial_board pci_boards[] __devinitdata = {
1001         [pbn_default] = {
1002                 .flags          = FL_BASE0,
1003                 .num_ports      = 1,
1004                 .base_baud      = 115200,
1005                 .uart_offset    = 8,
1006         },
1007         [pbn_b0_1_115200] = {
1008                 .flags          = FL_BASE0,
1009                 .num_ports      = 1,
1010                 .base_baud      = 115200,
1011                 .uart_offset    = 8,
1012         },
1013         [pbn_b0_2_115200] = {
1014                 .flags          = FL_BASE0,
1015                 .num_ports      = 2,
1016                 .base_baud      = 115200,
1017                 .uart_offset    = 8,
1018         },
1019         [pbn_b0_4_115200] = {
1020                 .flags          = FL_BASE0,
1021                 .num_ports      = 4,
1022                 .base_baud      = 115200,
1023                 .uart_offset    = 8,
1024         },
1025         [pbn_b0_5_115200] = {
1026                 .flags          = FL_BASE0,
1027                 .num_ports      = 5,
1028                 .base_baud      = 115200,
1029                 .uart_offset    = 8,
1030         },
1031
1032         [pbn_b0_1_921600] = {
1033                 .flags          = FL_BASE0,
1034                 .num_ports      = 1,
1035                 .base_baud      = 921600,
1036                 .uart_offset    = 8,
1037         },
1038         [pbn_b0_2_921600] = {
1039                 .flags          = FL_BASE0,
1040                 .num_ports      = 2,
1041                 .base_baud      = 921600,
1042                 .uart_offset    = 8,
1043         },
1044         [pbn_b0_4_921600] = {
1045                 .flags          = FL_BASE0,
1046                 .num_ports      = 4,
1047                 .base_baud      = 921600,
1048                 .uart_offset    = 8,
1049         },
1050
1051         [pbn_b0_2_1130000] = {
1052                 .flags          = FL_BASE0,
1053                 .num_ports      = 2,
1054                 .base_baud      = 1130000,
1055                 .uart_offset    = 8,
1056         },
1057
1058         [pbn_b0_4_1152000] = {
1059                 .flags          = FL_BASE0,
1060                 .num_ports      = 4,
1061                 .base_baud      = 1152000,
1062                 .uart_offset    = 8,
1063         },
1064
1065         [pbn_b0_2_1843200] = {
1066                 .flags          = FL_BASE0,
1067                 .num_ports      = 2,
1068                 .base_baud      = 1843200,
1069                 .uart_offset    = 8,
1070         },
1071         [pbn_b0_4_1843200] = {
1072                 .flags          = FL_BASE0,
1073                 .num_ports      = 4,
1074                 .base_baud      = 1843200,
1075                 .uart_offset    = 8,
1076         },
1077
1078         [pbn_b0_2_1843200_200] = {
1079                 .flags          = FL_BASE0,
1080                 .num_ports      = 2,
1081                 .base_baud      = 1843200,
1082                 .uart_offset    = 0x200,
1083         },
1084         [pbn_b0_4_1843200_200] = {
1085                 .flags          = FL_BASE0,
1086                 .num_ports      = 4,
1087                 .base_baud      = 1843200,
1088                 .uart_offset    = 0x200,
1089         },
1090         [pbn_b0_8_1843200_200] = {
1091                 .flags          = FL_BASE0,
1092                 .num_ports      = 8,
1093                 .base_baud      = 1843200,
1094                 .uart_offset    = 0x200,
1095         },
1096
1097         [pbn_b0_bt_1_115200] = {
1098                 .flags          = FL_BASE0|FL_BASE_BARS,
1099                 .num_ports      = 1,
1100                 .base_baud      = 115200,
1101                 .uart_offset    = 8,
1102         },
1103         [pbn_b0_bt_2_115200] = {
1104                 .flags          = FL_BASE0|FL_BASE_BARS,
1105                 .num_ports      = 2,
1106                 .base_baud      = 115200,
1107                 .uart_offset    = 8,
1108         },
1109         [pbn_b0_bt_8_115200] = {
1110                 .flags          = FL_BASE0|FL_BASE_BARS,
1111                 .num_ports      = 8,
1112                 .base_baud      = 115200,
1113                 .uart_offset    = 8,
1114         },
1115
1116         [pbn_b0_bt_1_460800] = {
1117                 .flags          = FL_BASE0|FL_BASE_BARS,
1118                 .num_ports      = 1,
1119                 .base_baud      = 460800,
1120                 .uart_offset    = 8,
1121         },
1122         [pbn_b0_bt_2_460800] = {
1123                 .flags          = FL_BASE0|FL_BASE_BARS,
1124                 .num_ports      = 2,
1125                 .base_baud      = 460800,
1126                 .uart_offset    = 8,
1127         },
1128         [pbn_b0_bt_4_460800] = {
1129                 .flags          = FL_BASE0|FL_BASE_BARS,
1130                 .num_ports      = 4,
1131                 .base_baud      = 460800,
1132                 .uart_offset    = 8,
1133         },
1134
1135         [pbn_b0_bt_1_921600] = {
1136                 .flags          = FL_BASE0|FL_BASE_BARS,
1137                 .num_ports      = 1,
1138                 .base_baud      = 921600,
1139                 .uart_offset    = 8,
1140         },
1141         [pbn_b0_bt_2_921600] = {
1142                 .flags          = FL_BASE0|FL_BASE_BARS,
1143                 .num_ports      = 2,
1144                 .base_baud      = 921600,
1145                 .uart_offset    = 8,
1146         },
1147         [pbn_b0_bt_4_921600] = {
1148                 .flags          = FL_BASE0|FL_BASE_BARS,
1149                 .num_ports      = 4,
1150                 .base_baud      = 921600,
1151                 .uart_offset    = 8,
1152         },
1153         [pbn_b0_bt_8_921600] = {
1154                 .flags          = FL_BASE0|FL_BASE_BARS,
1155                 .num_ports      = 8,
1156                 .base_baud      = 921600,
1157                 .uart_offset    = 8,
1158         },
1159
1160         [pbn_b1_1_115200] = {
1161                 .flags          = FL_BASE1,
1162                 .num_ports      = 1,
1163                 .base_baud      = 115200,
1164                 .uart_offset    = 8,
1165         },
1166         [pbn_b1_2_115200] = {
1167                 .flags          = FL_BASE1,
1168                 .num_ports      = 2,
1169                 .base_baud      = 115200,
1170                 .uart_offset    = 8,
1171         },
1172         [pbn_b1_4_115200] = {
1173                 .flags          = FL_BASE1,
1174                 .num_ports      = 4,
1175                 .base_baud      = 115200,
1176                 .uart_offset    = 8,
1177         },
1178         [pbn_b1_8_115200] = {
1179                 .flags          = FL_BASE1,
1180                 .num_ports      = 8,
1181                 .base_baud      = 115200,
1182                 .uart_offset    = 8,
1183         },
1184
1185         [pbn_b1_1_921600] = {
1186                 .flags          = FL_BASE1,
1187                 .num_ports      = 1,
1188                 .base_baud      = 921600,
1189                 .uart_offset    = 8,
1190         },
1191         [pbn_b1_2_921600] = {
1192                 .flags          = FL_BASE1,
1193                 .num_ports      = 2,
1194                 .base_baud      = 921600,
1195                 .uart_offset    = 8,
1196         },
1197         [pbn_b1_4_921600] = {
1198                 .flags          = FL_BASE1,
1199                 .num_ports      = 4,
1200                 .base_baud      = 921600,
1201                 .uart_offset    = 8,
1202         },
1203         [pbn_b1_8_921600] = {
1204                 .flags          = FL_BASE1,
1205                 .num_ports      = 8,
1206                 .base_baud      = 921600,
1207                 .uart_offset    = 8,
1208         },
1209         [pbn_b1_2_1250000] = {
1210                 .flags          = FL_BASE1,
1211                 .num_ports      = 2,
1212                 .base_baud      = 1250000,
1213                 .uart_offset    = 8,
1214         },
1215
1216         [pbn_b1_bt_2_921600] = {
1217                 .flags          = FL_BASE1|FL_BASE_BARS,
1218                 .num_ports      = 2,
1219                 .base_baud      = 921600,
1220                 .uart_offset    = 8,
1221         },
1222
1223         [pbn_b1_1_1382400] = {
1224                 .flags          = FL_BASE1,
1225                 .num_ports      = 1,
1226                 .base_baud      = 1382400,
1227                 .uart_offset    = 8,
1228         },
1229         [pbn_b1_2_1382400] = {
1230                 .flags          = FL_BASE1,
1231                 .num_ports      = 2,
1232                 .base_baud      = 1382400,
1233                 .uart_offset    = 8,
1234         },
1235         [pbn_b1_4_1382400] = {
1236                 .flags          = FL_BASE1,
1237                 .num_ports      = 4,
1238                 .base_baud      = 1382400,
1239                 .uart_offset    = 8,
1240         },
1241         [pbn_b1_8_1382400] = {
1242                 .flags          = FL_BASE1,
1243                 .num_ports      = 8,
1244                 .base_baud      = 1382400,
1245                 .uart_offset    = 8,
1246         },
1247
1248         [pbn_b2_1_115200] = {
1249                 .flags          = FL_BASE2,
1250                 .num_ports      = 1,
1251                 .base_baud      = 115200,
1252                 .uart_offset    = 8,
1253         },
1254         [pbn_b2_2_115200] = {
1255                 .flags          = FL_BASE2,
1256                 .num_ports      = 2,
1257                 .base_baud      = 115200,
1258                 .uart_offset    = 8,
1259         },
1260         [pbn_b2_4_115200] = {
1261                 .flags          = FL_BASE2,
1262                 .num_ports      = 4,
1263                 .base_baud      = 115200,
1264                 .uart_offset    = 8,
1265         },
1266         [pbn_b2_8_115200] = {
1267                 .flags          = FL_BASE2,
1268                 .num_ports      = 8,
1269                 .base_baud      = 115200,
1270                 .uart_offset    = 8,
1271         },
1272
1273         [pbn_b2_1_460800] = {
1274                 .flags          = FL_BASE2,
1275                 .num_ports      = 1,
1276                 .base_baud      = 460800,
1277                 .uart_offset    = 8,
1278         },
1279         [pbn_b2_4_460800] = {
1280                 .flags          = FL_BASE2,
1281                 .num_ports      = 4,
1282                 .base_baud      = 460800,
1283                 .uart_offset    = 8,
1284         },
1285         [pbn_b2_8_460800] = {
1286                 .flags          = FL_BASE2,
1287                 .num_ports      = 8,
1288                 .base_baud      = 460800,
1289                 .uart_offset    = 8,
1290         },
1291         [pbn_b2_16_460800] = {
1292                 .flags          = FL_BASE2,
1293                 .num_ports      = 16,
1294                 .base_baud      = 460800,
1295                 .uart_offset    = 8,
1296          },
1297
1298         [pbn_b2_1_921600] = {
1299                 .flags          = FL_BASE2,
1300                 .num_ports      = 1,
1301                 .base_baud      = 921600,
1302                 .uart_offset    = 8,
1303         },
1304         [pbn_b2_4_921600] = {
1305                 .flags          = FL_BASE2,
1306                 .num_ports      = 4,
1307                 .base_baud      = 921600,
1308                 .uart_offset    = 8,
1309         },
1310         [pbn_b2_8_921600] = {
1311                 .flags          = FL_BASE2,
1312                 .num_ports      = 8,
1313                 .base_baud      = 921600,
1314                 .uart_offset    = 8,
1315         },
1316
1317         [pbn_b2_bt_1_115200] = {
1318                 .flags          = FL_BASE2|FL_BASE_BARS,
1319                 .num_ports      = 1,
1320                 .base_baud      = 115200,
1321                 .uart_offset    = 8,
1322         },
1323         [pbn_b2_bt_2_115200] = {
1324                 .flags          = FL_BASE2|FL_BASE_BARS,
1325                 .num_ports      = 2,
1326                 .base_baud      = 115200,
1327                 .uart_offset    = 8,
1328         },
1329         [pbn_b2_bt_4_115200] = {
1330                 .flags          = FL_BASE2|FL_BASE_BARS,
1331                 .num_ports      = 4,
1332                 .base_baud      = 115200,
1333                 .uart_offset    = 8,
1334         },
1335
1336         [pbn_b2_bt_2_921600] = {
1337                 .flags          = FL_BASE2|FL_BASE_BARS,
1338                 .num_ports      = 2,
1339                 .base_baud      = 921600,
1340                 .uart_offset    = 8,
1341         },
1342         [pbn_b2_bt_4_921600] = {
1343                 .flags          = FL_BASE2|FL_BASE_BARS,
1344                 .num_ports      = 4,
1345                 .base_baud      = 921600,
1346                 .uart_offset    = 8,
1347         },
1348
1349         [pbn_b3_2_115200] = {
1350                 .flags          = FL_BASE3,
1351                 .num_ports      = 2,
1352                 .base_baud      = 115200,
1353                 .uart_offset    = 8,
1354         },
1355         [pbn_b3_4_115200] = {
1356                 .flags          = FL_BASE3,
1357                 .num_ports      = 4,
1358                 .base_baud      = 115200,
1359                 .uart_offset    = 8,
1360         },
1361         [pbn_b3_8_115200] = {
1362                 .flags          = FL_BASE3,
1363                 .num_ports      = 8,
1364                 .base_baud      = 115200,
1365                 .uart_offset    = 8,
1366         },
1367
1368         /*
1369          * Entries following this are board-specific.
1370          */
1371
1372         /*
1373          * Panacom - IOMEM
1374          */
1375         [pbn_panacom] = {
1376                 .flags          = FL_BASE2,
1377                 .num_ports      = 2,
1378                 .base_baud      = 921600,
1379                 .uart_offset    = 0x400,
1380                 .reg_shift      = 7,
1381         },
1382         [pbn_panacom2] = {
1383                 .flags          = FL_BASE2|FL_BASE_BARS,
1384                 .num_ports      = 2,
1385                 .base_baud      = 921600,
1386                 .uart_offset    = 0x400,
1387                 .reg_shift      = 7,
1388         },
1389         [pbn_panacom4] = {
1390                 .flags          = FL_BASE2|FL_BASE_BARS,
1391                 .num_ports      = 4,
1392                 .base_baud      = 921600,
1393                 .uart_offset    = 0x400,
1394                 .reg_shift      = 7,
1395         },
1396
1397         [pbn_exsys_4055] = {
1398                 .flags          = FL_BASE2,
1399                 .num_ports      = 4,
1400                 .base_baud      = 115200,
1401                 .uart_offset    = 8,
1402         },
1403
1404         /* I think this entry is broken - the first_offset looks wrong --rmk */
1405         [pbn_plx_romulus] = {
1406                 .flags          = FL_BASE2,
1407                 .num_ports      = 4,
1408                 .base_baud      = 921600,
1409                 .uart_offset    = 8 << 2,
1410                 .reg_shift      = 2,
1411                 .first_offset   = 0x03,
1412         },
1413
1414         /*
1415          * This board uses the size of PCI Base region 0 to
1416          * signal now many ports are available
1417          */
1418         [pbn_oxsemi] = {
1419                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1420                 .num_ports      = 32,
1421                 .base_baud      = 115200,
1422                 .uart_offset    = 8,
1423         },
1424
1425         /*
1426          * EKF addition for i960 Boards form EKF with serial port.
1427          * Max 256 ports.
1428          */
1429         [pbn_intel_i960] = {
1430                 .flags          = FL_BASE0,
1431                 .num_ports      = 32,
1432                 .base_baud      = 921600,
1433                 .uart_offset    = 8 << 2,
1434                 .reg_shift      = 2,
1435                 .first_offset   = 0x10000,
1436         },
1437         [pbn_sgi_ioc3] = {
1438                 .flags          = FL_BASE0|FL_NOIRQ,
1439                 .num_ports      = 1,
1440                 .base_baud      = 458333,
1441                 .uart_offset    = 8,
1442                 .reg_shift      = 0,
1443                 .first_offset   = 0x20178,
1444         },
1445
1446         /*
1447          * NEC Vrc-5074 (Nile 4) builtin UART.
1448          */
1449         [pbn_nec_nile4] = {
1450                 .flags          = FL_BASE0,
1451                 .num_ports      = 1,
1452                 .base_baud      = 520833,
1453                 .uart_offset    = 8 << 3,
1454                 .reg_shift      = 3,
1455                 .first_offset   = 0x300,
1456         },
1457
1458         /*
1459          * Computone - uses IOMEM.
1460          */
1461         [pbn_computone_4] = {
1462                 .flags          = FL_BASE0,
1463                 .num_ports      = 4,
1464                 .base_baud      = 921600,
1465                 .uart_offset    = 0x40,
1466                 .reg_shift      = 2,
1467                 .first_offset   = 0x200,
1468         },
1469         [pbn_computone_6] = {
1470                 .flags          = FL_BASE0,
1471                 .num_ports      = 6,
1472                 .base_baud      = 921600,
1473                 .uart_offset    = 0x40,
1474                 .reg_shift      = 2,
1475                 .first_offset   = 0x200,
1476         },
1477         [pbn_computone_8] = {
1478                 .flags          = FL_BASE0,
1479                 .num_ports      = 8,
1480                 .base_baud      = 921600,
1481                 .uart_offset    = 0x40,
1482                 .reg_shift      = 2,
1483                 .first_offset   = 0x200,
1484         },
1485         [pbn_sbsxrsio] = {
1486                 .flags          = FL_BASE0,
1487                 .num_ports      = 8,
1488                 .base_baud      = 460800,
1489                 .uart_offset    = 256,
1490                 .reg_shift      = 4,
1491         },
1492         /*
1493          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1494          *  Only basic 16550A support.
1495          *  XR17C15[24] are not tested, but they should work.
1496          */
1497         [pbn_exar_XR17C152] = {
1498                 .flags          = FL_BASE0,
1499                 .num_ports      = 2,
1500                 .base_baud      = 921600,
1501                 .uart_offset    = 0x200,
1502         },
1503         [pbn_exar_XR17C154] = {
1504                 .flags          = FL_BASE0,
1505                 .num_ports      = 4,
1506                 .base_baud      = 921600,
1507                 .uart_offset    = 0x200,
1508         },
1509         [pbn_exar_XR17C158] = {
1510                 .flags          = FL_BASE0,
1511                 .num_ports      = 8,
1512                 .base_baud      = 921600,
1513                 .uart_offset    = 0x200,
1514         },
1515 };
1516
1517 /*
1518  * Given a complete unknown PCI device, try to use some heuristics to
1519  * guess what the configuration might be, based on the pitiful PCI
1520  * serial specs.  Returns 0 on success, 1 on failure.
1521  */
1522 static int __devinit
1523 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1524 {
1525         int num_iomem, num_port, first_port = -1, i;
1526
1527         /*
1528          * If it is not a communications device or the programming
1529          * interface is greater than 6, give up.
1530          *
1531          * (Should we try to make guesses for multiport serial devices
1532          * later?)
1533          */
1534         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1535              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1536             (dev->class & 0xff) > 6)
1537                 return -ENODEV;
1538
1539         num_iomem = num_port = 0;
1540         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1541                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1542                         num_port++;
1543                         if (first_port == -1)
1544                                 first_port = i;
1545                 }
1546                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1547                         num_iomem++;
1548         }
1549
1550         /*
1551          * If there is 1 or 0 iomem regions, and exactly one port,
1552          * use it.  We guess the number of ports based on the IO
1553          * region size.
1554          */
1555         if (num_iomem <= 1 && num_port == 1) {
1556                 board->flags = first_port;
1557                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1558                 return 0;
1559         }
1560
1561         /*
1562          * Now guess if we've got a board which indexes by BARs.
1563          * Each IO BAR should be 8 bytes, and they should follow
1564          * consecutively.
1565          */
1566         first_port = -1;
1567         num_port = 0;
1568         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1569                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1570                     pci_resource_len(dev, i) == 8 &&
1571                     (first_port == -1 || (first_port + num_port) == i)) {
1572                         num_port++;
1573                         if (first_port == -1)
1574                                 first_port = i;
1575                 }
1576         }
1577
1578         if (num_port > 1) {
1579                 board->flags = first_port | FL_BASE_BARS;
1580                 board->num_ports = num_port;
1581                 return 0;
1582         }
1583
1584         return -ENODEV;
1585 }
1586
1587 static inline int
1588 serial_pci_matches(struct pciserial_board *board,
1589                    struct pciserial_board *guessed)
1590 {
1591         return
1592             board->num_ports == guessed->num_ports &&
1593             board->base_baud == guessed->base_baud &&
1594             board->uart_offset == guessed->uart_offset &&
1595             board->reg_shift == guessed->reg_shift &&
1596             board->first_offset == guessed->first_offset;
1597 }
1598
1599 struct serial_private *
1600 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1601 {
1602         struct uart_port serial_port;
1603         struct serial_private *priv;
1604         struct pci_serial_quirk *quirk;
1605         int rc, nr_ports, i;
1606
1607         nr_ports = board->num_ports;
1608
1609         /*
1610          * Find an init and setup quirks.
1611          */
1612         quirk = find_quirk(dev);
1613
1614         /*
1615          * Run the new-style initialization function.
1616          * The initialization function returns:
1617          *  <0  - error
1618          *   0  - use board->num_ports
1619          *  >0  - number of ports
1620          */
1621         if (quirk->init) {
1622                 rc = quirk->init(dev);
1623                 if (rc < 0) {
1624                         priv = ERR_PTR(rc);
1625                         goto err_out;
1626                 }
1627                 if (rc)
1628                         nr_ports = rc;
1629         }
1630
1631         priv = kzalloc(sizeof(struct serial_private) +
1632                        sizeof(unsigned int) * nr_ports,
1633                        GFP_KERNEL);
1634         if (!priv) {
1635                 priv = ERR_PTR(-ENOMEM);
1636                 goto err_deinit;
1637         }
1638
1639         priv->dev = dev;
1640         priv->quirk = quirk;
1641
1642         memset(&serial_port, 0, sizeof(struct uart_port));
1643         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1644         serial_port.uartclk = board->base_baud * 16;
1645         serial_port.irq = get_pci_irq(dev, board);
1646         serial_port.dev = &dev->dev;
1647
1648         for (i = 0; i < nr_ports; i++) {
1649                 if (quirk->setup(priv, board, &serial_port, i))
1650                         break;
1651
1652 #ifdef SERIAL_DEBUG_PCI
1653                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1654                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1655 #endif
1656
1657                 priv->line[i] = serial8250_register_port(&serial_port);
1658                 if (priv->line[i] < 0) {
1659                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1660                         break;
1661                 }
1662         }
1663
1664         priv->nr = i;
1665
1666         return priv;
1667
1668  err_deinit:
1669         if (quirk->exit)
1670                 quirk->exit(dev);
1671  err_out:
1672         return priv;
1673 }
1674 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1675
1676 void pciserial_remove_ports(struct serial_private *priv)
1677 {
1678         struct pci_serial_quirk *quirk;
1679         int i;
1680
1681         for (i = 0; i < priv->nr; i++)
1682                 serial8250_unregister_port(priv->line[i]);
1683
1684         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1685                 if (priv->remapped_bar[i])
1686                         iounmap(priv->remapped_bar[i]);
1687                 priv->remapped_bar[i] = NULL;
1688         }
1689
1690         /*
1691          * Find the exit quirks.
1692          */
1693         quirk = find_quirk(priv->dev);
1694         if (quirk->exit)
1695                 quirk->exit(priv->dev);
1696
1697         kfree(priv);
1698 }
1699 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1700
1701 void pciserial_suspend_ports(struct serial_private *priv)
1702 {
1703         int i;
1704
1705         for (i = 0; i < priv->nr; i++)
1706                 if (priv->line[i] >= 0)
1707                         serial8250_suspend_port(priv->line[i]);
1708 }
1709 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1710
1711 void pciserial_resume_ports(struct serial_private *priv)
1712 {
1713         int i;
1714
1715         /*
1716          * Ensure that the board is correctly configured.
1717          */
1718         if (priv->quirk->init)
1719                 priv->quirk->init(priv->dev);
1720
1721         for (i = 0; i < priv->nr; i++)
1722                 if (priv->line[i] >= 0)
1723                         serial8250_resume_port(priv->line[i]);
1724 }
1725 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1726
1727 /*
1728  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1729  * to the arrangement of serial ports on a PCI card.
1730  */
1731 static int __devinit
1732 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1733 {
1734         struct serial_private *priv;
1735         struct pciserial_board *board, tmp;
1736         int rc;
1737
1738         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1739                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1740                         ent->driver_data);
1741                 return -EINVAL;
1742         }
1743
1744         board = &pci_boards[ent->driver_data];
1745
1746         rc = pci_enable_device(dev);
1747         if (rc)
1748                 return rc;
1749
1750         if (ent->driver_data == pbn_default) {
1751                 /*
1752                  * Use a copy of the pci_board entry for this;
1753                  * avoid changing entries in the table.
1754                  */
1755                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1756                 board = &tmp;
1757
1758                 /*
1759                  * We matched one of our class entries.  Try to
1760                  * determine the parameters of this board.
1761                  */
1762                 rc = serial_pci_guess_board(dev, board);
1763                 if (rc)
1764                         goto disable;
1765         } else {
1766                 /*
1767                  * We matched an explicit entry.  If we are able to
1768                  * detect this boards settings with our heuristic,
1769                  * then we no longer need this entry.
1770                  */
1771                 memcpy(&tmp, &pci_boards[pbn_default],
1772                        sizeof(struct pciserial_board));
1773                 rc = serial_pci_guess_board(dev, &tmp);
1774                 if (rc == 0 && serial_pci_matches(board, &tmp))
1775                         moan_device("Redundant entry in serial pci_table.",
1776                                     dev);
1777         }
1778
1779         priv = pciserial_init_ports(dev, board);
1780         if (!IS_ERR(priv)) {
1781                 pci_set_drvdata(dev, priv);
1782                 return 0;
1783         }
1784
1785         rc = PTR_ERR(priv);
1786
1787  disable:
1788         pci_disable_device(dev);
1789         return rc;
1790 }
1791
1792 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1793 {
1794         struct serial_private *priv = pci_get_drvdata(dev);
1795
1796         pci_set_drvdata(dev, NULL);
1797
1798         pciserial_remove_ports(priv);
1799
1800         pci_disable_device(dev);
1801 }
1802
1803 #ifdef CONFIG_PM
1804 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1805 {
1806         struct serial_private *priv = pci_get_drvdata(dev);
1807
1808         if (priv)
1809                 pciserial_suspend_ports(priv);
1810
1811         pci_save_state(dev);
1812         pci_set_power_state(dev, pci_choose_state(dev, state));
1813         return 0;
1814 }
1815
1816 static int pciserial_resume_one(struct pci_dev *dev)
1817 {
1818         struct serial_private *priv = pci_get_drvdata(dev);
1819
1820         pci_set_power_state(dev, PCI_D0);
1821         pci_restore_state(dev);
1822
1823         if (priv) {
1824                 /*
1825                  * The device may have been disabled.  Re-enable it.
1826                  */
1827                 pci_enable_device(dev);
1828
1829                 pciserial_resume_ports(priv);
1830         }
1831         return 0;
1832 }
1833 #endif
1834
1835 static struct pci_device_id serial_pci_tbl[] = {
1836         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1837                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1839                 pbn_b1_8_1382400 },
1840         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1841                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1843                 pbn_b1_4_1382400 },
1844         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1845                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1847                 pbn_b1_2_1382400 },
1848         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1851                 pbn_b1_8_1382400 },
1852         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1855                 pbn_b1_4_1382400 },
1856         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1857                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1859                 pbn_b1_2_1382400 },
1860         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1863                 pbn_b1_8_921600 },
1864         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1867                 pbn_b1_8_921600 },
1868         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1871                 pbn_b1_4_921600 },
1872         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1875                 pbn_b1_4_921600 },
1876         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1879                 pbn_b1_2_921600 },
1880         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1883                 pbn_b1_8_921600 },
1884         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1885                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1887                 pbn_b1_8_921600 },
1888         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1889                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1891                 pbn_b1_4_921600 },
1892         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1893                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1894                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1895                 pbn_b1_2_1250000 },
1896         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1897                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1899                 pbn_b0_2_1843200 },
1900         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1901                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1903                 pbn_b0_4_1843200 },
1904         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1905                 PCI_VENDOR_ID_AFAVLAB,
1906                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1907                 pbn_b0_4_1152000 },
1908         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1909                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1911                 pbn_b0_2_1843200_200 },
1912         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1913                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1914                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1915                 pbn_b0_4_1843200_200 },
1916         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1917                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1918                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1919                 pbn_b0_8_1843200_200 },
1920         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1921                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1922                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1923                 pbn_b0_2_1843200_200 },
1924         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1925                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1926                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1927                 pbn_b0_4_1843200_200 },
1928         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1929                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1930                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1931                 pbn_b0_8_1843200_200 },
1932         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1933                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1934                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1935                 pbn_b0_2_1843200_200 },
1936         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1937                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1938                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1939                 pbn_b0_4_1843200_200 },
1940         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1941                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1942                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1943                 pbn_b0_8_1843200_200 },
1944         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1945                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1946                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1947                 pbn_b0_2_1843200_200 },
1948         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1949                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1950                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1951                 pbn_b0_4_1843200_200 },
1952         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1953                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1954                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1955                 pbn_b0_8_1843200_200 },
1956
1957         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959                 pbn_b2_bt_1_115200 },
1960         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962                 pbn_b2_bt_2_115200 },
1963         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965                 pbn_b2_bt_4_115200 },
1966         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1967                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1968                 pbn_b2_bt_2_115200 },
1969         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971                 pbn_b2_bt_4_115200 },
1972         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1974                 pbn_b2_8_115200 },
1975         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1976                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977                 pbn_b2_8_115200 },
1978
1979         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981                 pbn_b2_bt_2_115200 },
1982         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984                 pbn_b2_bt_2_921600 },
1985         /*
1986          * VScom SPCOM800, from sl@s.pl
1987          */
1988         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1990                 pbn_b2_8_921600 },
1991         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1993                 pbn_b2_4_921600 },
1994         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1995                 PCI_SUBVENDOR_ID_KEYSPAN,
1996                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1997                 pbn_panacom },
1998         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000                 pbn_panacom4 },
2001         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2003                 pbn_panacom2 },
2004         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2005                 PCI_VENDOR_ID_ESDGMBH,
2006                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2007                 pbn_b2_4_115200 },
2008         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2009                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2010                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2011                 pbn_b2_4_460800 },
2012         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2013                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2014                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2015                 pbn_b2_8_460800 },
2016         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2017                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2018                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2019                 pbn_b2_16_460800 },
2020         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2021                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2022                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2023                 pbn_b2_16_460800 },
2024         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2025                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2026                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2027                 pbn_b2_4_460800 },
2028         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2029                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2030                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2031                 pbn_b2_8_460800 },
2032         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2033                 PCI_SUBVENDOR_ID_EXSYS,
2034                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2035                 pbn_exsys_4055 },
2036         /*
2037          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2038          * (Exoray@isys.ca)
2039          */
2040         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2041                 0x10b5, 0x106a, 0, 0,
2042                 pbn_plx_romulus },
2043         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045                 pbn_b1_4_115200 },
2046         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2048                 pbn_b1_2_115200 },
2049         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2051                 pbn_b1_8_115200 },
2052         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054                 pbn_b1_8_115200 },
2055         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2056                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2057                 pbn_b0_4_921600 },
2058         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2059                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2060                 pbn_b0_4_1152000 },
2061
2062                 /*
2063                  * The below card is a little controversial since it is the
2064                  * subject of a PCI vendor/device ID clash.  (See
2065                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2066                  * For now just used the hex ID 0x950a.
2067                  */
2068         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2069                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2070                 pbn_b0_2_1130000 },
2071         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2072                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073                 pbn_b0_4_115200 },
2074         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2075                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076                 pbn_b0_bt_2_921600 },
2077
2078         /*
2079          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2080          * from skokodyn@yahoo.com
2081          */
2082         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2083                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2084                 pbn_sbsxrsio },
2085         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2086                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2087                 pbn_sbsxrsio },
2088         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2089                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2090                 pbn_sbsxrsio },
2091         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2092                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2093                 pbn_sbsxrsio },
2094
2095         /*
2096          * Digitan DS560-558, from jimd@esoft.com
2097          */
2098         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100                 pbn_b1_1_115200 },
2101
2102         /*
2103          * Titan Electronic cards
2104          *  The 400L and 800L have a custom setup quirk.
2105          */
2106         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2108                 pbn_b0_1_921600 },
2109         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2110                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2111                 pbn_b0_2_921600 },
2112         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2113                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2114                 pbn_b0_4_921600 },
2115         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2117                 pbn_b0_4_921600 },
2118         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120                 pbn_b1_1_921600 },
2121         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123                 pbn_b1_bt_2_921600 },
2124         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126                 pbn_b0_bt_4_921600 },
2127         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129                 pbn_b0_bt_8_921600 },
2130
2131         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133                 pbn_b2_1_460800 },
2134         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2135                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136                 pbn_b2_1_460800 },
2137         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139                 pbn_b2_1_460800 },
2140         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142                 pbn_b2_bt_2_921600 },
2143         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145                 pbn_b2_bt_2_921600 },
2146         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148                 pbn_b2_bt_2_921600 },
2149         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151                 pbn_b2_bt_4_921600 },
2152         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154                 pbn_b2_bt_4_921600 },
2155         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157                 pbn_b2_bt_4_921600 },
2158         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2160                 pbn_b0_1_921600 },
2161         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2163                 pbn_b0_1_921600 },
2164         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2166                 pbn_b0_1_921600 },
2167         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169                 pbn_b0_bt_2_921600 },
2170         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2172                 pbn_b0_bt_2_921600 },
2173         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175                 pbn_b0_bt_2_921600 },
2176         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2178                 pbn_b0_bt_4_921600 },
2179         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2181                 pbn_b0_bt_4_921600 },
2182         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2184                 pbn_b0_bt_4_921600 },
2185         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2187                 pbn_b0_bt_8_921600 },
2188         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2190                 pbn_b0_bt_8_921600 },
2191         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2193                 pbn_b0_bt_8_921600 },
2194
2195         /*
2196          * Computone devices submitted by Doug McNash dmcnash@computone.com
2197          */
2198         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2199                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2200                 0, 0, pbn_computone_4 },
2201         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2202                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2203                 0, 0, pbn_computone_8 },
2204         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2205                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2206                 0, 0, pbn_computone_6 },
2207
2208         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2210                 pbn_oxsemi },
2211         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2212                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2213                 pbn_b0_bt_1_921600 },
2214
2215         /*
2216          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2217          */
2218         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220                 pbn_b0_bt_8_115200 },
2221         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223                 pbn_b0_bt_8_115200 },
2224
2225         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2227                 pbn_b0_bt_2_115200 },
2228         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2230                 pbn_b0_bt_2_115200 },
2231         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2233                 pbn_b0_bt_2_115200 },
2234         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2236                 pbn_b0_bt_4_460800 },
2237         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2239                 pbn_b0_bt_4_460800 },
2240         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2242                 pbn_b0_bt_2_460800 },
2243         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2245                 pbn_b0_bt_2_460800 },
2246         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248                 pbn_b0_bt_2_460800 },
2249         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251                 pbn_b0_bt_1_115200 },
2252         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2254                 pbn_b0_bt_1_460800 },
2255
2256         /*
2257          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2258          * Cards are identified by their subsystem vendor IDs, which
2259          * (in hex) match the model number.
2260          *
2261          * Note that JC140x are RS422/485 cards which require ox950
2262          * ACR = 0x10, and as such are not currently fully supported.
2263          */
2264         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2265                 0x1204, 0x0004, 0, 0,
2266                 pbn_b0_4_921600 },
2267         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2268                 0x1208, 0x0004, 0, 0,
2269                 pbn_b0_4_921600 },
2270 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2271                 0x1402, 0x0002, 0, 0,
2272                 pbn_b0_2_921600 }, */
2273 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2274                 0x1404, 0x0004, 0, 0,
2275                 pbn_b0_4_921600 }, */
2276         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2277                 0x1208, 0x0004, 0, 0,
2278                 pbn_b0_4_921600 },
2279
2280         /*
2281          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2282          */
2283         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2285                 pbn_b1_1_1382400 },
2286
2287         /*
2288          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2289          */
2290         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2292                 pbn_b1_1_1382400 },
2293
2294         /*
2295          * RAStel 2 port modem, gerg@moreton.com.au
2296          */
2297         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2299                 pbn_b2_bt_2_115200 },
2300
2301         /*
2302          * EKF addition for i960 Boards form EKF with serial port
2303          */
2304         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2305                 0xE4BF, PCI_ANY_ID, 0, 0,
2306                 pbn_intel_i960 },
2307
2308         /*
2309          * Xircom Cardbus/Ethernet combos
2310          */
2311         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2313                 pbn_b0_1_115200 },
2314         /*
2315          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2316          */
2317         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2319                 pbn_b0_1_115200 },
2320
2321         /*
2322          * Untested PCI modems, sent in from various folks...
2323          */
2324
2325         /*
2326          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2327          */
2328         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2329                 0x1048, 0x1500, 0, 0,
2330                 pbn_b1_1_115200 },
2331
2332         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2333                 0xFF00, 0, 0, 0,
2334                 pbn_sgi_ioc3 },
2335
2336         /*
2337          * HP Diva card
2338          */
2339         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2340                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2341                 pbn_b1_1_115200 },
2342         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2344                 pbn_b0_5_115200 },
2345         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2347                 pbn_b2_1_115200 },
2348
2349         /*
2350          * NEC Vrc-5074 (Nile 4) builtin UART.
2351          */
2352         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2354                 pbn_nec_nile4 },
2355
2356         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358                 pbn_b3_2_115200 },
2359         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361                 pbn_b3_4_115200 },
2362         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364                 pbn_b3_8_115200 },
2365
2366         /*
2367          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2368          */
2369         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2370                 PCI_ANY_ID, PCI_ANY_ID,
2371                 0,
2372                 0, pbn_exar_XR17C152 },
2373         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2374                 PCI_ANY_ID, PCI_ANY_ID,
2375                 0,
2376                 0, pbn_exar_XR17C154 },
2377         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2378                 PCI_ANY_ID, PCI_ANY_ID,
2379                 0,
2380                 0, pbn_exar_XR17C158 },
2381
2382         /*
2383          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2384          */
2385         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2387                 pbn_b0_1_115200 },
2388
2389         /*
2390          * IntaShield IS-200
2391          */
2392         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2394                 pbn_b2_2_115200 },
2395
2396         /*
2397          * Perle PCI-RAS cards
2398          */
2399         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2400                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2401                 0, 0, pbn_b2_4_921600 },
2402         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2403                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2404                 0, 0, pbn_b2_8_921600 },
2405         /*
2406          * These entries match devices with class COMMUNICATION_SERIAL,
2407          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2408          */
2409         {       PCI_ANY_ID, PCI_ANY_ID,
2410                 PCI_ANY_ID, PCI_ANY_ID,
2411                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2412                 0xffff00, pbn_default },
2413         {       PCI_ANY_ID, PCI_ANY_ID,
2414                 PCI_ANY_ID, PCI_ANY_ID,
2415                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2416                 0xffff00, pbn_default },
2417         {       PCI_ANY_ID, PCI_ANY_ID,
2418                 PCI_ANY_ID, PCI_ANY_ID,
2419                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2420                 0xffff00, pbn_default },
2421         { 0, }
2422 };
2423
2424 static struct pci_driver serial_pci_driver = {
2425         .name           = "serial",
2426         .probe          = pciserial_init_one,
2427         .remove         = __devexit_p(pciserial_remove_one),
2428 #ifdef CONFIG_PM
2429         .suspend        = pciserial_suspend_one,
2430         .resume         = pciserial_resume_one,
2431 #endif
2432         .id_table       = serial_pci_tbl,
2433 };
2434
2435 static int __init serial8250_pci_init(void)
2436 {
2437         return pci_register_driver(&serial_pci_driver);
2438 }
2439
2440 static void __exit serial8250_pci_exit(void)
2441 {
2442         pci_unregister_driver(&serial_pci_driver);
2443 }
2444
2445 module_init(serial8250_pci_init);
2446 module_exit(serial8250_pci_exit);
2447
2448 MODULE_LICENSE("GPL");
2449 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2450 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);