drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * init function returns:
  38  *  > 0 - number of ports
  39  *  = 0 - use board->num_ports
  40  *  < 0 - error
  41  */
  42 struct pci_serial_quirk {
  43         u32     vendor;
  44         u32     device;
  45         u32     subvendor;
  46         u32     subdevice;
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *, struct pciserial_board *,
  49                          struct uart_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING "%s: %s\n"
  66                KERN_WARNING "Please send the output of lspci -vv, this\n"
  67                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                KERN_WARNING "manufacturer and name of serial board or\n"
  69                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * AFAVLAB uses a different mixture of BARs and offsets
 111  * Not that ugly ;) -- HW
 112  */
 113 static int
 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 115               struct uart_port *port, int idx)
 116 {
 117         unsigned int bar, offset = board->first_offset;
 118
 119         bar = FL_GET_BASE(board->flags);
 120         if (idx < 4)
 121                 bar += idx;
 122         else {
 123                 bar = 4;
 124                 offset += (idx - 4) * board->uart_offset;
 125         }
 126
 127         return setup_port(priv, port, bar, offset, board->reg_shift);
 128 }
 129
 130 /*
 131  * HP's Remote Management Console.  The Diva chip came in several
 132  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 133  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 134  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 135  * one Diva chip, but it has been expanded to 5 UARTs.
 136  */
 137 static int pci_hp_diva_init(struct pci_dev *dev)
 138 {
 139         int rc = 0;
 140
 141         switch (dev->subsystem_device) {
 142         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 143         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 144         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 145         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 146                 rc = 3;
 147                 break;
 148         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 149                 rc = 2;
 150                 break;
 151         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 152                 rc = 4;
 153                 break;
 154         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 155         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 156                 rc = 1;
 157                 break;
 158         }
 159
 160         return rc;
 161 }
 162
 163 /*
 164  * HP's Diva chip puts the 4th/5th serial port further out, and
 165  * some serial ports are supposed to be hidden on certain models.
 166  */
 167 static int
 168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 169               struct uart_port *port, int idx)
 170 {
 171         unsigned int offset = board->first_offset;
 172         unsigned int bar = FL_GET_BASE(board->flags);
 173
 174         switch (priv->dev->subsystem_device) {
 175         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 176                 if (idx == 3)
 177                         idx++;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 180                 if (idx > 0)
 181                         idx++;
 182                 if (idx > 2)
 183                         idx++;
 184                 break;
 185         }
 186         if (idx > 2)
 187                 offset = 0x18;
 188
 189         offset += idx * board->uart_offset;
 190
 191         return setup_port(priv, port, bar, offset, board->reg_shift);
 192 }
 193
 194 /*
 195  * Added for EKF Intel i960 serial boards
 196  */
 197 static int pci_inteli960ni_init(struct pci_dev *dev)
 198 {
 199         unsigned long oldval;
 200
 201         if (!(dev->subsystem_device & 0x1000))
 202                 return -ENODEV;
 203
 204         /* is firmware started? */
 205         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 206         if (oldval == 0x00001000L) { /* RESET value */
 207                 printk(KERN_DEBUG "Local i960 firmware missing");
 208                 return -ENODEV;
 209         }
 210         return 0;
 211 }
 212
 213 /*
 214  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 215  * that the card interrupt be explicitly enabled or disabled.  This
 216  * seems to be mainly needed on card using the PLX which also use I/O
 217  * mapped memory.
 218  */
 219 static int pci_plx9050_init(struct pci_dev *dev)
 220 {
 221         u8 irq_config;
 222         void __iomem *p;
 223
 224         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 225                 moan_device("no memory in bar 0", dev);
 226                 return 0;
 227         }
 228
 229         irq_config = 0x41;
 230         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 231             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 232                 irq_config = 0x43;
 233         }
 234         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 235             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 236                 /*
 237                  * As the megawolf cards have the int pins active
 238                  * high, and have 2 UART chips, both ints must be
 239                  * enabled on the 9050. Also, the UARTS are set in
 240                  * 16450 mode by default, so we have to enable the
 241                  * 16C950 'enhanced' mode so that we can use the
 242                  * deep FIFOs
 243                  */
 244                 irq_config = 0x5b;
 245         }
 246
 247         /*
 248          * enable/disable interrupts
 249          */
 250         p = ioremap(pci_resource_start(dev, 0), 0x80);
 251         if (p == NULL)
 252                 return -ENOMEM;
 253         writel(irq_config, p + 0x4c);
 254
 255         /*
 256          * Read the register back to ensure that it took effect.
 257          */
 258         readl(p + 0x4c);
 259         iounmap(p);
 260
 261         return 0;
 262 }
 263
 264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 265 {
 266         u8 __iomem *p;
 267
 268         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 269                 return;
 270
 271         /*
 272          * disable interrupts
 273          */
 274         p = ioremap(pci_resource_start(dev, 0), 0x80);
 275         if (p != NULL) {
 276                 writel(0, p + 0x4c);
 277
 278                 /*
 279                  * Read the register back to ensure that it took effect.
 280                  */
 281                 readl(p + 0x4c);
 282                 iounmap(p);
 283         }
 284 }
 285
 286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 287 static int
 288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 289                 struct uart_port *port, int idx)
 290 {
 291         unsigned int bar, offset = board->first_offset;
 292
 293         bar = 0;
 294
 295         if (idx < 4) {
 296                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 297                 offset += idx * board->uart_offset;
 298         } else if (idx < 8) {
 299                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 300                 offset += idx * board->uart_offset + 0xC00;
 301         } else /* we have only 8 ports on PMC-OCTALPRO */
 302                 return 1;
 303
 304         return setup_port(priv, port, bar, offset, board->reg_shift);
 305 }
 306
 307 /*
 308 * This does initialization for PMC OCTALPRO cards:
 309 * maps the device memory, resets the UARTs (needed, bc
 310 * if the module is removed and inserted again, the card
 311 * is in the sleep mode) and enables global interrupt.
 312 */
 313
 314 /* global control register offset for SBS PMC-OctalPro */
 315 #define OCT_REG_CR_OFF          0x500
 316
 317 static int sbs_init(struct pci_dev *dev)
 318 {
 319         u8 __iomem *p;
 320
 321         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 322
 323         if (p == NULL)
 324                 return -ENOMEM;
 325         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 326         writeb(0x10,p + OCT_REG_CR_OFF);
 327         udelay(50);
 328         writeb(0x0,p + OCT_REG_CR_OFF);
 329
 330         /* Set bit-2 (INTENABLE) of Control Register */
 331         writeb(0x4, p + OCT_REG_CR_OFF);
 332         iounmap(p);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Disables the global interrupt of PMC-OctalPro
 339  */
 340
 341 static void __devexit sbs_exit(struct pci_dev *dev)
 342 {
 343         u8 __iomem *p;
 344
 345         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 346         if (p != NULL) {
 347                 writeb(0, p + OCT_REG_CR_OFF);
 348         }
 349         iounmap(p);
 350 }
 351
 352 /*
 353  * SIIG serial cards have an PCI interface chip which also controls
 354  * the UART clocking frequency. Each UART can be clocked independently
 355  * (except cards equiped with 4 UARTs) and initial clocking settings
 356  * are stored in the EEPROM chip. It can cause problems because this
 357  * version of serial driver doesn't support differently clocked UART's
 358  * on single PCI card. To prevent this, initialization functions set
 359  * high frequency clocking for all UART's on given card. It is safe (I
 360  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 361  * with other OSes (like M$ DOS).
 362  *
 363  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 364  *
 365  * There is two family of SIIG serial cards with different PCI
 366  * interface chip and different configuration methods:
 367  *     - 10x cards have control registers in IO and/or memory space;
 368  *     - 20x cards have control registers in standard PCI configuration space.
 369  *
 370  * Note: all 10x cards have PCI device ids 0x10..
 371  *       all 20x cards have PCI device ids 0x20..
 372  *
 373  * There are also Quartet Serial cards which use Oxford Semiconductor
 374  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 375  *
 376  * Note: some SIIG cards are probed by the parport_serial object.
 377  */
 378
 379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 381
 382 static int pci_siig10x_init(struct pci_dev *dev)
 383 {
 384         u16 data;
 385         void __iomem *p;
 386
 387         switch (dev->device & 0xfff8) {
 388         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 389                 data = 0xffdf;
 390                 break;
 391         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 392                 data = 0xf7ff;
 393                 break;
 394         default:                        /* 1S1P, 4S */
 395                 data = 0xfffb;
 396                 break;
 397         }
 398
 399         p = ioremap(pci_resource_start(dev, 0), 0x80);
 400         if (p == NULL)
 401                 return -ENOMEM;
 402
 403         writew(readw(p + 0x28) & data, p + 0x28);
 404         readw(p + 0x28);
 405         iounmap(p);
 406         return 0;
 407 }
 408
 409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 411
 412 static int pci_siig20x_init(struct pci_dev *dev)
 413 {
 414         u8 data;
 415
 416         /* Change clock frequency for the first UART. */
 417         pci_read_config_byte(dev, 0x6f, &data);
 418         pci_write_config_byte(dev, 0x6f, data & 0xef);
 419
 420         /* If this card has 2 UART, we have to do the same with second UART. */
 421         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 422             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 423                 pci_read_config_byte(dev, 0x73, &data);
 424                 pci_write_config_byte(dev, 0x73, data & 0xef);
 425         }
 426         return 0;
 427 }
 428
 429 static int pci_siig_init(struct pci_dev *dev)
 430 {
 431         unsigned int type = dev->device & 0xff00;
 432
 433         if (type == 0x1000)
 434                 return pci_siig10x_init(dev);
 435         else if (type == 0x2000)
 436                 return pci_siig20x_init(dev);
 437
 438         moan_device("Unknown SIIG card", dev);
 439         return -ENODEV;
 440 }
 441
 442 static int pci_siig_setup(struct serial_private *priv,
 443                           struct pciserial_board *board,
 444                           struct uart_port *port, int idx)
 445 {
 446         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 447
 448         if (idx > 3) {
 449                 bar = 4;
 450                 offset = (idx - 4) * 8;
 451         }
 452
 453         return setup_port(priv, port, bar, offset, 0);
 454 }
 455
 456 /*
 457  * Timedia has an explosion of boards, and to avoid the PCI table from
 458  * growing *huge*, we use this function to collapse some 70 entries
 459  * in the PCI table into one, for sanity's and compactness's sake.
 460  */
 461 static unsigned short timedia_single_port[] = {
 462         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 463 };
 464
 465 static unsigned short timedia_dual_port[] = {
 466         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 467         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 468         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 469         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 470         0xD079, 0
 471 };
 472
 473 static unsigned short timedia_quad_port[] = {
 474         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 475         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 476         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 477         0xB157, 0
 478 };
 479
 480 static unsigned short timedia_eight_port[] = {
 481         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 482         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 483 };
 484
 485 static const struct timedia_struct {
 486         int num;
 487         unsigned short *ids;
 488 } timedia_data[] = {
 489         { 1, timedia_single_port },
 490         { 2, timedia_dual_port },
 491         { 4, timedia_quad_port },
 492         { 8, timedia_eight_port },
 493         { 0, NULL }
 494 };
 495
 496 static int pci_timedia_init(struct pci_dev *dev)
 497 {
 498         unsigned short *ids;
 499         int i, j;
 500
 501         for (i = 0; timedia_data[i].num; i++) {
 502                 ids = timedia_data[i].ids;
 503                 for (j = 0; ids[j]; j++)
 504                         if (dev->subsystem_device == ids[j])
 505                                 return timedia_data[i].num;
 506         }
 507         return 0;
 508 }
 509
 510 /*
 511  * Timedia/SUNIX uses a mixture of BARs and offsets
 512  * Ugh, this is ugly as all hell --- TYT
 513  */
 514 static int
 515 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 516                   struct uart_port *port, int idx)
 517 {
 518         unsigned int bar = 0, offset = board->first_offset;
 519
 520         switch (idx) {
 521         case 0:
 522                 bar = 0;
 523                 break;
 524         case 1:
 525                 offset = board->uart_offset;
 526                 bar = 0;
 527                 break;
 528         case 2:
 529                 bar = 1;
 530                 break;
 531         case 3:
 532                 offset = board->uart_offset;
 533                 /* FALLTHROUGH */
 534         case 4: /* BAR 2 */
 535         case 5: /* BAR 3 */
 536         case 6: /* BAR 4 */
 537         case 7: /* BAR 5 */
 538                 bar = idx - 2;
 539         }
 540
 541         return setup_port(priv, port, bar, offset, board->reg_shift);
 542 }
 543
 544 /*
 545  * Some Titan cards are also a little weird
 546  */
 547 static int
 548 titan_400l_800l_setup(struct serial_private *priv,
 549                       struct pciserial_board *board,
 550                       struct uart_port *port, int idx)
 551 {
 552         unsigned int bar, offset = board->first_offset;
 553
 554         switch (idx) {
 555         case 0:
 556                 bar = 1;
 557                 break;
 558         case 1:
 559                 bar = 2;
 560                 break;
 561         default:
 562                 bar = 4;
 563                 offset = (idx - 2) * board->uart_offset;
 564         }
 565
 566         return setup_port(priv, port, bar, offset, board->reg_shift);
 567 }
 568
 569 static int pci_xircom_init(struct pci_dev *dev)
 570 {
 571         msleep(100);
 572         return 0;
 573 }
 574
 575 static int pci_netmos_init(struct pci_dev *dev)
 576 {
 577         /* subdevice 0x00PS means <P> parallel, <S> serial */
 578         unsigned int num_serial = dev->subsystem_device & 0xf;
 579
 580         if (num_serial == 0)
 581                 return -ENODEV;
 582         return num_serial;
 583 }
 584
 585 static int
 586 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 587                   struct uart_port *port, int idx)
 588 {
 589         unsigned int bar, offset = board->first_offset, maxnr;
 590
 591         bar = FL_GET_BASE(board->flags);
 592         if (board->flags & FL_BASE_BARS)
 593                 bar += idx;
 594         else
 595                 offset += idx * board->uart_offset;
 596
 597         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 598                 (board->reg_shift + 3);
 599
 600         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 601                 return 1;
 602
 603         return setup_port(priv, port, bar, offset, board->reg_shift);
 604 }
 605
 606 /* This should be in linux/pci_ids.h */
 607 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 608 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 609 #define PCI_DEVICE_ID_OCTPRO            0x0001
 610 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 611 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 612 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 613 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 614
 615 /*
 616  * Master list of serial port init/setup/exit quirks.
 617  * This does not describe the general nature of the port.
 618  * (ie, baud base, number and location of ports, etc)
 619  *
 620  * This list is ordered alphabetically by vendor then device.
 621  * Specific entries must come before more generic entries.
 622  */
 623 static struct pci_serial_quirk pci_serial_quirks[] = {
 624         /*
 625          * AFAVLAB cards - these may be called via parport_serial
 626          *  It is not clear whether this applies to all products.
 627          */
 628         {
 629                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 630                 .device         = PCI_ANY_ID,
 631                 .subvendor      = PCI_ANY_ID,
 632                 .subdevice      = PCI_ANY_ID,
 633                 .setup          = afavlab_setup,
 634         },
 635         /*
 636          * HP Diva
 637          */
 638         {
 639                 .vendor         = PCI_VENDOR_ID_HP,
 640                 .device         = PCI_DEVICE_ID_HP_DIVA,
 641                 .subvendor      = PCI_ANY_ID,
 642                 .subdevice      = PCI_ANY_ID,
 643                 .init           = pci_hp_diva_init,
 644                 .setup          = pci_hp_diva_setup,
 645         },
 646         /*
 647          * Intel
 648          */
 649         {
 650                 .vendor         = PCI_VENDOR_ID_INTEL,
 651                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 652                 .subvendor      = 0xe4bf,
 653                 .subdevice      = PCI_ANY_ID,
 654                 .init           = pci_inteli960ni_init,
 655                 .setup          = pci_default_setup,
 656         },
 657         /*
 658          * Panacom
 659          */
 660         {
 661                 .vendor         = PCI_VENDOR_ID_PANACOM,
 662                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 663                 .subvendor      = PCI_ANY_ID,
 664                 .subdevice      = PCI_ANY_ID,
 665                 .init           = pci_plx9050_init,
 666                 .setup          = pci_default_setup,
 667                 .exit           = __devexit_p(pci_plx9050_exit),
 668         },
 669         {
 670                 .vendor         = PCI_VENDOR_ID_PANACOM,
 671                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 672                 .subvendor      = PCI_ANY_ID,
 673                 .subdevice      = PCI_ANY_ID,
 674                 .init           = pci_plx9050_init,
 675                 .setup          = pci_default_setup,
 676                 .exit           = __devexit_p(pci_plx9050_exit),
 677         },
 678         /*
 679          * PLX
 680          */
 681         {
 682                 .vendor         = PCI_VENDOR_ID_PLX,
 683                 .device         = PCI_DEVICE_ID_PLX_9050,
 684                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 685                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 686                 .init           = pci_plx9050_init,
 687                 .setup          = pci_default_setup,
 688                 .exit           = __devexit_p(pci_plx9050_exit),
 689         },
 690         {
 691                 .vendor         = PCI_VENDOR_ID_PLX,
 692                 .device         = PCI_DEVICE_ID_PLX_9050,
 693                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 694                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 695                 .init           = pci_plx9050_init,
 696                 .setup          = pci_default_setup,
 697                 .exit           = __devexit_p(pci_plx9050_exit),
 698         },
 699         {
 700                 .vendor         = PCI_VENDOR_ID_PLX,
 701                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 702                 .subvendor      = PCI_VENDOR_ID_PLX,
 703                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 704                 .init           = pci_plx9050_init,
 705                 .setup          = pci_default_setup,
 706                 .exit           = __devexit_p(pci_plx9050_exit),
 707         },
 708         /*
 709          * SBS Technologies, Inc., PMC-OCTALPRO 232
 710          */
 711         {
 712                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 713                 .device         = PCI_DEVICE_ID_OCTPRO,
 714                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 715                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 716                 .init           = sbs_init,
 717                 .setup          = sbs_setup,
 718                 .exit           = __devexit_p(sbs_exit),
 719         },
 720         /*
 721          * SBS Technologies, Inc., PMC-OCTALPRO 422
 722          */
 723         {
 724                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 725                 .device         = PCI_DEVICE_ID_OCTPRO,
 726                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 727                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 728                 .init           = sbs_init,
 729                 .setup          = sbs_setup,
 730                 .exit           = __devexit_p(sbs_exit),
 731         },
 732         /*
 733          * SBS Technologies, Inc., P-Octal 232
 734          */
 735         {
 736                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 737                 .device         = PCI_DEVICE_ID_OCTPRO,
 738                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 739                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 740                 .init           = sbs_init,
 741                 .setup          = sbs_setup,
 742                 .exit           = __devexit_p(sbs_exit),
 743         },
 744         /*
 745          * SBS Technologies, Inc., P-Octal 422
 746          */
 747         {
 748                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 749                 .device         = PCI_DEVICE_ID_OCTPRO,
 750                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 751                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 752                 .init           = sbs_init,
 753                 .setup          = sbs_setup,
 754                 .exit           = __devexit_p(sbs_exit),
 755         },
 756         /*
 757          * SIIG cards - these may be called via parport_serial
 758          */
 759         {
 760                 .vendor         = PCI_VENDOR_ID_SIIG,
 761                 .device         = PCI_ANY_ID,
 762                 .subvendor      = PCI_ANY_ID,
 763                 .subdevice      = PCI_ANY_ID,
 764                 .init           = pci_siig_init,
 765                 .setup          = pci_siig_setup,
 766         },
 767         /*
 768          * Titan cards
 769          */
 770         {
 771                 .vendor         = PCI_VENDOR_ID_TITAN,
 772                 .device         = PCI_DEVICE_ID_TITAN_400L,
 773                 .subvendor      = PCI_ANY_ID,
 774                 .subdevice      = PCI_ANY_ID,
 775                 .setup          = titan_400l_800l_setup,
 776         },
 777         {
 778                 .vendor         = PCI_VENDOR_ID_TITAN,
 779                 .device         = PCI_DEVICE_ID_TITAN_800L,
 780                 .subvendor      = PCI_ANY_ID,
 781                 .subdevice      = PCI_ANY_ID,
 782                 .setup          = titan_400l_800l_setup,
 783         },
 784         /*
 785          * Timedia cards
 786          */
 787         {
 788                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 789                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 790                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 791                 .subdevice      = PCI_ANY_ID,
 792                 .init           = pci_timedia_init,
 793                 .setup          = pci_timedia_setup,
 794         },
 795         {
 796                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 797                 .device         = PCI_ANY_ID,
 798                 .subvendor      = PCI_ANY_ID,
 799                 .subdevice      = PCI_ANY_ID,
 800                 .setup          = pci_timedia_setup,
 801         },
 802         /*
 803          * Xircom cards
 804          */
 805         {
 806                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 807                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 808                 .subvendor      = PCI_ANY_ID,
 809                 .subdevice      = PCI_ANY_ID,
 810                 .init           = pci_xircom_init,
 811                 .setup          = pci_default_setup,
 812         },
 813         /*
 814          * Netmos cards - these may be called via parport_serial
 815          */
 816         {
 817                 .vendor         = PCI_VENDOR_ID_NETMOS,
 818                 .device         = PCI_ANY_ID,
 819                 .subvendor      = PCI_ANY_ID,
 820                 .subdevice      = PCI_ANY_ID,
 821                 .init           = pci_netmos_init,
 822                 .setup          = pci_default_setup,
 823         },
 824         /*
 825          * Default "match everything" terminator entry
 826          */
 827         {
 828                 .vendor         = PCI_ANY_ID,
 829                 .device         = PCI_ANY_ID,
 830                 .subvendor      = PCI_ANY_ID,
 831                 .subdevice      = PCI_ANY_ID,
 832                 .setup          = pci_default_setup,
 833         }
 834 };
 835
 836 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 837 {
 838         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 839 }
 840
 841 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 842 {
 843         struct pci_serial_quirk *quirk;
 844
 845         for (quirk = pci_serial_quirks; ; quirk++)
 846                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 847                     quirk_id_matches(quirk->device, dev->device) &&
 848                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 849                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 850                         break;
 851         return quirk;
 852 }
 853
 854 static inline int get_pci_irq(struct pci_dev *dev,
 855                                 struct pciserial_board *board)
 856 {
 857         if (board->flags & FL_NOIRQ)
 858                 return 0;
 859         else
 860                 return dev->irq;
 861 }
 862
 863 /*
 864  * This is the configuration table for all of the PCI serial boards
 865  * which we support.  It is directly indexed by the pci_board_num_t enum
 866  * value, which is encoded in the pci_device_id PCI probe table's
 867  * driver_data member.
 868  *
 869  * The makeup of these names are:
 870  *  pbn_bn{_bt}_n_baud{_offsetinhex}
 871  *
 872  *  bn          = PCI BAR number
 873  *  bt          = Index using PCI BARs
 874  *  n           = number of serial ports
 875  *  baud        = baud rate
 876  *  offsetinhex = offset for each sequential port (in hex)
 877  *
 878  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
 879  *
 880  * Please note: in theory if n = 1, _bt infix should make no difference.
 881  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 882  */
 883 enum pci_board_num_t {
 884         pbn_default = 0,
 885
 886         pbn_b0_1_115200,
 887         pbn_b0_2_115200,
 888         pbn_b0_4_115200,
 889         pbn_b0_5_115200,
 890
 891         pbn_b0_1_921600,
 892         pbn_b0_2_921600,
 893         pbn_b0_4_921600,
 894
 895         pbn_b0_2_1130000,
 896
 897         pbn_b0_4_1152000,
 898
 899         pbn_b0_2_1843200,
 900         pbn_b0_4_1843200,
 901
 902         pbn_b0_2_1843200_200,
 903         pbn_b0_4_1843200_200,
 904         pbn_b0_8_1843200_200,
 905
 906         pbn_b0_bt_1_115200,
 907         pbn_b0_bt_2_115200,
 908         pbn_b0_bt_8_115200,
 909
 910         pbn_b0_bt_1_460800,
 911         pbn_b0_bt_2_460800,
 912         pbn_b0_bt_4_460800,
 913
 914         pbn_b0_bt_1_921600,
 915         pbn_b0_bt_2_921600,
 916         pbn_b0_bt_4_921600,
 917         pbn_b0_bt_8_921600,
 918
 919         pbn_b1_1_115200,
 920         pbn_b1_2_115200,
 921         pbn_b1_4_115200,
 922         pbn_b1_8_115200,
 923
 924         pbn_b1_1_921600,
 925         pbn_b1_2_921600,
 926         pbn_b1_4_921600,
 927         pbn_b1_8_921600,
 928
 929         pbn_b1_2_1250000,
 930
 931         pbn_b1_bt_2_921600,
 932
 933         pbn_b1_1_1382400,
 934         pbn_b1_2_1382400,
 935         pbn_b1_4_1382400,
 936         pbn_b1_8_1382400,
 937
 938         pbn_b2_1_115200,
 939         pbn_b2_2_115200,
 940         pbn_b2_8_115200,
 941
 942         pbn_b2_1_460800,
 943         pbn_b2_4_460800,
 944         pbn_b2_8_460800,
 945         pbn_b2_16_460800,
 946
 947         pbn_b2_1_921600,
 948         pbn_b2_4_921600,
 949         pbn_b2_8_921600,
 950
 951         pbn_b2_bt_1_115200,
 952         pbn_b2_bt_2_115200,
 953         pbn_b2_bt_4_115200,
 954
 955         pbn_b2_bt_2_921600,
 956         pbn_b2_bt_4_921600,
 957
 958         pbn_b3_2_115200,
 959         pbn_b3_4_115200,
 960         pbn_b3_8_115200,
 961
 962         /*
 963          * Board-specific versions.
 964          */
 965         pbn_panacom,
 966         pbn_panacom2,
 967         pbn_panacom4,
 968         pbn_exsys_4055,
 969         pbn_plx_romulus,
 970         pbn_oxsemi,
 971         pbn_intel_i960,
 972         pbn_sgi_ioc3,
 973         pbn_nec_nile4,
 974         pbn_computone_4,
 975         pbn_computone_6,
 976         pbn_computone_8,
 977         pbn_sbsxrsio,
 978         pbn_exar_XR17C152,
 979         pbn_exar_XR17C154,
 980         pbn_exar_XR17C158,
 981 };
 982
 983 /*
 984  * uart_offset - the space between channels
 985  * reg_shift   - describes how the UART registers are mapped
 986  *               to PCI memory by the card.
 987  * For example IER register on SBS, Inc. PMC-OctPro is located at
 988  * offset 0x10 from the UART base, while UART_IER is defined as 1
 989  * in include/linux/serial_reg.h,
 990  * see first lines of serial_in() and serial_out() in 8250.c
 991 */
 992
 993 static struct pciserial_board pci_boards[] __devinitdata = {
 994         [pbn_default] = {
 995                 .flags          = FL_BASE0,
 996                 .num_ports      = 1,
 997                 .base_baud      = 115200,
 998                 .uart_offset    = 8,
 999         },
1000         [pbn_b0_1_115200] = {
1001                 .flags          = FL_BASE0,
1002                 .num_ports      = 1,
1003                 .base_baud      = 115200,
1004                 .uart_offset    = 8,
1005         },
1006         [pbn_b0_2_115200] = {
1007                 .flags          = FL_BASE0,
1008                 .num_ports      = 2,
1009                 .base_baud      = 115200,
1010                 .uart_offset    = 8,
1011         },
1012         [pbn_b0_4_115200] = {
1013                 .flags          = FL_BASE0,
1014                 .num_ports      = 4,
1015                 .base_baud      = 115200,
1016                 .uart_offset    = 8,
1017         },
1018         [pbn_b0_5_115200] = {
1019                 .flags          = FL_BASE0,
1020                 .num_ports      = 5,
1021                 .base_baud      = 115200,
1022                 .uart_offset    = 8,
1023         },
1024
1025         [pbn_b0_1_921600] = {
1026                 .flags          = FL_BASE0,
1027                 .num_ports      = 1,
1028                 .base_baud      = 921600,
1029                 .uart_offset    = 8,
1030         },
1031         [pbn_b0_2_921600] = {
1032                 .flags          = FL_BASE0,
1033                 .num_ports      = 2,
1034                 .base_baud      = 921600,
1035                 .uart_offset    = 8,
1036         },
1037         [pbn_b0_4_921600] = {
1038                 .flags          = FL_BASE0,
1039                 .num_ports      = 4,
1040                 .base_baud      = 921600,
1041                 .uart_offset    = 8,
1042         },
1043
1044         [pbn_b0_2_1130000] = {
1045                 .flags          = FL_BASE0,
1046                 .num_ports      = 2,
1047                 .base_baud      = 1130000,
1048                 .uart_offset    = 8,
1049         },
1050
1051         [pbn_b0_4_1152000] = {
1052                 .flags          = FL_BASE0,
1053                 .num_ports      = 4,
1054                 .base_baud      = 1152000,
1055                 .uart_offset    = 8,
1056         },
1057
1058         [pbn_b0_2_1843200] = {
1059                 .flags          = FL_BASE0,
1060                 .num_ports      = 2,
1061                 .base_baud      = 1843200,
1062                 .uart_offset    = 8,
1063         },
1064         [pbn_b0_4_1843200] = {
1065                 .flags          = FL_BASE0,
1066                 .num_ports      = 4,
1067                 .base_baud      = 1843200,
1068                 .uart_offset    = 8,
1069         },
1070
1071         [pbn_b0_2_1843200_200] = {
1072                 .flags          = FL_BASE0,
1073                 .num_ports      = 2,
1074                 .base_baud      = 1843200,
1075                 .uart_offset    = 0x200,
1076         },
1077         [pbn_b0_4_1843200_200] = {
1078                 .flags          = FL_BASE0,
1079                 .num_ports      = 4,
1080                 .base_baud      = 1843200,
1081                 .uart_offset    = 0x200,
1082         },
1083         [pbn_b0_8_1843200_200] = {
1084                 .flags          = FL_BASE0,
1085                 .num_ports      = 8,
1086                 .base_baud      = 1843200,
1087                 .uart_offset    = 0x200,
1088         },
1089
1090         [pbn_b0_bt_1_115200] = {
1091                 .flags          = FL_BASE0|FL_BASE_BARS,
1092                 .num_ports      = 1,
1093                 .base_baud      = 115200,
1094                 .uart_offset    = 8,
1095         },
1096         [pbn_b0_bt_2_115200] = {
1097                 .flags          = FL_BASE0|FL_BASE_BARS,
1098                 .num_ports      = 2,
1099                 .base_baud      = 115200,
1100                 .uart_offset    = 8,
1101         },
1102         [pbn_b0_bt_8_115200] = {
1103                 .flags          = FL_BASE0|FL_BASE_BARS,
1104                 .num_ports      = 8,
1105                 .base_baud      = 115200,
1106                 .uart_offset    = 8,
1107         },
1108
1109         [pbn_b0_bt_1_460800] = {
1110                 .flags          = FL_BASE0|FL_BASE_BARS,
1111                 .num_ports      = 1,
1112                 .base_baud      = 460800,
1113                 .uart_offset    = 8,
1114         },
1115         [pbn_b0_bt_2_460800] = {
1116                 .flags          = FL_BASE0|FL_BASE_BARS,
1117                 .num_ports      = 2,
1118                 .base_baud      = 460800,
1119                 .uart_offset    = 8,
1120         },
1121         [pbn_b0_bt_4_460800] = {
1122                 .flags          = FL_BASE0|FL_BASE_BARS,
1123                 .num_ports      = 4,
1124                 .base_baud      = 460800,
1125                 .uart_offset    = 8,
1126         },
1127
1128         [pbn_b0_bt_1_921600] = {
1129                 .flags          = FL_BASE0|FL_BASE_BARS,
1130                 .num_ports      = 1,
1131                 .base_baud      = 921600,
1132                 .uart_offset    = 8,
1133         },
1134         [pbn_b0_bt_2_921600] = {
1135                 .flags          = FL_BASE0|FL_BASE_BARS,
1136                 .num_ports      = 2,
1137                 .base_baud      = 921600,
1138                 .uart_offset    = 8,
1139         },
1140         [pbn_b0_bt_4_921600] = {
1141                 .flags          = FL_BASE0|FL_BASE_BARS,
1142                 .num_ports      = 4,
1143                 .base_baud      = 921600,
1144                 .uart_offset    = 8,
1145         },
1146         [pbn_b0_bt_8_921600] = {
1147                 .flags          = FL_BASE0|FL_BASE_BARS,
1148                 .num_ports      = 8,
1149                 .base_baud      = 921600,
1150                 .uart_offset    = 8,
1151         },
1152
1153         [pbn_b1_1_115200] = {
1154                 .flags          = FL_BASE1,
1155                 .num_ports      = 1,
1156                 .base_baud      = 115200,
1157                 .uart_offset    = 8,
1158         },
1159         [pbn_b1_2_115200] = {
1160                 .flags          = FL_BASE1,
1161                 .num_ports      = 2,
1162                 .base_baud      = 115200,
1163                 .uart_offset    = 8,
1164         },
1165         [pbn_b1_4_115200] = {
1166                 .flags          = FL_BASE1,
1167                 .num_ports      = 4,
1168                 .base_baud      = 115200,
1169                 .uart_offset    = 8,
1170         },
1171         [pbn_b1_8_115200] = {
1172                 .flags          = FL_BASE1,
1173                 .num_ports      = 8,
1174                 .base_baud      = 115200,
1175                 .uart_offset    = 8,
1176         },
1177
1178         [pbn_b1_1_921600] = {
1179                 .flags          = FL_BASE1,
1180                 .num_ports      = 1,
1181                 .base_baud      = 921600,
1182                 .uart_offset    = 8,
1183         },
1184         [pbn_b1_2_921600] = {
1185                 .flags          = FL_BASE1,
1186                 .num_ports      = 2,
1187                 .base_baud      = 921600,
1188                 .uart_offset    = 8,
1189         },
1190         [pbn_b1_4_921600] = {
1191                 .flags          = FL_BASE1,
1192                 .num_ports      = 4,
1193                 .base_baud      = 921600,
1194                 .uart_offset    = 8,
1195         },
1196         [pbn_b1_8_921600] = {
1197                 .flags          = FL_BASE1,
1198                 .num_ports      = 8,
1199                 .base_baud      = 921600,
1200                 .uart_offset    = 8,
1201         },
1202         [pbn_b1_2_1250000] = {
1203                 .flags          = FL_BASE1,
1204                 .num_ports      = 2,
1205                 .base_baud      = 1250000,
1206                 .uart_offset    = 8,
1207         },
1208
1209         [pbn_b1_bt_2_921600] = {
1210                 .flags          = FL_BASE1|FL_BASE_BARS,
1211                 .num_ports      = 2,
1212                 .base_baud      = 921600,
1213                 .uart_offset    = 8,
1214         },
1215
1216         [pbn_b1_1_1382400] = {
1217                 .flags          = FL_BASE1,
1218                 .num_ports      = 1,
1219                 .base_baud      = 1382400,
1220                 .uart_offset    = 8,
1221         },
1222         [pbn_b1_2_1382400] = {
1223                 .flags          = FL_BASE1,
1224                 .num_ports      = 2,
1225                 .base_baud      = 1382400,
1226                 .uart_offset    = 8,
1227         },
1228         [pbn_b1_4_1382400] = {
1229                 .flags          = FL_BASE1,
1230                 .num_ports      = 4,
1231                 .base_baud      = 1382400,
1232                 .uart_offset    = 8,
1233         },
1234         [pbn_b1_8_1382400] = {
1235                 .flags          = FL_BASE1,
1236                 .num_ports      = 8,
1237                 .base_baud      = 1382400,
1238                 .uart_offset    = 8,
1239         },
1240
1241         [pbn_b2_1_115200] = {
1242                 .flags          = FL_BASE2,
1243                 .num_ports      = 1,
1244                 .base_baud      = 115200,
1245                 .uart_offset    = 8,
1246         },
1247         [pbn_b2_2_115200] = {
1248                 .flags          = FL_BASE2,
1249                 .num_ports      = 2,
1250                 .base_baud      = 115200,
1251                 .uart_offset    = 8,
1252         },
1253         [pbn_b2_8_115200] = {
1254                 .flags          = FL_BASE2,
1255                 .num_ports      = 8,
1256                 .base_baud      = 115200,
1257                 .uart_offset    = 8,
1258         },
1259
1260         [pbn_b2_1_460800] = {
1261                 .flags          = FL_BASE2,
1262                 .num_ports      = 1,
1263                 .base_baud      = 460800,
1264                 .uart_offset    = 8,
1265         },
1266         [pbn_b2_4_460800] = {
1267                 .flags          = FL_BASE2,
1268                 .num_ports      = 4,
1269                 .base_baud      = 460800,
1270                 .uart_offset    = 8,
1271         },
1272         [pbn_b2_8_460800] = {
1273                 .flags          = FL_BASE2,
1274                 .num_ports      = 8,
1275                 .base_baud      = 460800,
1276                 .uart_offset    = 8,
1277         },
1278         [pbn_b2_16_460800] = {
1279                 .flags          = FL_BASE2,
1280                 .num_ports      = 16,
1281                 .base_baud      = 460800,
1282                 .uart_offset    = 8,
1283          },
1284
1285         [pbn_b2_1_921600] = {
1286                 .flags          = FL_BASE2,
1287                 .num_ports      = 1,
1288                 .base_baud      = 921600,
1289                 .uart_offset    = 8,
1290         },
1291         [pbn_b2_4_921600] = {
1292                 .flags          = FL_BASE2,
1293                 .num_ports      = 4,
1294                 .base_baud      = 921600,
1295                 .uart_offset    = 8,
1296         },
1297         [pbn_b2_8_921600] = {
1298                 .flags          = FL_BASE2,
1299                 .num_ports      = 8,
1300                 .base_baud      = 921600,
1301                 .uart_offset    = 8,
1302         },
1303
1304         [pbn_b2_bt_1_115200] = {
1305                 .flags          = FL_BASE2|FL_BASE_BARS,
1306                 .num_ports      = 1,
1307                 .base_baud      = 115200,
1308                 .uart_offset    = 8,
1309         },
1310         [pbn_b2_bt_2_115200] = {
1311                 .flags          = FL_BASE2|FL_BASE_BARS,
1312                 .num_ports      = 2,
1313                 .base_baud      = 115200,
1314                 .uart_offset    = 8,
1315         },
1316         [pbn_b2_bt_4_115200] = {
1317                 .flags          = FL_BASE2|FL_BASE_BARS,
1318                 .num_ports      = 4,
1319                 .base_baud      = 115200,
1320                 .uart_offset    = 8,
1321         },
1322
1323         [pbn_b2_bt_2_921600] = {
1324                 .flags          = FL_BASE2|FL_BASE_BARS,
1325                 .num_ports      = 2,
1326                 .base_baud      = 921600,
1327                 .uart_offset    = 8,
1328         },
1329         [pbn_b2_bt_4_921600] = {
1330                 .flags          = FL_BASE2|FL_BASE_BARS,
1331                 .num_ports      = 4,
1332                 .base_baud      = 921600,
1333                 .uart_offset    = 8,
1334         },
1335
1336         [pbn_b3_2_115200] = {
1337                 .flags          = FL_BASE3,
1338                 .num_ports      = 2,
1339                 .base_baud      = 115200,
1340                 .uart_offset    = 8,
1341         },
1342         [pbn_b3_4_115200] = {
1343                 .flags          = FL_BASE3,
1344                 .num_ports      = 4,
1345                 .base_baud      = 115200,
1346                 .uart_offset    = 8,
1347         },
1348         [pbn_b3_8_115200] = {
1349                 .flags          = FL_BASE3,
1350                 .num_ports      = 8,
1351                 .base_baud      = 115200,
1352                 .uart_offset    = 8,
1353         },
1354
1355         /*
1356          * Entries following this are board-specific.
1357          */
1358
1359         /*
1360          * Panacom - IOMEM
1361          */
1362         [pbn_panacom] = {
1363                 .flags          = FL_BASE2,
1364                 .num_ports      = 2,
1365                 .base_baud      = 921600,
1366                 .uart_offset    = 0x400,
1367                 .reg_shift      = 7,
1368         },
1369         [pbn_panacom2] = {
1370                 .flags          = FL_BASE2|FL_BASE_BARS,
1371                 .num_ports      = 2,
1372                 .base_baud      = 921600,
1373                 .uart_offset    = 0x400,
1374                 .reg_shift      = 7,
1375         },
1376         [pbn_panacom4] = {
1377                 .flags          = FL_BASE2|FL_BASE_BARS,
1378                 .num_ports      = 4,
1379                 .base_baud      = 921600,
1380                 .uart_offset    = 0x400,
1381                 .reg_shift      = 7,
1382         },
1383
1384         [pbn_exsys_4055] = {
1385                 .flags          = FL_BASE2,
1386                 .num_ports      = 4,
1387                 .base_baud      = 115200,
1388                 .uart_offset    = 8,
1389         },
1390
1391         /* I think this entry is broken - the first_offset looks wrong --rmk */
1392         [pbn_plx_romulus] = {
1393                 .flags          = FL_BASE2,
1394                 .num_ports      = 4,
1395                 .base_baud      = 921600,
1396                 .uart_offset    = 8 << 2,
1397                 .reg_shift      = 2,
1398                 .first_offset   = 0x03,
1399         },
1400
1401         /*
1402          * This board uses the size of PCI Base region 0 to
1403          * signal now many ports are available
1404          */
1405         [pbn_oxsemi] = {
1406                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1407                 .num_ports      = 32,
1408                 .base_baud      = 115200,
1409                 .uart_offset    = 8,
1410         },
1411
1412         /*
1413          * EKF addition for i960 Boards form EKF with serial port.
1414          * Max 256 ports.
1415          */
1416         [pbn_intel_i960] = {
1417                 .flags          = FL_BASE0,
1418                 .num_ports      = 32,
1419                 .base_baud      = 921600,
1420                 .uart_offset    = 8 << 2,
1421                 .reg_shift      = 2,
1422                 .first_offset   = 0x10000,
1423         },
1424         [pbn_sgi_ioc3] = {
1425                 .flags          = FL_BASE0|FL_NOIRQ,
1426                 .num_ports      = 1,
1427                 .base_baud      = 458333,
1428                 .uart_offset    = 8,
1429                 .reg_shift      = 0,
1430                 .first_offset   = 0x20178,
1431         },
1432
1433         /*
1434          * NEC Vrc-5074 (Nile 4) builtin UART.
1435          */
1436         [pbn_nec_nile4] = {
1437                 .flags          = FL_BASE0,
1438                 .num_ports      = 1,
1439                 .base_baud      = 520833,
1440                 .uart_offset    = 8 << 3,
1441                 .reg_shift      = 3,
1442                 .first_offset   = 0x300,
1443         },
1444
1445         /*
1446          * Computone - uses IOMEM.
1447          */
1448         [pbn_computone_4] = {
1449                 .flags          = FL_BASE0,
1450                 .num_ports      = 4,
1451                 .base_baud      = 921600,
1452                 .uart_offset    = 0x40,
1453                 .reg_shift      = 2,
1454                 .first_offset   = 0x200,
1455         },
1456         [pbn_computone_6] = {
1457                 .flags          = FL_BASE0,
1458                 .num_ports      = 6,
1459                 .base_baud      = 921600,
1460                 .uart_offset    = 0x40,
1461                 .reg_shift      = 2,
1462                 .first_offset   = 0x200,
1463         },
1464         [pbn_computone_8] = {
1465                 .flags          = FL_BASE0,
1466                 .num_ports      = 8,
1467                 .base_baud      = 921600,
1468                 .uart_offset    = 0x40,
1469                 .reg_shift      = 2,
1470                 .first_offset   = 0x200,
1471         },
1472         [pbn_sbsxrsio] = {
1473                 .flags          = FL_BASE0,
1474                 .num_ports      = 8,
1475                 .base_baud      = 460800,
1476                 .uart_offset    = 256,
1477                 .reg_shift      = 4,
1478         },
1479         /*
1480          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1481          *  Only basic 16550A support.
1482          *  XR17C15[24] are not tested, but they should work.
1483          */
1484         [pbn_exar_XR17C152] = {
1485                 .flags          = FL_BASE0,
1486                 .num_ports      = 2,
1487                 .base_baud      = 921600,
1488                 .uart_offset    = 0x200,
1489         },
1490         [pbn_exar_XR17C154] = {
1491                 .flags          = FL_BASE0,
1492                 .num_ports      = 4,
1493                 .base_baud      = 921600,
1494                 .uart_offset    = 0x200,
1495         },
1496         [pbn_exar_XR17C158] = {
1497                 .flags          = FL_BASE0,
1498                 .num_ports      = 8,
1499                 .base_baud      = 921600,
1500                 .uart_offset    = 0x200,
1501         },
1502 };
1503
1504 /*
1505  * Given a complete unknown PCI device, try to use some heuristics to
1506  * guess what the configuration might be, based on the pitiful PCI
1507  * serial specs.  Returns 0 on success, 1 on failure.
1508  */
1509 static int __devinit
1510 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1511 {
1512         int num_iomem, num_port, first_port = -1, i;
1513
1514         /*
1515          * If it is not a communications device or the programming
1516          * interface is greater than 6, give up.
1517          *
1518          * (Should we try to make guesses for multiport serial devices
1519          * later?)
1520          */
1521         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1522              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1523             (dev->class & 0xff) > 6)
1524                 return -ENODEV;
1525
1526         num_iomem = num_port = 0;
1527         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1528                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1529                         num_port++;
1530                         if (first_port == -1)
1531                                 first_port = i;
1532                 }
1533                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1534                         num_iomem++;
1535         }
1536
1537         /*
1538          * If there is 1 or 0 iomem regions, and exactly one port,
1539          * use it.  We guess the number of ports based on the IO
1540          * region size.
1541          */
1542         if (num_iomem <= 1 && num_port == 1) {
1543                 board->flags = first_port;
1544                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1545                 return 0;
1546         }
1547
1548         /*
1549          * Now guess if we've got a board which indexes by BARs.
1550          * Each IO BAR should be 8 bytes, and they should follow
1551          * consecutively.
1552          */
1553         first_port = -1;
1554         num_port = 0;
1555         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1556                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1557                     pci_resource_len(dev, i) == 8 &&
1558                     (first_port == -1 || (first_port + num_port) == i)) {
1559                         num_port++;
1560                         if (first_port == -1)
1561                                 first_port = i;
1562                 }
1563         }
1564
1565         if (num_port > 1) {
1566                 board->flags = first_port | FL_BASE_BARS;
1567                 board->num_ports = num_port;
1568                 return 0;
1569         }
1570
1571         return -ENODEV;
1572 }
1573
1574 static inline int
1575 serial_pci_matches(struct pciserial_board *board,
1576                    struct pciserial_board *guessed)
1577 {
1578         return
1579             board->num_ports == guessed->num_ports &&
1580             board->base_baud == guessed->base_baud &&
1581             board->uart_offset == guessed->uart_offset &&
1582             board->reg_shift == guessed->reg_shift &&
1583             board->first_offset == guessed->first_offset;
1584 }
1585
1586 struct serial_private *
1587 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1588 {
1589         struct uart_port serial_port;
1590         struct serial_private *priv;
1591         struct pci_serial_quirk *quirk;
1592         int rc, nr_ports, i;
1593
1594         nr_ports = board->num_ports;
1595
1596         /*
1597          * Find an init and setup quirks.
1598          */
1599         quirk = find_quirk(dev);
1600
1601         /*
1602          * Run the new-style initialization function.
1603          * The initialization function returns:
1604          *  <0  - error
1605          *   0  - use board->num_ports
1606          *  >0  - number of ports
1607          */
1608         if (quirk->init) {
1609                 rc = quirk->init(dev);
1610                 if (rc < 0) {
1611                         priv = ERR_PTR(rc);
1612                         goto err_out;
1613                 }
1614                 if (rc)
1615                         nr_ports = rc;
1616         }
1617
1618         priv = kmalloc(sizeof(struct serial_private) +
1619                        sizeof(unsigned int) * nr_ports,
1620                        GFP_KERNEL);
1621         if (!priv) {
1622                 priv = ERR_PTR(-ENOMEM);
1623                 goto err_deinit;
1624         }
1625
1626         memset(priv, 0, sizeof(struct serial_private) +
1627                         sizeof(unsigned int) * nr_ports);
1628
1629         priv->dev = dev;
1630         priv->quirk = quirk;
1631
1632         memset(&serial_port, 0, sizeof(struct uart_port));
1633         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1634         serial_port.uartclk = board->base_baud * 16;
1635         serial_port.irq = get_pci_irq(dev, board);
1636         serial_port.dev = &dev->dev;
1637
1638         for (i = 0; i < nr_ports; i++) {
1639                 if (quirk->setup(priv, board, &serial_port, i))
1640                         break;
1641
1642 #ifdef SERIAL_DEBUG_PCI
1643                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1644                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1645 #endif
1646
1647                 priv->line[i] = serial8250_register_port(&serial_port);
1648                 if (priv->line[i] < 0) {
1649                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1650                         break;
1651                 }
1652         }
1653
1654         priv->nr = i;
1655
1656         return priv;
1657
1658  err_deinit:
1659         if (quirk->exit)
1660                 quirk->exit(dev);
1661  err_out:
1662         return priv;
1663 }
1664 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1665
1666 void pciserial_remove_ports(struct serial_private *priv)
1667 {
1668         struct pci_serial_quirk *quirk;
1669         int i;
1670
1671         for (i = 0; i < priv->nr; i++)
1672                 serial8250_unregister_port(priv->line[i]);
1673
1674         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1675                 if (priv->remapped_bar[i])
1676                         iounmap(priv->remapped_bar[i]);
1677                 priv->remapped_bar[i] = NULL;
1678         }
1679
1680         /*
1681          * Find the exit quirks.
1682          */
1683         quirk = find_quirk(priv->dev);
1684         if (quirk->exit)
1685                 quirk->exit(priv->dev);
1686
1687         kfree(priv);
1688 }
1689 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1690
1691 void pciserial_suspend_ports(struct serial_private *priv)
1692 {
1693         int i;
1694
1695         for (i = 0; i < priv->nr; i++)
1696                 if (priv->line[i] >= 0)
1697                         serial8250_suspend_port(priv->line[i]);
1698 }
1699 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1700
1701 void pciserial_resume_ports(struct serial_private *priv)
1702 {
1703         int i;
1704
1705         /*
1706          * Ensure that the board is correctly configured.
1707          */
1708         if (priv->quirk->init)
1709                 priv->quirk->init(priv->dev);
1710
1711         for (i = 0; i < priv->nr; i++)
1712                 if (priv->line[i] >= 0)
1713                         serial8250_resume_port(priv->line[i]);
1714 }
1715 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1716
1717 /*
1718  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1719  * to the arrangement of serial ports on a PCI card.
1720  */
1721 static int __devinit
1722 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1723 {
1724         struct serial_private *priv;
1725         struct pciserial_board *board, tmp;
1726         int rc;
1727
1728         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1729                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1730                         ent->driver_data);
1731                 return -EINVAL;
1732         }
1733
1734         board = &pci_boards[ent->driver_data];
1735
1736         rc = pci_enable_device(dev);
1737         if (rc)
1738                 return rc;
1739
1740         if (ent->driver_data == pbn_default) {
1741                 /*
1742                  * Use a copy of the pci_board entry for this;
1743                  * avoid changing entries in the table.
1744                  */
1745                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1746                 board = &tmp;
1747
1748                 /*
1749                  * We matched one of our class entries.  Try to
1750                  * determine the parameters of this board.
1751                  */
1752                 rc = serial_pci_guess_board(dev, board);
1753                 if (rc)
1754                         goto disable;
1755         } else {
1756                 /*
1757                  * We matched an explicit entry.  If we are able to
1758                  * detect this boards settings with our heuristic,
1759                  * then we no longer need this entry.
1760                  */
1761                 memcpy(&tmp, &pci_boards[pbn_default],
1762                        sizeof(struct pciserial_board));
1763                 rc = serial_pci_guess_board(dev, &tmp);
1764                 if (rc == 0 && serial_pci_matches(board, &tmp))
1765                         moan_device("Redundant entry in serial pci_table.",
1766                                     dev);
1767         }
1768
1769         priv = pciserial_init_ports(dev, board);
1770         if (!IS_ERR(priv)) {
1771                 pci_set_drvdata(dev, priv);
1772                 return 0;
1773         }
1774
1775         rc = PTR_ERR(priv);
1776
1777  disable:
1778         pci_disable_device(dev);
1779         return rc;
1780 }
1781
1782 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1783 {
1784         struct serial_private *priv = pci_get_drvdata(dev);
1785
1786         pci_set_drvdata(dev, NULL);
1787
1788         pciserial_remove_ports(priv);
1789
1790         pci_disable_device(dev);
1791 }
1792
1793 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1794 {
1795         struct serial_private *priv = pci_get_drvdata(dev);
1796
1797         if (priv)
1798                 pciserial_suspend_ports(priv);
1799
1800         pci_save_state(dev);
1801         pci_set_power_state(dev, pci_choose_state(dev, state));
1802         return 0;
1803 }
1804
1805 static int pciserial_resume_one(struct pci_dev *dev)
1806 {
1807         struct serial_private *priv = pci_get_drvdata(dev);
1808
1809         pci_set_power_state(dev, PCI_D0);
1810         pci_restore_state(dev);
1811
1812         if (priv) {
1813                 /*
1814                  * The device may have been disabled.  Re-enable it.
1815                  */
1816                 pci_enable_device(dev);
1817
1818                 pciserial_resume_ports(priv);
1819         }
1820         return 0;
1821 }
1822
1823 static struct pci_device_id serial_pci_tbl[] = {
1824         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1825                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1826                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1827                 pbn_b1_8_1382400 },
1828         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1829                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1830                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1831                 pbn_b1_4_1382400 },
1832         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1833                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1834                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1835                 pbn_b1_2_1382400 },
1836         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1837                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1839                 pbn_b1_8_1382400 },
1840         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1841                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1843                 pbn_b1_4_1382400 },
1844         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1845                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1847                 pbn_b1_2_1382400 },
1848         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1851                 pbn_b1_8_921600 },
1852         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1855                 pbn_b1_8_921600 },
1856         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1857                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1859                 pbn_b1_4_921600 },
1860         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1863                 pbn_b1_4_921600 },
1864         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1867                 pbn_b1_2_921600 },
1868         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1871                 pbn_b1_8_921600 },
1872         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1875                 pbn_b1_8_921600 },
1876         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1879                 pbn_b1_4_921600 },
1880         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1883                 pbn_b1_2_1250000 },
1884         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1885                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1887                 pbn_b0_2_1843200 },
1888         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1889                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1891                 pbn_b0_4_1843200 },
1892         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1893                 PCI_VENDOR_ID_AFAVLAB,
1894                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1895                 pbn_b0_4_1152000 },
1896         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1897                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1899                 pbn_b0_2_1843200_200 },
1900         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1901                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1903                 pbn_b0_4_1843200_200 },
1904         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1905                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1906                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1907                 pbn_b0_8_1843200_200 },
1908         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1909                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1911                 pbn_b0_2_1843200_200 },
1912         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1913                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1914                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1915                 pbn_b0_4_1843200_200 },
1916         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1917                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1918                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1919                 pbn_b0_8_1843200_200 },
1920         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1921                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1922                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1923                 pbn_b0_2_1843200_200 },
1924         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1925                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1926                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1927                 pbn_b0_4_1843200_200 },
1928         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1929                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1930                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1931                 pbn_b0_8_1843200_200 },
1932         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1933                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1934                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1935                 pbn_b0_2_1843200_200 },
1936         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1937                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1938                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1939                 pbn_b0_4_1843200_200 },
1940         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1941                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1942                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1943                 pbn_b0_8_1843200_200 },
1944
1945         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1947                 pbn_b2_bt_1_115200 },
1948         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1950                 pbn_b2_bt_2_115200 },
1951         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953                 pbn_b2_bt_4_115200 },
1954         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956                 pbn_b2_bt_2_115200 },
1957         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1958                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959                 pbn_b2_bt_4_115200 },
1960         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962                 pbn_b2_8_115200 },
1963         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965                 pbn_b2_8_115200 },
1966
1967         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1968                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969                 pbn_b2_bt_2_115200 },
1970         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972                 pbn_b2_bt_2_921600 },
1973         /*
1974          * VScom SPCOM800, from sl@s.pl
1975          */
1976         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978                 pbn_b2_8_921600 },
1979         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981                 pbn_b2_4_921600 },
1982         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1983                 PCI_SUBVENDOR_ID_KEYSPAN,
1984                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1985                 pbn_panacom },
1986         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988                 pbn_panacom4 },
1989         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991                 pbn_panacom2 },
1992         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1993                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1994                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1995                 pbn_b2_4_460800 },
1996         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1997                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1998                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1999                 pbn_b2_8_460800 },
2000         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2001                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2002                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2003                 pbn_b2_16_460800 },
2004         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2005                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2006                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2007                 pbn_b2_16_460800 },
2008         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2009                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2010                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2011                 pbn_b2_4_460800 },
2012         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2013                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2014                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2015                 pbn_b2_8_460800 },
2016         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2017                 PCI_SUBVENDOR_ID_EXSYS,
2018                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2019                 pbn_exsys_4055 },
2020         /*
2021          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2022          * (Exoray@isys.ca)
2023          */
2024         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2025                 0x10b5, 0x106a, 0, 0,
2026                 pbn_plx_romulus },
2027         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2028                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2029                 pbn_b1_4_115200 },
2030         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2031                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2032                 pbn_b1_2_115200 },
2033         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2034                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2035                 pbn_b1_8_115200 },
2036         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2038                 pbn_b1_8_115200 },
2039         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2040                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2041                 pbn_b0_4_921600 },
2042         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2043                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2044                 pbn_b0_4_1152000 },
2045
2046                 /*
2047                  * The below card is a little controversial since it is the
2048                  * subject of a PCI vendor/device ID clash.  (See
2049                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2050                  * For now just used the hex ID 0x950a.
2051                  */
2052         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054                 pbn_b0_2_1130000 },
2055         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2056                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2057                 pbn_b0_4_115200 },
2058         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2059                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2060                 pbn_b0_bt_2_921600 },
2061
2062         /*
2063          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2064          * from skokodyn@yahoo.com
2065          */
2066         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2067                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2068                 pbn_sbsxrsio },
2069         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2070                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2071                 pbn_sbsxrsio },
2072         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2073                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2074                 pbn_sbsxrsio },
2075         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2076                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2077                 pbn_sbsxrsio },
2078
2079         /*
2080          * Digitan DS560-558, from jimd@esoft.com
2081          */
2082         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2084                 pbn_b1_1_115200 },
2085
2086         /*
2087          * Titan Electronic cards
2088          *  The 400L and 800L have a custom setup quirk.
2089          */
2090         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092                 pbn_b0_1_921600 },
2093         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095                 pbn_b0_2_921600 },
2096         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098                 pbn_b0_4_921600 },
2099         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101                 pbn_b0_4_921600 },
2102         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104                 pbn_b1_1_921600 },
2105         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107                 pbn_b1_bt_2_921600 },
2108         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b0_bt_4_921600 },
2111         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113                 pbn_b0_bt_8_921600 },
2114
2115         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2117                 pbn_b2_1_460800 },
2118         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120                 pbn_b2_1_460800 },
2121         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123                 pbn_b2_1_460800 },
2124         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126                 pbn_b2_bt_2_921600 },
2127         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129                 pbn_b2_bt_2_921600 },
2130         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132                 pbn_b2_bt_2_921600 },
2133         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2135                 pbn_b2_bt_4_921600 },
2136         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138                 pbn_b2_bt_4_921600 },
2139         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_b2_bt_4_921600 },
2142         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144                 pbn_b0_1_921600 },
2145         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2147                 pbn_b0_1_921600 },
2148         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2149                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2150                 pbn_b0_1_921600 },
2151         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2152                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153                 pbn_b0_bt_2_921600 },
2154         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2155                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2156                 pbn_b0_bt_2_921600 },
2157         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2158                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159                 pbn_b0_bt_2_921600 },
2160         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2161                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162                 pbn_b0_bt_4_921600 },
2163         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2164                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165                 pbn_b0_bt_4_921600 },
2166         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2167                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168                 pbn_b0_bt_4_921600 },
2169         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2170                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171                 pbn_b0_bt_8_921600 },
2172         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2173                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174                 pbn_b0_bt_8_921600 },
2175         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177                 pbn_b0_bt_8_921600 },
2178
2179         /*
2180          * Computone devices submitted by Doug McNash dmcnash@computone.com
2181          */
2182         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2183                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2184                 0, 0, pbn_computone_4 },
2185         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2186                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2187                 0, 0, pbn_computone_8 },
2188         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2189                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2190                 0, 0, pbn_computone_6 },
2191
2192         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2194                 pbn_oxsemi },
2195         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2196                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2197                 pbn_b0_bt_1_921600 },
2198
2199         /*
2200          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2201          */
2202         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2203                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204                 pbn_b0_bt_8_115200 },
2205         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2206                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2207                 pbn_b0_bt_8_115200 },
2208
2209         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211                 pbn_b0_bt_2_115200 },
2212         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2214                 pbn_b0_bt_2_115200 },
2215         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2217                 pbn_b0_bt_2_115200 },
2218         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220                 pbn_b0_bt_4_460800 },
2221         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223                 pbn_b0_bt_4_460800 },
2224         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2226                 pbn_b0_bt_2_460800 },
2227         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2229                 pbn_b0_bt_2_460800 },
2230         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2232                 pbn_b0_bt_2_460800 },
2233         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2235                 pbn_b0_bt_1_115200 },
2236         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2238                 pbn_b0_bt_1_460800 },
2239
2240         /*
2241          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2242          */
2243         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2245                 pbn_b1_1_1382400 },
2246
2247         /*
2248          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2249          */
2250         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2252                 pbn_b1_1_1382400 },
2253
2254         /*
2255          * RAStel 2 port modem, gerg@moreton.com.au
2256          */
2257         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2259                 pbn_b2_bt_2_115200 },
2260
2261         /*
2262          * EKF addition for i960 Boards form EKF with serial port
2263          */
2264         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2265                 0xE4BF, PCI_ANY_ID, 0, 0,
2266                 pbn_intel_i960 },
2267
2268         /*
2269          * Xircom Cardbus/Ethernet combos
2270          */
2271         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2273                 pbn_b0_1_115200 },
2274         /*
2275          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2276          */
2277         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2279                 pbn_b0_1_115200 },
2280
2281         /*
2282          * Untested PCI modems, sent in from various folks...
2283          */
2284
2285         /*
2286          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2287          */
2288         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2289                 0x1048, 0x1500, 0, 0,
2290                 pbn_b1_1_115200 },
2291
2292         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2293                 0xFF00, 0, 0, 0,
2294                 pbn_sgi_ioc3 },
2295
2296         /*
2297          * HP Diva card
2298          */
2299         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2300                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2301                 pbn_b1_1_115200 },
2302         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2304                 pbn_b0_5_115200 },
2305         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2307                 pbn_b2_1_115200 },
2308
2309         /*
2310          * NEC Vrc-5074 (Nile 4) builtin UART.
2311          */
2312         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2314                 pbn_nec_nile4 },
2315
2316         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2318                 pbn_b3_2_115200 },
2319         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2321                 pbn_b3_4_115200 },
2322         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2324                 pbn_b3_8_115200 },
2325
2326         /*
2327          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2328          */
2329         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2330                 PCI_ANY_ID, PCI_ANY_ID,
2331                 0,
2332                 0, pbn_exar_XR17C152 },
2333         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2334                 PCI_ANY_ID, PCI_ANY_ID,
2335                 0,
2336                 0, pbn_exar_XR17C154 },
2337         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2338                 PCI_ANY_ID, PCI_ANY_ID,
2339                 0,
2340                 0, pbn_exar_XR17C158 },
2341
2342         /*
2343          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2344          */
2345         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2347                 pbn_b0_1_115200 },
2348
2349         /*
2350          * IntaShield IS-200
2351          */
2352         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2354                 pbn_b2_2_115200 },
2355
2356         /*
2357          * These entries match devices with class COMMUNICATION_SERIAL,
2358          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2359          */
2360         {       PCI_ANY_ID, PCI_ANY_ID,
2361                 PCI_ANY_ID, PCI_ANY_ID,
2362                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2363                 0xffff00, pbn_default },
2364         {       PCI_ANY_ID, PCI_ANY_ID,
2365                 PCI_ANY_ID, PCI_ANY_ID,
2366                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2367                 0xffff00, pbn_default },
2368         {       PCI_ANY_ID, PCI_ANY_ID,
2369                 PCI_ANY_ID, PCI_ANY_ID,
2370                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2371                 0xffff00, pbn_default },
2372         { 0, }
2373 };
2374
2375 static struct pci_driver serial_pci_driver = {
2376         .name           = "serial",
2377         .probe          = pciserial_init_one,
2378         .remove         = __devexit_p(pciserial_remove_one),
2379         .suspend        = pciserial_suspend_one,
2380         .resume         = pciserial_resume_one,
2381         .id_table       = serial_pci_tbl,
2382 };
2383
2384 static int __init serial8250_pci_init(void)
2385 {
2386         return pci_register_driver(&serial_pci_driver);
2387 }
2388
2389 static void __exit serial8250_pci_exit(void)
2390 {
2391         pci_unregister_driver(&serial_pci_driver);
2392 }
2393
2394 module_init(serial8250_pci_init);
2395 module_exit(serial8250_pci_exit);
2396
2397 MODULE_LICENSE("GPL");
2398 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2399 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);