drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/tty.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/8250_pci.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/byteorder.h>
  29 #include <asm/io.h>
  30
  31 #include "8250.h"
  32
  33 #undef SERIAL_DEBUG_PCI
  34
  35 /*
  36  * init function returns:
  37  *  > 0 - number of ports
  38  *  = 0 - use board->num_ports
  39  *  < 0 - error
  40  */
  41 struct pci_serial_quirk {
  42         u32     vendor;
  43         u32     device;
  44         u32     subvendor;
  45         u32     subdevice;
  46         int     (*init)(struct pci_dev *dev);
  47         int     (*setup)(struct serial_private *, struct pciserial_board *,
  48                          struct uart_port *, int);
  49         void    (*exit)(struct pci_dev *dev);
  50 };
  51
  52 #define PCI_NUM_BAR_RESOURCES   6
  53
  54 struct serial_private {
  55         struct pci_dev          *dev;
  56         unsigned int            nr;
  57         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  58         struct pci_serial_quirk *quirk;
  59         int                     line[0];
  60 };
  61
  62 static void moan_device(const char *str, struct pci_dev *dev)
  63 {
  64         printk(KERN_WARNING "%s: %s\n"
  65                KERN_WARNING "Please send the output of lspci -vv, this\n"
  66                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                KERN_WARNING "manufacturer and name of serial board or\n"
  68                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * AFAVLAB uses a different mixture of BARs and offsets
 110  * Not that ugly ;) -- HW
 111  */
 112 static int
 113 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 114               struct uart_port *port, int idx)
 115 {
 116         unsigned int bar, offset = board->first_offset;
 117
 118         bar = FL_GET_BASE(board->flags);
 119         if (idx < 4)
 120                 bar += idx;
 121         else {
 122                 bar = 4;
 123                 offset += (idx - 4) * board->uart_offset;
 124         }
 125
 126         return setup_port(priv, port, bar, offset, board->reg_shift);
 127 }
 128
 129 /*
 130  * HP's Remote Management Console.  The Diva chip came in several
 131  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 132  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 133  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 134  * one Diva chip, but it has been expanded to 5 UARTs.
 135  */
 136 static int pci_hp_diva_init(struct pci_dev *dev)
 137 {
 138         int rc = 0;
 139
 140         switch (dev->subsystem_device) {
 141         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 142         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 143         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 144         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 145                 rc = 3;
 146                 break;
 147         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 148                 rc = 2;
 149                 break;
 150         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 151                 rc = 4;
 152                 break;
 153         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 154         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 155                 rc = 1;
 156                 break;
 157         }
 158
 159         return rc;
 160 }
 161
 162 /*
 163  * HP's Diva chip puts the 4th/5th serial port further out, and
 164  * some serial ports are supposed to be hidden on certain models.
 165  */
 166 static int
 167 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 168               struct uart_port *port, int idx)
 169 {
 170         unsigned int offset = board->first_offset;
 171         unsigned int bar = FL_GET_BASE(board->flags);
 172
 173         switch (priv->dev->subsystem_device) {
 174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                 if (idx == 3)
 176                         idx++;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 179                 if (idx > 0)
 180                         idx++;
 181                 if (idx > 2)
 182                         idx++;
 183                 break;
 184         }
 185         if (idx > 2)
 186                 offset = 0x18;
 187
 188         offset += idx * board->uart_offset;
 189
 190         return setup_port(priv, port, bar, offset, board->reg_shift);
 191 }
 192
 193 /*
 194  * Added for EKF Intel i960 serial boards
 195  */
 196 static int pci_inteli960ni_init(struct pci_dev *dev)
 197 {
 198         unsigned long oldval;
 199
 200         if (!(dev->subsystem_device & 0x1000))
 201                 return -ENODEV;
 202
 203         /* is firmware started? */
 204         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 205         if (oldval == 0x00001000L) { /* RESET value */
 206                 printk(KERN_DEBUG "Local i960 firmware missing");
 207                 return -ENODEV;
 208         }
 209         return 0;
 210 }
 211
 212 /*
 213  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 214  * that the card interrupt be explicitly enabled or disabled.  This
 215  * seems to be mainly needed on card using the PLX which also use I/O
 216  * mapped memory.
 217  */
 218 static int pci_plx9050_init(struct pci_dev *dev)
 219 {
 220         u8 irq_config;
 221         void __iomem *p;
 222
 223         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 224                 moan_device("no memory in bar 0", dev);
 225                 return 0;
 226         }
 227
 228         irq_config = 0x41;
 229         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 230             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 231                 irq_config = 0x43;
 232         }
 233         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 234             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 235                 /*
 236                  * As the megawolf cards have the int pins active
 237                  * high, and have 2 UART chips, both ints must be
 238                  * enabled on the 9050. Also, the UARTS are set in
 239                  * 16450 mode by default, so we have to enable the
 240                  * 16C950 'enhanced' mode so that we can use the
 241                  * deep FIFOs
 242                  */
 243                 irq_config = 0x5b;
 244         }
 245
 246         /*
 247          * enable/disable interrupts
 248          */
 249         p = ioremap(pci_resource_start(dev, 0), 0x80);
 250         if (p == NULL)
 251                 return -ENOMEM;
 252         writel(irq_config, p + 0x4c);
 253
 254         /*
 255          * Read the register back to ensure that it took effect.
 256          */
 257         readl(p + 0x4c);
 258         iounmap(p);
 259
 260         return 0;
 261 }
 262
 263 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 264 {
 265         u8 __iomem *p;
 266
 267         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 268                 return;
 269
 270         /*
 271          * disable interrupts
 272          */
 273         p = ioremap(pci_resource_start(dev, 0), 0x80);
 274         if (p != NULL) {
 275                 writel(0, p + 0x4c);
 276
 277                 /*
 278                  * Read the register back to ensure that it took effect.
 279                  */
 280                 readl(p + 0x4c);
 281                 iounmap(p);
 282         }
 283 }
 284
 285 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 286 static int
 287 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 288                 struct uart_port *port, int idx)
 289 {
 290         unsigned int bar, offset = board->first_offset;
 291
 292         bar = 0;
 293
 294         if (idx < 4) {
 295                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 296                 offset += idx * board->uart_offset;
 297         } else if (idx < 8) {
 298                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 299                 offset += idx * board->uart_offset + 0xC00;
 300         } else /* we have only 8 ports on PMC-OCTALPRO */
 301                 return 1;
 302
 303         return setup_port(priv, port, bar, offset, board->reg_shift);
 304 }
 305
 306 /*
 307 * This does initialization for PMC OCTALPRO cards:
 308 * maps the device memory, resets the UARTs (needed, bc
 309 * if the module is removed and inserted again, the card
 310 * is in the sleep mode) and enables global interrupt.
 311 */
 312
 313 /* global control register offset for SBS PMC-OctalPro */
 314 #define OCT_REG_CR_OFF          0x500
 315
 316 static int sbs_init(struct pci_dev *dev)
 317 {
 318         u8 __iomem *p;
 319
 320         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 321
 322         if (p == NULL)
 323                 return -ENOMEM;
 324         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 325         writeb(0x10,p + OCT_REG_CR_OFF);
 326         udelay(50);
 327         writeb(0x0,p + OCT_REG_CR_OFF);
 328
 329         /* Set bit-2 (INTENABLE) of Control Register */
 330         writeb(0x4, p + OCT_REG_CR_OFF);
 331         iounmap(p);
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * Disables the global interrupt of PMC-OctalPro
 338  */
 339
 340 static void __devexit sbs_exit(struct pci_dev *dev)
 341 {
 342         u8 __iomem *p;
 343
 344         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 345         if (p != NULL) {
 346                 writeb(0, p + OCT_REG_CR_OFF);
 347         }
 348         iounmap(p);
 349 }
 350
 351 /*
 352  * SIIG serial cards have an PCI interface chip which also controls
 353  * the UART clocking frequency. Each UART can be clocked independently
 354  * (except cards equiped with 4 UARTs) and initial clocking settings
 355  * are stored in the EEPROM chip. It can cause problems because this
 356  * version of serial driver doesn't support differently clocked UART's
 357  * on single PCI card. To prevent this, initialization functions set
 358  * high frequency clocking for all UART's on given card. It is safe (I
 359  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 360  * with other OSes (like M$ DOS).
 361  *
 362  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 363  *
 364  * There is two family of SIIG serial cards with different PCI
 365  * interface chip and different configuration methods:
 366  *     - 10x cards have control registers in IO and/or memory space;
 367  *     - 20x cards have control registers in standard PCI configuration space.
 368  *
 369  * Note: all 10x cards have PCI device ids 0x10..
 370  *       all 20x cards have PCI device ids 0x20..
 371  *
 372  * There are also Quartet Serial cards which use Oxford Semiconductor
 373  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 374  *
 375  * Note: some SIIG cards are probed by the parport_serial object.
 376  */
 377
 378 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 379 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 380
 381 static int pci_siig10x_init(struct pci_dev *dev)
 382 {
 383         u16 data;
 384         void __iomem *p;
 385
 386         switch (dev->device & 0xfff8) {
 387         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 388                 data = 0xffdf;
 389                 break;
 390         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 391                 data = 0xf7ff;
 392                 break;
 393         default:                        /* 1S1P, 4S */
 394                 data = 0xfffb;
 395                 break;
 396         }
 397
 398         p = ioremap(pci_resource_start(dev, 0), 0x80);
 399         if (p == NULL)
 400                 return -ENOMEM;
 401
 402         writew(readw(p + 0x28) & data, p + 0x28);
 403         readw(p + 0x28);
 404         iounmap(p);
 405         return 0;
 406 }
 407
 408 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 409 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 410
 411 static int pci_siig20x_init(struct pci_dev *dev)
 412 {
 413         u8 data;
 414
 415         /* Change clock frequency for the first UART. */
 416         pci_read_config_byte(dev, 0x6f, &data);
 417         pci_write_config_byte(dev, 0x6f, data & 0xef);
 418
 419         /* If this card has 2 UART, we have to do the same with second UART. */
 420         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 421             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 422                 pci_read_config_byte(dev, 0x73, &data);
 423                 pci_write_config_byte(dev, 0x73, data & 0xef);
 424         }
 425         return 0;
 426 }
 427
 428 static int pci_siig_init(struct pci_dev *dev)
 429 {
 430         unsigned int type = dev->device & 0xff00;
 431
 432         if (type == 0x1000)
 433                 return pci_siig10x_init(dev);
 434         else if (type == 0x2000)
 435                 return pci_siig20x_init(dev);
 436
 437         moan_device("Unknown SIIG card", dev);
 438         return -ENODEV;
 439 }
 440
 441 static int pci_siig_setup(struct serial_private *priv,
 442                           struct pciserial_board *board,
 443                           struct uart_port *port, int idx)
 444 {
 445         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 446
 447         if (idx > 3) {
 448                 bar = 4;
 449                 offset = (idx - 4) * 8;
 450         }
 451
 452         return setup_port(priv, port, bar, offset, 0);
 453 }
 454
 455 /*
 456  * Timedia has an explosion of boards, and to avoid the PCI table from
 457  * growing *huge*, we use this function to collapse some 70 entries
 458  * in the PCI table into one, for sanity's and compactness's sake.
 459  */
 460 static const unsigned short timedia_single_port[] = {
 461         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 462 };
 463
 464 static const unsigned short timedia_dual_port[] = {
 465         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 466         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 467         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 468         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 469         0xD079, 0
 470 };
 471
 472 static const unsigned short timedia_quad_port[] = {
 473         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 474         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 475         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 476         0xB157, 0
 477 };
 478
 479 static const unsigned short timedia_eight_port[] = {
 480         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 481         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 482 };
 483
 484 static const struct timedia_struct {
 485         int num;
 486         const unsigned short *ids;
 487 } timedia_data[] = {
 488         { 1, timedia_single_port },
 489         { 2, timedia_dual_port },
 490         { 4, timedia_quad_port },
 491         { 8, timedia_eight_port }
 492 };
 493
 494 static int pci_timedia_init(struct pci_dev *dev)
 495 {
 496         const unsigned short *ids;
 497         int i, j;
 498
 499         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 500                 ids = timedia_data[i].ids;
 501                 for (j = 0; ids[j]; j++)
 502                         if (dev->subsystem_device == ids[j])
 503                                 return timedia_data[i].num;
 504         }
 505         return 0;
 506 }
 507
 508 /*
 509  * Timedia/SUNIX uses a mixture of BARs and offsets
 510  * Ugh, this is ugly as all hell --- TYT
 511  */
 512 static int
 513 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 514                   struct uart_port *port, int idx)
 515 {
 516         unsigned int bar = 0, offset = board->first_offset;
 517
 518         switch (idx) {
 519         case 0:
 520                 bar = 0;
 521                 break;
 522         case 1:
 523                 offset = board->uart_offset;
 524                 bar = 0;
 525                 break;
 526         case 2:
 527                 bar = 1;
 528                 break;
 529         case 3:
 530                 offset = board->uart_offset;
 531                 /* FALLTHROUGH */
 532         case 4: /* BAR 2 */
 533         case 5: /* BAR 3 */
 534         case 6: /* BAR 4 */
 535         case 7: /* BAR 5 */
 536                 bar = idx - 2;
 537         }
 538
 539         return setup_port(priv, port, bar, offset, board->reg_shift);
 540 }
 541
 542 /*
 543  * Some Titan cards are also a little weird
 544  */
 545 static int
 546 titan_400l_800l_setup(struct serial_private *priv,
 547                       struct pciserial_board *board,
 548                       struct uart_port *port, int idx)
 549 {
 550         unsigned int bar, offset = board->first_offset;
 551
 552         switch (idx) {
 553         case 0:
 554                 bar = 1;
 555                 break;
 556         case 1:
 557                 bar = 2;
 558                 break;
 559         default:
 560                 bar = 4;
 561                 offset = (idx - 2) * board->uart_offset;
 562         }
 563
 564         return setup_port(priv, port, bar, offset, board->reg_shift);
 565 }
 566
 567 static int pci_xircom_init(struct pci_dev *dev)
 568 {
 569         msleep(100);
 570         return 0;
 571 }
 572
 573 static int pci_netmos_init(struct pci_dev *dev)
 574 {
 575         /* subdevice 0x00PS means <P> parallel, <S> serial */
 576         unsigned int num_serial = dev->subsystem_device & 0xf;
 577
 578         if (num_serial == 0)
 579                 return -ENODEV;
 580         return num_serial;
 581 }
 582
 583 static int
 584 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 585                   struct uart_port *port, int idx)
 586 {
 587         unsigned int bar, offset = board->first_offset, maxnr;
 588
 589         bar = FL_GET_BASE(board->flags);
 590         if (board->flags & FL_BASE_BARS)
 591                 bar += idx;
 592         else
 593                 offset += idx * board->uart_offset;
 594
 595         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 596                 (board->reg_shift + 3);
 597
 598         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 599                 return 1;
 600
 601         return setup_port(priv, port, bar, offset, board->reg_shift);
 602 }
 603
 604 /* This should be in linux/pci_ids.h */
 605 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 606 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 607 #define PCI_DEVICE_ID_OCTPRO            0x0001
 608 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 609 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 610 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 611 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 612
 613 /*
 614  * Master list of serial port init/setup/exit quirks.
 615  * This does not describe the general nature of the port.
 616  * (ie, baud base, number and location of ports, etc)
 617  *
 618  * This list is ordered alphabetically by vendor then device.
 619  * Specific entries must come before more generic entries.
 620  */
 621 static struct pci_serial_quirk pci_serial_quirks[] = {
 622         /*
 623          * AFAVLAB cards - these may be called via parport_serial
 624          *  It is not clear whether this applies to all products.
 625          */
 626         {
 627                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 628                 .device         = PCI_ANY_ID,
 629                 .subvendor      = PCI_ANY_ID,
 630                 .subdevice      = PCI_ANY_ID,
 631                 .setup          = afavlab_setup,
 632         },
 633         /*
 634          * HP Diva
 635          */
 636         {
 637                 .vendor         = PCI_VENDOR_ID_HP,
 638                 .device         = PCI_DEVICE_ID_HP_DIVA,
 639                 .subvendor      = PCI_ANY_ID,
 640                 .subdevice      = PCI_ANY_ID,
 641                 .init           = pci_hp_diva_init,
 642                 .setup          = pci_hp_diva_setup,
 643         },
 644         /*
 645          * Intel
 646          */
 647         {
 648                 .vendor         = PCI_VENDOR_ID_INTEL,
 649                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 650                 .subvendor      = 0xe4bf,
 651                 .subdevice      = PCI_ANY_ID,
 652                 .init           = pci_inteli960ni_init,
 653                 .setup          = pci_default_setup,
 654         },
 655         /*
 656          * Panacom
 657          */
 658         {
 659                 .vendor         = PCI_VENDOR_ID_PANACOM,
 660                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 661                 .subvendor      = PCI_ANY_ID,
 662                 .subdevice      = PCI_ANY_ID,
 663                 .init           = pci_plx9050_init,
 664                 .setup          = pci_default_setup,
 665                 .exit           = __devexit_p(pci_plx9050_exit),
 666         },
 667         {
 668                 .vendor         = PCI_VENDOR_ID_PANACOM,
 669                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 670                 .subvendor      = PCI_ANY_ID,
 671                 .subdevice      = PCI_ANY_ID,
 672                 .init           = pci_plx9050_init,
 673                 .setup          = pci_default_setup,
 674                 .exit           = __devexit_p(pci_plx9050_exit),
 675         },
 676         /*
 677          * PLX
 678          */
 679         {
 680                 .vendor         = PCI_VENDOR_ID_PLX,
 681                 .device         = PCI_DEVICE_ID_PLX_9030,
 682                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 683                 .subdevice      = PCI_ANY_ID,
 684                 .setup          = pci_default_setup,
 685         },
 686         {
 687                 .vendor         = PCI_VENDOR_ID_PLX,
 688                 .device         = PCI_DEVICE_ID_PLX_9050,
 689                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 690                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 691                 .init           = pci_plx9050_init,
 692                 .setup          = pci_default_setup,
 693                 .exit           = __devexit_p(pci_plx9050_exit),
 694         },
 695         {
 696                 .vendor         = PCI_VENDOR_ID_PLX,
 697                 .device         = PCI_DEVICE_ID_PLX_9050,
 698                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 699                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 700                 .init           = pci_plx9050_init,
 701                 .setup          = pci_default_setup,
 702                 .exit           = __devexit_p(pci_plx9050_exit),
 703         },
 704         {
 705                 .vendor         = PCI_VENDOR_ID_PLX,
 706                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 707                 .subvendor      = PCI_VENDOR_ID_PLX,
 708                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 709                 .init           = pci_plx9050_init,
 710                 .setup          = pci_default_setup,
 711                 .exit           = __devexit_p(pci_plx9050_exit),
 712         },
 713         /*
 714          * SBS Technologies, Inc., PMC-OCTALPRO 232
 715          */
 716         {
 717                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 718                 .device         = PCI_DEVICE_ID_OCTPRO,
 719                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 720                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 721                 .init           = sbs_init,
 722                 .setup          = sbs_setup,
 723                 .exit           = __devexit_p(sbs_exit),
 724         },
 725         /*
 726          * SBS Technologies, Inc., PMC-OCTALPRO 422
 727          */
 728         {
 729                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 730                 .device         = PCI_DEVICE_ID_OCTPRO,
 731                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 732                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 733                 .init           = sbs_init,
 734                 .setup          = sbs_setup,
 735                 .exit           = __devexit_p(sbs_exit),
 736         },
 737         /*
 738          * SBS Technologies, Inc., P-Octal 232
 739          */
 740         {
 741                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 742                 .device         = PCI_DEVICE_ID_OCTPRO,
 743                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 744                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 745                 .init           = sbs_init,
 746                 .setup          = sbs_setup,
 747                 .exit           = __devexit_p(sbs_exit),
 748         },
 749         /*
 750          * SBS Technologies, Inc., P-Octal 422
 751          */
 752         {
 753                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 754                 .device         = PCI_DEVICE_ID_OCTPRO,
 755                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 756                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 757                 .init           = sbs_init,
 758                 .setup          = sbs_setup,
 759                 .exit           = __devexit_p(sbs_exit),
 760         },
 761         /*
 762          * SIIG cards - these may be called via parport_serial
 763          */
 764         {
 765                 .vendor         = PCI_VENDOR_ID_SIIG,
 766                 .device         = PCI_ANY_ID,
 767                 .subvendor      = PCI_ANY_ID,
 768                 .subdevice      = PCI_ANY_ID,
 769                 .init           = pci_siig_init,
 770                 .setup          = pci_siig_setup,
 771         },
 772         /*
 773          * Titan cards
 774          */
 775         {
 776                 .vendor         = PCI_VENDOR_ID_TITAN,
 777                 .device         = PCI_DEVICE_ID_TITAN_400L,
 778                 .subvendor      = PCI_ANY_ID,
 779                 .subdevice      = PCI_ANY_ID,
 780                 .setup          = titan_400l_800l_setup,
 781         },
 782         {
 783                 .vendor         = PCI_VENDOR_ID_TITAN,
 784                 .device         = PCI_DEVICE_ID_TITAN_800L,
 785                 .subvendor      = PCI_ANY_ID,
 786                 .subdevice      = PCI_ANY_ID,
 787                 .setup          = titan_400l_800l_setup,
 788         },
 789         /*
 790          * Timedia cards
 791          */
 792         {
 793                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 794                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 795                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 796                 .subdevice      = PCI_ANY_ID,
 797                 .init           = pci_timedia_init,
 798                 .setup          = pci_timedia_setup,
 799         },
 800         {
 801                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 802                 .device         = PCI_ANY_ID,
 803                 .subvendor      = PCI_ANY_ID,
 804                 .subdevice      = PCI_ANY_ID,
 805                 .setup          = pci_timedia_setup,
 806         },
 807         /*
 808          * Xircom cards
 809          */
 810         {
 811                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 812                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 813                 .subvendor      = PCI_ANY_ID,
 814                 .subdevice      = PCI_ANY_ID,
 815                 .init           = pci_xircom_init,
 816                 .setup          = pci_default_setup,
 817         },
 818         /*
 819          * Netmos cards - these may be called via parport_serial
 820          */
 821         {
 822                 .vendor         = PCI_VENDOR_ID_NETMOS,
 823                 .device         = PCI_ANY_ID,
 824                 .subvendor      = PCI_ANY_ID,
 825                 .subdevice      = PCI_ANY_ID,
 826                 .init           = pci_netmos_init,
 827                 .setup          = pci_default_setup,
 828         },
 829         /*
 830          * Default "match everything" terminator entry
 831          */
 832         {
 833                 .vendor         = PCI_ANY_ID,
 834                 .device         = PCI_ANY_ID,
 835                 .subvendor      = PCI_ANY_ID,
 836                 .subdevice      = PCI_ANY_ID,
 837                 .setup          = pci_default_setup,
 838         }
 839 };
 840
 841 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 842 {
 843         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 844 }
 845
 846 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 847 {
 848         struct pci_serial_quirk *quirk;
 849
 850         for (quirk = pci_serial_quirks; ; quirk++)
 851                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 852                     quirk_id_matches(quirk->device, dev->device) &&
 853                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 854                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 855                         break;
 856         return quirk;
 857 }
 858
 859 static inline int get_pci_irq(struct pci_dev *dev,
 860                                 struct pciserial_board *board)
 861 {
 862         if (board->flags & FL_NOIRQ)
 863                 return 0;
 864         else
 865                 return dev->irq;
 866 }
 867
 868 /*
 869  * This is the configuration table for all of the PCI serial boards
 870  * which we support.  It is directly indexed by the pci_board_num_t enum
 871  * value, which is encoded in the pci_device_id PCI probe table's
 872  * driver_data member.
 873  *
 874  * The makeup of these names are:
 875  *  pbn_bn{_bt}_n_baud{_offsetinhex}
 876  *
 877  *  bn          = PCI BAR number
 878  *  bt          = Index using PCI BARs
 879  *  n           = number of serial ports
 880  *  baud        = baud rate
 881  *  offsetinhex = offset for each sequential port (in hex)
 882  *
 883  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
 884  *
 885  * Please note: in theory if n = 1, _bt infix should make no difference.
 886  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 887  */
 888 enum pci_board_num_t {
 889         pbn_default = 0,
 890
 891         pbn_b0_1_115200,
 892         pbn_b0_2_115200,
 893         pbn_b0_4_115200,
 894         pbn_b0_5_115200,
 895
 896         pbn_b0_1_921600,
 897         pbn_b0_2_921600,
 898         pbn_b0_4_921600,
 899
 900         pbn_b0_2_1130000,
 901
 902         pbn_b0_4_1152000,
 903
 904         pbn_b0_2_1843200,
 905         pbn_b0_4_1843200,
 906
 907         pbn_b0_2_1843200_200,
 908         pbn_b0_4_1843200_200,
 909         pbn_b0_8_1843200_200,
 910
 911         pbn_b0_bt_1_115200,
 912         pbn_b0_bt_2_115200,
 913         pbn_b0_bt_8_115200,
 914
 915         pbn_b0_bt_1_460800,
 916         pbn_b0_bt_2_460800,
 917         pbn_b0_bt_4_460800,
 918
 919         pbn_b0_bt_1_921600,
 920         pbn_b0_bt_2_921600,
 921         pbn_b0_bt_4_921600,
 922         pbn_b0_bt_8_921600,
 923
 924         pbn_b1_1_115200,
 925         pbn_b1_2_115200,
 926         pbn_b1_4_115200,
 927         pbn_b1_8_115200,
 928
 929         pbn_b1_1_921600,
 930         pbn_b1_2_921600,
 931         pbn_b1_4_921600,
 932         pbn_b1_8_921600,
 933
 934         pbn_b1_2_1250000,
 935
 936         pbn_b1_bt_2_921600,
 937
 938         pbn_b1_1_1382400,
 939         pbn_b1_2_1382400,
 940         pbn_b1_4_1382400,
 941         pbn_b1_8_1382400,
 942
 943         pbn_b2_1_115200,
 944         pbn_b2_2_115200,
 945         pbn_b2_4_115200,
 946         pbn_b2_8_115200,
 947
 948         pbn_b2_1_460800,
 949         pbn_b2_4_460800,
 950         pbn_b2_8_460800,
 951         pbn_b2_16_460800,
 952
 953         pbn_b2_1_921600,
 954         pbn_b2_4_921600,
 955         pbn_b2_8_921600,
 956
 957         pbn_b2_bt_1_115200,
 958         pbn_b2_bt_2_115200,
 959         pbn_b2_bt_4_115200,
 960
 961         pbn_b2_bt_2_921600,
 962         pbn_b2_bt_4_921600,
 963
 964         pbn_b3_2_115200,
 965         pbn_b3_4_115200,
 966         pbn_b3_8_115200,
 967
 968         /*
 969          * Board-specific versions.
 970          */
 971         pbn_panacom,
 972         pbn_panacom2,
 973         pbn_panacom4,
 974         pbn_exsys_4055,
 975         pbn_plx_romulus,
 976         pbn_oxsemi,
 977         pbn_intel_i960,
 978         pbn_sgi_ioc3,
 979         pbn_nec_nile4,
 980         pbn_computone_4,
 981         pbn_computone_6,
 982         pbn_computone_8,
 983         pbn_sbsxrsio,
 984         pbn_exar_XR17C152,
 985         pbn_exar_XR17C154,
 986         pbn_exar_XR17C158,
 987 };
 988
 989 /*
 990  * uart_offset - the space between channels
 991  * reg_shift   - describes how the UART registers are mapped
 992  *               to PCI memory by the card.
 993  * For example IER register on SBS, Inc. PMC-OctPro is located at
 994  * offset 0x10 from the UART base, while UART_IER is defined as 1
 995  * in include/linux/serial_reg.h,
 996  * see first lines of serial_in() and serial_out() in 8250.c
 997 */
 998
 999 static struct pciserial_board pci_boards[] __devinitdata = {
1000         [pbn_default] = {
1001                 .flags          = FL_BASE0,
1002                 .num_ports      = 1,
1003                 .base_baud      = 115200,
1004                 .uart_offset    = 8,
1005         },
1006         [pbn_b0_1_115200] = {
1007                 .flags          = FL_BASE0,
1008                 .num_ports      = 1,
1009                 .base_baud      = 115200,
1010                 .uart_offset    = 8,
1011         },
1012         [pbn_b0_2_115200] = {
1013                 .flags          = FL_BASE0,
1014                 .num_ports      = 2,
1015                 .base_baud      = 115200,
1016                 .uart_offset    = 8,
1017         },
1018         [pbn_b0_4_115200] = {
1019                 .flags          = FL_BASE0,
1020                 .num_ports      = 4,
1021                 .base_baud      = 115200,
1022                 .uart_offset    = 8,
1023         },
1024         [pbn_b0_5_115200] = {
1025                 .flags          = FL_BASE0,
1026                 .num_ports      = 5,
1027                 .base_baud      = 115200,
1028                 .uart_offset    = 8,
1029         },
1030
1031         [pbn_b0_1_921600] = {
1032                 .flags          = FL_BASE0,
1033                 .num_ports      = 1,
1034                 .base_baud      = 921600,
1035                 .uart_offset    = 8,
1036         },
1037         [pbn_b0_2_921600] = {
1038                 .flags          = FL_BASE0,
1039                 .num_ports      = 2,
1040                 .base_baud      = 921600,
1041                 .uart_offset    = 8,
1042         },
1043         [pbn_b0_4_921600] = {
1044                 .flags          = FL_BASE0,
1045                 .num_ports      = 4,
1046                 .base_baud      = 921600,
1047                 .uart_offset    = 8,
1048         },
1049
1050         [pbn_b0_2_1130000] = {
1051                 .flags          = FL_BASE0,
1052                 .num_ports      = 2,
1053                 .base_baud      = 1130000,
1054                 .uart_offset    = 8,
1055         },
1056
1057         [pbn_b0_4_1152000] = {
1058                 .flags          = FL_BASE0,
1059                 .num_ports      = 4,
1060                 .base_baud      = 1152000,
1061                 .uart_offset    = 8,
1062         },
1063
1064         [pbn_b0_2_1843200] = {
1065                 .flags          = FL_BASE0,
1066                 .num_ports      = 2,
1067                 .base_baud      = 1843200,
1068                 .uart_offset    = 8,
1069         },
1070         [pbn_b0_4_1843200] = {
1071                 .flags          = FL_BASE0,
1072                 .num_ports      = 4,
1073                 .base_baud      = 1843200,
1074                 .uart_offset    = 8,
1075         },
1076
1077         [pbn_b0_2_1843200_200] = {
1078                 .flags          = FL_BASE0,
1079                 .num_ports      = 2,
1080                 .base_baud      = 1843200,
1081                 .uart_offset    = 0x200,
1082         },
1083         [pbn_b0_4_1843200_200] = {
1084                 .flags          = FL_BASE0,
1085                 .num_ports      = 4,
1086                 .base_baud      = 1843200,
1087                 .uart_offset    = 0x200,
1088         },
1089         [pbn_b0_8_1843200_200] = {
1090                 .flags          = FL_BASE0,
1091                 .num_ports      = 8,
1092                 .base_baud      = 1843200,
1093                 .uart_offset    = 0x200,
1094         },
1095
1096         [pbn_b0_bt_1_115200] = {
1097                 .flags          = FL_BASE0|FL_BASE_BARS,
1098                 .num_ports      = 1,
1099                 .base_baud      = 115200,
1100                 .uart_offset    = 8,
1101         },
1102         [pbn_b0_bt_2_115200] = {
1103                 .flags          = FL_BASE0|FL_BASE_BARS,
1104                 .num_ports      = 2,
1105                 .base_baud      = 115200,
1106                 .uart_offset    = 8,
1107         },
1108         [pbn_b0_bt_8_115200] = {
1109                 .flags          = FL_BASE0|FL_BASE_BARS,
1110                 .num_ports      = 8,
1111                 .base_baud      = 115200,
1112                 .uart_offset    = 8,
1113         },
1114
1115         [pbn_b0_bt_1_460800] = {
1116                 .flags          = FL_BASE0|FL_BASE_BARS,
1117                 .num_ports      = 1,
1118                 .base_baud      = 460800,
1119                 .uart_offset    = 8,
1120         },
1121         [pbn_b0_bt_2_460800] = {
1122                 .flags          = FL_BASE0|FL_BASE_BARS,
1123                 .num_ports      = 2,
1124                 .base_baud      = 460800,
1125                 .uart_offset    = 8,
1126         },
1127         [pbn_b0_bt_4_460800] = {
1128                 .flags          = FL_BASE0|FL_BASE_BARS,
1129                 .num_ports      = 4,
1130                 .base_baud      = 460800,
1131                 .uart_offset    = 8,
1132         },
1133
1134         [pbn_b0_bt_1_921600] = {
1135                 .flags          = FL_BASE0|FL_BASE_BARS,
1136                 .num_ports      = 1,
1137                 .base_baud      = 921600,
1138                 .uart_offset    = 8,
1139         },
1140         [pbn_b0_bt_2_921600] = {
1141                 .flags          = FL_BASE0|FL_BASE_BARS,
1142                 .num_ports      = 2,
1143                 .base_baud      = 921600,
1144                 .uart_offset    = 8,
1145         },
1146         [pbn_b0_bt_4_921600] = {
1147                 .flags          = FL_BASE0|FL_BASE_BARS,
1148                 .num_ports      = 4,
1149                 .base_baud      = 921600,
1150                 .uart_offset    = 8,
1151         },
1152         [pbn_b0_bt_8_921600] = {
1153                 .flags          = FL_BASE0|FL_BASE_BARS,
1154                 .num_ports      = 8,
1155                 .base_baud      = 921600,
1156                 .uart_offset    = 8,
1157         },
1158
1159         [pbn_b1_1_115200] = {
1160                 .flags          = FL_BASE1,
1161                 .num_ports      = 1,
1162                 .base_baud      = 115200,
1163                 .uart_offset    = 8,
1164         },
1165         [pbn_b1_2_115200] = {
1166                 .flags          = FL_BASE1,
1167                 .num_ports      = 2,
1168                 .base_baud      = 115200,
1169                 .uart_offset    = 8,
1170         },
1171         [pbn_b1_4_115200] = {
1172                 .flags          = FL_BASE1,
1173                 .num_ports      = 4,
1174                 .base_baud      = 115200,
1175                 .uart_offset    = 8,
1176         },
1177         [pbn_b1_8_115200] = {
1178                 .flags          = FL_BASE1,
1179                 .num_ports      = 8,
1180                 .base_baud      = 115200,
1181                 .uart_offset    = 8,
1182         },
1183
1184         [pbn_b1_1_921600] = {
1185                 .flags          = FL_BASE1,
1186                 .num_ports      = 1,
1187                 .base_baud      = 921600,
1188                 .uart_offset    = 8,
1189         },
1190         [pbn_b1_2_921600] = {
1191                 .flags          = FL_BASE1,
1192                 .num_ports      = 2,
1193                 .base_baud      = 921600,
1194                 .uart_offset    = 8,
1195         },
1196         [pbn_b1_4_921600] = {
1197                 .flags          = FL_BASE1,
1198                 .num_ports      = 4,
1199                 .base_baud      = 921600,
1200                 .uart_offset    = 8,
1201         },
1202         [pbn_b1_8_921600] = {
1203                 .flags          = FL_BASE1,
1204                 .num_ports      = 8,
1205                 .base_baud      = 921600,
1206                 .uart_offset    = 8,
1207         },
1208         [pbn_b1_2_1250000] = {
1209                 .flags          = FL_BASE1,
1210                 .num_ports      = 2,
1211                 .base_baud      = 1250000,
1212                 .uart_offset    = 8,
1213         },
1214
1215         [pbn_b1_bt_2_921600] = {
1216                 .flags          = FL_BASE1|FL_BASE_BARS,
1217                 .num_ports      = 2,
1218                 .base_baud      = 921600,
1219                 .uart_offset    = 8,
1220         },
1221
1222         [pbn_b1_1_1382400] = {
1223                 .flags          = FL_BASE1,
1224                 .num_ports      = 1,
1225                 .base_baud      = 1382400,
1226                 .uart_offset    = 8,
1227         },
1228         [pbn_b1_2_1382400] = {
1229                 .flags          = FL_BASE1,
1230                 .num_ports      = 2,
1231                 .base_baud      = 1382400,
1232                 .uart_offset    = 8,
1233         },
1234         [pbn_b1_4_1382400] = {
1235                 .flags          = FL_BASE1,
1236                 .num_ports      = 4,
1237                 .base_baud      = 1382400,
1238                 .uart_offset    = 8,
1239         },
1240         [pbn_b1_8_1382400] = {
1241                 .flags          = FL_BASE1,
1242                 .num_ports      = 8,
1243                 .base_baud      = 1382400,
1244                 .uart_offset    = 8,
1245         },
1246
1247         [pbn_b2_1_115200] = {
1248                 .flags          = FL_BASE2,
1249                 .num_ports      = 1,
1250                 .base_baud      = 115200,
1251                 .uart_offset    = 8,
1252         },
1253         [pbn_b2_2_115200] = {
1254                 .flags          = FL_BASE2,
1255                 .num_ports      = 2,
1256                 .base_baud      = 115200,
1257                 .uart_offset    = 8,
1258         },
1259         [pbn_b2_4_115200] = {
1260                 .flags          = FL_BASE2,
1261                 .num_ports      = 4,
1262                 .base_baud      = 115200,
1263                 .uart_offset    = 8,
1264         },
1265         [pbn_b2_8_115200] = {
1266                 .flags          = FL_BASE2,
1267                 .num_ports      = 8,
1268                 .base_baud      = 115200,
1269                 .uart_offset    = 8,
1270         },
1271
1272         [pbn_b2_1_460800] = {
1273                 .flags          = FL_BASE2,
1274                 .num_ports      = 1,
1275                 .base_baud      = 460800,
1276                 .uart_offset    = 8,
1277         },
1278         [pbn_b2_4_460800] = {
1279                 .flags          = FL_BASE2,
1280                 .num_ports      = 4,
1281                 .base_baud      = 460800,
1282                 .uart_offset    = 8,
1283         },
1284         [pbn_b2_8_460800] = {
1285                 .flags          = FL_BASE2,
1286                 .num_ports      = 8,
1287                 .base_baud      = 460800,
1288                 .uart_offset    = 8,
1289         },
1290         [pbn_b2_16_460800] = {
1291                 .flags          = FL_BASE2,
1292                 .num_ports      = 16,
1293                 .base_baud      = 460800,
1294                 .uart_offset    = 8,
1295          },
1296
1297         [pbn_b2_1_921600] = {
1298                 .flags          = FL_BASE2,
1299                 .num_ports      = 1,
1300                 .base_baud      = 921600,
1301                 .uart_offset    = 8,
1302         },
1303         [pbn_b2_4_921600] = {
1304                 .flags          = FL_BASE2,
1305                 .num_ports      = 4,
1306                 .base_baud      = 921600,
1307                 .uart_offset    = 8,
1308         },
1309         [pbn_b2_8_921600] = {
1310                 .flags          = FL_BASE2,
1311                 .num_ports      = 8,
1312                 .base_baud      = 921600,
1313                 .uart_offset    = 8,
1314         },
1315
1316         [pbn_b2_bt_1_115200] = {
1317                 .flags          = FL_BASE2|FL_BASE_BARS,
1318                 .num_ports      = 1,
1319                 .base_baud      = 115200,
1320                 .uart_offset    = 8,
1321         },
1322         [pbn_b2_bt_2_115200] = {
1323                 .flags          = FL_BASE2|FL_BASE_BARS,
1324                 .num_ports      = 2,
1325                 .base_baud      = 115200,
1326                 .uart_offset    = 8,
1327         },
1328         [pbn_b2_bt_4_115200] = {
1329                 .flags          = FL_BASE2|FL_BASE_BARS,
1330                 .num_ports      = 4,
1331                 .base_baud      = 115200,
1332                 .uart_offset    = 8,
1333         },
1334
1335         [pbn_b2_bt_2_921600] = {
1336                 .flags          = FL_BASE2|FL_BASE_BARS,
1337                 .num_ports      = 2,
1338                 .base_baud      = 921600,
1339                 .uart_offset    = 8,
1340         },
1341         [pbn_b2_bt_4_921600] = {
1342                 .flags          = FL_BASE2|FL_BASE_BARS,
1343                 .num_ports      = 4,
1344                 .base_baud      = 921600,
1345                 .uart_offset    = 8,
1346         },
1347
1348         [pbn_b3_2_115200] = {
1349                 .flags          = FL_BASE3,
1350                 .num_ports      = 2,
1351                 .base_baud      = 115200,
1352                 .uart_offset    = 8,
1353         },
1354         [pbn_b3_4_115200] = {
1355                 .flags          = FL_BASE3,
1356                 .num_ports      = 4,
1357                 .base_baud      = 115200,
1358                 .uart_offset    = 8,
1359         },
1360         [pbn_b3_8_115200] = {
1361                 .flags          = FL_BASE3,
1362                 .num_ports      = 8,
1363                 .base_baud      = 115200,
1364                 .uart_offset    = 8,
1365         },
1366
1367         /*
1368          * Entries following this are board-specific.
1369          */
1370
1371         /*
1372          * Panacom - IOMEM
1373          */
1374         [pbn_panacom] = {
1375                 .flags          = FL_BASE2,
1376                 .num_ports      = 2,
1377                 .base_baud      = 921600,
1378                 .uart_offset    = 0x400,
1379                 .reg_shift      = 7,
1380         },
1381         [pbn_panacom2] = {
1382                 .flags          = FL_BASE2|FL_BASE_BARS,
1383                 .num_ports      = 2,
1384                 .base_baud      = 921600,
1385                 .uart_offset    = 0x400,
1386                 .reg_shift      = 7,
1387         },
1388         [pbn_panacom4] = {
1389                 .flags          = FL_BASE2|FL_BASE_BARS,
1390                 .num_ports      = 4,
1391                 .base_baud      = 921600,
1392                 .uart_offset    = 0x400,
1393                 .reg_shift      = 7,
1394         },
1395
1396         [pbn_exsys_4055] = {
1397                 .flags          = FL_BASE2,
1398                 .num_ports      = 4,
1399                 .base_baud      = 115200,
1400                 .uart_offset    = 8,
1401         },
1402
1403         /* I think this entry is broken - the first_offset looks wrong --rmk */
1404         [pbn_plx_romulus] = {
1405                 .flags          = FL_BASE2,
1406                 .num_ports      = 4,
1407                 .base_baud      = 921600,
1408                 .uart_offset    = 8 << 2,
1409                 .reg_shift      = 2,
1410                 .first_offset   = 0x03,
1411         },
1412
1413         /*
1414          * This board uses the size of PCI Base region 0 to
1415          * signal now many ports are available
1416          */
1417         [pbn_oxsemi] = {
1418                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1419                 .num_ports      = 32,
1420                 .base_baud      = 115200,
1421                 .uart_offset    = 8,
1422         },
1423
1424         /*
1425          * EKF addition for i960 Boards form EKF with serial port.
1426          * Max 256 ports.
1427          */
1428         [pbn_intel_i960] = {
1429                 .flags          = FL_BASE0,
1430                 .num_ports      = 32,
1431                 .base_baud      = 921600,
1432                 .uart_offset    = 8 << 2,
1433                 .reg_shift      = 2,
1434                 .first_offset   = 0x10000,
1435         },
1436         [pbn_sgi_ioc3] = {
1437                 .flags          = FL_BASE0|FL_NOIRQ,
1438                 .num_ports      = 1,
1439                 .base_baud      = 458333,
1440                 .uart_offset    = 8,
1441                 .reg_shift      = 0,
1442                 .first_offset   = 0x20178,
1443         },
1444
1445         /*
1446          * NEC Vrc-5074 (Nile 4) builtin UART.
1447          */
1448         [pbn_nec_nile4] = {
1449                 .flags          = FL_BASE0,
1450                 .num_ports      = 1,
1451                 .base_baud      = 520833,
1452                 .uart_offset    = 8 << 3,
1453                 .reg_shift      = 3,
1454                 .first_offset   = 0x300,
1455         },
1456
1457         /*
1458          * Computone - uses IOMEM.
1459          */
1460         [pbn_computone_4] = {
1461                 .flags          = FL_BASE0,
1462                 .num_ports      = 4,
1463                 .base_baud      = 921600,
1464                 .uart_offset    = 0x40,
1465                 .reg_shift      = 2,
1466                 .first_offset   = 0x200,
1467         },
1468         [pbn_computone_6] = {
1469                 .flags          = FL_BASE0,
1470                 .num_ports      = 6,
1471                 .base_baud      = 921600,
1472                 .uart_offset    = 0x40,
1473                 .reg_shift      = 2,
1474                 .first_offset   = 0x200,
1475         },
1476         [pbn_computone_8] = {
1477                 .flags          = FL_BASE0,
1478                 .num_ports      = 8,
1479                 .base_baud      = 921600,
1480                 .uart_offset    = 0x40,
1481                 .reg_shift      = 2,
1482                 .first_offset   = 0x200,
1483         },
1484         [pbn_sbsxrsio] = {
1485                 .flags          = FL_BASE0,
1486                 .num_ports      = 8,
1487                 .base_baud      = 460800,
1488                 .uart_offset    = 256,
1489                 .reg_shift      = 4,
1490         },
1491         /*
1492          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1493          *  Only basic 16550A support.
1494          *  XR17C15[24] are not tested, but they should work.
1495          */
1496         [pbn_exar_XR17C152] = {
1497                 .flags          = FL_BASE0,
1498                 .num_ports      = 2,
1499                 .base_baud      = 921600,
1500                 .uart_offset    = 0x200,
1501         },
1502         [pbn_exar_XR17C154] = {
1503                 .flags          = FL_BASE0,
1504                 .num_ports      = 4,
1505                 .base_baud      = 921600,
1506                 .uart_offset    = 0x200,
1507         },
1508         [pbn_exar_XR17C158] = {
1509                 .flags          = FL_BASE0,
1510                 .num_ports      = 8,
1511                 .base_baud      = 921600,
1512                 .uart_offset    = 0x200,
1513         },
1514 };
1515
1516 /*
1517  * Given a complete unknown PCI device, try to use some heuristics to
1518  * guess what the configuration might be, based on the pitiful PCI
1519  * serial specs.  Returns 0 on success, 1 on failure.
1520  */
1521 static int __devinit
1522 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1523 {
1524         int num_iomem, num_port, first_port = -1, i;
1525
1526         /*
1527          * If it is not a communications device or the programming
1528          * interface is greater than 6, give up.
1529          *
1530          * (Should we try to make guesses for multiport serial devices
1531          * later?)
1532          */
1533         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1534              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1535             (dev->class & 0xff) > 6)
1536                 return -ENODEV;
1537
1538         num_iomem = num_port = 0;
1539         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1540                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1541                         num_port++;
1542                         if (first_port == -1)
1543                                 first_port = i;
1544                 }
1545                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1546                         num_iomem++;
1547         }
1548
1549         /*
1550          * If there is 1 or 0 iomem regions, and exactly one port,
1551          * use it.  We guess the number of ports based on the IO
1552          * region size.
1553          */
1554         if (num_iomem <= 1 && num_port == 1) {
1555                 board->flags = first_port;
1556                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1557                 return 0;
1558         }
1559
1560         /*
1561          * Now guess if we've got a board which indexes by BARs.
1562          * Each IO BAR should be 8 bytes, and they should follow
1563          * consecutively.
1564          */
1565         first_port = -1;
1566         num_port = 0;
1567         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1568                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1569                     pci_resource_len(dev, i) == 8 &&
1570                     (first_port == -1 || (first_port + num_port) == i)) {
1571                         num_port++;
1572                         if (first_port == -1)
1573                                 first_port = i;
1574                 }
1575         }
1576
1577         if (num_port > 1) {
1578                 board->flags = first_port | FL_BASE_BARS;
1579                 board->num_ports = num_port;
1580                 return 0;
1581         }
1582
1583         return -ENODEV;
1584 }
1585
1586 static inline int
1587 serial_pci_matches(struct pciserial_board *board,
1588                    struct pciserial_board *guessed)
1589 {
1590         return
1591             board->num_ports == guessed->num_ports &&
1592             board->base_baud == guessed->base_baud &&
1593             board->uart_offset == guessed->uart_offset &&
1594             board->reg_shift == guessed->reg_shift &&
1595             board->first_offset == guessed->first_offset;
1596 }
1597
1598 struct serial_private *
1599 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1600 {
1601         struct uart_port serial_port;
1602         struct serial_private *priv;
1603         struct pci_serial_quirk *quirk;
1604         int rc, nr_ports, i;
1605
1606         nr_ports = board->num_ports;
1607
1608         /*
1609          * Find an init and setup quirks.
1610          */
1611         quirk = find_quirk(dev);
1612
1613         /*
1614          * Run the new-style initialization function.
1615          * The initialization function returns:
1616          *  <0  - error
1617          *   0  - use board->num_ports
1618          *  >0  - number of ports
1619          */
1620         if (quirk->init) {
1621                 rc = quirk->init(dev);
1622                 if (rc < 0) {
1623                         priv = ERR_PTR(rc);
1624                         goto err_out;
1625                 }
1626                 if (rc)
1627                         nr_ports = rc;
1628         }
1629
1630         priv = kzalloc(sizeof(struct serial_private) +
1631                        sizeof(unsigned int) * nr_ports,
1632                        GFP_KERNEL);
1633         if (!priv) {
1634                 priv = ERR_PTR(-ENOMEM);
1635                 goto err_deinit;
1636         }
1637
1638         priv->dev = dev;
1639         priv->quirk = quirk;
1640
1641         memset(&serial_port, 0, sizeof(struct uart_port));
1642         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1643         serial_port.uartclk = board->base_baud * 16;
1644         serial_port.irq = get_pci_irq(dev, board);
1645         serial_port.dev = &dev->dev;
1646
1647         for (i = 0; i < nr_ports; i++) {
1648                 if (quirk->setup(priv, board, &serial_port, i))
1649                         break;
1650
1651 #ifdef SERIAL_DEBUG_PCI
1652                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1653                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1654 #endif
1655
1656                 priv->line[i] = serial8250_register_port(&serial_port);
1657                 if (priv->line[i] < 0) {
1658                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1659                         break;
1660                 }
1661         }
1662
1663         priv->nr = i;
1664
1665         return priv;
1666
1667  err_deinit:
1668         if (quirk->exit)
1669                 quirk->exit(dev);
1670  err_out:
1671         return priv;
1672 }
1673 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1674
1675 void pciserial_remove_ports(struct serial_private *priv)
1676 {
1677         struct pci_serial_quirk *quirk;
1678         int i;
1679
1680         for (i = 0; i < priv->nr; i++)
1681                 serial8250_unregister_port(priv->line[i]);
1682
1683         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1684                 if (priv->remapped_bar[i])
1685                         iounmap(priv->remapped_bar[i]);
1686                 priv->remapped_bar[i] = NULL;
1687         }
1688
1689         /*
1690          * Find the exit quirks.
1691          */
1692         quirk = find_quirk(priv->dev);
1693         if (quirk->exit)
1694                 quirk->exit(priv->dev);
1695
1696         kfree(priv);
1697 }
1698 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1699
1700 void pciserial_suspend_ports(struct serial_private *priv)
1701 {
1702         int i;
1703
1704         for (i = 0; i < priv->nr; i++)
1705                 if (priv->line[i] >= 0)
1706                         serial8250_suspend_port(priv->line[i]);
1707 }
1708 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1709
1710 void pciserial_resume_ports(struct serial_private *priv)
1711 {
1712         int i;
1713
1714         /*
1715          * Ensure that the board is correctly configured.
1716          */
1717         if (priv->quirk->init)
1718                 priv->quirk->init(priv->dev);
1719
1720         for (i = 0; i < priv->nr; i++)
1721                 if (priv->line[i] >= 0)
1722                         serial8250_resume_port(priv->line[i]);
1723 }
1724 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1725
1726 /*
1727  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1728  * to the arrangement of serial ports on a PCI card.
1729  */
1730 static int __devinit
1731 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1732 {
1733         struct serial_private *priv;
1734         struct pciserial_board *board, tmp;
1735         int rc;
1736
1737         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1738                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1739                         ent->driver_data);
1740                 return -EINVAL;
1741         }
1742
1743         board = &pci_boards[ent->driver_data];
1744
1745         rc = pci_enable_device(dev);
1746         if (rc)
1747                 return rc;
1748
1749         if (ent->driver_data == pbn_default) {
1750                 /*
1751                  * Use a copy of the pci_board entry for this;
1752                  * avoid changing entries in the table.
1753                  */
1754                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1755                 board = &tmp;
1756
1757                 /*
1758                  * We matched one of our class entries.  Try to
1759                  * determine the parameters of this board.
1760                  */
1761                 rc = serial_pci_guess_board(dev, board);
1762                 if (rc)
1763                         goto disable;
1764         } else {
1765                 /*
1766                  * We matched an explicit entry.  If we are able to
1767                  * detect this boards settings with our heuristic,
1768                  * then we no longer need this entry.
1769                  */
1770                 memcpy(&tmp, &pci_boards[pbn_default],
1771                        sizeof(struct pciserial_board));
1772                 rc = serial_pci_guess_board(dev, &tmp);
1773                 if (rc == 0 && serial_pci_matches(board, &tmp))
1774                         moan_device("Redundant entry in serial pci_table.",
1775                                     dev);
1776         }
1777
1778         priv = pciserial_init_ports(dev, board);
1779         if (!IS_ERR(priv)) {
1780                 pci_set_drvdata(dev, priv);
1781                 return 0;
1782         }
1783
1784         rc = PTR_ERR(priv);
1785
1786  disable:
1787         pci_disable_device(dev);
1788         return rc;
1789 }
1790
1791 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1792 {
1793         struct serial_private *priv = pci_get_drvdata(dev);
1794
1795         pci_set_drvdata(dev, NULL);
1796
1797         pciserial_remove_ports(priv);
1798
1799         pci_disable_device(dev);
1800 }
1801
1802 #ifdef CONFIG_PM
1803 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1804 {
1805         struct serial_private *priv = pci_get_drvdata(dev);
1806
1807         if (priv)
1808                 pciserial_suspend_ports(priv);
1809
1810         pci_save_state(dev);
1811         pci_set_power_state(dev, pci_choose_state(dev, state));
1812         return 0;
1813 }
1814
1815 static int pciserial_resume_one(struct pci_dev *dev)
1816 {
1817         struct serial_private *priv = pci_get_drvdata(dev);
1818
1819         pci_set_power_state(dev, PCI_D0);
1820         pci_restore_state(dev);
1821
1822         if (priv) {
1823                 /*
1824                  * The device may have been disabled.  Re-enable it.
1825                  */
1826                 pci_enable_device(dev);
1827
1828                 pciserial_resume_ports(priv);
1829         }
1830         return 0;
1831 }
1832 #endif
1833
1834 static struct pci_device_id serial_pci_tbl[] = {
1835         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1836                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1837                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1838                 pbn_b1_8_1382400 },
1839         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1840                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1841                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1842                 pbn_b1_4_1382400 },
1843         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1844                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1845                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1846                 pbn_b1_2_1382400 },
1847         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1848                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1849                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1850                 pbn_b1_8_1382400 },
1851         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1852                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1853                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1854                 pbn_b1_4_1382400 },
1855         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1856                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1857                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1858                 pbn_b1_2_1382400 },
1859         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1860                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1861                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1862                 pbn_b1_8_921600 },
1863         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1864                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1865                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1866                 pbn_b1_8_921600 },
1867         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1868                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1869                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1870                 pbn_b1_4_921600 },
1871         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1872                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1873                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1874                 pbn_b1_4_921600 },
1875         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1876                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1877                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1878                 pbn_b1_2_921600 },
1879         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1880                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1881                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1882                 pbn_b1_8_921600 },
1883         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1884                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1885                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1886                 pbn_b1_8_921600 },
1887         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1888                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1889                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1890                 pbn_b1_4_921600 },
1891         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1892                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1893                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1894                 pbn_b1_2_1250000 },
1895         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1896                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1897                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1898                 pbn_b0_2_1843200 },
1899         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1900                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1901                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1902                 pbn_b0_4_1843200 },
1903         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1904                 PCI_VENDOR_ID_AFAVLAB,
1905                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1906                 pbn_b0_4_1152000 },
1907         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1908                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1909                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1910                 pbn_b0_2_1843200_200 },
1911         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1912                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1913                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1914                 pbn_b0_4_1843200_200 },
1915         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1916                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1917                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1918                 pbn_b0_8_1843200_200 },
1919         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1920                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1921                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1922                 pbn_b0_2_1843200_200 },
1923         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1924                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1925                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1926                 pbn_b0_4_1843200_200 },
1927         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1928                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1929                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1930                 pbn_b0_8_1843200_200 },
1931         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1932                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1933                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1934                 pbn_b0_2_1843200_200 },
1935         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1936                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1937                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1938                 pbn_b0_4_1843200_200 },
1939         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1940                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1941                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1942                 pbn_b0_8_1843200_200 },
1943         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1944                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1945                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1946                 pbn_b0_2_1843200_200 },
1947         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1948                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1949                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1950                 pbn_b0_4_1843200_200 },
1951         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1952                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1953                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1954                 pbn_b0_8_1843200_200 },
1955
1956         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958                 pbn_b2_bt_1_115200 },
1959         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961                 pbn_b2_bt_2_115200 },
1962         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964                 pbn_b2_bt_4_115200 },
1965         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967                 pbn_b2_bt_2_115200 },
1968         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970                 pbn_b2_bt_4_115200 },
1971         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973                 pbn_b2_8_115200 },
1974         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976                 pbn_b2_8_115200 },
1977
1978         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1979                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980                 pbn_b2_bt_2_115200 },
1981         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1982                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983                 pbn_b2_bt_2_921600 },
1984         /*
1985          * VScom SPCOM800, from sl@s.pl
1986          */
1987         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1988                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989                 pbn_b2_8_921600 },
1990         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1991                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992                 pbn_b2_4_921600 },
1993         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1994                 PCI_SUBVENDOR_ID_KEYSPAN,
1995                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1996                 pbn_panacom },
1997         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1999                 pbn_panacom4 },
2000         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2002                 pbn_panacom2 },
2003         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2004                 PCI_VENDOR_ID_ESDGMBH,
2005                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2006                 pbn_b2_4_115200 },
2007         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2008                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2009                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2010                 pbn_b2_4_460800 },
2011         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2012                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2013                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2014                 pbn_b2_8_460800 },
2015         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2016                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2017                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2018                 pbn_b2_16_460800 },
2019         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2020                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2021                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2022                 pbn_b2_16_460800 },
2023         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2024                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2025                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2026                 pbn_b2_4_460800 },
2027         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2028                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2029                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2030                 pbn_b2_8_460800 },
2031         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2032                 PCI_SUBVENDOR_ID_EXSYS,
2033                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2034                 pbn_exsys_4055 },
2035         /*
2036          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2037          * (Exoray@isys.ca)
2038          */
2039         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2040                 0x10b5, 0x106a, 0, 0,
2041                 pbn_plx_romulus },
2042         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2044                 pbn_b1_4_115200 },
2045         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2047                 pbn_b1_2_115200 },
2048         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2050                 pbn_b1_8_115200 },
2051         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2053                 pbn_b1_8_115200 },
2054         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2055                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2056                 pbn_b0_4_921600 },
2057         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2058                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2059                 pbn_b0_4_1152000 },
2060
2061                 /*
2062                  * The below card is a little controversial since it is the
2063                  * subject of a PCI vendor/device ID clash.  (See
2064                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2065                  * For now just used the hex ID 0x950a.
2066                  */
2067         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2068                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2069                 pbn_b0_2_1130000 },
2070         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072                 pbn_b0_4_115200 },
2073         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2075                 pbn_b0_bt_2_921600 },
2076
2077         /*
2078          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2079          * from skokodyn@yahoo.com
2080          */
2081         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2082                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2083                 pbn_sbsxrsio },
2084         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2085                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2086                 pbn_sbsxrsio },
2087         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2088                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2089                 pbn_sbsxrsio },
2090         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2091                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2092                 pbn_sbsxrsio },
2093
2094         /*
2095          * Digitan DS560-558, from jimd@esoft.com
2096          */
2097         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2099                 pbn_b1_1_115200 },
2100
2101         /*
2102          * Titan Electronic cards
2103          *  The 400L and 800L have a custom setup quirk.
2104          */
2105         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107                 pbn_b0_1_921600 },
2108         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b0_2_921600 },
2111         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113                 pbn_b0_4_921600 },
2114         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116                 pbn_b0_4_921600 },
2117         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2119                 pbn_b1_1_921600 },
2120         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2121                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2122                 pbn_b1_bt_2_921600 },
2123         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125                 pbn_b0_bt_4_921600 },
2126         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128                 pbn_b0_bt_8_921600 },
2129
2130         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2132                 pbn_b2_1_460800 },
2133         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2135                 pbn_b2_1_460800 },
2136         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2138                 pbn_b2_1_460800 },
2139         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141                 pbn_b2_bt_2_921600 },
2142         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144                 pbn_b2_bt_2_921600 },
2145         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2147                 pbn_b2_bt_2_921600 },
2148         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2149                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2150                 pbn_b2_bt_4_921600 },
2151         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2152                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153                 pbn_b2_bt_4_921600 },
2154         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2155                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2156                 pbn_b2_bt_4_921600 },
2157         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2158                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159                 pbn_b0_1_921600 },
2160         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2161                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162                 pbn_b0_1_921600 },
2163         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2164                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165                 pbn_b0_1_921600 },
2166         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2167                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168                 pbn_b0_bt_2_921600 },
2169         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2170                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171                 pbn_b0_bt_2_921600 },
2172         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2173                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2174                 pbn_b0_bt_2_921600 },
2175         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177                 pbn_b0_bt_4_921600 },
2178         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2180                 pbn_b0_bt_4_921600 },
2181         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2182                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2183                 pbn_b0_bt_4_921600 },
2184         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2185                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2186                 pbn_b0_bt_8_921600 },
2187         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189                 pbn_b0_bt_8_921600 },
2190         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192                 pbn_b0_bt_8_921600 },
2193
2194         /*
2195          * Computone devices submitted by Doug McNash dmcnash@computone.com
2196          */
2197         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2198                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2199                 0, 0, pbn_computone_4 },
2200         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2201                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2202                 0, 0, pbn_computone_8 },
2203         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2204                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2205                 0, 0, pbn_computone_6 },
2206
2207         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209                 pbn_oxsemi },
2210         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2211                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2212                 pbn_b0_bt_1_921600 },
2213
2214         /*
2215          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2216          */
2217         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219                 pbn_b0_bt_8_115200 },
2220         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2222                 pbn_b0_bt_8_115200 },
2223
2224         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2226                 pbn_b0_bt_2_115200 },
2227         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2229                 pbn_b0_bt_2_115200 },
2230         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2232                 pbn_b0_bt_2_115200 },
2233         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2235                 pbn_b0_bt_4_460800 },
2236         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2238                 pbn_b0_bt_4_460800 },
2239         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2241                 pbn_b0_bt_2_460800 },
2242         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2244                 pbn_b0_bt_2_460800 },
2245         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2247                 pbn_b0_bt_2_460800 },
2248         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2250                 pbn_b0_bt_1_115200 },
2251         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2253                 pbn_b0_bt_1_460800 },
2254
2255         /*
2256          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2257          * Cards are identified by their subsystem vendor IDs, which
2258          * (in hex) match the model number.
2259          *
2260          * Note that JC140x are RS422/485 cards which require ox950
2261          * ACR = 0x10, and as such are not currently fully supported.
2262          */
2263         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2264                 0x1204, 0x0004, 0, 0,
2265                 pbn_b0_4_921600 },
2266         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2267                 0x1208, 0x0004, 0, 0,
2268                 pbn_b0_4_921600 },
2269 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2270                 0x1402, 0x0002, 0, 0,
2271                 pbn_b0_2_921600 }, */
2272 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2273                 0x1404, 0x0004, 0, 0,
2274                 pbn_b0_4_921600 }, */
2275         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2276                 0x1208, 0x0004, 0, 0,
2277                 pbn_b0_4_921600 },
2278
2279         /*
2280          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2281          */
2282         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284                 pbn_b1_1_1382400 },
2285
2286         /*
2287          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2288          */
2289         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291                 pbn_b1_1_1382400 },
2292
2293         /*
2294          * RAStel 2 port modem, gerg@moreton.com.au
2295          */
2296         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2298                 pbn_b2_bt_2_115200 },
2299
2300         /*
2301          * EKF addition for i960 Boards form EKF with serial port
2302          */
2303         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2304                 0xE4BF, PCI_ANY_ID, 0, 0,
2305                 pbn_intel_i960 },
2306
2307         /*
2308          * Xircom Cardbus/Ethernet combos
2309          */
2310         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2312                 pbn_b0_1_115200 },
2313         /*
2314          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2315          */
2316         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2318                 pbn_b0_1_115200 },
2319
2320         /*
2321          * Untested PCI modems, sent in from various folks...
2322          */
2323
2324         /*
2325          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2326          */
2327         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2328                 0x1048, 0x1500, 0, 0,
2329                 pbn_b1_1_115200 },
2330
2331         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2332                 0xFF00, 0, 0, 0,
2333                 pbn_sgi_ioc3 },
2334
2335         /*
2336          * HP Diva card
2337          */
2338         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2339                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2340                 pbn_b1_1_115200 },
2341         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2343                 pbn_b0_5_115200 },
2344         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2346                 pbn_b2_1_115200 },
2347
2348         /*
2349          * NEC Vrc-5074 (Nile 4) builtin UART.
2350          */
2351         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2353                 pbn_nec_nile4 },
2354
2355         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2357                 pbn_b3_2_115200 },
2358         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2359                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2360                 pbn_b3_4_115200 },
2361         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2362                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2363                 pbn_b3_8_115200 },
2364
2365         /*
2366          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2367          */
2368         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2369                 PCI_ANY_ID, PCI_ANY_ID,
2370                 0,
2371                 0, pbn_exar_XR17C152 },
2372         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2373                 PCI_ANY_ID, PCI_ANY_ID,
2374                 0,
2375                 0, pbn_exar_XR17C154 },
2376         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2377                 PCI_ANY_ID, PCI_ANY_ID,
2378                 0,
2379                 0, pbn_exar_XR17C158 },
2380
2381         /*
2382          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2383          */
2384         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2385                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2386                 pbn_b0_1_115200 },
2387
2388         /*
2389          * IntaShield IS-200
2390          */
2391         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2393                 pbn_b2_2_115200 },
2394
2395         /*
2396          * Perle PCI-RAS cards
2397          */
2398         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2399                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2400                 0, 0, pbn_b2_4_921600 },
2401         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2402                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2403                 0, 0, pbn_b2_8_921600 },
2404         /*
2405          * These entries match devices with class COMMUNICATION_SERIAL,
2406          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2407          */
2408         {       PCI_ANY_ID, PCI_ANY_ID,
2409                 PCI_ANY_ID, PCI_ANY_ID,
2410                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2411                 0xffff00, pbn_default },
2412         {       PCI_ANY_ID, PCI_ANY_ID,
2413                 PCI_ANY_ID, PCI_ANY_ID,
2414                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2415                 0xffff00, pbn_default },
2416         {       PCI_ANY_ID, PCI_ANY_ID,
2417                 PCI_ANY_ID, PCI_ANY_ID,
2418                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2419                 0xffff00, pbn_default },
2420         { 0, }
2421 };
2422
2423 static struct pci_driver serial_pci_driver = {
2424         .name           = "serial",
2425         .probe          = pciserial_init_one,
2426         .remove         = __devexit_p(pciserial_remove_one),
2427 #ifdef CONFIG_PM
2428         .suspend        = pciserial_suspend_one,
2429         .resume         = pciserial_resume_one,
2430 #endif
2431         .id_table       = serial_pci_tbl,
2432 };
2433
2434 static int __init serial8250_pci_init(void)
2435 {
2436         return pci_register_driver(&serial_pci_driver);
2437 }
2438
2439 static void __exit serial8250_pci_exit(void)
2440 {
2441         pci_unregister_driver(&serial_pci_driver);
2442 }
2443
2444 module_init(serial8250_pci_init);
2445 module_exit(serial8250_pci_exit);
2446
2447 MODULE_LICENSE("GPL");
2448 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2449 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);