drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35 #include <scsi/scsi_dbg.h>
  36 #include <scsi/scsi_eh.h>
  37
  38 #define DRV_NAME "stex"
  39 #define ST_DRIVER_VERSION "4.6.0000.4"
  40 #define ST_VER_MAJOR            4
  41 #define ST_VER_MINOR            6
  42 #define ST_OEM                  0
  43 #define ST_BUILD_VER            4
  44
  45 enum {
  46         /* MU register offset */
  47         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  48         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  49         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  50         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  51         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  52         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  53         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  54         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  55         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  56         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  57
  58         YIOA_STATUS                             = 0x00,
  59         YH2I_INT                                = 0x20,
  60         YINT_EN                                 = 0x34,
  61         YI2H_INT                                = 0x9c,
  62         YI2H_INT_C                              = 0xa0,
  63         YH2I_REQ                                = 0xc0,
  64         YH2I_REQ_HI                             = 0xc4,
  65
  66         /* MU register value */
  67         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  68         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  69         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  70         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  71         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  72
  73         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  74         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  75         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  76         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  77         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  78         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  79
  80         /* MU status code */
  81         MU_STATE_STARTING                       = 1,
  82         MU_STATE_STARTED                        = 2,
  83         MU_STATE_RESETTING                      = 3,
  84         MU_STATE_FAILED                         = 4,
  85
  86         MU_MAX_DELAY                            = 120,
  87         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  88         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  89         MU_HARD_RESET_WAIT                      = 30000,
  90         HMU_PARTNER_TYPE                        = 2,
  91
  92         /* firmware returned values */
  93         SRB_STATUS_SUCCESS                      = 0x01,
  94         SRB_STATUS_ERROR                        = 0x04,
  95         SRB_STATUS_BUSY                         = 0x05,
  96         SRB_STATUS_INVALID_REQUEST              = 0x06,
  97         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  98         SRB_SEE_SENSE                           = 0x80,
  99
 100         /* task attribute */
 101         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 102         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 103         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 104         TASK_ATTRIBUTE_ACA                      = 0x4,
 105
 106         SS_STS_NORMAL                           = 0x80000000,
 107         SS_STS_DONE                             = 0x40000000,
 108         SS_STS_HANDSHAKE                        = 0x20000000,
 109
 110         SS_HEAD_HANDSHAKE                       = 0x80,
 111
 112         SS_H2I_INT_RESET                        = 0x100,
 113
 114         SS_I2H_REQUEST_RESET                    = 0x2000,
 115
 116         SS_MU_OPERATIONAL                       = 0x80000000,
 117
 118         STEX_CDB_LENGTH                         = 16,
 119         STATUS_VAR_LEN                          = 128,
 120
 121         /* sg flags */
 122         SG_CF_EOT                               = 0x80, /* end of table */
 123         SG_CF_64B                               = 0x40, /* 64 bit item */
 124         SG_CF_HOST                              = 0x20, /* sg in host memory */
 125         MSG_DATA_DIR_ND                         = 0,
 126         MSG_DATA_DIR_IN                         = 1,
 127         MSG_DATA_DIR_OUT                        = 2,
 128
 129         st_shasta                               = 0,
 130         st_vsc                                  = 1,
 131         st_yosemite                             = 2,
 132         st_seq                                  = 3,
 133         st_yel                                  = 4,
 134
 135         PASSTHRU_REQ_TYPE                       = 0x00000001,
 136         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 137         ST_INTERNAL_TIMEOUT                     = 180,
 138
 139         ST_TO_CMD                               = 0,
 140         ST_FROM_CMD                             = 1,
 141
 142         /* vendor specific commands of Promise */
 143         MGT_CMD                                 = 0xd8,
 144         SINBAND_MGT_CMD                         = 0xd9,
 145         ARRAY_CMD                               = 0xe0,
 146         CONTROLLER_CMD                          = 0xe1,
 147         DEBUGGING_CMD                           = 0xe2,
 148         PASSTHRU_CMD                            = 0xe3,
 149
 150         PASSTHRU_GET_ADAPTER                    = 0x05,
 151         PASSTHRU_GET_DRVVER                     = 0x10,
 152
 153         CTLR_CONFIG_CMD                         = 0x03,
 154         CTLR_SHUTDOWN                           = 0x0d,
 155
 156         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 157         CTLR_POWER_SAVING                       = 0x01,
 158
 159         PASSTHRU_SIGNATURE                      = 0x4e415041,
 160         MGT_CMD_SIGNATURE                       = 0xba,
 161
 162         INQUIRY_EVPD                            = 0x01,
 163
 164         ST_ADDITIONAL_MEM                       = 0x200000,
 165         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 166 };
 167
 168 struct st_sgitem {
 169         u8 ctrl;        /* SG_CF_xxx */
 170         u8 reserved[3];
 171         __le32 count;
 172         __le64 addr;
 173 };
 174
 175 struct st_ss_sgitem {
 176         __le32 addr;
 177         __le32 addr_hi;
 178         __le32 count;
 179 };
 180
 181 struct st_sgtable {
 182         __le16 sg_count;
 183         __le16 max_sg_count;
 184         __le32 sz_in_byte;
 185 };
 186
 187 struct st_msg_header {
 188         __le64 handle;
 189         u8 flag;
 190         u8 channel;
 191         __le16 timeout;
 192         u32 reserved;
 193 };
 194
 195 struct handshake_frame {
 196         __le64 rb_phy;          /* request payload queue physical address */
 197         __le16 req_sz;          /* size of each request payload */
 198         __le16 req_cnt;         /* count of reqs the buffer can hold */
 199         __le16 status_sz;       /* size of each status payload */
 200         __le16 status_cnt;      /* count of status the buffer can hold */
 201         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 202         u8 partner_type;        /* who sends this frame */
 203         u8 reserved0[7];
 204         __le32 partner_ver_major;
 205         __le32 partner_ver_minor;
 206         __le32 partner_ver_oem;
 207         __le32 partner_ver_build;
 208         __le32 extra_offset;    /* NEW */
 209         __le32 extra_size;      /* NEW */
 210         __le32 scratch_size;
 211         u32 reserved1;
 212 };
 213
 214 struct req_msg {
 215         __le16 tag;
 216         u8 lun;
 217         u8 target;
 218         u8 task_attr;
 219         u8 task_manage;
 220         u8 data_dir;
 221         u8 payload_sz;          /* payload size in 4-byte, not used */
 222         u8 cdb[STEX_CDB_LENGTH];
 223         u32 variable[0];
 224 };
 225
 226 struct status_msg {
 227         __le16 tag;
 228         u8 lun;
 229         u8 target;
 230         u8 srb_status;
 231         u8 scsi_status;
 232         u8 reserved;
 233         u8 payload_sz;          /* payload size in 4-byte */
 234         u8 variable[STATUS_VAR_LEN];
 235 };
 236
 237 struct ver_info {
 238         u32 major;
 239         u32 minor;
 240         u32 oem;
 241         u32 build;
 242         u32 reserved[2];
 243 };
 244
 245 struct st_frame {
 246         u32 base[6];
 247         u32 rom_addr;
 248
 249         struct ver_info drv_ver;
 250         struct ver_info bios_ver;
 251
 252         u32 bus;
 253         u32 slot;
 254         u32 irq_level;
 255         u32 irq_vec;
 256         u32 id;
 257         u32 subid;
 258
 259         u32 dimm_size;
 260         u8 dimm_type;
 261         u8 reserved[3];
 262
 263         u32 channel;
 264         u32 reserved1;
 265 };
 266
 267 struct st_drvver {
 268         u32 major;
 269         u32 minor;
 270         u32 oem;
 271         u32 build;
 272         u32 signature[2];
 273         u8 console_id;
 274         u8 host_no;
 275         u8 reserved0[2];
 276         u32 reserved[3];
 277 };
 278
 279 struct st_ccb {
 280         struct req_msg *req;
 281         struct scsi_cmnd *cmd;
 282
 283         void *sense_buffer;
 284         unsigned int sense_bufflen;
 285         int sg_count;
 286
 287         u32 req_type;
 288         u8 srb_status;
 289         u8 scsi_status;
 290         u8 reserved[2];
 291 };
 292
 293 struct st_hba {
 294         void __iomem *mmio_base;        /* iomapped PCI memory space */
 295         void *dma_mem;
 296         dma_addr_t dma_handle;
 297         size_t dma_size;
 298
 299         struct Scsi_Host *host;
 300         struct pci_dev *pdev;
 301
 302         struct req_msg * (*alloc_rq) (struct st_hba *);
 303         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 304         void (*send) (struct st_hba *, struct req_msg *, u16);
 305
 306         u32 req_head;
 307         u32 req_tail;
 308         u32 status_head;
 309         u32 status_tail;
 310
 311         struct status_msg *status_buffer;
 312         void *copy_buffer; /* temp buffer for driver-handled commands */
 313         struct st_ccb *ccb;
 314         struct st_ccb *wait_ccb;
 315         __le32 *scratch;
 316
 317         char work_q_name[20];
 318         struct workqueue_struct *work_q;
 319         struct work_struct reset_work;
 320         wait_queue_head_t reset_waitq;
 321         unsigned int mu_status;
 322         unsigned int cardtype;
 323         int msi_enabled;
 324         int out_req_cnt;
 325         u32 extra_offset;
 326         u16 rq_count;
 327         u16 rq_size;
 328         u16 sts_count;
 329 };
 330
 331 struct st_card_info {
 332         struct req_msg * (*alloc_rq) (struct st_hba *);
 333         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 334         void (*send) (struct st_hba *, struct req_msg *, u16);
 335         unsigned int max_id;
 336         unsigned int max_lun;
 337         unsigned int max_channel;
 338         u16 rq_count;
 339         u16 rq_size;
 340         u16 sts_count;
 341 };
 342
 343 static int msi;
 344 module_param(msi, int, 0);
 345 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 346
 347 static const char console_inq_page[] =
 348 {
 349         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 350         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 351         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 352         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 353         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 354         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 355         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 356         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 357 };
 358
 359 MODULE_AUTHOR("Ed Lin");
 360 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 361 MODULE_LICENSE("GPL");
 362 MODULE_VERSION(ST_DRIVER_VERSION);
 363
 364 static void stex_gettime(__le64 *time)
 365 {
 366         struct timeval tv;
 367
 368         do_gettimeofday(&tv);
 369         *time = cpu_to_le64(tv.tv_sec);
 370 }
 371
 372 static struct status_msg *stex_get_status(struct st_hba *hba)
 373 {
 374         struct status_msg *status = hba->status_buffer + hba->status_tail;
 375
 376         ++hba->status_tail;
 377         hba->status_tail %= hba->sts_count+1;
 378
 379         return status;
 380 }
 381
 382 static void stex_invalid_field(struct scsi_cmnd *cmd,
 383                                void (*done)(struct scsi_cmnd *))
 384 {
 385         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 386
 387         /* "Invalid field in cdb" */
 388         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 389                                 0x0);
 390         done(cmd);
 391 }
 392
 393 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 394 {
 395         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 396
 397         ++hba->req_head;
 398         hba->req_head %= hba->rq_count+1;
 399
 400         return req;
 401 }
 402
 403 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 404 {
 405         return (struct req_msg *)(hba->dma_mem +
 406                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 407 }
 408
 409 static int stex_map_sg(struct st_hba *hba,
 410         struct req_msg *req, struct st_ccb *ccb)
 411 {
 412         struct scsi_cmnd *cmd;
 413         struct scatterlist *sg;
 414         struct st_sgtable *dst;
 415         struct st_sgitem *table;
 416         int i, nseg;
 417
 418         cmd = ccb->cmd;
 419         nseg = scsi_dma_map(cmd);
 420         BUG_ON(nseg < 0);
 421         if (nseg) {
 422                 dst = (struct st_sgtable *)req->variable;
 423
 424                 ccb->sg_count = nseg;
 425                 dst->sg_count = cpu_to_le16((u16)nseg);
 426                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 427                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 428
 429                 table = (struct st_sgitem *)(dst + 1);
 430                 scsi_for_each_sg(cmd, sg, nseg, i) {
 431                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 432                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 433                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 434                 }
 435                 table[--i].ctrl |= SG_CF_EOT;
 436         }
 437
 438         return nseg;
 439 }
 440
 441 static int stex_ss_map_sg(struct st_hba *hba,
 442         struct req_msg *req, struct st_ccb *ccb)
 443 {
 444         struct scsi_cmnd *cmd;
 445         struct scatterlist *sg;
 446         struct st_sgtable *dst;
 447         struct st_ss_sgitem *table;
 448         int i, nseg;
 449
 450         cmd = ccb->cmd;
 451         nseg = scsi_dma_map(cmd);
 452         BUG_ON(nseg < 0);
 453         if (nseg) {
 454                 dst = (struct st_sgtable *)req->variable;
 455
 456                 ccb->sg_count = nseg;
 457                 dst->sg_count = cpu_to_le16((u16)nseg);
 458                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 459                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 460
 461                 table = (struct st_ss_sgitem *)(dst + 1);
 462                 scsi_for_each_sg(cmd, sg, nseg, i) {
 463                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 464                         table[i].addr =
 465                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 466                         table[i].addr_hi =
 467                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 468                 }
 469         }
 470
 471         return nseg;
 472 }
 473
 474 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 475 {
 476         struct st_frame *p;
 477         size_t count = sizeof(struct st_frame);
 478
 479         p = hba->copy_buffer;
 480         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 481         memset(p->base, 0, sizeof(u32)*6);
 482         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 483         p->rom_addr = 0;
 484
 485         p->drv_ver.major = ST_VER_MAJOR;
 486         p->drv_ver.minor = ST_VER_MINOR;
 487         p->drv_ver.oem = ST_OEM;
 488         p->drv_ver.build = ST_BUILD_VER;
 489
 490         p->bus = hba->pdev->bus->number;
 491         p->slot = hba->pdev->devfn;
 492         p->irq_level = 0;
 493         p->irq_vec = hba->pdev->irq;
 494         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 495         p->subid =
 496                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 497
 498         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 499 }
 500
 501 static void
 502 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 503 {
 504         req->tag = cpu_to_le16(tag);
 505
 506         hba->ccb[tag].req = req;
 507         hba->out_req_cnt++;
 508
 509         writel(hba->req_head, hba->mmio_base + IMR0);
 510         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 511         readl(hba->mmio_base + IDBL); /* flush */
 512 }
 513
 514 static void
 515 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 516 {
 517         struct scsi_cmnd *cmd;
 518         struct st_msg_header *msg_h;
 519         dma_addr_t addr;
 520
 521         req->tag = cpu_to_le16(tag);
 522
 523         hba->ccb[tag].req = req;
 524         hba->out_req_cnt++;
 525
 526         cmd = hba->ccb[tag].cmd;
 527         msg_h = (struct st_msg_header *)req - 1;
 528         if (likely(cmd)) {
 529                 msg_h->channel = (u8)cmd->device->channel;
 530                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 531         }
 532         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 533         addr += (hba->ccb[tag].sg_count+4)/11;
 534         msg_h->handle = cpu_to_le64(addr);
 535
 536         ++hba->req_head;
 537         hba->req_head %= hba->rq_count+1;
 538
 539         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 540         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 541         writel(addr, hba->mmio_base + YH2I_REQ);
 542         readl(hba->mmio_base + YH2I_REQ); /* flush */
 543 }
 544
 545 static int
 546 stex_slave_alloc(struct scsi_device *sdev)
 547 {
 548         /* Cheat: usually extracted from Inquiry data */
 549         sdev->tagged_supported = 1;
 550
 551         scsi_activate_tcq(sdev, sdev->host->can_queue);
 552
 553         return 0;
 554 }
 555
 556 static int
 557 stex_slave_config(struct scsi_device *sdev)
 558 {
 559         sdev->use_10_for_rw = 1;
 560         sdev->use_10_for_ms = 1;
 561         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 562         sdev->tagged_supported = 1;
 563
 564         return 0;
 565 }
 566
 567 static void
 568 stex_slave_destroy(struct scsi_device *sdev)
 569 {
 570         scsi_deactivate_tcq(sdev, 1);
 571 }
 572
 573 static int
 574 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 575 {
 576         struct st_hba *hba;
 577         struct Scsi_Host *host;
 578         unsigned int id, lun;
 579         struct req_msg *req;
 580         u16 tag;
 581
 582         host = cmd->device->host;
 583         id = cmd->device->id;
 584         lun = cmd->device->lun;
 585         hba = (struct st_hba *) &host->hostdata[0];
 586
 587         if (unlikely(hba->mu_status == MU_STATE_RESETTING))
 588                 return SCSI_MLQUEUE_HOST_BUSY;
 589
 590         switch (cmd->cmnd[0]) {
 591         case MODE_SENSE_10:
 592         {
 593                 static char ms10_caching_page[12] =
 594                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 595                 unsigned char page;
 596
 597                 page = cmd->cmnd[2] & 0x3f;
 598                 if (page == 0x8 || page == 0x3f) {
 599                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 600                                                  sizeof(ms10_caching_page));
 601                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 602                         done(cmd);
 603                 } else
 604                         stex_invalid_field(cmd, done);
 605                 return 0;
 606         }
 607         case REPORT_LUNS:
 608                 /*
 609                  * The shasta firmware does not report actual luns in the
 610                  * target, so fail the command to force sequential lun scan.
 611                  * Also, the console device does not support this command.
 612                  */
 613                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 614                         stex_invalid_field(cmd, done);
 615                         return 0;
 616                 }
 617                 break;
 618         case TEST_UNIT_READY:
 619                 if (id == host->max_id - 1) {
 620                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 621                         done(cmd);
 622                         return 0;
 623                 }
 624                 break;
 625         case INQUIRY:
 626                 if (lun >= host->max_lun) {
 627                         cmd->result = DID_NO_CONNECT << 16;
 628                         done(cmd);
 629                         return 0;
 630                 }
 631                 if (id != host->max_id - 1)
 632                         break;
 633                 if (!lun && !cmd->device->channel &&
 634                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 635                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 636                                                  sizeof(console_inq_page));
 637                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 638                         done(cmd);
 639                 } else
 640                         stex_invalid_field(cmd, done);
 641                 return 0;
 642         case PASSTHRU_CMD:
 643                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 644                         struct st_drvver ver;
 645                         size_t cp_len = sizeof(ver);
 646
 647                         ver.major = ST_VER_MAJOR;
 648                         ver.minor = ST_VER_MINOR;
 649                         ver.oem = ST_OEM;
 650                         ver.build = ST_BUILD_VER;
 651                         ver.signature[0] = PASSTHRU_SIGNATURE;
 652                         ver.console_id = host->max_id - 1;
 653                         ver.host_no = hba->host->host_no;
 654                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 655                         cmd->result = sizeof(ver) == cp_len ?
 656                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 657                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 658                         done(cmd);
 659                         return 0;
 660                 }
 661         default:
 662                 break;
 663         }
 664
 665         cmd->scsi_done = done;
 666
 667         tag = cmd->request->tag;
 668
 669         if (unlikely(tag >= host->can_queue))
 670                 return SCSI_MLQUEUE_HOST_BUSY;
 671
 672         req = hba->alloc_rq(hba);
 673
 674         req->lun = lun;
 675         req->target = id;
 676
 677         /* cdb */
 678         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 679
 680         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 681                 req->data_dir = MSG_DATA_DIR_IN;
 682         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 683                 req->data_dir = MSG_DATA_DIR_OUT;
 684         else
 685                 req->data_dir = MSG_DATA_DIR_ND;
 686
 687         hba->ccb[tag].cmd = cmd;
 688         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 689         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 690
 691         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 692                 hba->ccb[tag].sg_count = 0;
 693                 memset(&req->variable[0], 0, 8);
 694         }
 695
 696         hba->send(hba, req, tag);
 697         return 0;
 698 }
 699
 700 static void stex_scsi_done(struct st_ccb *ccb)
 701 {
 702         struct scsi_cmnd *cmd = ccb->cmd;
 703         int result;
 704
 705         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 706                 result = ccb->scsi_status;
 707                 switch (ccb->scsi_status) {
 708                 case SAM_STAT_GOOD:
 709                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 710                         break;
 711                 case SAM_STAT_CHECK_CONDITION:
 712                         result |= DRIVER_SENSE << 24;
 713                         break;
 714                 case SAM_STAT_BUSY:
 715                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 716                         break;
 717                 default:
 718                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 719                         break;
 720                 }
 721         }
 722         else if (ccb->srb_status & SRB_SEE_SENSE)
 723                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 724         else switch (ccb->srb_status) {
 725                 case SRB_STATUS_SELECTION_TIMEOUT:
 726                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 727                         break;
 728                 case SRB_STATUS_BUSY:
 729                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 730                         break;
 731                 case SRB_STATUS_INVALID_REQUEST:
 732                 case SRB_STATUS_ERROR:
 733                 default:
 734                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 735                         break;
 736         }
 737
 738         cmd->result = result;
 739         cmd->scsi_done(cmd);
 740 }
 741
 742 static void stex_copy_data(struct st_ccb *ccb,
 743         struct status_msg *resp, unsigned int variable)
 744 {
 745         if (resp->scsi_status != SAM_STAT_GOOD) {
 746                 if (ccb->sense_buffer != NULL)
 747                         memcpy(ccb->sense_buffer, resp->variable,
 748                                 min(variable, ccb->sense_bufflen));
 749                 return;
 750         }
 751
 752         if (ccb->cmd == NULL)
 753                 return;
 754         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 755 }
 756
 757 static void stex_check_cmd(struct st_hba *hba,
 758         struct st_ccb *ccb, struct status_msg *resp)
 759 {
 760         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 761                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 762                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 763                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 764 }
 765
 766 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 767 {
 768         void __iomem *base = hba->mmio_base;
 769         struct status_msg *resp;
 770         struct st_ccb *ccb;
 771         unsigned int size;
 772         u16 tag;
 773
 774         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 775                 return;
 776
 777         /* status payloads */
 778         hba->status_head = readl(base + OMR1);
 779         if (unlikely(hba->status_head > hba->sts_count)) {
 780                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 781                         pci_name(hba->pdev));
 782                 return;
 783         }
 784
 785         /*
 786          * it's not a valid status payload if:
 787          * 1. there are no pending requests(e.g. during init stage)
 788          * 2. there are some pending requests, but the controller is in
 789          *     reset status, and its type is not st_yosemite
 790          * firmware of st_yosemite in reset status will return pending requests
 791          * to driver, so we allow it to pass
 792          */
 793         if (unlikely(hba->out_req_cnt <= 0 ||
 794                         (hba->mu_status == MU_STATE_RESETTING &&
 795                          hba->cardtype != st_yosemite))) {
 796                 hba->status_tail = hba->status_head;
 797                 goto update_status;
 798         }
 799
 800         while (hba->status_tail != hba->status_head) {
 801                 resp = stex_get_status(hba);
 802                 tag = le16_to_cpu(resp->tag);
 803                 if (unlikely(tag >= hba->host->can_queue)) {
 804                         printk(KERN_WARNING DRV_NAME
 805                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 806                         continue;
 807                 }
 808
 809                 hba->out_req_cnt--;
 810                 ccb = &hba->ccb[tag];
 811                 if (unlikely(hba->wait_ccb == ccb))
 812                         hba->wait_ccb = NULL;
 813                 if (unlikely(ccb->req == NULL)) {
 814                         printk(KERN_WARNING DRV_NAME
 815                                 "(%s): lagging req\n", pci_name(hba->pdev));
 816                         continue;
 817                 }
 818
 819                 size = resp->payload_sz * sizeof(u32); /* payload size */
 820                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 821                         size > sizeof(*resp))) {
 822                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 823                                 pci_name(hba->pdev));
 824                 } else {
 825                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 826                         if (size)
 827                                 stex_copy_data(ccb, resp, size);
 828                 }
 829
 830                 ccb->req = NULL;
 831                 ccb->srb_status = resp->srb_status;
 832                 ccb->scsi_status = resp->scsi_status;
 833
 834                 if (likely(ccb->cmd != NULL)) {
 835                         if (hba->cardtype == st_yosemite)
 836                                 stex_check_cmd(hba, ccb, resp);
 837
 838                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 839                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 840                                 stex_controller_info(hba, ccb);
 841
 842                         scsi_dma_unmap(ccb->cmd);
 843                         stex_scsi_done(ccb);
 844                 } else
 845                         ccb->req_type = 0;
 846         }
 847
 848 update_status:
 849         writel(hba->status_head, base + IMR1);
 850         readl(base + IMR1); /* flush */
 851 }
 852
 853 static irqreturn_t stex_intr(int irq, void *__hba)
 854 {
 855         struct st_hba *hba = __hba;
 856         void __iomem *base = hba->mmio_base;
 857         u32 data;
 858         unsigned long flags;
 859
 860         spin_lock_irqsave(hba->host->host_lock, flags);
 861
 862         data = readl(base + ODBL);
 863
 864         if (data && data != 0xffffffff) {
 865                 /* clear the interrupt */
 866                 writel(data, base + ODBL);
 867                 readl(base + ODBL); /* flush */
 868                 stex_mu_intr(hba, data);
 869                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 870                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 871                         hba->cardtype == st_shasta))
 872                         queue_work(hba->work_q, &hba->reset_work);
 873                 return IRQ_HANDLED;
 874         }
 875
 876         spin_unlock_irqrestore(hba->host->host_lock, flags);
 877
 878         return IRQ_NONE;
 879 }
 880
 881 static void stex_ss_mu_intr(struct st_hba *hba)
 882 {
 883         struct status_msg *resp;
 884         struct st_ccb *ccb;
 885         __le32 *scratch;
 886         unsigned int size;
 887         int count = 0;
 888         u32 value;
 889         u16 tag;
 890
 891         if (unlikely(hba->out_req_cnt <= 0 ||
 892                         hba->mu_status == MU_STATE_RESETTING))
 893                 return;
 894
 895         while (count < hba->sts_count) {
 896                 scratch = hba->scratch + hba->status_tail;
 897                 value = le32_to_cpu(*scratch);
 898                 if (unlikely(!(value & SS_STS_NORMAL)))
 899                         return;
 900
 901                 resp = hba->status_buffer + hba->status_tail;
 902                 *scratch = 0;
 903                 ++count;
 904                 ++hba->status_tail;
 905                 hba->status_tail %= hba->sts_count+1;
 906
 907                 tag = (u16)value;
 908                 if (unlikely(tag >= hba->host->can_queue)) {
 909                         printk(KERN_WARNING DRV_NAME
 910                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 911                         continue;
 912                 }
 913
 914                 hba->out_req_cnt--;
 915                 ccb = &hba->ccb[tag];
 916                 if (unlikely(hba->wait_ccb == ccb))
 917                         hba->wait_ccb = NULL;
 918                 if (unlikely(ccb->req == NULL)) {
 919                         printk(KERN_WARNING DRV_NAME
 920                                 "(%s): lagging req\n", pci_name(hba->pdev));
 921                         continue;
 922                 }
 923
 924                 ccb->req = NULL;
 925                 if (likely(value & SS_STS_DONE)) { /* normal case */
 926                         ccb->srb_status = SRB_STATUS_SUCCESS;
 927                         ccb->scsi_status = SAM_STAT_GOOD;
 928                 } else {
 929                         ccb->srb_status = resp->srb_status;
 930                         ccb->scsi_status = resp->scsi_status;
 931                         size = resp->payload_sz * sizeof(u32);
 932                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 933                                 size > sizeof(*resp))) {
 934                                 printk(KERN_WARNING DRV_NAME
 935                                         "(%s): bad status size\n",
 936                                         pci_name(hba->pdev));
 937                         } else {
 938                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 939                                 if (size)
 940                                         stex_copy_data(ccb, resp, size);
 941                         }
 942                         if (likely(ccb->cmd != NULL))
 943                                 stex_check_cmd(hba, ccb, resp);
 944                 }
 945
 946                 if (likely(ccb->cmd != NULL)) {
 947                         scsi_dma_unmap(ccb->cmd);
 948                         stex_scsi_done(ccb);
 949                 } else
 950                         ccb->req_type = 0;
 951         }
 952 }
 953
 954 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 955 {
 956         struct st_hba *hba = __hba;
 957         void __iomem *base = hba->mmio_base;
 958         u32 data;
 959         unsigned long flags;
 960
 961         spin_lock_irqsave(hba->host->host_lock, flags);
 962
 963         data = readl(base + YI2H_INT);
 964         if (data && data != 0xffffffff) {
 965                 /* clear the interrupt */
 966                 writel(data, base + YI2H_INT_C);
 967                 stex_ss_mu_intr(hba);
 968                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 969                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 970                         queue_work(hba->work_q, &hba->reset_work);
 971                 return IRQ_HANDLED;
 972         }
 973
 974         spin_unlock_irqrestore(hba->host->host_lock, flags);
 975
 976         return IRQ_NONE;
 977 }
 978
 979 static int stex_common_handshake(struct st_hba *hba)
 980 {
 981         void __iomem *base = hba->mmio_base;
 982         struct handshake_frame *h;
 983         dma_addr_t status_phys;
 984         u32 data;
 985         unsigned long before;
 986
 987         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 988                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 989                 readl(base + IDBL);
 990                 before = jiffies;
 991                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 992                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 993                                 printk(KERN_ERR DRV_NAME
 994                                         "(%s): no handshake signature\n",
 995                                         pci_name(hba->pdev));
 996                                 return -1;
 997                         }
 998                         rmb();
 999                         msleep(1);
1000                 }
1001         }
1002
1003         udelay(10);
1004
1005         data = readl(base + OMR1);
1006         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1007                 data &= 0x0000ffff;
1008                 if (hba->host->can_queue > data) {
1009                         hba->host->can_queue = data;
1010                         hba->host->cmd_per_lun = data;
1011                 }
1012         }
1013
1014         h = (struct handshake_frame *)hba->status_buffer;
1015         h->rb_phy = cpu_to_le64(hba->dma_handle);
1016         h->req_sz = cpu_to_le16(hba->rq_size);
1017         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1018         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1019         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1020         stex_gettime(&h->hosttime);
1021         h->partner_type = HMU_PARTNER_TYPE;
1022         if (hba->extra_offset) {
1023                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1024                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1025         } else
1026                 h->extra_offset = h->extra_size = 0;
1027
1028         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1029         writel(status_phys, base + IMR0);
1030         readl(base + IMR0);
1031         writel((status_phys >> 16) >> 16, base + IMR1);
1032         readl(base + IMR1);
1033
1034         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1035         readl(base + OMR0);
1036         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1037         readl(base + IDBL); /* flush */
1038
1039         udelay(10);
1040         before = jiffies;
1041         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1042                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1043                         printk(KERN_ERR DRV_NAME
1044                                 "(%s): no signature after handshake frame\n",
1045                                 pci_name(hba->pdev));
1046                         return -1;
1047                 }
1048                 rmb();
1049                 msleep(1);
1050         }
1051
1052         writel(0, base + IMR0);
1053         readl(base + IMR0);
1054         writel(0, base + OMR0);
1055         readl(base + OMR0);
1056         writel(0, base + IMR1);
1057         readl(base + IMR1);
1058         writel(0, base + OMR1);
1059         readl(base + OMR1); /* flush */
1060         return 0;
1061 }
1062
1063 static int stex_ss_handshake(struct st_hba *hba)
1064 {
1065         void __iomem *base = hba->mmio_base;
1066         struct st_msg_header *msg_h;
1067         struct handshake_frame *h;
1068         __le32 *scratch;
1069         u32 data, scratch_size;
1070         unsigned long before;
1071         int ret = 0;
1072
1073         before = jiffies;
1074         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1075                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1076                         printk(KERN_ERR DRV_NAME
1077                                 "(%s): firmware not operational\n",
1078                                 pci_name(hba->pdev));
1079                         return -1;
1080                 }
1081                 msleep(1);
1082         }
1083
1084         msg_h = (struct st_msg_header *)hba->dma_mem;
1085         msg_h->handle = cpu_to_le64(hba->dma_handle);
1086         msg_h->flag = SS_HEAD_HANDSHAKE;
1087
1088         h = (struct handshake_frame *)(msg_h + 1);
1089         h->rb_phy = cpu_to_le64(hba->dma_handle);
1090         h->req_sz = cpu_to_le16(hba->rq_size);
1091         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1092         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1093         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1094         stex_gettime(&h->hosttime);
1095         h->partner_type = HMU_PARTNER_TYPE;
1096         h->extra_offset = h->extra_size = 0;
1097         scratch_size = (hba->sts_count+1)*sizeof(u32);
1098         h->scratch_size = cpu_to_le32(scratch_size);
1099
1100         data = readl(base + YINT_EN);
1101         data &= ~4;
1102         writel(data, base + YINT_EN);
1103         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1104         readl(base + YH2I_REQ_HI);
1105         writel(hba->dma_handle, base + YH2I_REQ);
1106         readl(base + YH2I_REQ); /* flush */
1107
1108         scratch = hba->scratch;
1109         before = jiffies;
1110         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1111                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1112                         printk(KERN_ERR DRV_NAME
1113                                 "(%s): no signature after handshake frame\n",
1114                                 pci_name(hba->pdev));
1115                         ret = -1;
1116                         break;
1117                 }
1118                 rmb();
1119                 msleep(1);
1120         }
1121
1122         memset(scratch, 0, scratch_size);
1123         msg_h->flag = 0;
1124         return ret;
1125 }
1126
1127 static int stex_handshake(struct st_hba *hba)
1128 {
1129         int err;
1130         unsigned long flags;
1131         unsigned int mu_status;
1132
1133         err = (hba->cardtype == st_yel) ?
1134                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1135         spin_lock_irqsave(hba->host->host_lock, flags);
1136         mu_status = hba->mu_status;
1137         if (err == 0) {
1138                 hba->req_head = 0;
1139                 hba->req_tail = 0;
1140                 hba->status_head = 0;
1141                 hba->status_tail = 0;
1142                 hba->out_req_cnt = 0;
1143                 hba->mu_status = MU_STATE_STARTED;
1144         } else
1145                 hba->mu_status = MU_STATE_FAILED;
1146         if (mu_status == MU_STATE_RESETTING)
1147                 wake_up_all(&hba->reset_waitq);
1148         spin_unlock_irqrestore(hba->host->host_lock, flags);
1149         return err;
1150 }
1151
1152 static int stex_abort(struct scsi_cmnd *cmd)
1153 {
1154         struct Scsi_Host *host = cmd->device->host;
1155         struct st_hba *hba = (struct st_hba *)host->hostdata;
1156         u16 tag = cmd->request->tag;
1157         void __iomem *base;
1158         u32 data;
1159         int result = SUCCESS;
1160         unsigned long flags;
1161
1162         printk(KERN_INFO DRV_NAME
1163                 "(%s): aborting command\n", pci_name(hba->pdev));
1164         scsi_print_command(cmd);
1165
1166         base = hba->mmio_base;
1167         spin_lock_irqsave(host->host_lock, flags);
1168         if (tag < host->can_queue &&
1169                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1170                 hba->wait_ccb = &hba->ccb[tag];
1171         else
1172                 goto out;
1173
1174         if (hba->cardtype == st_yel) {
1175                 data = readl(base + YI2H_INT);
1176                 if (data == 0 || data == 0xffffffff)
1177                         goto fail_out;
1178
1179                 writel(data, base + YI2H_INT_C);
1180                 stex_ss_mu_intr(hba);
1181         } else {
1182                 data = readl(base + ODBL);
1183                 if (data == 0 || data == 0xffffffff)
1184                         goto fail_out;
1185
1186                 writel(data, base + ODBL);
1187                 readl(base + ODBL); /* flush */
1188
1189                 stex_mu_intr(hba, data);
1190         }
1191         if (hba->wait_ccb == NULL) {
1192                 printk(KERN_WARNING DRV_NAME
1193                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1194                 goto out;
1195         }
1196
1197 fail_out:
1198         scsi_dma_unmap(cmd);
1199         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1200         hba->wait_ccb = NULL;
1201         result = FAILED;
1202 out:
1203         spin_unlock_irqrestore(host->host_lock, flags);
1204         return result;
1205 }
1206
1207 static void stex_hard_reset(struct st_hba *hba)
1208 {
1209         struct pci_bus *bus;
1210         int i;
1211         u16 pci_cmd;
1212         u8 pci_bctl;
1213
1214         for (i = 0; i < 16; i++)
1215                 pci_read_config_dword(hba->pdev, i * 4,
1216                         &hba->pdev->saved_config_space[i]);
1217
1218         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1219            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1220         bus = hba->pdev->bus;
1221         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1222         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1223         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1224
1225         /*
1226          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1227          * require more time to finish bus reset. Use 100 ms here for safety
1228          */
1229         msleep(100);
1230         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1231         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1232
1233         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1234                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1235                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1236                         break;
1237                 msleep(1);
1238         }
1239
1240         ssleep(5);
1241         for (i = 0; i < 16; i++)
1242                 pci_write_config_dword(hba->pdev, i * 4,
1243                         hba->pdev->saved_config_space[i]);
1244 }
1245
1246 static int stex_yos_reset(struct st_hba *hba)
1247 {
1248         void __iomem *base;
1249         unsigned long flags, before;
1250         int ret = 0;
1251
1252         base = hba->mmio_base;
1253         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1254         readl(base + IDBL); /* flush */
1255         before = jiffies;
1256         while (hba->out_req_cnt > 0) {
1257                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1258                         printk(KERN_WARNING DRV_NAME
1259                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1260                         ret = -1;
1261                         break;
1262                 }
1263                 msleep(1);
1264         }
1265
1266         spin_lock_irqsave(hba->host->host_lock, flags);
1267         if (ret == -1)
1268                 hba->mu_status = MU_STATE_FAILED;
1269         else
1270                 hba->mu_status = MU_STATE_STARTED;
1271         wake_up_all(&hba->reset_waitq);
1272         spin_unlock_irqrestore(hba->host->host_lock, flags);
1273
1274         return ret;
1275 }
1276
1277 static void stex_ss_reset(struct st_hba *hba)
1278 {
1279         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1280         readl(hba->mmio_base + YH2I_INT);
1281         ssleep(5);
1282 }
1283
1284 static int stex_do_reset(struct st_hba *hba)
1285 {
1286         struct st_ccb *ccb;
1287         unsigned long flags;
1288         unsigned int mu_status = MU_STATE_RESETTING;
1289         u16 tag;
1290
1291         spin_lock_irqsave(hba->host->host_lock, flags);
1292         if (hba->mu_status == MU_STATE_STARTING) {
1293                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1294                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1295                         pci_name(hba->pdev));
1296                 return 0;
1297         }
1298         while (hba->mu_status == MU_STATE_RESETTING) {
1299                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1300                 wait_event_timeout(hba->reset_waitq,
1301                                    hba->mu_status != MU_STATE_RESETTING,
1302                                    MU_MAX_DELAY * HZ);
1303                 spin_lock_irqsave(hba->host->host_lock, flags);
1304                 mu_status = hba->mu_status;
1305         }
1306
1307         if (mu_status != MU_STATE_RESETTING) {
1308                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1309                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1310         }
1311
1312         hba->mu_status = MU_STATE_RESETTING;
1313         spin_unlock_irqrestore(hba->host->host_lock, flags);
1314
1315         if (hba->cardtype == st_yosemite)
1316                 return stex_yos_reset(hba);
1317
1318         if (hba->cardtype == st_shasta)
1319                 stex_hard_reset(hba);
1320         else if (hba->cardtype == st_yel)
1321                 stex_ss_reset(hba);
1322
1323         spin_lock_irqsave(hba->host->host_lock, flags);
1324         for (tag = 0; tag < hba->host->can_queue; tag++) {
1325                 ccb = &hba->ccb[tag];
1326                 if (ccb->req == NULL)
1327                         continue;
1328                 ccb->req = NULL;
1329                 if (ccb->cmd) {
1330                         scsi_dma_unmap(ccb->cmd);
1331                         ccb->cmd->result = DID_RESET << 16;
1332                         ccb->cmd->scsi_done(ccb->cmd);
1333                         ccb->cmd = NULL;
1334                 }
1335         }
1336         spin_unlock_irqrestore(hba->host->host_lock, flags);
1337
1338         if (stex_handshake(hba) == 0)
1339                 return 0;
1340
1341         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1342                 pci_name(hba->pdev));
1343         return -1;
1344 }
1345
1346 static int stex_reset(struct scsi_cmnd *cmd)
1347 {
1348         struct st_hba *hba;
1349
1350         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1351
1352         printk(KERN_INFO DRV_NAME
1353                 "(%s): resetting host\n", pci_name(hba->pdev));
1354         scsi_print_command(cmd);
1355
1356         return stex_do_reset(hba) ? FAILED : SUCCESS;
1357 }
1358
1359 static void stex_reset_work(struct work_struct *work)
1360 {
1361         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1362
1363         stex_do_reset(hba);
1364 }
1365
1366 static int stex_biosparam(struct scsi_device *sdev,
1367         struct block_device *bdev, sector_t capacity, int geom[])
1368 {
1369         int heads = 255, sectors = 63;
1370
1371         if (capacity < 0x200000) {
1372                 heads = 64;
1373                 sectors = 32;
1374         }
1375
1376         sector_div(capacity, heads * sectors);
1377
1378         geom[0] = heads;
1379         geom[1] = sectors;
1380         geom[2] = capacity;
1381
1382         return 0;
1383 }
1384
1385 static struct scsi_host_template driver_template = {
1386         .module                         = THIS_MODULE,
1387         .name                           = DRV_NAME,
1388         .proc_name                      = DRV_NAME,
1389         .bios_param                     = stex_biosparam,
1390         .queuecommand                   = stex_queuecommand,
1391         .slave_alloc                    = stex_slave_alloc,
1392         .slave_configure                = stex_slave_config,
1393         .slave_destroy                  = stex_slave_destroy,
1394         .eh_abort_handler               = stex_abort,
1395         .eh_host_reset_handler          = stex_reset,
1396         .this_id                        = -1,
1397 };
1398
1399 static struct pci_device_id stex_pci_tbl[] = {
1400         /* st_shasta */
1401         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1402                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1403         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1404                 st_shasta }, /* SuperTrak EX12350 */
1405         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1406                 st_shasta }, /* SuperTrak EX4350 */
1407         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1408                 st_shasta }, /* SuperTrak EX24350 */
1409
1410         /* st_vsc */
1411         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1412
1413         /* st_yosemite */
1414         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1415
1416         /* st_seq */
1417         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1418
1419         /* st_yel */
1420         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1421         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1422         { }     /* terminate list */
1423 };
1424
1425 static struct st_card_info stex_card_info[] = {
1426         /* st_shasta */
1427         {
1428                 .max_id         = 17,
1429                 .max_lun        = 8,
1430                 .max_channel    = 0,
1431                 .rq_count       = 32,
1432                 .rq_size        = 1048,
1433                 .sts_count      = 32,
1434                 .alloc_rq       = stex_alloc_req,
1435                 .map_sg         = stex_map_sg,
1436                 .send           = stex_send_cmd,
1437         },
1438
1439         /* st_vsc */
1440         {
1441                 .max_id         = 129,
1442                 .max_lun        = 1,
1443                 .max_channel    = 0,
1444                 .rq_count       = 32,
1445                 .rq_size        = 1048,
1446                 .sts_count      = 32,
1447                 .alloc_rq       = stex_alloc_req,
1448                 .map_sg         = stex_map_sg,
1449                 .send           = stex_send_cmd,
1450         },
1451
1452         /* st_yosemite */
1453         {
1454                 .max_id         = 2,
1455                 .max_lun        = 256,
1456                 .max_channel    = 0,
1457                 .rq_count       = 256,
1458                 .rq_size        = 1048,
1459                 .sts_count      = 256,
1460                 .alloc_rq       = stex_alloc_req,
1461                 .map_sg         = stex_map_sg,
1462                 .send           = stex_send_cmd,
1463         },
1464
1465         /* st_seq */
1466         {
1467                 .max_id         = 129,
1468                 .max_lun        = 1,
1469                 .max_channel    = 0,
1470                 .rq_count       = 32,
1471                 .rq_size        = 1048,
1472                 .sts_count      = 32,
1473                 .alloc_rq       = stex_alloc_req,
1474                 .map_sg         = stex_map_sg,
1475                 .send           = stex_send_cmd,
1476         },
1477
1478         /* st_yel */
1479         {
1480                 .max_id         = 129,
1481                 .max_lun        = 256,
1482                 .max_channel    = 3,
1483                 .rq_count       = 801,
1484                 .rq_size        = 512,
1485                 .sts_count      = 801,
1486                 .alloc_rq       = stex_ss_alloc_req,
1487                 .map_sg         = stex_ss_map_sg,
1488                 .send           = stex_ss_send_cmd,
1489         },
1490 };
1491
1492 static int stex_set_dma_mask(struct pci_dev * pdev)
1493 {
1494         int ret;
1495
1496         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1497                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1498                 return 0;
1499         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1500         if (!ret)
1501                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1502         return ret;
1503 }
1504
1505 static int stex_request_irq(struct st_hba *hba)
1506 {
1507         struct pci_dev *pdev = hba->pdev;
1508         int status;
1509
1510         if (msi) {
1511                 status = pci_enable_msi(pdev);
1512                 if (status != 0)
1513                         printk(KERN_ERR DRV_NAME
1514                                 "(%s): error %d setting up MSI\n",
1515                                 pci_name(pdev), status);
1516                 else
1517                         hba->msi_enabled = 1;
1518         } else
1519                 hba->msi_enabled = 0;
1520
1521         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1522                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1523
1524         if (status != 0) {
1525                 if (hba->msi_enabled)
1526                         pci_disable_msi(pdev);
1527         }
1528         return status;
1529 }
1530
1531 static void stex_free_irq(struct st_hba *hba)
1532 {
1533         struct pci_dev *pdev = hba->pdev;
1534
1535         free_irq(pdev->irq, hba);
1536         if (hba->msi_enabled)
1537                 pci_disable_msi(pdev);
1538 }
1539
1540 static int __devinit
1541 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1542 {
1543         struct st_hba *hba;
1544         struct Scsi_Host *host;
1545         const struct st_card_info *ci = NULL;
1546         u32 sts_offset, cp_offset, scratch_offset;
1547         int err;
1548
1549         err = pci_enable_device(pdev);
1550         if (err)
1551                 return err;
1552
1553         pci_set_master(pdev);
1554
1555         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1556
1557         if (!host) {
1558                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1559                         pci_name(pdev));
1560                 err = -ENOMEM;
1561                 goto out_disable;
1562         }
1563
1564         hba = (struct st_hba *)host->hostdata;
1565         memset(hba, 0, sizeof(struct st_hba));
1566
1567         err = pci_request_regions(pdev, DRV_NAME);
1568         if (err < 0) {
1569                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1570                         pci_name(pdev));
1571                 goto out_scsi_host_put;
1572         }
1573
1574         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1575         if ( !hba->mmio_base) {
1576                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1577                         pci_name(pdev));
1578                 err = -ENOMEM;
1579                 goto out_release_regions;
1580         }
1581
1582         err = stex_set_dma_mask(pdev);
1583         if (err) {
1584                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1585                         pci_name(pdev));
1586                 goto out_iounmap;
1587         }
1588
1589         hba->cardtype = (unsigned int) id->driver_data;
1590         ci = &stex_card_info[hba->cardtype];
1591         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1592         if (hba->cardtype == st_yel)
1593                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1594         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1595         hba->dma_size = cp_offset + sizeof(struct st_frame);
1596         if (hba->cardtype == st_seq ||
1597                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1598                 hba->extra_offset = hba->dma_size;
1599                 hba->dma_size += ST_ADDITIONAL_MEM;
1600         }
1601         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1602                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1603         if (!hba->dma_mem) {
1604                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1605                 if (hba->cardtype == st_seq ||
1606                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1607                         printk(KERN_WARNING DRV_NAME
1608                                 "(%s): allocating min buffer for controller\n",
1609                                 pci_name(pdev));
1610                         hba->dma_size = hba->extra_offset
1611                                 + ST_ADDITIONAL_MEM_MIN;
1612                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1613                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1614                 }
1615
1616                 if (!hba->dma_mem) {
1617                         err = -ENOMEM;
1618                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1619                                 pci_name(pdev));
1620                         goto out_iounmap;
1621                 }
1622         }
1623
1624         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1625         if (!hba->ccb) {
1626                 err = -ENOMEM;
1627                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1628                         pci_name(pdev));
1629                 goto out_pci_free;
1630         }
1631
1632         if (hba->cardtype == st_yel)
1633                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1634         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1635         hba->copy_buffer = hba->dma_mem + cp_offset;
1636         hba->rq_count = ci->rq_count;
1637         hba->rq_size = ci->rq_size;
1638         hba->sts_count = ci->sts_count;
1639         hba->alloc_rq = ci->alloc_rq;
1640         hba->map_sg = ci->map_sg;
1641         hba->send = ci->send;
1642         hba->mu_status = MU_STATE_STARTING;
1643
1644         if (hba->cardtype == st_yel)
1645                 host->sg_tablesize = 38;
1646         else
1647                 host->sg_tablesize = 32;
1648         host->can_queue = ci->rq_count;
1649         host->cmd_per_lun = ci->rq_count;
1650         host->max_id = ci->max_id;
1651         host->max_lun = ci->max_lun;
1652         host->max_channel = ci->max_channel;
1653         host->unique_id = host->host_no;
1654         host->max_cmd_len = STEX_CDB_LENGTH;
1655
1656         hba->host = host;
1657         hba->pdev = pdev;
1658         init_waitqueue_head(&hba->reset_waitq);
1659
1660         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1661                  "stex_wq_%d", host->host_no);
1662         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1663         if (!hba->work_q) {
1664                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1665                         pci_name(pdev));
1666                 err = -ENOMEM;
1667                 goto out_ccb_free;
1668         }
1669         INIT_WORK(&hba->reset_work, stex_reset_work);
1670
1671         err = stex_request_irq(hba);
1672         if (err) {
1673                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1674                         pci_name(pdev));
1675                 goto out_free_wq;
1676         }
1677
1678         err = stex_handshake(hba);
1679         if (err)
1680                 goto out_free_irq;
1681
1682         err = scsi_init_shared_tag_map(host, host->can_queue);
1683         if (err) {
1684                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1685                         pci_name(pdev));
1686                 goto out_free_irq;
1687         }
1688
1689         pci_set_drvdata(pdev, hba);
1690
1691         err = scsi_add_host(host, &pdev->dev);
1692         if (err) {
1693                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1694                         pci_name(pdev));
1695                 goto out_free_irq;
1696         }
1697
1698         scsi_scan_host(host);
1699
1700         return 0;
1701
1702 out_free_irq:
1703         stex_free_irq(hba);
1704 out_free_wq:
1705         destroy_workqueue(hba->work_q);
1706 out_ccb_free:
1707         kfree(hba->ccb);
1708 out_pci_free:
1709         dma_free_coherent(&pdev->dev, hba->dma_size,
1710                           hba->dma_mem, hba->dma_handle);
1711 out_iounmap:
1712         iounmap(hba->mmio_base);
1713 out_release_regions:
1714         pci_release_regions(pdev);
1715 out_scsi_host_put:
1716         scsi_host_put(host);
1717 out_disable:
1718         pci_disable_device(pdev);
1719
1720         return err;
1721 }
1722
1723 static void stex_hba_stop(struct st_hba *hba)
1724 {
1725         struct req_msg *req;
1726         struct st_msg_header *msg_h;
1727         unsigned long flags;
1728         unsigned long before;
1729         u16 tag = 0;
1730
1731         spin_lock_irqsave(hba->host->host_lock, flags);
1732         req = hba->alloc_rq(hba);
1733         if (hba->cardtype == st_yel) {
1734                 msg_h = (struct st_msg_header *)req - 1;
1735                 memset(msg_h, 0, hba->rq_size);
1736         } else
1737                 memset(req, 0, hba->rq_size);
1738
1739         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1740                 req->cdb[0] = MGT_CMD;
1741                 req->cdb[1] = MGT_CMD_SIGNATURE;
1742                 req->cdb[2] = CTLR_CONFIG_CMD;
1743                 req->cdb[3] = CTLR_SHUTDOWN;
1744         } else {
1745                 req->cdb[0] = CONTROLLER_CMD;
1746                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1747                 req->cdb[2] = CTLR_POWER_SAVING;
1748         }
1749
1750         hba->ccb[tag].cmd = NULL;
1751         hba->ccb[tag].sg_count = 0;
1752         hba->ccb[tag].sense_bufflen = 0;
1753         hba->ccb[tag].sense_buffer = NULL;
1754         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1755
1756         hba->send(hba, req, tag);
1757         spin_unlock_irqrestore(hba->host->host_lock, flags);
1758
1759         before = jiffies;
1760         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1761                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1762                         hba->ccb[tag].req_type = 0;
1763                         return;
1764                 }
1765                 msleep(1);
1766         }
1767 }
1768
1769 static void stex_hba_free(struct st_hba *hba)
1770 {
1771         stex_free_irq(hba);
1772
1773         destroy_workqueue(hba->work_q);
1774
1775         iounmap(hba->mmio_base);
1776
1777         pci_release_regions(hba->pdev);
1778
1779         kfree(hba->ccb);
1780
1781         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1782                           hba->dma_mem, hba->dma_handle);
1783 }
1784
1785 static void stex_remove(struct pci_dev *pdev)
1786 {
1787         struct st_hba *hba = pci_get_drvdata(pdev);
1788
1789         scsi_remove_host(hba->host);
1790
1791         pci_set_drvdata(pdev, NULL);
1792
1793         stex_hba_stop(hba);
1794
1795         stex_hba_free(hba);
1796
1797         scsi_host_put(hba->host);
1798
1799         pci_disable_device(pdev);
1800 }
1801
1802 static void stex_shutdown(struct pci_dev *pdev)
1803 {
1804         struct st_hba *hba = pci_get_drvdata(pdev);
1805
1806         stex_hba_stop(hba);
1807 }
1808
1809 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1810
1811 static struct pci_driver stex_pci_driver = {
1812         .name           = DRV_NAME,
1813         .id_table       = stex_pci_tbl,
1814         .probe          = stex_probe,
1815         .remove         = __devexit_p(stex_remove),
1816         .shutdown       = stex_shutdown,
1817 };
1818
1819 static int __init stex_init(void)
1820 {
1821         printk(KERN_INFO DRV_NAME
1822                 ": Promise SuperTrak EX Driver version: %s\n",
1823                  ST_DRIVER_VERSION);
1824
1825         return pci_register_driver(&stex_pci_driver);
1826 }
1827
1828 static void __exit stex_exit(void)
1829 {
1830         pci_unregister_driver(&stex_pci_driver);
1831 }
1832
1833 module_init(stex_init);
1834 module_exit(stex_exit);