drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include "ql4_def.h"
  11 #include "ql4_glbl.h"
  12
  13 #define MASK(n)         DMA_BIT_MASK(n)
  14 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  15 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  16 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  17 #define QLA82XX_PCI_MN_2M       (0)
  18 #define QLA82XX_PCI_MS_2M       (0x80000)
  19 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  20 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  21 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  22
  23 /* CRB window related */
  24 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  25 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  26 #define CRB_WINDOW_2M   (0x130060)
  27 #define CRB_HI(off)     ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  28                         ((off) & 0xf0000))
  29 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  30 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  31 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  32
  33 static inline void __iomem *
  34 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  35 {
  36         if ((off < ha->first_page_group_end) &&
  37             (off >= ha->first_page_group_start))
  38                 return (void __iomem *)(ha->nx_pcibase + off);
  39
  40         return NULL;
  41 }
  42
  43 #define MAX_CRB_XFORM 60
  44 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  45 static int qla4_8xxx_crb_table_initialized;
  46
  47 #define qla4_8xxx_crb_addr_transform(name) \
  48         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  49          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  50 static void
  51 qla4_8xxx_crb_addr_transform_setup(void)
  52 {
  53         qla4_8xxx_crb_addr_transform(XDMA);
  54         qla4_8xxx_crb_addr_transform(TIMR);
  55         qla4_8xxx_crb_addr_transform(SRE);
  56         qla4_8xxx_crb_addr_transform(SQN3);
  57         qla4_8xxx_crb_addr_transform(SQN2);
  58         qla4_8xxx_crb_addr_transform(SQN1);
  59         qla4_8xxx_crb_addr_transform(SQN0);
  60         qla4_8xxx_crb_addr_transform(SQS3);
  61         qla4_8xxx_crb_addr_transform(SQS2);
  62         qla4_8xxx_crb_addr_transform(SQS1);
  63         qla4_8xxx_crb_addr_transform(SQS0);
  64         qla4_8xxx_crb_addr_transform(RPMX7);
  65         qla4_8xxx_crb_addr_transform(RPMX6);
  66         qla4_8xxx_crb_addr_transform(RPMX5);
  67         qla4_8xxx_crb_addr_transform(RPMX4);
  68         qla4_8xxx_crb_addr_transform(RPMX3);
  69         qla4_8xxx_crb_addr_transform(RPMX2);
  70         qla4_8xxx_crb_addr_transform(RPMX1);
  71         qla4_8xxx_crb_addr_transform(RPMX0);
  72         qla4_8xxx_crb_addr_transform(ROMUSB);
  73         qla4_8xxx_crb_addr_transform(SN);
  74         qla4_8xxx_crb_addr_transform(QMN);
  75         qla4_8xxx_crb_addr_transform(QMS);
  76         qla4_8xxx_crb_addr_transform(PGNI);
  77         qla4_8xxx_crb_addr_transform(PGND);
  78         qla4_8xxx_crb_addr_transform(PGN3);
  79         qla4_8xxx_crb_addr_transform(PGN2);
  80         qla4_8xxx_crb_addr_transform(PGN1);
  81         qla4_8xxx_crb_addr_transform(PGN0);
  82         qla4_8xxx_crb_addr_transform(PGSI);
  83         qla4_8xxx_crb_addr_transform(PGSD);
  84         qla4_8xxx_crb_addr_transform(PGS3);
  85         qla4_8xxx_crb_addr_transform(PGS2);
  86         qla4_8xxx_crb_addr_transform(PGS1);
  87         qla4_8xxx_crb_addr_transform(PGS0);
  88         qla4_8xxx_crb_addr_transform(PS);
  89         qla4_8xxx_crb_addr_transform(PH);
  90         qla4_8xxx_crb_addr_transform(NIU);
  91         qla4_8xxx_crb_addr_transform(I2Q);
  92         qla4_8xxx_crb_addr_transform(EG);
  93         qla4_8xxx_crb_addr_transform(MN);
  94         qla4_8xxx_crb_addr_transform(MS);
  95         qla4_8xxx_crb_addr_transform(CAS2);
  96         qla4_8xxx_crb_addr_transform(CAS1);
  97         qla4_8xxx_crb_addr_transform(CAS0);
  98         qla4_8xxx_crb_addr_transform(CAM);
  99         qla4_8xxx_crb_addr_transform(C2C1);
 100         qla4_8xxx_crb_addr_transform(C2C0);
 101         qla4_8xxx_crb_addr_transform(SMB);
 102         qla4_8xxx_crb_addr_transform(OCM0);
 103         qla4_8xxx_crb_addr_transform(I2C0);
 104
 105         qla4_8xxx_crb_table_initialized = 1;
 106 }
 107
 108 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 109         {{{0, 0,         0,         0} } },             /* 0: PCI */
 110         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 111                 {1, 0x0110000, 0x0120000, 0x130000},
 112                 {1, 0x0120000, 0x0122000, 0x124000},
 113                 {1, 0x0130000, 0x0132000, 0x126000},
 114                 {1, 0x0140000, 0x0142000, 0x128000},
 115                 {1, 0x0150000, 0x0152000, 0x12a000},
 116                 {1, 0x0160000, 0x0170000, 0x110000},
 117                 {1, 0x0170000, 0x0172000, 0x12e000},
 118                 {0, 0x0000000, 0x0000000, 0x000000},
 119                 {0, 0x0000000, 0x0000000, 0x000000},
 120                 {0, 0x0000000, 0x0000000, 0x000000},
 121                 {0, 0x0000000, 0x0000000, 0x000000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {1, 0x01e0000, 0x01e0800, 0x122000},
 125                 {0, 0x0000000, 0x0000000, 0x000000} } },
 126         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 127         {{{0, 0,         0,         0} } },         /* 3: */
 128         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 129         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 130         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 131         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 132         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 133                 {0, 0x0000000, 0x0000000, 0x000000},
 134                 {0, 0x0000000, 0x0000000, 0x000000},
 135                 {0, 0x0000000, 0x0000000, 0x000000},
 136                 {0, 0x0000000, 0x0000000, 0x000000},
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 148         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {0, 0x0000000, 0x0000000, 0x000000},
 152                 {0, 0x0000000, 0x0000000, 0x000000},
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 164         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {0, 0x0000000, 0x0000000, 0x000000},
 168                 {0, 0x0000000, 0x0000000, 0x000000},
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 180         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {0, 0x0000000, 0x0000000, 0x000000},
 184                 {0, 0x0000000, 0x0000000, 0x000000},
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 196         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 197         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 198         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 199         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 200         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 201         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 202         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 203         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 204         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 205         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 206         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 207         {{{0, 0,         0,         0} } },     /* 23: */
 208         {{{0, 0,         0,         0} } },     /* 24: */
 209         {{{0, 0,         0,         0} } },     /* 25: */
 210         {{{0, 0,         0,         0} } },     /* 26: */
 211         {{{0, 0,         0,         0} } },     /* 27: */
 212         {{{0, 0,         0,         0} } },     /* 28: */
 213         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 214         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 215         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 216         {{{0} } },                              /* 32: PCI */
 217         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 218                 {1, 0x2110000, 0x2120000, 0x130000},
 219                 {1, 0x2120000, 0x2122000, 0x124000},
 220                 {1, 0x2130000, 0x2132000, 0x126000},
 221                 {1, 0x2140000, 0x2142000, 0x128000},
 222                 {1, 0x2150000, 0x2152000, 0x12a000},
 223                 {1, 0x2160000, 0x2170000, 0x110000},
 224                 {1, 0x2170000, 0x2172000, 0x12e000},
 225                 {0, 0x0000000, 0x0000000, 0x000000},
 226                 {0, 0x0000000, 0x0000000, 0x000000},
 227                 {0, 0x0000000, 0x0000000, 0x000000},
 228                 {0, 0x0000000, 0x0000000, 0x000000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000} } },
 233         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 234         {{{0} } },                              /* 35: */
 235         {{{0} } },                              /* 36: */
 236         {{{0} } },                              /* 37: */
 237         {{{0} } },                              /* 38: */
 238         {{{0} } },                              /* 39: */
 239         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 240         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 241         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 242         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 243         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 244         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 245         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 246         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 247         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 248         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 249         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 250         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 251         {{{0} } },                              /* 52: */
 252         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 253         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 254         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 255         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 256         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 257         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 258         {{{0} } },                              /* 59: I2C0 */
 259         {{{0} } },                              /* 60: I2C1 */
 260         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 261         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 262         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 263 };
 264
 265 /*
 266  * top 12 bits of crb internal address (hub, agent)
 267  */
 268 static unsigned qla4_8xxx_crb_hub_agt[64] = {
 269         0,
 270         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 271         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 272         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 273         0,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 296         0,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 299         0,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 301         0,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 304         0,
 305         0,
 306         0,
 307         0,
 308         0,
 309         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 310         0,
 311         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 321         0,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 326         0,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 329         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 330         0,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 332         0,
 333 };
 334
 335 /* Device states */
 336 static char *qdev_state[] = {
 337         "Unknown",
 338         "Cold",
 339         "Initializing",
 340         "Ready",
 341         "Need Reset",
 342         "Need Quiescent",
 343         "Failed",
 344         "Quiescent",
 345 };
 346
 347 /*
 348  * In: 'off' is offset from CRB space in 128M pci map
 349  * Out: 'off' is 2M pci map addr
 350  * side effect: lock crb window
 351  */
 352 static void
 353 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 354 {
 355         u32 win_read;
 356
 357         ha->crb_win = CRB_HI(*off);
 358         writel(ha->crb_win,
 359                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 360
 361         /* Read back value to make sure write has gone through before trying
 362         * to use it. */
 363         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 364         if (win_read != ha->crb_win) {
 365                 DEBUG2(ql4_printk(KERN_INFO, ha,
 366                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 367                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 368         }
 369         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 370 }
 371
 372 void
 373 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 374 {
 375         unsigned long flags = 0;
 376         int rv;
 377
 378         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 379
 380         BUG_ON(rv == -1);
 381
 382         if (rv == 1) {
 383                 write_lock_irqsave(&ha->hw_lock, flags);
 384                 qla4_8xxx_crb_win_lock(ha);
 385                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 386         }
 387
 388         writel(data, (void __iomem *)off);
 389
 390         if (rv == 1) {
 391                 qla4_8xxx_crb_win_unlock(ha);
 392                 write_unlock_irqrestore(&ha->hw_lock, flags);
 393         }
 394 }
 395
 396 int
 397 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
 398 {
 399         unsigned long flags = 0;
 400         int rv;
 401         u32 data;
 402
 403         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 404
 405         BUG_ON(rv == -1);
 406
 407         if (rv == 1) {
 408                 write_lock_irqsave(&ha->hw_lock, flags);
 409                 qla4_8xxx_crb_win_lock(ha);
 410                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 411         }
 412         data = readl((void __iomem *)off);
 413
 414         if (rv == 1) {
 415                 qla4_8xxx_crb_win_unlock(ha);
 416                 write_unlock_irqrestore(&ha->hw_lock, flags);
 417         }
 418         return data;
 419 }
 420
 421 #define CRB_WIN_LOCK_TIMEOUT 100000000
 422
 423 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
 424 {
 425         int i;
 426         int done = 0, timeout = 0;
 427
 428         while (!done) {
 429                 /* acquire semaphore3 from PCI HW block */
 430                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 431                 if (done == 1)
 432                         break;
 433                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 434                         return -1;
 435
 436                 timeout++;
 437
 438                 /* Yield CPU */
 439                 if (!in_interrupt())
 440                         schedule();
 441                 else {
 442                         for (i = 0; i < 20; i++)
 443                                 cpu_relax();    /*This a nop instr on i386*/
 444                 }
 445         }
 446         qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 447         return 0;
 448 }
 449
 450 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
 451 {
 452         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 453 }
 454
 455 #define IDC_LOCK_TIMEOUT 100000000
 456
 457 /**
 458  * qla4_8xxx_idc_lock - hw_lock
 459  * @ha: pointer to adapter structure
 460  *
 461  * General purpose lock used to synchronize access to
 462  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 463  **/
 464 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
 465 {
 466         int i;
 467         int done = 0, timeout = 0;
 468
 469         while (!done) {
 470                 /* acquire semaphore5 from PCI HW block */
 471                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 472                 if (done == 1)
 473                         break;
 474                 if (timeout >= IDC_LOCK_TIMEOUT)
 475                         return -1;
 476
 477                 timeout++;
 478
 479                 /* Yield CPU */
 480                 if (!in_interrupt())
 481                         schedule();
 482                 else {
 483                         for (i = 0; i < 20; i++)
 484                                 cpu_relax();    /*This a nop instr on i386*/
 485                 }
 486         }
 487         return 0;
 488 }
 489
 490 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
 491 {
 492         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 493 }
 494
 495 int
 496 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 497 {
 498         struct crb_128M_2M_sub_block_map *m;
 499
 500         if (*off >= QLA82XX_CRB_MAX)
 501                 return -1;
 502
 503         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 504                 *off = (*off - QLA82XX_PCI_CAMQM) +
 505                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 506                 return 0;
 507         }
 508
 509         if (*off < QLA82XX_PCI_CRBSPACE)
 510                 return -1;
 511
 512         *off -= QLA82XX_PCI_CRBSPACE;
 513         /*
 514          * Try direct map
 515          */
 516
 517         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 518
 519         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 520                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 521                 return 0;
 522         }
 523
 524         /*
 525          * Not in direct map, use crb window
 526          */
 527         return 1;
 528 }
 529
 530 /*  PCI Windowing for DDR regions.  */
 531 #define QLA82XX_ADDR_IN_RANGE(addr, low, high)            \
 532         (((addr) <= (high)) && ((addr) >= (low)))
 533
 534 /*
 535 * check memory access boundary.
 536 * used by test agent. support ddr access only for now
 537 */
 538 static unsigned long
 539 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
 540                 unsigned long long addr, int size)
 541 {
 542         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 543             QLA82XX_ADDR_DDR_NET_MAX) ||
 544             !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
 545             QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
 546             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 547                 return 0;
 548         }
 549         return 1;
 550 }
 551
 552 static int qla4_8xxx_pci_set_window_warning_count;
 553
 554 static unsigned long
 555 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 556 {
 557         int window;
 558         u32 win_read;
 559
 560         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 561             QLA82XX_ADDR_DDR_NET_MAX)) {
 562                 /* DDR network side */
 563                 window = MN_WIN(addr);
 564                 ha->ddr_mn_window = window;
 565                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 566                     QLA82XX_PCI_CRBSPACE, window);
 567                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 568                     QLA82XX_PCI_CRBSPACE);
 569                 if ((win_read << 17) != window) {
 570                         ql4_printk(KERN_WARNING, ha,
 571                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 572                         __func__, window, win_read);
 573                 }
 574                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 575         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 576                                 QLA82XX_ADDR_OCM0_MAX)) {
 577                 unsigned int temp1;
 578                 /* if bits 19:18&17:11 are on */
 579                 if ((addr & 0x00ff800) == 0xff800) {
 580                         printk("%s: QM access not handled.\n", __func__);
 581                         addr = -1UL;
 582                 }
 583
 584                 window = OCM_WIN(addr);
 585                 ha->ddr_mn_window = window;
 586                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 587                     QLA82XX_PCI_CRBSPACE, window);
 588                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 589                     QLA82XX_PCI_CRBSPACE);
 590                 temp1 = ((window & 0x1FF) << 7) |
 591                     ((window & 0x0FFFE0000) >> 17);
 592                 if (win_read != temp1) {
 593                         printk("%s: Written OCMwin (0x%x) != Read"
 594                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 595                 }
 596                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 597
 598         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 599                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 600                 /* QDR network side */
 601                 window = MS_WIN(addr);
 602                 ha->qdr_sn_window = window;
 603                 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
 604                     QLA82XX_PCI_CRBSPACE, window);
 605                 win_read = qla4_8xxx_rd_32(ha,
 606                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 607                 if (win_read != window) {
 608                         printk("%s: Written MSwin (0x%x) != Read "
 609                             "MSwin (0x%x)\n", __func__, window, win_read);
 610                 }
 611                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 612
 613         } else {
 614                 /*
 615                  * peg gdb frequently accesses memory that doesn't exist,
 616                  * this limits the chit chat so debugging isn't slowed down.
 617                  */
 618                 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
 619                     (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
 620                         printk("%s: Warning:%s Unknown address range!\n",
 621                             __func__, DRIVER_NAME);
 622                 }
 623                 addr = -1UL;
 624         }
 625         return addr;
 626 }
 627
 628 /* check if address is in the same windows as the previous access */
 629 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
 630                 unsigned long long addr)
 631 {
 632         int window;
 633         unsigned long long qdr_max;
 634
 635         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 636
 637         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 638             QLA82XX_ADDR_DDR_NET_MAX)) {
 639                 /* DDR network side */
 640                 BUG();  /* MN access can not come here */
 641         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 642              QLA82XX_ADDR_OCM0_MAX)) {
 643                 return 1;
 644         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 645              QLA82XX_ADDR_OCM1_MAX)) {
 646                 return 1;
 647         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 648             qdr_max)) {
 649                 /* QDR network side */
 650                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 651                 if (ha->qdr_sn_window == window)
 652                         return 1;
 653         }
 654
 655         return 0;
 656 }
 657
 658 #ifndef readq
 659 static inline __u64 readq(const volatile void __iomem *addr)
 660 {
 661         const volatile u32 __iomem *p = addr;
 662         u32 low, high;
 663
 664         low = readl(p);
 665         high = readl(p + 1);
 666
 667         return low + ((u64)high << 32);
 668 }
 669 #endif
 670
 671 #ifndef writeq
 672 static inline void writeq(__u64 val, volatile void __iomem *addr)
 673 {
 674         writel(val, addr);
 675         writel(val >> 32, addr+4);
 676 }
 677 #endif
 678
 679 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
 680                 u64 off, void *data, int size)
 681 {
 682         unsigned long flags;
 683         void __iomem *addr;
 684         int ret = 0;
 685         u64 start;
 686         void __iomem *mem_ptr = NULL;
 687         unsigned long mem_base;
 688         unsigned long mem_page;
 689
 690         write_lock_irqsave(&ha->hw_lock, flags);
 691
 692         /*
 693          * If attempting to access unknown address or straddle hw windows,
 694          * do not access.
 695          */
 696         start = qla4_8xxx_pci_set_window(ha, off);
 697         if ((start == -1UL) ||
 698             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 699                 write_unlock_irqrestore(&ha->hw_lock, flags);
 700                 printk(KERN_ERR"%s out of bound pci memory access. "
 701                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 702                 return -1;
 703         }
 704
 705         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 706         if (!addr) {
 707                 write_unlock_irqrestore(&ha->hw_lock, flags);
 708                 mem_base = pci_resource_start(ha->pdev, 0);
 709                 mem_page = start & PAGE_MASK;
 710                 /* Map two pages whenever user tries to access addresses in two
 711                    consecutive pages.
 712                  */
 713                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 714                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 715                 else
 716                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 717
 718                 if (mem_ptr == NULL) {
 719                         *(u8 *)data = 0;
 720                         return -1;
 721                 }
 722                 addr = mem_ptr;
 723                 addr += start & (PAGE_SIZE - 1);
 724                 write_lock_irqsave(&ha->hw_lock, flags);
 725         }
 726
 727         switch (size) {
 728         case 1:
 729                 *(u8  *)data = readb(addr);
 730                 break;
 731         case 2:
 732                 *(u16 *)data = readw(addr);
 733                 break;
 734         case 4:
 735                 *(u32 *)data = readl(addr);
 736                 break;
 737         case 8:
 738                 *(u64 *)data = readq(addr);
 739                 break;
 740         default:
 741                 ret = -1;
 742                 break;
 743         }
 744         write_unlock_irqrestore(&ha->hw_lock, flags);
 745
 746         if (mem_ptr)
 747                 iounmap(mem_ptr);
 748         return ret;
 749 }
 750
 751 static int
 752 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 753                 void *data, int size)
 754 {
 755         unsigned long flags;
 756         void __iomem *addr;
 757         int ret = 0;
 758         u64 start;
 759         void __iomem *mem_ptr = NULL;
 760         unsigned long mem_base;
 761         unsigned long mem_page;
 762
 763         write_lock_irqsave(&ha->hw_lock, flags);
 764
 765         /*
 766          * If attempting to access unknown address or straddle hw windows,
 767          * do not access.
 768          */
 769         start = qla4_8xxx_pci_set_window(ha, off);
 770         if ((start == -1UL) ||
 771             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 772                 write_unlock_irqrestore(&ha->hw_lock, flags);
 773                 printk(KERN_ERR"%s out of bound pci memory access. "
 774                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 775                 return -1;
 776         }
 777
 778         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 779         if (!addr) {
 780                 write_unlock_irqrestore(&ha->hw_lock, flags);
 781                 mem_base = pci_resource_start(ha->pdev, 0);
 782                 mem_page = start & PAGE_MASK;
 783                 /* Map two pages whenever user tries to access addresses in two
 784                    consecutive pages.
 785                  */
 786                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 787                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 788                 else
 789                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 790                 if (mem_ptr == NULL)
 791                         return -1;
 792
 793                 addr = mem_ptr;
 794                 addr += start & (PAGE_SIZE - 1);
 795                 write_lock_irqsave(&ha->hw_lock, flags);
 796         }
 797
 798         switch (size) {
 799         case 1:
 800                 writeb(*(u8 *)data, addr);
 801                 break;
 802         case 2:
 803                 writew(*(u16 *)data, addr);
 804                 break;
 805         case 4:
 806                 writel(*(u32 *)data, addr);
 807                 break;
 808         case 8:
 809                 writeq(*(u64 *)data, addr);
 810                 break;
 811         default:
 812                 ret = -1;
 813                 break;
 814         }
 815         write_unlock_irqrestore(&ha->hw_lock, flags);
 816         if (mem_ptr)
 817                 iounmap(mem_ptr);
 818         return ret;
 819 }
 820
 821 #define MTU_FUDGE_FACTOR 100
 822
 823 static unsigned long
 824 qla4_8xxx_decode_crb_addr(unsigned long addr)
 825 {
 826         int i;
 827         unsigned long base_addr, offset, pci_base;
 828
 829         if (!qla4_8xxx_crb_table_initialized)
 830                 qla4_8xxx_crb_addr_transform_setup();
 831
 832         pci_base = ADDR_ERROR;
 833         base_addr = addr & 0xfff00000;
 834         offset = addr & 0x000fffff;
 835
 836         for (i = 0; i < MAX_CRB_XFORM; i++) {
 837                 if (crb_addr_xform[i] == base_addr) {
 838                         pci_base = i << 20;
 839                         break;
 840                 }
 841         }
 842         if (pci_base == ADDR_ERROR)
 843                 return pci_base;
 844         else
 845                 return pci_base + offset;
 846 }
 847
 848 static long rom_max_timeout = 100;
 849 static long qla4_8xxx_rom_lock_timeout = 100;
 850
 851 static int
 852 qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
 853 {
 854         int i;
 855         int done = 0, timeout = 0;
 856
 857         while (!done) {
 858                 /* acquire semaphore2 from PCI HW block */
 859
 860                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 861                 if (done == 1)
 862                         break;
 863                 if (timeout >= qla4_8xxx_rom_lock_timeout) {
 864                         ql4_printk(KERN_WARNING, ha,
 865                             "%s: Failed to acquire rom lock", __func__);
 866                         return -1;
 867                 }
 868
 869                 timeout++;
 870
 871                 /* Yield CPU */
 872                 if (!in_interrupt())
 873                         schedule();
 874                 else {
 875                         for (i = 0; i < 20; i++)
 876                                 cpu_relax();    /*This a nop instr on i386*/
 877                 }
 878         }
 879         qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 880         return 0;
 881 }
 882
 883 static void
 884 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
 885 {
 886         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 887 }
 888
 889 static int
 890 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
 891 {
 892         long timeout = 0;
 893         long done = 0 ;
 894
 895         while (done == 0) {
 896                 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 897                 done &= 2;
 898                 timeout++;
 899                 if (timeout >= rom_max_timeout) {
 900                         printk("%s: Timeout reached  waiting for rom done",
 901                                         DRIVER_NAME);
 902                         return -1;
 903                 }
 904         }
 905         return 0;
 906 }
 907
 908 static int
 909 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 910 {
 911         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 912         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 913         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 914         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 915         if (qla4_8xxx_wait_rom_done(ha)) {
 916                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 917                 return -1;
 918         }
 919         /* reset abyte_cnt and dummy_byte_cnt */
 920         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 921         udelay(10);
 922         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 923
 924         *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 925         return 0;
 926 }
 927
 928 static int
 929 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 930 {
 931         int ret, loops = 0;
 932
 933         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
 934                 udelay(100);
 935                 loops++;
 936         }
 937         if (loops >= 50000) {
 938                 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
 939                 return -1;
 940         }
 941         ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
 942         qla4_8xxx_rom_unlock(ha);
 943         return ret;
 944 }
 945
 946 /**
 947  * This routine does CRB initialize sequence
 948  * to put the ISP into operational state
 949  **/
 950 static int
 951 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 952 {
 953         int addr, val;
 954         int i ;
 955         struct crb_addr_pair *buf;
 956         unsigned long off;
 957         unsigned offset, n;
 958
 959         struct crb_addr_pair {
 960                 long addr;
 961                 long data;
 962         };
 963
 964         /* Halt all the indiviual PEGs and other blocks of the ISP */
 965         qla4_8xxx_rom_lock(ha);
 966
 967         /* disable all I2Q */
 968         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 969         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 970         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
 971         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
 972         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
 973         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
 974
 975         /* disable all niu interrupts */
 976         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
 977         /* disable xge rx/tx */
 978         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
 979         /* disable xg1 rx/tx */
 980         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
 981         /* disable sideband mac */
 982         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
 983         /* disable ap0 mac */
 984         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
 985         /* disable ap1 mac */
 986         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
 987
 988         /* halt sre */
 989         val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
 990         qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
 991
 992         /* halt epg */
 993         qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
 994
 995         /* halt timers */
 996         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
 997         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
 998         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
 999         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1000         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1001         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1002
1003         /* halt pegs */
1004         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1005         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1006         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1007         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1008         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1009         msleep(5);
1010
1011         /* big hammer */
1012         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1013                 /* don't reset CAM block on reset */
1014                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1015         else
1016                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1017
1018         /* reset ms */
1019         val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1020         val |= (1 << 1);
1021         qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1022
1023         msleep(20);
1024         /* unreset ms */
1025         val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1026         val &= ~(1 << 1);
1027         qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1028         msleep(20);
1029
1030         qla4_8xxx_rom_unlock(ha);
1031
1032         /* Read the signature value from the flash.
1033          * Offset 0: Contain signature (0xcafecafe)
1034          * Offset 4: Offset and number of addr/value pairs
1035          * that present in CRB initialize sequence
1036          */
1037         if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1038             qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
1039                 ql4_printk(KERN_WARNING, ha,
1040                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1041                 return -1;
1042         }
1043
1044         /* Offset in flash = lower 16 bits
1045          * Number of enteries = upper 16 bits
1046          */
1047         offset = n & 0xffffU;
1048         n = (n >> 16) & 0xffffU;
1049
1050         /* number of addr/value pair should not exceed 1024 enteries */
1051         if (n  >= 1024) {
1052                 ql4_printk(KERN_WARNING, ha,
1053                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1054                     DRIVER_NAME, __func__, n);
1055                 return -1;
1056         }
1057
1058         ql4_printk(KERN_INFO, ha,
1059                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1060
1061         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1062         if (buf == NULL) {
1063                 ql4_printk(KERN_WARNING, ha,
1064                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1065                 return -1;
1066         }
1067
1068         for (i = 0; i < n; i++) {
1069                 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1070                     qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1071                     0) {
1072                         kfree(buf);
1073                         return -1;
1074                 }
1075
1076                 buf[i].addr = addr;
1077                 buf[i].data = val;
1078         }
1079
1080         for (i = 0; i < n; i++) {
1081                 /* Translate internal CRB initialization
1082                  * address to PCI bus address
1083                  */
1084                 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1085                     QLA82XX_PCI_CRBSPACE;
1086                 /* Not all CRB  addr/value pair to be written,
1087                  * some of them are skipped
1088                  */
1089
1090                 /* skip if LS bit is set*/
1091                 if (off & 0x1) {
1092                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1093                             "Skip CRB init replay for offset = 0x%lx\n", off));
1094                         continue;
1095                 }
1096
1097                 /* skipping cold reboot MAGIC */
1098                 if (off == QLA82XX_CAM_RAM(0x1fc))
1099                         continue;
1100
1101                 /* do not reset PCI */
1102                 if (off == (ROMUSB_GLB + 0xbc))
1103                         continue;
1104
1105                 /* skip core clock, so that firmware can increase the clock */
1106                 if (off == (ROMUSB_GLB + 0xc8))
1107                         continue;
1108
1109                 /* skip the function enable register */
1110                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1111                         continue;
1112
1113                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1114                         continue;
1115
1116                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1117                         continue;
1118
1119                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1120                         continue;
1121
1122                 if (off == ADDR_ERROR) {
1123                         ql4_printk(KERN_WARNING, ha,
1124                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1125                             DRIVER_NAME, buf[i].addr);
1126                         continue;
1127                 }
1128
1129                 qla4_8xxx_wr_32(ha, off, buf[i].data);
1130
1131                 /* ISP requires much bigger delay to settle down,
1132                  * else crb_window returns 0xffffffff
1133                  */
1134                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1135                         msleep(1000);
1136
1137                 /* ISP requires millisec delay between
1138                  * successive CRB register updation
1139                  */
1140                 msleep(1);
1141         }
1142
1143         kfree(buf);
1144
1145         /* Resetting the data and instruction cache */
1146         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1147         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1148         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1149
1150         /* Clear all protocol processing engines */
1151         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1152         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1153         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1154         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1155         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1156         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1157         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1158         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1159
1160         return 0;
1161 }
1162
1163 static int
1164 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1165 {
1166         int  i, rval = 0;
1167         long size = 0;
1168         long flashaddr, memaddr;
1169         u64 data;
1170         u32 high, low;
1171
1172         flashaddr = memaddr = ha->hw.flt_region_bootload;
1173         size = (image_start - flashaddr) / 8;
1174
1175         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1176             ha->host_no, __func__, flashaddr, image_start));
1177
1178         for (i = 0; i < size; i++) {
1179                 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1180                     (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1181                     (int *)&high))) {
1182                         rval = -1;
1183                         goto exit_load_from_flash;
1184                 }
1185                 data = ((u64)high << 32) | low ;
1186                 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1187                 if (rval)
1188                         goto exit_load_from_flash;
1189
1190                 flashaddr += 8;
1191                 memaddr   += 8;
1192
1193                 if (i % 0x1000 == 0)
1194                         msleep(1);
1195
1196         }
1197
1198         udelay(100);
1199
1200         read_lock(&ha->hw_lock);
1201         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1202         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1203         read_unlock(&ha->hw_lock);
1204
1205 exit_load_from_flash:
1206         return rval;
1207 }
1208
1209 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1210 {
1211         u32 rst;
1212
1213         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1214         if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1215                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1216                     __func__);
1217                 return QLA_ERROR;
1218         }
1219
1220         udelay(500);
1221
1222         /* at this point, QM is in reset. This could be a problem if there are
1223          * incoming d* transition queue messages. QM/PCIE could wedge.
1224          * To get around this, QM is brought out of reset.
1225          */
1226
1227         rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1228         /* unreset qm */
1229         rst &= ~(1 << 28);
1230         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1231
1232         if (qla4_8xxx_load_from_flash(ha, image_start)) {
1233                 printk("%s: Error trying to load fw from flash!\n", __func__);
1234                 return QLA_ERROR;
1235         }
1236
1237         return QLA_SUCCESS;
1238 }
1239
1240 int
1241 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1242                 u64 off, void *data, int size)
1243 {
1244         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1245         int shift_amount;
1246         uint32_t temp;
1247         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1248
1249         /*
1250          * If not MN, go check for MS or invalid.
1251          */
1252
1253         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1254                 mem_crb = QLA82XX_CRB_QDR_NET;
1255         else {
1256                 mem_crb = QLA82XX_CRB_DDR_NET;
1257                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1258                         return qla4_8xxx_pci_mem_read_direct(ha,
1259                                         off, data, size);
1260         }
1261
1262
1263         off8 = off & 0xfffffff0;
1264         off0[0] = off & 0xf;
1265         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1266         shift_amount = 4;
1267
1268         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1269         off0[1] = 0;
1270         sz[1] = size - sz[0];
1271
1272         for (i = 0; i < loop; i++) {
1273                 temp = off8 + (i << shift_amount);
1274                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1275                 temp = 0;
1276                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1277                 temp = MIU_TA_CTL_ENABLE;
1278                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1279                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1280                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1281
1282                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1283                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1284                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1285                                 break;
1286                 }
1287
1288                 if (j >= MAX_CTL_CHECK) {
1289                         if (printk_ratelimit())
1290                                 ql4_printk(KERN_ERR, ha,
1291                                     "failed to read through agent\n");
1292                         break;
1293                 }
1294
1295                 start = off0[i] >> 2;
1296                 end   = (off0[i] + sz[i] - 1) >> 2;
1297                 for (k = start; k <= end; k++) {
1298                         temp = qla4_8xxx_rd_32(ha,
1299                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1300                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1301                 }
1302         }
1303
1304         if (j >= MAX_CTL_CHECK)
1305                 return -1;
1306
1307         if ((off0[0] & 7) == 0) {
1308                 val = word[0];
1309         } else {
1310                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1311                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1312         }
1313
1314         switch (size) {
1315         case 1:
1316                 *(uint8_t  *)data = val;
1317                 break;
1318         case 2:
1319                 *(uint16_t *)data = val;
1320                 break;
1321         case 4:
1322                 *(uint32_t *)data = val;
1323                 break;
1324         case 8:
1325                 *(uint64_t *)data = val;
1326                 break;
1327         }
1328         return 0;
1329 }
1330
1331 int
1332 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1333                 u64 off, void *data, int size)
1334 {
1335         int i, j, ret = 0, loop, sz[2], off0;
1336         int scale, shift_amount, startword;
1337         uint32_t temp;
1338         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340         /*
1341          * If not MN, go check for MS or invalid.
1342          */
1343         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344                 mem_crb = QLA82XX_CRB_QDR_NET;
1345         else {
1346                 mem_crb = QLA82XX_CRB_DDR_NET;
1347                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1348                         return qla4_8xxx_pci_mem_write_direct(ha,
1349                                         off, data, size);
1350         }
1351
1352         off0 = off & 0x7;
1353         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354         sz[1] = size - sz[0];
1355
1356         off8 = off & 0xfffffff0;
1357         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358         shift_amount = 4;
1359         scale = 2;
1360         startword = (off & 0xf)/8;
1361
1362         for (i = 0; i < loop; i++) {
1363                 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1364                     (i << shift_amount), &word[i * scale], 8))
1365                         return -1;
1366         }
1367
1368         switch (size) {
1369         case 1:
1370                 tmpw = *((uint8_t *)data);
1371                 break;
1372         case 2:
1373                 tmpw = *((uint16_t *)data);
1374                 break;
1375         case 4:
1376                 tmpw = *((uint32_t *)data);
1377                 break;
1378         case 8:
1379         default:
1380                 tmpw = *((uint64_t *)data);
1381                 break;
1382         }
1383
1384         if (sz[0] == 8)
1385                 word[startword] = tmpw;
1386         else {
1387                 word[startword] &=
1388                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1389                 word[startword] |= tmpw << (off0 * 8);
1390         }
1391
1392         if (sz[1] != 0) {
1393                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1394                 word[startword+1] |= tmpw >> (sz[0] * 8);
1395         }
1396
1397         for (i = 0; i < loop; i++) {
1398                 temp = off8 + (i << shift_amount);
1399                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1400                 temp = 0;
1401                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1402                 temp = word[i * scale] & 0xffffffff;
1403                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1404                 temp = (word[i * scale] >> 32) & 0xffffffff;
1405                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1406                 temp = word[i*scale + 1] & 0xffffffff;
1407                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1408                     temp);
1409                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1410                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1411                     temp);
1412
1413                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1414                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1415                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1416                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1417
1418                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1419                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1420                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1421                                 break;
1422                 }
1423
1424                 if (j >= MAX_CTL_CHECK) {
1425                         if (printk_ratelimit())
1426                                 ql4_printk(KERN_ERR, ha,
1427                                     "failed to write through agent\n");
1428                         ret = -1;
1429                         break;
1430                 }
1431         }
1432
1433         return ret;
1434 }
1435
1436 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1437 {
1438         u32 val = 0;
1439         int retries = 60;
1440
1441         if (!pegtune_val) {
1442                 do {
1443                         val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1444                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1445                             (val == PHAN_INITIALIZE_ACK))
1446                                 return 0;
1447                         set_current_state(TASK_UNINTERRUPTIBLE);
1448                         schedule_timeout(500);
1449
1450                 } while (--retries);
1451
1452                 if (!retries) {
1453                         pegtune_val = qla4_8xxx_rd_32(ha,
1454                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1455                         printk(KERN_WARNING "%s: init failed, "
1456                                 "pegtune_val = %x\n", __func__, pegtune_val);
1457                         return -1;
1458                 }
1459         }
1460         return 0;
1461 }
1462
1463 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1464 {
1465         uint32_t state = 0;
1466         int loops = 0;
1467
1468         /* Window 1 call */
1469         read_lock(&ha->hw_lock);
1470         state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1471         read_unlock(&ha->hw_lock);
1472
1473         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1474                 udelay(100);
1475                 /* Window 1 call */
1476                 read_lock(&ha->hw_lock);
1477                 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1478                 read_unlock(&ha->hw_lock);
1479
1480                 loops++;
1481         }
1482
1483         if (loops >= 30000) {
1484                 DEBUG2(ql4_printk(KERN_INFO, ha,
1485                     "Receive Peg initialization not complete: 0x%x.\n", state));
1486                 return QLA_ERROR;
1487         }
1488
1489         return QLA_SUCCESS;
1490 }
1491
1492 void
1493 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1494 {
1495         uint32_t drv_active;
1496
1497         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1498         drv_active |= (1 << (ha->func_num * 4));
1499         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1500 }
1501
1502 void
1503 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1504 {
1505         uint32_t drv_active;
1506
1507         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1508         drv_active &= ~(1 << (ha->func_num * 4));
1509         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1510 }
1511
1512 static inline int
1513 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1514 {
1515         uint32_t drv_state, drv_active;
1516         int rval;
1517
1518         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1519         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1520         rval = drv_state & (1 << (ha->func_num * 4));
1521         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1522                 rval = 1;
1523
1524         return rval;
1525 }
1526
1527 static inline void
1528 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1529 {
1530         uint32_t drv_state;
1531
1532         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1533         drv_state |= (1 << (ha->func_num * 4));
1534         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1535 }
1536
1537 static inline void
1538 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1539 {
1540         uint32_t drv_state;
1541
1542         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1543         drv_state &= ~(1 << (ha->func_num * 4));
1544         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1545 }
1546
1547 static inline void
1548 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1549 {
1550         uint32_t qsnt_state;
1551
1552         qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1553         qsnt_state |= (2 << (ha->func_num * 4));
1554         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1555 }
1556
1557
1558 static int
1559 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1560 {
1561         int pcie_cap;
1562         uint16_t lnk;
1563
1564         /* scrub dma mask expansion register */
1565         qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1566
1567         /* Overwrite stale initialization register values */
1568         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1569         qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1570         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1571         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1572
1573         if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1574                 printk("%s: Error trying to start fw!\n", __func__);
1575                 return QLA_ERROR;
1576         }
1577
1578         /* Handshake with the card before we register the devices. */
1579         if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1580                 printk("%s: Error during card handshake!\n", __func__);
1581                 return QLA_ERROR;
1582         }
1583
1584         /* Negotiated Link width */
1585         pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1586         pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1587         ha->link_width = (lnk >> 4) & 0x3f;
1588
1589         /* Synchronize with Receive peg */
1590         return qla4_8xxx_rcvpeg_ready(ha);
1591 }
1592
1593 static int
1594 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1595 {
1596         int rval = QLA_ERROR;
1597
1598         /*
1599          * FW Load priority:
1600          * 1) Operational firmware residing in flash.
1601          * 2) Fail
1602          */
1603
1604         ql4_printk(KERN_INFO, ha,
1605             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1606         rval = qla4_8xxx_get_flash_info(ha);
1607         if (rval != QLA_SUCCESS)
1608                 return rval;
1609
1610         ql4_printk(KERN_INFO, ha,
1611             "FW: Attempting to load firmware from flash...\n");
1612         rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1613
1614         if (rval != QLA_SUCCESS) {
1615                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1616                     " FAILED...\n");
1617                 return rval;
1618         }
1619
1620         return rval;
1621 }
1622
1623 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1624 {
1625         if (qla4_8xxx_rom_lock(ha)) {
1626                 /* Someone else is holding the lock. */
1627                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1628         }
1629
1630         /*
1631          * Either we got the lock, or someone
1632          * else died while holding it.
1633          * In either case, unlock.
1634          */
1635         qla4_8xxx_rom_unlock(ha);
1636 }
1637
1638 /**
1639  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1640  * @ha: pointer to adapter structure
1641  *
1642  * Note: IDC lock must be held upon entry
1643  **/
1644 static int
1645 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
1646 {
1647         int rval = QLA_ERROR;
1648         int i, timeout;
1649         uint32_t old_count, count;
1650         int need_reset = 0, peg_stuck = 1;
1651
1652         need_reset = qla4_8xxx_need_reset(ha);
1653
1654         old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1655
1656         for (i = 0; i < 10; i++) {
1657                 timeout = msleep_interruptible(200);
1658                 if (timeout) {
1659                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1660                            QLA82XX_DEV_FAILED);
1661                         return rval;
1662                 }
1663
1664                 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1665                 if (count != old_count)
1666                         peg_stuck = 0;
1667         }
1668
1669         if (need_reset) {
1670                 /* We are trying to perform a recovery here. */
1671                 if (peg_stuck)
1672                         qla4_8xxx_rom_lock_recovery(ha);
1673                 goto dev_initialize;
1674         } else  {
1675                 /* Start of day for this ha context. */
1676                 if (peg_stuck) {
1677                         /* Either we are the first or recovery in progress. */
1678                         qla4_8xxx_rom_lock_recovery(ha);
1679                         goto dev_initialize;
1680                 } else {
1681                         /* Firmware already running. */
1682                         rval = QLA_SUCCESS;
1683                         goto dev_ready;
1684                 }
1685         }
1686
1687 dev_initialize:
1688         /* set to DEV_INITIALIZING */
1689         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
1690         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
1691
1692         /* Driver that sets device state to initializating sets IDC version */
1693         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
1694
1695         qla4_8xxx_idc_unlock(ha);
1696         rval = qla4_8xxx_try_start_fw(ha);
1697         qla4_8xxx_idc_lock(ha);
1698
1699         if (rval != QLA_SUCCESS) {
1700                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
1701                 qla4_8xxx_clear_drv_active(ha);
1702                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
1703                 return rval;
1704         }
1705
1706 dev_ready:
1707         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
1708         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
1709
1710         return rval;
1711 }
1712
1713 /**
1714  * qla4_8xxx_need_reset_handler - Code to start reset sequence
1715  * @ha: pointer to adapter structure
1716  *
1717  * Note: IDC lock must be held upon entry
1718  **/
1719 static void
1720 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
1721 {
1722         uint32_t dev_state, drv_state, drv_active;
1723         unsigned long reset_timeout;
1724
1725         ql4_printk(KERN_INFO, ha,
1726                 "Performing ISP error recovery\n");
1727
1728         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
1729                 qla4_8xxx_idc_unlock(ha);
1730                 ha->isp_ops->disable_intrs(ha);
1731                 qla4_8xxx_idc_lock(ha);
1732         }
1733
1734         qla4_8xxx_set_rst_ready(ha);
1735
1736         /* wait for 10 seconds for reset ack from all functions */
1737         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
1738
1739         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1740         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1741
1742         ql4_printk(KERN_INFO, ha,
1743                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1744                 __func__, ha->host_no, drv_state, drv_active);
1745
1746         while (drv_state != drv_active) {
1747                 if (time_after_eq(jiffies, reset_timeout)) {
1748                         printk("%s: RESET TIMEOUT!\n", DRIVER_NAME);
1749                         break;
1750                 }
1751
1752                 qla4_8xxx_idc_unlock(ha);
1753                 msleep(1000);
1754                 qla4_8xxx_idc_lock(ha);
1755
1756                 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1757                 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1758         }
1759
1760         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1761         ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
1762                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1763
1764         /* Force to DEV_COLD unless someone else is starting a reset */
1765         if (dev_state != QLA82XX_DEV_INITIALIZING) {
1766                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
1767                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
1768         }
1769 }
1770
1771 /**
1772  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1773  * @ha: pointer to adapter structure
1774  **/
1775 void
1776 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
1777 {
1778         qla4_8xxx_idc_lock(ha);
1779         qla4_8xxx_set_qsnt_ready(ha);
1780         qla4_8xxx_idc_unlock(ha);
1781 }
1782
1783 /**
1784  * qla4_8xxx_device_state_handler - Adapter state machine
1785  * @ha: pointer to host adapter structure.
1786  *
1787  * Note: IDC lock must be UNLOCKED upon entry
1788  **/
1789 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
1790 {
1791         uint32_t dev_state;
1792         int rval = QLA_SUCCESS;
1793         unsigned long dev_init_timeout;
1794
1795         if (!test_bit(AF_INIT_DONE, &ha->flags))
1796                 qla4_8xxx_set_drv_active(ha);
1797
1798         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1799         ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
1800                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1801
1802         /* wait for 30 seconds for device to go ready */
1803         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
1804
1805         while (1) {
1806                 qla4_8xxx_idc_lock(ha);
1807
1808                 if (time_after_eq(jiffies, dev_init_timeout)) {
1809                         ql4_printk(KERN_WARNING, ha, "Device init failed!\n");
1810                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1811                                 QLA82XX_DEV_FAILED);
1812                 }
1813
1814                 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1815                 ql4_printk(KERN_INFO, ha,
1816                     "2:Device state is 0x%x = %s\n", dev_state,
1817                     dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1818
1819                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1820                 switch (dev_state) {
1821                 case QLA82XX_DEV_READY:
1822                         qla4_8xxx_idc_unlock(ha);
1823                         goto exit;
1824                 case QLA82XX_DEV_COLD:
1825                         rval = qla4_8xxx_device_bootstrap(ha);
1826                         qla4_8xxx_idc_unlock(ha);
1827                         goto exit;
1828                 case QLA82XX_DEV_INITIALIZING:
1829                         qla4_8xxx_idc_unlock(ha);
1830                         msleep(1000);
1831                         break;
1832                 case QLA82XX_DEV_NEED_RESET:
1833                         if (!ql4xdontresethba) {
1834                                 qla4_8xxx_need_reset_handler(ha);
1835                                 /* Update timeout value after need
1836                                  * reset handler */
1837                                 dev_init_timeout = jiffies +
1838                                         (ha->nx_dev_init_timeout * HZ);
1839                         }
1840                         qla4_8xxx_idc_unlock(ha);
1841                         break;
1842                 case QLA82XX_DEV_NEED_QUIESCENT:
1843                         qla4_8xxx_idc_unlock(ha);
1844                         /* idc locked/unlocked in handler */
1845                         qla4_8xxx_need_qsnt_handler(ha);
1846                         qla4_8xxx_idc_lock(ha);
1847                         /* fall thru needs idc_locked */
1848                 case QLA82XX_DEV_QUIESCENT:
1849                         qla4_8xxx_idc_unlock(ha);
1850                         msleep(1000);
1851                         break;
1852                 case QLA82XX_DEV_FAILED:
1853                         qla4_8xxx_idc_unlock(ha);
1854                         qla4xxx_dead_adapter_cleanup(ha);
1855                         rval = QLA_ERROR;
1856                         goto exit;
1857                 default:
1858                         qla4_8xxx_idc_unlock(ha);
1859                         qla4xxx_dead_adapter_cleanup(ha);
1860                         rval = QLA_ERROR;
1861                         goto exit;
1862                 }
1863         }
1864 exit:
1865         return rval;
1866 }
1867
1868 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
1869 {
1870         int retval;
1871         retval = qla4_8xxx_device_state_handler(ha);
1872
1873         if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
1874                 retval = qla4xxx_request_irqs(ha);
1875
1876         return retval;
1877 }
1878
1879 /*****************************************************************************/
1880 /* Flash Manipulation Routines                                               */
1881 /*****************************************************************************/
1882
1883 #define OPTROM_BURST_SIZE       0x1000
1884 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
1885
1886 #define FARX_DATA_FLAG  BIT_31
1887 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
1888 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
1889
1890 static inline uint32_t
1891 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1892 {
1893         return hw->flash_conf_off | faddr;
1894 }
1895
1896 static inline uint32_t
1897 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1898 {
1899         return hw->flash_data_off | faddr;
1900 }
1901
1902 static uint32_t *
1903 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
1904     uint32_t faddr, uint32_t length)
1905 {
1906         uint32_t i;
1907         uint32_t val;
1908         int loops = 0;
1909         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
1910                 udelay(100);
1911                 cond_resched();
1912                 loops++;
1913         }
1914         if (loops >= 50000) {
1915                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
1916                 return dwptr;
1917         }
1918
1919         /* Dword reads to flash. */
1920         for (i = 0; i < length/4; i++, faddr += 4) {
1921                 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
1922                         ql4_printk(KERN_WARNING, ha,
1923                             "Do ROM fast read failed\n");
1924                         goto done_read;
1925                 }
1926                 dwptr[i] = __constant_cpu_to_le32(val);
1927         }
1928
1929 done_read:
1930         qla4_8xxx_rom_unlock(ha);
1931         return dwptr;
1932 }
1933
1934 /**
1935  * Address and length are byte address
1936  **/
1937 static uint8_t *
1938 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1939                 uint32_t offset, uint32_t length)
1940 {
1941         qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
1942         return buf;
1943 }
1944
1945 static int
1946 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
1947 {
1948         const char *loc, *locations[] = { "DEF", "PCI" };
1949
1950         /*
1951          * FLT-location structure resides after the last PCI region.
1952          */
1953
1954         /* Begin with sane defaults. */
1955         loc = locations[0];
1956         *start = FA_FLASH_LAYOUT_ADDR_82;
1957
1958         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
1959         return QLA_SUCCESS;
1960 }
1961
1962 static void
1963 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
1964 {
1965         const char *loc, *locations[] = { "DEF", "FLT" };
1966         uint16_t *wptr;
1967         uint16_t cnt, chksum;
1968         uint32_t start;
1969         struct qla_flt_header *flt;
1970         struct qla_flt_region *region;
1971         struct ql82xx_hw_data *hw = &ha->hw;
1972
1973         hw->flt_region_flt = flt_addr;
1974         wptr = (uint16_t *)ha->request_ring;
1975         flt = (struct qla_flt_header *)ha->request_ring;
1976         region = (struct qla_flt_region *)&flt[1];
1977         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1978                         flt_addr << 2, OPTROM_BURST_SIZE);
1979         if (*wptr == __constant_cpu_to_le16(0xffff))
1980                 goto no_flash_data;
1981         if (flt->version != __constant_cpu_to_le16(1)) {
1982                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
1983                         "version=0x%x length=0x%x checksum=0x%x.\n",
1984                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1985                         le16_to_cpu(flt->checksum)));
1986                 goto no_flash_data;
1987         }
1988
1989         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
1990         for (chksum = 0; cnt; cnt--)
1991                 chksum += le16_to_cpu(*wptr++);
1992         if (chksum) {
1993                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
1994                         "version=0x%x length=0x%x checksum=0x%x.\n",
1995                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1996                         chksum));
1997                 goto no_flash_data;
1998         }
1999
2000         loc = locations[1];
2001         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2002         for ( ; cnt; cnt--, region++) {
2003                 /* Store addresses as DWORD offsets. */
2004                 start = le32_to_cpu(region->start) >> 2;
2005
2006                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
2007                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
2008                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
2009
2010                 switch (le32_to_cpu(region->code) & 0xff) {
2011                 case FLT_REG_FDT:
2012                         hw->flt_region_fdt = start;
2013                         break;
2014                 case FLT_REG_BOOT_CODE_82:
2015                         hw->flt_region_boot = start;
2016                         break;
2017                 case FLT_REG_FW_82:
2018                         hw->flt_region_fw = start;
2019                         break;
2020                 case FLT_REG_BOOTLOAD_82:
2021                         hw->flt_region_bootload = start;
2022                         break;
2023                 }
2024         }
2025         goto done;
2026
2027 no_flash_data:
2028         /* Use hardcoded defaults. */
2029         loc = locations[0];
2030
2031         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
2032         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
2033         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2034         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
2035 done:
2036         DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2037             "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2038             hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2039             hw->flt_region_fw));
2040 }
2041
2042 static void
2043 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2044 {
2045 #define FLASH_BLK_SIZE_4K       0x1000
2046 #define FLASH_BLK_SIZE_32K      0x8000
2047 #define FLASH_BLK_SIZE_64K      0x10000
2048         const char *loc, *locations[] = { "MID", "FDT" };
2049         uint16_t cnt, chksum;
2050         uint16_t *wptr;
2051         struct qla_fdt_layout *fdt;
2052         uint16_t mid = 0;
2053         uint16_t fid = 0;
2054         struct ql82xx_hw_data *hw = &ha->hw;
2055
2056         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2057         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2058
2059         wptr = (uint16_t *)ha->request_ring;
2060         fdt = (struct qla_fdt_layout *)ha->request_ring;
2061         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2062             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2063
2064         if (*wptr == __constant_cpu_to_le16(0xffff))
2065                 goto no_flash_data;
2066
2067         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2068             fdt->sig[3] != 'D')
2069                 goto no_flash_data;
2070
2071         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2072             cnt++)
2073                 chksum += le16_to_cpu(*wptr++);
2074
2075         if (chksum) {
2076                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2077                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2078                     le16_to_cpu(fdt->version)));
2079                 goto no_flash_data;
2080         }
2081
2082         loc = locations[1];
2083         mid = le16_to_cpu(fdt->man_id);
2084         fid = le16_to_cpu(fdt->id);
2085         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2086         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2087         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2088
2089         if (fdt->unprotect_sec_cmd) {
2090                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2091                     fdt->unprotect_sec_cmd);
2092                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2093                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2094                     flash_conf_addr(hw, 0x0336);
2095         }
2096         goto done;
2097
2098 no_flash_data:
2099         loc = locations[0];
2100         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2101 done:
2102         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2103                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2104                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2105                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2106                 hw->fdt_block_size));
2107 }
2108
2109 static void
2110 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2111 {
2112 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
2113         uint32_t *wptr;
2114
2115         if (!is_qla8022(ha))
2116                 return;
2117         wptr = (uint32_t *)ha->request_ring;
2118         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2119                         QLA82XX_IDC_PARAM_ADDR , 8);
2120
2121         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2122                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2123                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2124         } else {
2125                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2126                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2127         }
2128
2129         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2130                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2131         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2132                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2133         return;
2134 }
2135
2136 int
2137 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2138 {
2139         int ret;
2140         uint32_t flt_addr;
2141
2142         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2143         if (ret != QLA_SUCCESS)
2144                 return ret;
2145
2146         qla4_8xxx_get_flt_info(ha, flt_addr);
2147         qla4_8xxx_get_fdt_info(ha);
2148         qla4_8xxx_get_idc_param(ha);
2149
2150         return QLA_SUCCESS;
2151 }
2152
2153 /**
2154  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2155  * @ha: pointer to host adapter structure.
2156  *
2157  * Remarks:
2158  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2159  * not be available after successful return.  Driver must cleanup potential
2160  * outstanding I/O's after calling this funcion.
2161  **/
2162 int
2163 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2164 {
2165         int status;
2166         uint32_t mbox_cmd[MBOX_REG_COUNT];
2167         uint32_t mbox_sts[MBOX_REG_COUNT];
2168
2169         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2170         memset(&mbox_sts, 0, sizeof(mbox_sts));
2171
2172         mbox_cmd[0] = MBOX_CMD_STOP_FW;
2173         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2174             &mbox_cmd[0], &mbox_sts[0]);
2175
2176         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2177             __func__, status));
2178         return status;
2179 }
2180
2181 /**
2182  * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2183  * @ha: pointer to host adapter structure.
2184  **/
2185 int
2186 qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2187 {
2188         int rval;
2189         uint32_t dev_state;
2190
2191         qla4_8xxx_idc_lock(ha);
2192         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2193
2194         if (dev_state == QLA82XX_DEV_READY) {
2195                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2196                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2197                     QLA82XX_DEV_NEED_RESET);
2198         } else
2199                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2200
2201         qla4_8xxx_idc_unlock(ha);
2202
2203         rval = qla4_8xxx_device_state_handler(ha);
2204
2205         qla4_8xxx_idc_lock(ha);
2206         qla4_8xxx_clear_rst_ready(ha);
2207         qla4_8xxx_idc_unlock(ha);
2208
2209         if (rval == QLA_SUCCESS)
2210                 clear_bit(AF_FW_RECOVERY, &ha->flags);
2211
2212         return rval;
2213 }
2214
2215 /**
2216  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2217  * @ha: pointer to host adapter structure.
2218  *
2219  **/
2220 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2221 {
2222         uint32_t mbox_cmd[MBOX_REG_COUNT];
2223         uint32_t mbox_sts[MBOX_REG_COUNT];
2224         struct mbx_sys_info *sys_info;
2225         dma_addr_t sys_info_dma;
2226         int status = QLA_ERROR;
2227
2228         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2229                                       &sys_info_dma, GFP_KERNEL);
2230         if (sys_info == NULL) {
2231                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2232                     ha->host_no, __func__));
2233                 return status;
2234         }
2235
2236         memset(sys_info, 0, sizeof(*sys_info));
2237         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2238         memset(&mbox_sts, 0, sizeof(mbox_sts));
2239
2240         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2241         mbox_cmd[1] = LSDW(sys_info_dma);
2242         mbox_cmd[2] = MSDW(sys_info_dma);
2243         mbox_cmd[4] = sizeof(*sys_info);
2244
2245         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2246             &mbox_sts[0]) != QLA_SUCCESS) {
2247                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2248                     ha->host_no, __func__));
2249                 goto exit_validate_mac82;
2250         }
2251
2252         /* Make sure we receive the minimum required data to cache internally */
2253         if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
2254                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2255                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2256                 goto exit_validate_mac82;
2257
2258         }
2259
2260         /* Save M.A.C. address & serial_number */
2261         memcpy(ha->my_mac, &sys_info->mac_addr[0],
2262             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2263         memcpy(ha->serial_number, &sys_info->serial_number,
2264             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2265
2266         DEBUG2(printk("scsi%ld: %s: "
2267             "mac %02x:%02x:%02x:%02x:%02x:%02x "
2268             "serial %s\n", ha->host_no, __func__,
2269             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2270             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2271             ha->serial_number));
2272
2273         status = QLA_SUCCESS;
2274
2275 exit_validate_mac82:
2276         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2277                           sys_info_dma);
2278         return status;
2279 }
2280
2281 /* Interrupt handling helpers. */
2282
2283 static int
2284 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2285 {
2286         uint32_t mbox_cmd[MBOX_REG_COUNT];
2287         uint32_t mbox_sts[MBOX_REG_COUNT];
2288
2289         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2290
2291         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2292         memset(&mbox_sts, 0, sizeof(mbox_sts));
2293         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2294         mbox_cmd[1] = INTR_ENABLE;
2295         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2296                 &mbox_sts[0]) != QLA_SUCCESS) {
2297                 DEBUG2(ql4_printk(KERN_INFO, ha,
2298                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2299                     __func__, mbox_sts[0]));
2300                 return QLA_ERROR;
2301         }
2302         return QLA_SUCCESS;
2303 }
2304
2305 static int
2306 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
2307 {
2308         uint32_t mbox_cmd[MBOX_REG_COUNT];
2309         uint32_t mbox_sts[MBOX_REG_COUNT];
2310
2311         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2312
2313         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2314         memset(&mbox_sts, 0, sizeof(mbox_sts));
2315         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2316         mbox_cmd[1] = INTR_DISABLE;
2317         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2318             &mbox_sts[0]) != QLA_SUCCESS) {
2319                 DEBUG2(ql4_printk(KERN_INFO, ha,
2320                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2321                         __func__, mbox_sts[0]));
2322                 return QLA_ERROR;
2323         }
2324
2325         return QLA_SUCCESS;
2326 }
2327
2328 void
2329 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
2330 {
2331         qla4_8xxx_mbx_intr_enable(ha);
2332
2333         spin_lock_irq(&ha->hardware_lock);
2334         /* BIT 10 - reset */
2335         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2336         spin_unlock_irq(&ha->hardware_lock);
2337         set_bit(AF_INTERRUPTS_ON, &ha->flags);
2338 }
2339
2340 void
2341 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
2342 {
2343         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
2344                 qla4_8xxx_mbx_intr_disable(ha);
2345
2346         spin_lock_irq(&ha->hardware_lock);
2347         /* BIT 10 - set */
2348         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2349         spin_unlock_irq(&ha->hardware_lock);
2350 }
2351
2352 struct ql4_init_msix_entry {
2353         uint16_t entry;
2354         uint16_t index;
2355         const char *name;
2356         irq_handler_t handler;
2357 };
2358
2359 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
2360         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
2361             "qla4xxx (default)",
2362             (irq_handler_t)qla4_8xxx_default_intr_handler },
2363         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
2364             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
2365 };
2366
2367 void
2368 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
2369 {
2370         int i;
2371         struct ql4_msix_entry *qentry;
2372
2373         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2374                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2375                 if (qentry->have_irq) {
2376                         free_irq(qentry->msix_vector, ha);
2377                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2378                                 __func__, qla4_8xxx_msix_entries[i].name));
2379                 }
2380         }
2381         pci_disable_msix(ha->pdev);
2382         clear_bit(AF_MSIX_ENABLED, &ha->flags);
2383 }
2384
2385 int
2386 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
2387 {
2388         int i, ret;
2389         struct msix_entry entries[QLA_MSIX_ENTRIES];
2390         struct ql4_msix_entry *qentry;
2391
2392         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
2393                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
2394
2395         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
2396         if (ret) {
2397                 ql4_printk(KERN_WARNING, ha,
2398                     "MSI-X: Failed to enable support -- %d/%d\n",
2399                     QLA_MSIX_ENTRIES, ret);
2400                 goto msix_out;
2401         }
2402         set_bit(AF_MSIX_ENABLED, &ha->flags);
2403
2404         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2405                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2406                 qentry->msix_vector = entries[i].vector;
2407                 qentry->msix_entry = entries[i].entry;
2408                 qentry->have_irq = 0;
2409                 ret = request_irq(qentry->msix_vector,
2410                     qla4_8xxx_msix_entries[i].handler, 0,
2411                     qla4_8xxx_msix_entries[i].name, ha);
2412                 if (ret) {
2413                         ql4_printk(KERN_WARNING, ha,
2414                             "MSI-X: Unable to register handler -- %x/%d.\n",
2415                             qla4_8xxx_msix_entries[i].index, ret);
2416                         qla4_8xxx_disable_msix(ha);
2417                         goto msix_out;
2418                 }
2419                 qentry->have_irq = 1;
2420                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2421                         __func__, qla4_8xxx_msix_entries[i].name));
2422         }
2423 msix_out:
2424         return ret;
2425 }