drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/slab.h>
  11 #include <linux/vmalloc.h>
  12 #include <asm/uaccess.h>
  13
  14 /*
  15  * NVRAM support routines
  16  */
  17
  18 /**
  19  * qla2x00_lock_nvram_access() -
  20  * @ha: HA context
  21  */
  22 static void
  23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  24 {
  25         uint16_t data;
  26         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  27
  28         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  29                 data = RD_REG_WORD(&reg->nvram);
  30                 while (data & NVR_BUSY) {
  31                         udelay(100);
  32                         data = RD_REG_WORD(&reg->nvram);
  33                 }
  34
  35                 /* Lock resource */
  36                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  37                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  38                 udelay(5);
  39                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 while ((data & BIT_0) == 0) {
  41                         /* Lock failed */
  42                         udelay(100);
  43                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  44                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  45                         udelay(5);
  46                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                 }
  48         }
  49 }
  50
  51 /**
  52  * qla2x00_unlock_nvram_access() -
  53  * @ha: HA context
  54  */
  55 static void
  56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  57 {
  58         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  59
  60         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  61                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  62                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  63         }
  64 }
  65
  66 /**
  67  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  68  * @ha: HA context
  69  * @data: Serial interface selector
  70  */
  71 static void
  72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  73 {
  74         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  75
  76         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  77         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  78         NVRAM_DELAY();
  79         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  80             NVR_WRT_ENABLE);
  81         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  82         NVRAM_DELAY();
  83         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  84         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  85         NVRAM_DELAY();
  86 }
  87
  88 /**
  89  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  90  *      NVRAM.
  91  * @ha: HA context
  92  * @nv_cmd: NVRAM command
  93  *
  94  * Bit definitions for NVRAM command:
  95  *
  96  *      Bit 26     = start bit
  97  *      Bit 25, 24 = opcode
  98  *      Bit 23-16  = address
  99  *      Bit 15-0   = write data
 100  *
 101  * Returns the word read from nvram @addr.
 102  */
 103 static uint16_t
 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 105 {
 106         uint8_t         cnt;
 107         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 108         uint16_t        data = 0;
 109         uint16_t        reg_data;
 110
 111         /* Send command to NVRAM. */
 112         nv_cmd <<= 5;
 113         for (cnt = 0; cnt < 11; cnt++) {
 114                 if (nv_cmd & BIT_31)
 115                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 116                 else
 117                         qla2x00_nv_write(ha, 0);
 118                 nv_cmd <<= 1;
 119         }
 120
 121         /* Read data from NVRAM. */
 122         for (cnt = 0; cnt < 16; cnt++) {
 123                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 124                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 125                 NVRAM_DELAY();
 126                 data <<= 1;
 127                 reg_data = RD_REG_WORD(&reg->nvram);
 128                 if (reg_data & NVR_DATA_IN)
 129                         data |= BIT_0;
 130                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 131                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 132                 NVRAM_DELAY();
 133         }
 134
 135         /* Deselect chip. */
 136         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 137         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 138         NVRAM_DELAY();
 139
 140         return data;
 141 }
 142
 143
 144 /**
 145  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 146  *      request routine to get the word from NVRAM.
 147  * @ha: HA context
 148  * @addr: Address in NVRAM to read
 149  *
 150  * Returns the word read from nvram @addr.
 151  */
 152 static uint16_t
 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 154 {
 155         uint16_t        data;
 156         uint32_t        nv_cmd;
 157
 158         nv_cmd = addr << 16;
 159         nv_cmd |= NV_READ_OP;
 160         data = qla2x00_nvram_request(ha, nv_cmd);
 161
 162         return (data);
 163 }
 164
 165 /**
 166  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 167  * @ha: HA context
 168  */
 169 static void
 170 qla2x00_nv_deselect(struct qla_hw_data *ha)
 171 {
 172         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 173
 174         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 175         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 176         NVRAM_DELAY();
 177 }
 178
 179 /**
 180  * qla2x00_write_nvram_word() - Write NVRAM data.
 181  * @ha: HA context
 182  * @addr: Address in NVRAM to write
 183  * @data: word to program
 184  */
 185 static void
 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 187 {
 188         int count;
 189         uint16_t word;
 190         uint32_t nv_cmd, wait_cnt;
 191         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 192
 193         qla2x00_nv_write(ha, NVR_DATA_OUT);
 194         qla2x00_nv_write(ha, 0);
 195         qla2x00_nv_write(ha, 0);
 196
 197         for (word = 0; word < 8; word++)
 198                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 199
 200         qla2x00_nv_deselect(ha);
 201
 202         /* Write data */
 203         nv_cmd = (addr << 16) | NV_WRITE_OP;
 204         nv_cmd |= data;
 205         nv_cmd <<= 5;
 206         for (count = 0; count < 27; count++) {
 207                 if (nv_cmd & BIT_31)
 208                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 209                 else
 210                         qla2x00_nv_write(ha, 0);
 211
 212                 nv_cmd <<= 1;
 213         }
 214
 215         qla2x00_nv_deselect(ha);
 216
 217         /* Wait for NVRAM to become ready */
 218         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 219         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 220         wait_cnt = NVR_WAIT_CNT;
 221         do {
 222                 if (!--wait_cnt) {
 223                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 224                             "NVRAM didn't go ready...\n"));
 225                         break;
 226                 }
 227                 NVRAM_DELAY();
 228                 word = RD_REG_WORD(&reg->nvram);
 229         } while ((word & NVR_DATA_IN) == 0);
 230
 231         qla2x00_nv_deselect(ha);
 232
 233         /* Disable writes */
 234         qla2x00_nv_write(ha, NVR_DATA_OUT);
 235         for (count = 0; count < 10; count++)
 236                 qla2x00_nv_write(ha, 0);
 237
 238         qla2x00_nv_deselect(ha);
 239 }
 240
 241 static int
 242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 243         uint16_t data, uint32_t tmo)
 244 {
 245         int ret, count;
 246         uint16_t word;
 247         uint32_t nv_cmd;
 248         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 249
 250         ret = QLA_SUCCESS;
 251
 252         qla2x00_nv_write(ha, NVR_DATA_OUT);
 253         qla2x00_nv_write(ha, 0);
 254         qla2x00_nv_write(ha, 0);
 255
 256         for (word = 0; word < 8; word++)
 257                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 258
 259         qla2x00_nv_deselect(ha);
 260
 261         /* Write data */
 262         nv_cmd = (addr << 16) | NV_WRITE_OP;
 263         nv_cmd |= data;
 264         nv_cmd <<= 5;
 265         for (count = 0; count < 27; count++) {
 266                 if (nv_cmd & BIT_31)
 267                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 268                 else
 269                         qla2x00_nv_write(ha, 0);
 270
 271                 nv_cmd <<= 1;
 272         }
 273
 274         qla2x00_nv_deselect(ha);
 275
 276         /* Wait for NVRAM to become ready */
 277         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 278         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 279         do {
 280                 NVRAM_DELAY();
 281                 word = RD_REG_WORD(&reg->nvram);
 282                 if (!--tmo) {
 283                         ret = QLA_FUNCTION_FAILED;
 284                         break;
 285                 }
 286         } while ((word & NVR_DATA_IN) == 0);
 287
 288         qla2x00_nv_deselect(ha);
 289
 290         /* Disable writes */
 291         qla2x00_nv_write(ha, NVR_DATA_OUT);
 292         for (count = 0; count < 10; count++)
 293                 qla2x00_nv_write(ha, 0);
 294
 295         qla2x00_nv_deselect(ha);
 296
 297         return ret;
 298 }
 299
 300 /**
 301  * qla2x00_clear_nvram_protection() -
 302  * @ha: HA context
 303  */
 304 static int
 305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 306 {
 307         int ret, stat;
 308         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 309         uint32_t word, wait_cnt;
 310         uint16_t wprot, wprot_old;
 311
 312         /* Clear NVRAM write protection. */
 313         ret = QLA_FUNCTION_FAILED;
 314
 315         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 316         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 317             __constant_cpu_to_le16(0x1234), 100000);
 318         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 319         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 320                 /* Write enable. */
 321                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 322                 qla2x00_nv_write(ha, 0);
 323                 qla2x00_nv_write(ha, 0);
 324                 for (word = 0; word < 8; word++)
 325                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 326
 327                 qla2x00_nv_deselect(ha);
 328
 329                 /* Enable protection register. */
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 333                 for (word = 0; word < 8; word++)
 334                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 335
 336                 qla2x00_nv_deselect(ha);
 337
 338                 /* Clear protection register (ffff is cleared). */
 339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 for (word = 0; word < 8; word++)
 343                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 344
 345                 qla2x00_nv_deselect(ha);
 346
 347                 /* Wait for NVRAM to become ready. */
 348                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 349                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 350                 wait_cnt = NVR_WAIT_CNT;
 351                 do {
 352                         if (!--wait_cnt) {
 353                                 DEBUG9_10(qla_printk(KERN_WARNING, ha,
 354                                     "NVRAM didn't go ready...\n"));
 355                                 break;
 356                         }
 357                         NVRAM_DELAY();
 358                         word = RD_REG_WORD(&reg->nvram);
 359                 } while ((word & NVR_DATA_IN) == 0);
 360
 361                 if (wait_cnt)
 362                         ret = QLA_SUCCESS;
 363         } else
 364                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 365
 366         return ret;
 367 }
 368
 369 static void
 370 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 371 {
 372         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 373         uint32_t word, wait_cnt;
 374
 375         if (stat != QLA_SUCCESS)
 376                 return;
 377
 378         /* Set NVRAM write protection. */
 379         /* Write enable. */
 380         qla2x00_nv_write(ha, NVR_DATA_OUT);
 381         qla2x00_nv_write(ha, 0);
 382         qla2x00_nv_write(ha, 0);
 383         for (word = 0; word < 8; word++)
 384                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 385
 386         qla2x00_nv_deselect(ha);
 387
 388         /* Enable protection register. */
 389         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 391         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 392         for (word = 0; word < 8; word++)
 393                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 394
 395         qla2x00_nv_deselect(ha);
 396
 397         /* Enable protection register. */
 398         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 399         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 400         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 401         for (word = 0; word < 8; word++)
 402                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403
 404         qla2x00_nv_deselect(ha);
 405
 406         /* Wait for NVRAM to become ready. */
 407         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 408         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 409         wait_cnt = NVR_WAIT_CNT;
 410         do {
 411                 if (!--wait_cnt) {
 412                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 413                             "NVRAM didn't go ready...\n"));
 414                         break;
 415                 }
 416                 NVRAM_DELAY();
 417                 word = RD_REG_WORD(&reg->nvram);
 418         } while ((word & NVR_DATA_IN) == 0);
 419 }
 420
 421
 422 /*****************************************************************************/
 423 /* Flash Manipulation Routines                                               */
 424 /*****************************************************************************/
 425
 426 #define OPTROM_BURST_SIZE       0x1000
 427 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 428
 429 static inline uint32_t
 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 431 {
 432         return ha->flash_conf_off | faddr;
 433 }
 434
 435 static inline uint32_t
 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 437 {
 438         return ha->flash_data_off | faddr;
 439 }
 440
 441 static inline uint32_t
 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 443 {
 444         return ha->nvram_conf_off | naddr;
 445 }
 446
 447 static inline uint32_t
 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 449 {
 450         return ha->nvram_data_off | naddr;
 451 }
 452
 453 static uint32_t
 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 455 {
 456         int rval;
 457         uint32_t cnt, data;
 458         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 459
 460         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 461         /* Wait for READ cycle to complete. */
 462         rval = QLA_SUCCESS;
 463         for (cnt = 3000;
 464             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 465             rval == QLA_SUCCESS; cnt--) {
 466                 if (cnt)
 467                         udelay(10);
 468                 else
 469                         rval = QLA_FUNCTION_TIMEOUT;
 470                 cond_resched();
 471         }
 472
 473         /* TODO: What happens if we time out? */
 474         data = 0xDEADDEAD;
 475         if (rval == QLA_SUCCESS)
 476                 data = RD_REG_DWORD(&reg->flash_data);
 477
 478         return data;
 479 }
 480
 481 uint32_t *
 482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 483     uint32_t dwords)
 484 {
 485         uint32_t i;
 486         struct qla_hw_data *ha = vha->hw;
 487
 488         /* Dword reads to flash. */
 489         for (i = 0; i < dwords; i++, faddr++)
 490                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 491                     flash_data_addr(ha, faddr)));
 492
 493         return dwptr;
 494 }
 495
 496 static int
 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 498 {
 499         int rval;
 500         uint32_t cnt;
 501         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 502
 503         WRT_REG_DWORD(&reg->flash_data, data);
 504         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 505         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 506         /* Wait for Write cycle to complete. */
 507         rval = QLA_SUCCESS;
 508         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 509             rval == QLA_SUCCESS; cnt--) {
 510                 if (cnt)
 511                         udelay(10);
 512                 else
 513                         rval = QLA_FUNCTION_TIMEOUT;
 514                 cond_resched();
 515         }
 516         return rval;
 517 }
 518
 519 static void
 520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 521     uint8_t *flash_id)
 522 {
 523         uint32_t ids;
 524
 525         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 526         *man_id = LSB(ids);
 527         *flash_id = MSB(ids);
 528
 529         /* Check if man_id and flash_id are valid. */
 530         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 531                 /* Read information using 0x9f opcode
 532                  * Device ID, Mfg ID would be read in the format:
 533                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 534                  * Example: ATMEL 0x00 01 45 1F
 535                  * Extract MFG and Dev ID from last two bytes.
 536                  */
 537                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 538                 *man_id = LSB(ids);
 539                 *flash_id = MSB(ids);
 540         }
 541 }
 542
 543 static int
 544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 545 {
 546         const char *loc, *locations[] = { "DEF", "PCI" };
 547         uint32_t pcihdr, pcids;
 548         uint32_t *dcode;
 549         uint8_t *buf, *bcode, last_image;
 550         uint16_t cnt, chksum, *wptr;
 551         struct qla_flt_location *fltl;
 552         struct qla_hw_data *ha = vha->hw;
 553         struct req_que *req = ha->req_q_map[0];
 554
 555         /*
 556          * FLT-location structure resides after the last PCI region.
 557          */
 558
 559         /* Begin with sane defaults. */
 560         loc = locations[0];
 561         *start = 0;
 562         if (IS_QLA24XX_TYPE(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR_24;
 564         else if (IS_QLA25XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR;
 566         else if (IS_QLA81XX(ha))
 567                 *start = FA_FLASH_LAYOUT_ADDR_81;
 568         /* Begin with first PCI expansion ROM header. */
 569         buf = (uint8_t *)req->ring;
 570         dcode = (uint32_t *)req->ring;
 571         pcihdr = 0;
 572         last_image = 1;
 573         do {
 574                 /* Verify PCI expansion ROM header. */
 575                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 576                 bcode = buf + (pcihdr % 4);
 577                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 578                         goto end;
 579
 580                 /* Locate PCI data structure. */
 581                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 582                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 583                 bcode = buf + (pcihdr % 4);
 584
 585                 /* Validate signature of PCI data structure. */
 586                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 587                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 588                         goto end;
 589
 590                 last_image = bcode[0x15] & BIT_7;
 591
 592                 /* Locate next PCI expansion ROM. */
 593                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 594         } while (!last_image);
 595
 596         /* Now verify FLT-location structure. */
 597         fltl = (struct qla_flt_location *)req->ring;
 598         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 599             sizeof(struct qla_flt_location) >> 2);
 600         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 601             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 602                 goto end;
 603
 604         wptr = (uint16_t *)req->ring;
 605         cnt = sizeof(struct qla_flt_location) >> 1;
 606         for (chksum = 0; cnt; cnt--)
 607                 chksum += le16_to_cpu(*wptr++);
 608         if (chksum) {
 609                 qla_printk(KERN_ERR, ha,
 610                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 611                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 612                 return QLA_FUNCTION_FAILED;
 613         }
 614
 615         /* Good data.  Use specified location. */
 616         loc = locations[1];
 617         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 618             le16_to_cpu(fltl->start_lo)) >> 2;
 619 end:
 620         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 621         return QLA_SUCCESS;
 622 }
 623
 624 static void
 625 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 626 {
 627         const char *loc, *locations[] = { "DEF", "FLT" };
 628         const uint32_t def_fw[] =
 629                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 630         const uint32_t def_boot[] =
 631                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 632         const uint32_t def_vpd_nvram[] =
 633                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 634         const uint32_t def_vpd0[] =
 635                 { 0, 0, FA_VPD0_ADDR_81 };
 636         const uint32_t def_vpd1[] =
 637                 { 0, 0, FA_VPD1_ADDR_81 };
 638         const uint32_t def_nvram0[] =
 639                 { 0, 0, FA_NVRAM0_ADDR_81 };
 640         const uint32_t def_nvram1[] =
 641                 { 0, 0, FA_NVRAM1_ADDR_81 };
 642         const uint32_t def_fdt[] =
 643                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 644                         FA_FLASH_DESCR_ADDR_81 };
 645         const uint32_t def_npiv_conf0[] =
 646                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 647                         FA_NPIV_CONF0_ADDR_81 };
 648         const uint32_t def_npiv_conf1[] =
 649                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 650                         FA_NPIV_CONF1_ADDR_81 };
 651         uint32_t def;
 652         uint16_t *wptr;
 653         uint16_t cnt, chksum;
 654         uint32_t start;
 655         struct qla_flt_header *flt;
 656         struct qla_flt_region *region;
 657         struct qla_hw_data *ha = vha->hw;
 658         struct req_que *req = ha->req_q_map[0];
 659
 660         ha->flt_region_flt = flt_addr;
 661         wptr = (uint16_t *)req->ring;
 662         flt = (struct qla_flt_header *)req->ring;
 663         region = (struct qla_flt_region *)&flt[1];
 664         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 665             flt_addr << 2, OPTROM_BURST_SIZE);
 666         if (*wptr == __constant_cpu_to_le16(0xffff))
 667                 goto no_flash_data;
 668         if (flt->version != __constant_cpu_to_le16(1)) {
 669                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 670                     "version=0x%x length=0x%x checksum=0x%x.\n",
 671                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 672                     le16_to_cpu(flt->checksum)));
 673                 goto no_flash_data;
 674         }
 675
 676         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 677         for (chksum = 0; cnt; cnt--)
 678                 chksum += le16_to_cpu(*wptr++);
 679         if (chksum) {
 680                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 681                     "version=0x%x length=0x%x checksum=0x%x.\n",
 682                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 683                     chksum));
 684                 goto no_flash_data;
 685         }
 686
 687         loc = locations[1];
 688         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 689         for ( ; cnt; cnt--, region++) {
 690                 /* Store addresses as DWORD offsets. */
 691                 start = le32_to_cpu(region->start) >> 2;
 692
 693                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 694                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 695                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 696
 697                 switch (le32_to_cpu(region->code) & 0xff) {
 698                 case FLT_REG_FW:
 699                         ha->flt_region_fw = start;
 700                         break;
 701                 case FLT_REG_BOOT_CODE:
 702                         ha->flt_region_boot = start;
 703                         break;
 704                 case FLT_REG_VPD_0:
 705                         ha->flt_region_vpd_nvram = start;
 706                         if (ha->flags.port0)
 707                                 ha->flt_region_vpd = start;
 708                         break;
 709                 case FLT_REG_VPD_1:
 710                         if (!ha->flags.port0)
 711                                 ha->flt_region_vpd = start;
 712                         break;
 713                 case FLT_REG_NVRAM_0:
 714                         if (ha->flags.port0)
 715                                 ha->flt_region_nvram = start;
 716                         break;
 717                 case FLT_REG_NVRAM_1:
 718                         if (!ha->flags.port0)
 719                                 ha->flt_region_nvram = start;
 720                         break;
 721                 case FLT_REG_FDT:
 722                         ha->flt_region_fdt = start;
 723                         break;
 724                 case FLT_REG_NPIV_CONF_0:
 725                         if (ha->flags.port0)
 726                                 ha->flt_region_npiv_conf = start;
 727                         break;
 728                 case FLT_REG_NPIV_CONF_1:
 729                         if (!ha->flags.port0)
 730                                 ha->flt_region_npiv_conf = start;
 731                         break;
 732                 case FLT_REG_GOLD_FW:
 733                         ha->flt_region_gold_fw = start;
 734                         break;
 735                 }
 736         }
 737         goto done;
 738
 739 no_flash_data:
 740         /* Use hardcoded defaults. */
 741         loc = locations[0];
 742         def = 0;
 743         if (IS_QLA24XX_TYPE(ha))
 744                 def = 0;
 745         else if (IS_QLA25XX(ha))
 746                 def = 1;
 747         else if (IS_QLA81XX(ha))
 748                 def = 2;
 749         ha->flt_region_fw = def_fw[def];
 750         ha->flt_region_boot = def_boot[def];
 751         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 752         ha->flt_region_vpd = ha->flags.port0 ?
 753             def_vpd0[def]: def_vpd1[def];
 754         ha->flt_region_nvram = ha->flags.port0 ?
 755             def_nvram0[def]: def_nvram1[def];
 756         ha->flt_region_fdt = def_fdt[def];
 757         ha->flt_region_npiv_conf = ha->flags.port0 ?
 758             def_npiv_conf0[def]: def_npiv_conf1[def];
 759 done:
 760         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 761             "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
 762             "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
 763             ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 764             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
 765 }
 766
 767 static void
 768 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 769 {
 770 #define FLASH_BLK_SIZE_4K       0x1000
 771 #define FLASH_BLK_SIZE_32K      0x8000
 772 #define FLASH_BLK_SIZE_64K      0x10000
 773         const char *loc, *locations[] = { "MID", "FDT" };
 774         uint16_t cnt, chksum;
 775         uint16_t *wptr;
 776         struct qla_fdt_layout *fdt;
 777         uint8_t man_id, flash_id;
 778         uint16_t mid, fid;
 779         struct qla_hw_data *ha = vha->hw;
 780         struct req_que *req = ha->req_q_map[0];
 781
 782         wptr = (uint16_t *)req->ring;
 783         fdt = (struct qla_fdt_layout *)req->ring;
 784         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 785             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 786         if (*wptr == __constant_cpu_to_le16(0xffff))
 787                 goto no_flash_data;
 788         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 789             fdt->sig[3] != 'D')
 790                 goto no_flash_data;
 791
 792         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 793             cnt++)
 794                 chksum += le16_to_cpu(*wptr++);
 795         if (chksum) {
 796                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 797                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 798                     le16_to_cpu(fdt->version)));
 799                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 800                 goto no_flash_data;
 801         }
 802
 803         loc = locations[1];
 804         mid = le16_to_cpu(fdt->man_id);
 805         fid = le16_to_cpu(fdt->id);
 806         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 807         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 808         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 809         if (fdt->unprotect_sec_cmd) {
 810                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 811                     fdt->unprotect_sec_cmd);
 812                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 813                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 814                     flash_conf_addr(ha, 0x0336);
 815         }
 816         goto done;
 817 no_flash_data:
 818         loc = locations[0];
 819         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 820         mid = man_id;
 821         fid = flash_id;
 822         ha->fdt_wrt_disable = 0x9c;
 823         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 824         switch (man_id) {
 825         case 0xbf: /* STT flash. */
 826                 if (flash_id == 0x8e)
 827                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 828                 else
 829                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 830
 831                 if (flash_id == 0x80)
 832                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 833                 break;
 834         case 0x13: /* ST M25P80. */
 835                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 836                 break;
 837         case 0x1f: /* Atmel 26DF081A. */
 838                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 839                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 840                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 841                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 842                 break;
 843         default:
 844                 /* Default to 64 kb sector size. */
 845                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 846                 break;
 847         }
 848 done:
 849         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 850             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 851             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 852             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
 853             ha->fdt_block_size));
 854 }
 855
 856 int
 857 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 858 {
 859         int ret;
 860         uint32_t flt_addr;
 861         struct qla_hw_data *ha = vha->hw;
 862
 863         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 864                 return QLA_SUCCESS;
 865
 866         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 867         if (ret != QLA_SUCCESS)
 868                 return ret;
 869
 870         qla2xxx_get_flt_info(vha, flt_addr);
 871         qla2xxx_get_fdt_info(vha);
 872
 873         return QLA_SUCCESS;
 874 }
 875
 876 void
 877 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 878 {
 879 #define NPIV_CONFIG_SIZE        (16*1024)
 880         void *data;
 881         uint16_t *wptr;
 882         uint16_t cnt, chksum;
 883         int i;
 884         struct qla_npiv_header hdr;
 885         struct qla_npiv_entry *entry;
 886         struct qla_hw_data *ha = vha->hw;
 887
 888         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 889                 return;
 890
 891         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 892             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 893         if (hdr.version == __constant_cpu_to_le16(0xffff))
 894                 return;
 895         if (hdr.version != __constant_cpu_to_le16(1)) {
 896                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 897                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 898                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 899                     le16_to_cpu(hdr.checksum)));
 900                 return;
 901         }
 902
 903         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 904         if (!data) {
 905                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 906                     "allocate memory.\n"));
 907                 return;
 908         }
 909
 910         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
 911             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 912
 913         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 914             sizeof(struct qla_npiv_entry)) >> 1;
 915         for (wptr = data, chksum = 0; cnt; cnt--)
 916                 chksum += le16_to_cpu(*wptr++);
 917         if (chksum) {
 918                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 919                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 920                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 921                     chksum));
 922                 goto done;
 923         }
 924
 925         entry = data + sizeof(struct qla_npiv_header);
 926         cnt = le16_to_cpu(hdr.entries);
 927         for (i = 0; cnt; cnt--, entry++, i++) {
 928                 uint16_t flags;
 929                 struct fc_vport_identifiers vid;
 930                 struct fc_vport *vport;
 931
 932                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
 933
 934                 flags = le16_to_cpu(entry->flags);
 935                 if (flags == 0xffff)
 936                         continue;
 937                 if ((flags & BIT_0) == 0)
 938                         continue;
 939
 940                 memset(&vid, 0, sizeof(vid));
 941                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 942                 vid.vport_type = FC_PORTTYPE_NPIV;
 943                 vid.disable = false;
 944                 vid.port_name = wwn_to_u64(entry->port_name);
 945                 vid.node_name = wwn_to_u64(entry->node_name);
 946
 947                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
 948                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
 949                         (unsigned long long)vid.port_name,
 950                         (unsigned long long)vid.node_name,
 951                         le16_to_cpu(entry->vf_id),
 952                         entry->q_qos, entry->f_qos));
 953
 954                 if (i < QLA_PRECONFIG_VPORTS) {
 955                         vport = fc_vport_create(vha->host, 0, &vid);
 956                         if (!vport)
 957                                 qla_printk(KERN_INFO, ha,
 958                                 "NPIV-Config: Failed to create vport [%02x]: "
 959                                 "wwpn=%llx wwnn=%llx.\n", cnt,
 960                                 (unsigned long long)vid.port_name,
 961                                 (unsigned long long)vid.node_name);
 962                 }
 963         }
 964 done:
 965         kfree(data);
 966 }
 967
 968 static int
 969 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
 970 {
 971         struct qla_hw_data *ha = vha->hw;
 972         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 973
 974         if (ha->flags.fac_supported)
 975                 return qla81xx_fac_do_write_enable(vha, 1);
 976
 977         /* Enable flash write. */
 978         WRT_REG_DWORD(&reg->ctrl_status,
 979             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 980         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 981
 982         if (!ha->fdt_wrt_disable)
 983                 goto done;
 984
 985         /* Disable flash write-protection, first clear SR protection bit */
 986         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 987         /* Then write zero again to clear remaining SR bits.*/
 988         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 989 done:
 990         return QLA_SUCCESS;
 991 }
 992
 993 static int
 994 qla24xx_protect_flash(scsi_qla_host_t *vha)
 995 {
 996         uint32_t cnt;
 997         struct qla_hw_data *ha = vha->hw;
 998         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 999
1000         if (ha->flags.fac_supported)
1001                 return qla81xx_fac_do_write_enable(vha, 0);
1002
1003         if (!ha->fdt_wrt_disable)
1004                 goto skip_wrt_protect;
1005
1006         /* Enable flash write-protection and wait for completion. */
1007         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1008             ha->fdt_wrt_disable);
1009         for (cnt = 300; cnt &&
1010             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1011             cnt--) {
1012                 udelay(10);
1013         }
1014
1015 skip_wrt_protect:
1016         /* Disable flash write. */
1017         WRT_REG_DWORD(&reg->ctrl_status,
1018             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1019         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1020
1021         return QLA_SUCCESS;
1022 }
1023
1024 static int
1025 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1026 {
1027         struct qla_hw_data *ha = vha->hw;
1028         uint32_t start, finish;
1029
1030         if (ha->flags.fac_supported) {
1031                 start = fdata >> 2;
1032                 finish = start + (ha->fdt_block_size >> 2) - 1;
1033                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1034                     start), flash_data_addr(ha, finish));
1035         }
1036
1037         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1038             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1039             ((fdata >> 16) & 0xff));
1040 }
1041
1042 static int
1043 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1044     uint32_t dwords)
1045 {
1046         int ret;
1047         uint32_t liter;
1048         uint32_t sec_mask, rest_addr;
1049         uint32_t fdata;
1050         dma_addr_t optrom_dma;
1051         void *optrom = NULL;
1052         struct qla_hw_data *ha = vha->hw;
1053
1054         /* Prepare burst-capable write on supported ISPs. */
1055         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1056             dwords > OPTROM_BURST_DWORDS) {
1057                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1058                     &optrom_dma, GFP_KERNEL);
1059                 if (!optrom) {
1060                         qla_printk(KERN_DEBUG, ha,
1061                             "Unable to allocate memory for optrom burst write "
1062                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1063                 }
1064         }
1065
1066         rest_addr = (ha->fdt_block_size >> 2) - 1;
1067         sec_mask = ~rest_addr;
1068
1069         ret = qla24xx_unprotect_flash(vha);
1070         if (ret != QLA_SUCCESS) {
1071                 qla_printk(KERN_WARNING, ha,
1072                     "Unable to unprotect flash for update.\n");
1073                 goto done;
1074         }
1075
1076         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1077                 fdata = (faddr & sec_mask) << 2;
1078
1079                 /* Are we at the beginning of a sector? */
1080                 if ((faddr & rest_addr) == 0) {
1081                         /* Do sector unprotect. */
1082                         if (ha->fdt_unprotect_sec_cmd)
1083                                 qla24xx_write_flash_dword(ha,
1084                                     ha->fdt_unprotect_sec_cmd,
1085                                     (fdata & 0xff00) | ((fdata << 16) &
1086                                     0xff0000) | ((fdata >> 16) & 0xff));
1087                         ret = qla24xx_erase_sector(vha, fdata);
1088                         if (ret != QLA_SUCCESS) {
1089                                 DEBUG9(qla_printk(KERN_WARNING, ha,
1090                                     "Unable to erase sector: address=%x.\n",
1091                                     faddr));
1092                                 break;
1093                         }
1094                 }
1095
1096                 /* Go with burst-write. */
1097                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1098                         /* Copy data to DMA'ble buffer. */
1099                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1100
1101                         ret = qla2x00_load_ram(vha, optrom_dma,
1102                             flash_data_addr(ha, faddr),
1103                             OPTROM_BURST_DWORDS);
1104                         if (ret != QLA_SUCCESS) {
1105                                 qla_printk(KERN_WARNING, ha,
1106                                     "Unable to burst-write optrom segment "
1107                                     "(%x/%x/%llx).\n", ret,
1108                                     flash_data_addr(ha, faddr),
1109                                     (unsigned long long)optrom_dma);
1110                                 qla_printk(KERN_WARNING, ha,
1111                                     "Reverting to slow-write.\n");
1112
1113                                 dma_free_coherent(&ha->pdev->dev,
1114                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1115                                 optrom = NULL;
1116                         } else {
1117                                 liter += OPTROM_BURST_DWORDS - 1;
1118                                 faddr += OPTROM_BURST_DWORDS - 1;
1119                                 dwptr += OPTROM_BURST_DWORDS - 1;
1120                                 continue;
1121                         }
1122                 }
1123
1124                 ret = qla24xx_write_flash_dword(ha,
1125                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1126                 if (ret != QLA_SUCCESS) {
1127                         DEBUG9(printk("%s(%ld) Unable to program flash "
1128                             "address=%x data=%x.\n", __func__,
1129                             vha->host_no, faddr, *dwptr));
1130                         break;
1131                 }
1132
1133                 /* Do sector protect. */
1134                 if (ha->fdt_unprotect_sec_cmd &&
1135                     ((faddr & rest_addr) == rest_addr))
1136                         qla24xx_write_flash_dword(ha,
1137                             ha->fdt_protect_sec_cmd,
1138                             (fdata & 0xff00) | ((fdata << 16) &
1139                             0xff0000) | ((fdata >> 16) & 0xff));
1140         }
1141
1142         ret = qla24xx_protect_flash(vha);
1143         if (ret != QLA_SUCCESS)
1144                 qla_printk(KERN_WARNING, ha,
1145                     "Unable to protect flash after update.\n");
1146 done:
1147         if (optrom)
1148                 dma_free_coherent(&ha->pdev->dev,
1149                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1150
1151         return ret;
1152 }
1153
1154 uint8_t *
1155 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1156     uint32_t bytes)
1157 {
1158         uint32_t i;
1159         uint16_t *wptr;
1160         struct qla_hw_data *ha = vha->hw;
1161
1162         /* Word reads to NVRAM via registers. */
1163         wptr = (uint16_t *)buf;
1164         qla2x00_lock_nvram_access(ha);
1165         for (i = 0; i < bytes >> 1; i++, naddr++)
1166                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1167                     naddr));
1168         qla2x00_unlock_nvram_access(ha);
1169
1170         return buf;
1171 }
1172
1173 uint8_t *
1174 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1175     uint32_t bytes)
1176 {
1177         uint32_t i;
1178         uint32_t *dwptr;
1179         struct qla_hw_data *ha = vha->hw;
1180
1181         /* Dword reads to flash. */
1182         dwptr = (uint32_t *)buf;
1183         for (i = 0; i < bytes >> 2; i++, naddr++)
1184                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1185                     nvram_data_addr(ha, naddr)));
1186
1187         return buf;
1188 }
1189
1190 int
1191 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1192     uint32_t bytes)
1193 {
1194         int ret, stat;
1195         uint32_t i;
1196         uint16_t *wptr;
1197         unsigned long flags;
1198         struct qla_hw_data *ha = vha->hw;
1199
1200         ret = QLA_SUCCESS;
1201
1202         spin_lock_irqsave(&ha->hardware_lock, flags);
1203         qla2x00_lock_nvram_access(ha);
1204
1205         /* Disable NVRAM write-protection. */
1206         stat = qla2x00_clear_nvram_protection(ha);
1207
1208         wptr = (uint16_t *)buf;
1209         for (i = 0; i < bytes >> 1; i++, naddr++) {
1210                 qla2x00_write_nvram_word(ha, naddr,
1211                     cpu_to_le16(*wptr));
1212                 wptr++;
1213         }
1214
1215         /* Enable NVRAM write-protection. */
1216         qla2x00_set_nvram_protection(ha, stat);
1217
1218         qla2x00_unlock_nvram_access(ha);
1219         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1220
1221         return ret;
1222 }
1223
1224 int
1225 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1226     uint32_t bytes)
1227 {
1228         int ret;
1229         uint32_t i;
1230         uint32_t *dwptr;
1231         struct qla_hw_data *ha = vha->hw;
1232         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1233
1234         ret = QLA_SUCCESS;
1235
1236         /* Enable flash write. */
1237         WRT_REG_DWORD(&reg->ctrl_status,
1238             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1239         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1240
1241         /* Disable NVRAM write-protection. */
1242         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1243         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1244
1245         /* Dword writes to flash. */
1246         dwptr = (uint32_t *)buf;
1247         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1248                 ret = qla24xx_write_flash_dword(ha,
1249                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1250                 if (ret != QLA_SUCCESS) {
1251                         DEBUG9(qla_printk(KERN_WARNING, ha,
1252                             "Unable to program nvram address=%x data=%x.\n",
1253                             naddr, *dwptr));
1254                         break;
1255                 }
1256         }
1257
1258         /* Enable NVRAM write-protection. */
1259         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1260
1261         /* Disable flash write. */
1262         WRT_REG_DWORD(&reg->ctrl_status,
1263             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1264         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1265
1266         return ret;
1267 }
1268
1269 uint8_t *
1270 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1271     uint32_t bytes)
1272 {
1273         uint32_t i;
1274         uint32_t *dwptr;
1275         struct qla_hw_data *ha = vha->hw;
1276
1277         /* Dword reads to flash. */
1278         dwptr = (uint32_t *)buf;
1279         for (i = 0; i < bytes >> 2; i++, naddr++)
1280                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1281                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1282
1283         return buf;
1284 }
1285
1286 int
1287 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1288     uint32_t bytes)
1289 {
1290         struct qla_hw_data *ha = vha->hw;
1291 #define RMW_BUFFER_SIZE (64 * 1024)
1292         uint8_t *dbuf;
1293
1294         dbuf = vmalloc(RMW_BUFFER_SIZE);
1295         if (!dbuf)
1296                 return QLA_MEMORY_ALLOC_FAILED;
1297         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1298             RMW_BUFFER_SIZE);
1299         memcpy(dbuf + (naddr << 2), buf, bytes);
1300         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1301             RMW_BUFFER_SIZE);
1302         vfree(dbuf);
1303
1304         return QLA_SUCCESS;
1305 }
1306
1307 static inline void
1308 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1309 {
1310         if (IS_QLA2322(ha)) {
1311                 /* Flip all colors. */
1312                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1313                         /* Turn off. */
1314                         ha->beacon_color_state = 0;
1315                         *pflags = GPIO_LED_ALL_OFF;
1316                 } else {
1317                         /* Turn on. */
1318                         ha->beacon_color_state = QLA_LED_ALL_ON;
1319                         *pflags = GPIO_LED_RGA_ON;
1320                 }
1321         } else {
1322                 /* Flip green led only. */
1323                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1324                         /* Turn off. */
1325                         ha->beacon_color_state = 0;
1326                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1327                 } else {
1328                         /* Turn on. */
1329                         ha->beacon_color_state = QLA_LED_GRN_ON;
1330                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1331                 }
1332         }
1333 }
1334
1335 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1336
1337 void
1338 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1339 {
1340         uint16_t gpio_enable;
1341         uint16_t gpio_data;
1342         uint16_t led_color = 0;
1343         unsigned long flags;
1344         struct qla_hw_data *ha = vha->hw;
1345         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1346
1347         spin_lock_irqsave(&ha->hardware_lock, flags);
1348
1349         /* Save the Original GPIOE. */
1350         if (ha->pio_address) {
1351                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1352                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1353         } else {
1354                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1355                 gpio_data = RD_REG_WORD(&reg->gpiod);
1356         }
1357
1358         /* Set the modified gpio_enable values */
1359         gpio_enable |= GPIO_LED_MASK;
1360
1361         if (ha->pio_address) {
1362                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1363         } else {
1364                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1365                 RD_REG_WORD(&reg->gpioe);
1366         }
1367
1368         qla2x00_flip_colors(ha, &led_color);
1369
1370         /* Clear out any previously set LED color. */
1371         gpio_data &= ~GPIO_LED_MASK;
1372
1373         /* Set the new input LED color to GPIOD. */
1374         gpio_data |= led_color;
1375
1376         /* Set the modified gpio_data values */
1377         if (ha->pio_address) {
1378                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1379         } else {
1380                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1381                 RD_REG_WORD(&reg->gpiod);
1382         }
1383
1384         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1385 }
1386
1387 int
1388 qla2x00_beacon_on(struct scsi_qla_host *vha)
1389 {
1390         uint16_t gpio_enable;
1391         uint16_t gpio_data;
1392         unsigned long flags;
1393         struct qla_hw_data *ha = vha->hw;
1394         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1395
1396         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1397         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1398
1399         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1400                 qla_printk(KERN_WARNING, ha,
1401                     "Unable to update fw options (beacon on).\n");
1402                 return QLA_FUNCTION_FAILED;
1403         }
1404
1405         /* Turn off LEDs. */
1406         spin_lock_irqsave(&ha->hardware_lock, flags);
1407         if (ha->pio_address) {
1408                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1409                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1410         } else {
1411                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1412                 gpio_data = RD_REG_WORD(&reg->gpiod);
1413         }
1414         gpio_enable |= GPIO_LED_MASK;
1415
1416         /* Set the modified gpio_enable values. */
1417         if (ha->pio_address) {
1418                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1419         } else {
1420                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1421                 RD_REG_WORD(&reg->gpioe);
1422         }
1423
1424         /* Clear out previously set LED colour. */
1425         gpio_data &= ~GPIO_LED_MASK;
1426         if (ha->pio_address) {
1427                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1428         } else {
1429                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1430                 RD_REG_WORD(&reg->gpiod);
1431         }
1432         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1433
1434         /*
1435          * Let the per HBA timer kick off the blinking process based on
1436          * the following flags. No need to do anything else now.
1437          */
1438         ha->beacon_blink_led = 1;
1439         ha->beacon_color_state = 0;
1440
1441         return QLA_SUCCESS;
1442 }
1443
1444 int
1445 qla2x00_beacon_off(struct scsi_qla_host *vha)
1446 {
1447         int rval = QLA_SUCCESS;
1448         struct qla_hw_data *ha = vha->hw;
1449
1450         ha->beacon_blink_led = 0;
1451
1452         /* Set the on flag so when it gets flipped it will be off. */
1453         if (IS_QLA2322(ha))
1454                 ha->beacon_color_state = QLA_LED_ALL_ON;
1455         else
1456                 ha->beacon_color_state = QLA_LED_GRN_ON;
1457
1458         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1459
1460         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1461         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1462
1463         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1464         if (rval != QLA_SUCCESS)
1465                 qla_printk(KERN_WARNING, ha,
1466                     "Unable to update fw options (beacon off).\n");
1467         return rval;
1468 }
1469
1470
1471 static inline void
1472 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1473 {
1474         /* Flip all colors. */
1475         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1476                 /* Turn off. */
1477                 ha->beacon_color_state = 0;
1478                 *pflags = 0;
1479         } else {
1480                 /* Turn on. */
1481                 ha->beacon_color_state = QLA_LED_ALL_ON;
1482                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1483         }
1484 }
1485
1486 void
1487 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1488 {
1489         uint16_t led_color = 0;
1490         uint32_t gpio_data;
1491         unsigned long flags;
1492         struct qla_hw_data *ha = vha->hw;
1493         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1494
1495         /* Save the Original GPIOD. */
1496         spin_lock_irqsave(&ha->hardware_lock, flags);
1497         gpio_data = RD_REG_DWORD(&reg->gpiod);
1498
1499         /* Enable the gpio_data reg for update. */
1500         gpio_data |= GPDX_LED_UPDATE_MASK;
1501
1502         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1503         gpio_data = RD_REG_DWORD(&reg->gpiod);
1504
1505         /* Set the color bits. */
1506         qla24xx_flip_colors(ha, &led_color);
1507
1508         /* Clear out any previously set LED color. */
1509         gpio_data &= ~GPDX_LED_COLOR_MASK;
1510
1511         /* Set the new input LED color to GPIOD. */
1512         gpio_data |= led_color;
1513
1514         /* Set the modified gpio_data values. */
1515         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1516         gpio_data = RD_REG_DWORD(&reg->gpiod);
1517         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1518 }
1519
1520 int
1521 qla24xx_beacon_on(struct scsi_qla_host *vha)
1522 {
1523         uint32_t gpio_data;
1524         unsigned long flags;
1525         struct qla_hw_data *ha = vha->hw;
1526         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1527
1528         if (ha->beacon_blink_led == 0) {
1529                 /* Enable firmware for update */
1530                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1531
1532                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1533                         return QLA_FUNCTION_FAILED;
1534
1535                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1536                     QLA_SUCCESS) {
1537                         qla_printk(KERN_WARNING, ha,
1538                             "Unable to update fw options (beacon on).\n");
1539                         return QLA_FUNCTION_FAILED;
1540                 }
1541
1542                 spin_lock_irqsave(&ha->hardware_lock, flags);
1543                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1544
1545                 /* Enable the gpio_data reg for update. */
1546                 gpio_data |= GPDX_LED_UPDATE_MASK;
1547                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1548                 RD_REG_DWORD(&reg->gpiod);
1549
1550                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1551         }
1552
1553         /* So all colors blink together. */
1554         ha->beacon_color_state = 0;
1555
1556         /* Let the per HBA timer kick off the blinking process. */
1557         ha->beacon_blink_led = 1;
1558
1559         return QLA_SUCCESS;
1560 }
1561
1562 int
1563 qla24xx_beacon_off(struct scsi_qla_host *vha)
1564 {
1565         uint32_t gpio_data;
1566         unsigned long flags;
1567         struct qla_hw_data *ha = vha->hw;
1568         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1569
1570         ha->beacon_blink_led = 0;
1571         ha->beacon_color_state = QLA_LED_ALL_ON;
1572
1573         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1574
1575         /* Give control back to firmware. */
1576         spin_lock_irqsave(&ha->hardware_lock, flags);
1577         gpio_data = RD_REG_DWORD(&reg->gpiod);
1578
1579         /* Disable the gpio_data reg for update. */
1580         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1581         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1582         RD_REG_DWORD(&reg->gpiod);
1583         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1584
1585         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1586
1587         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1588                 qla_printk(KERN_WARNING, ha,
1589                     "Unable to update fw options (beacon off).\n");
1590                 return QLA_FUNCTION_FAILED;
1591         }
1592
1593         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1594                 qla_printk(KERN_WARNING, ha,
1595                     "Unable to get fw options (beacon off).\n");
1596                 return QLA_FUNCTION_FAILED;
1597         }
1598
1599         return QLA_SUCCESS;
1600 }
1601
1602
1603 /*
1604  * Flash support routines
1605  */
1606
1607 /**
1608  * qla2x00_flash_enable() - Setup flash for reading and writing.
1609  * @ha: HA context
1610  */
1611 static void
1612 qla2x00_flash_enable(struct qla_hw_data *ha)
1613 {
1614         uint16_t data;
1615         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1616
1617         data = RD_REG_WORD(&reg->ctrl_status);
1618         data |= CSR_FLASH_ENABLE;
1619         WRT_REG_WORD(&reg->ctrl_status, data);
1620         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1621 }
1622
1623 /**
1624  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1625  * @ha: HA context
1626  */
1627 static void
1628 qla2x00_flash_disable(struct qla_hw_data *ha)
1629 {
1630         uint16_t data;
1631         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1632
1633         data = RD_REG_WORD(&reg->ctrl_status);
1634         data &= ~(CSR_FLASH_ENABLE);
1635         WRT_REG_WORD(&reg->ctrl_status, data);
1636         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1637 }
1638
1639 /**
1640  * qla2x00_read_flash_byte() - Reads a byte from flash
1641  * @ha: HA context
1642  * @addr: Address in flash to read
1643  *
1644  * A word is read from the chip, but, only the lower byte is valid.
1645  *
1646  * Returns the byte read from flash @addr.
1647  */
1648 static uint8_t
1649 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1650 {
1651         uint16_t data;
1652         uint16_t bank_select;
1653         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1654
1655         bank_select = RD_REG_WORD(&reg->ctrl_status);
1656
1657         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1658                 /* Specify 64K address range: */
1659                 /*  clear out Module Select and Flash Address bits [19:16]. */
1660                 bank_select &= ~0xf8;
1661                 bank_select |= addr >> 12 & 0xf0;
1662                 bank_select |= CSR_FLASH_64K_BANK;
1663                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1664                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1665
1666                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1667                 data = RD_REG_WORD(&reg->flash_data);
1668
1669                 return (uint8_t)data;
1670         }
1671
1672         /* Setup bit 16 of flash address. */
1673         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1674                 bank_select |= CSR_FLASH_64K_BANK;
1675                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1676                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1677         } else if (((addr & BIT_16) == 0) &&
1678             (bank_select & CSR_FLASH_64K_BANK)) {
1679                 bank_select &= ~(CSR_FLASH_64K_BANK);
1680                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1681                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1682         }
1683
1684         /* Always perform IO mapped accesses to the FLASH registers. */
1685         if (ha->pio_address) {
1686                 uint16_t data2;
1687
1688                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1689                 do {
1690                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1691                         barrier();
1692                         cpu_relax();
1693                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1694                 } while (data != data2);
1695         } else {
1696                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1697                 data = qla2x00_debounce_register(&reg->flash_data);
1698         }
1699
1700         return (uint8_t)data;
1701 }
1702
1703 /**
1704  * qla2x00_write_flash_byte() - Write a byte to flash
1705  * @ha: HA context
1706  * @addr: Address in flash to write
1707  * @data: Data to write
1708  */
1709 static void
1710 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1711 {
1712         uint16_t bank_select;
1713         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1714
1715         bank_select = RD_REG_WORD(&reg->ctrl_status);
1716         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1717                 /* Specify 64K address range: */
1718                 /*  clear out Module Select and Flash Address bits [19:16]. */
1719                 bank_select &= ~0xf8;
1720                 bank_select |= addr >> 12 & 0xf0;
1721                 bank_select |= CSR_FLASH_64K_BANK;
1722                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1723                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1724
1725                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1726                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1727                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1728                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1729
1730                 return;
1731         }
1732
1733         /* Setup bit 16 of flash address. */
1734         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1735                 bank_select |= CSR_FLASH_64K_BANK;
1736                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1737                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1738         } else if (((addr & BIT_16) == 0) &&
1739             (bank_select & CSR_FLASH_64K_BANK)) {
1740                 bank_select &= ~(CSR_FLASH_64K_BANK);
1741                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1742                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1743         }
1744
1745         /* Always perform IO mapped accesses to the FLASH registers. */
1746         if (ha->pio_address) {
1747                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1748                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1749         } else {
1750                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1751                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1752                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1753                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1754         }
1755 }
1756
1757 /**
1758  * qla2x00_poll_flash() - Polls flash for completion.
1759  * @ha: HA context
1760  * @addr: Address in flash to poll
1761  * @poll_data: Data to be polled
1762  * @man_id: Flash manufacturer ID
1763  * @flash_id: Flash ID
1764  *
1765  * This function polls the device until bit 7 of what is read matches data
1766  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1767  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1768  * reading bit 5 as a 1.
1769  *
1770  * Returns 0 on success, else non-zero.
1771  */
1772 static int
1773 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1774     uint8_t man_id, uint8_t flash_id)
1775 {
1776         int status;
1777         uint8_t flash_data;
1778         uint32_t cnt;
1779
1780         status = 1;
1781
1782         /* Wait for 30 seconds for command to finish. */
1783         poll_data &= BIT_7;
1784         for (cnt = 3000000; cnt; cnt--) {
1785                 flash_data = qla2x00_read_flash_byte(ha, addr);
1786                 if ((flash_data & BIT_7) == poll_data) {
1787                         status = 0;
1788                         break;
1789                 }
1790
1791                 if (man_id != 0x40 && man_id != 0xda) {
1792                         if ((flash_data & BIT_5) && cnt > 2)
1793                                 cnt = 2;
1794                 }
1795                 udelay(10);
1796                 barrier();
1797                 cond_resched();
1798         }
1799         return status;
1800 }
1801
1802 /**
1803  * qla2x00_program_flash_address() - Programs a flash address
1804  * @ha: HA context
1805  * @addr: Address in flash to program
1806  * @data: Data to be written in flash
1807  * @man_id: Flash manufacturer ID
1808  * @flash_id: Flash ID
1809  *
1810  * Returns 0 on success, else non-zero.
1811  */
1812 static int
1813 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1814     uint8_t data, uint8_t man_id, uint8_t flash_id)
1815 {
1816         /* Write Program Command Sequence. */
1817         if (IS_OEM_001(ha)) {
1818                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1819                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1820                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1821                 qla2x00_write_flash_byte(ha, addr, data);
1822         } else {
1823                 if (man_id == 0xda && flash_id == 0xc1) {
1824                         qla2x00_write_flash_byte(ha, addr, data);
1825                         if (addr & 0x7e)
1826                                 return 0;
1827                 } else {
1828                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1829                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1830                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1831                         qla2x00_write_flash_byte(ha, addr, data);
1832                 }
1833         }
1834
1835         udelay(150);
1836
1837         /* Wait for write to complete. */
1838         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1839 }
1840
1841 /**
1842  * qla2x00_erase_flash() - Erase the flash.
1843  * @ha: HA context
1844  * @man_id: Flash manufacturer ID
1845  * @flash_id: Flash ID
1846  *
1847  * Returns 0 on success, else non-zero.
1848  */
1849 static int
1850 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1851 {
1852         /* Individual Sector Erase Command Sequence */
1853         if (IS_OEM_001(ha)) {
1854                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1855                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1856                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1857                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1858                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1859                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1860         } else {
1861                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1862                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1863                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1864                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1865                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1866                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1867         }
1868
1869         udelay(150);
1870
1871         /* Wait for erase to complete. */
1872         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1873 }
1874
1875 /**
1876  * qla2x00_erase_flash_sector() - Erase a flash sector.
1877  * @ha: HA context
1878  * @addr: Flash sector to erase
1879  * @sec_mask: Sector address mask
1880  * @man_id: Flash manufacturer ID
1881  * @flash_id: Flash ID
1882  *
1883  * Returns 0 on success, else non-zero.
1884  */
1885 static int
1886 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1887     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1888 {
1889         /* Individual Sector Erase Command Sequence */
1890         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1891         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1892         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1893         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1894         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1895         if (man_id == 0x1f && flash_id == 0x13)
1896                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1897         else
1898                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1899
1900         udelay(150);
1901
1902         /* Wait for erase to complete. */
1903         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1904 }
1905
1906 /**
1907  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1908  * @man_id: Flash manufacturer ID
1909  * @flash_id: Flash ID
1910  */
1911 static void
1912 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1913     uint8_t *flash_id)
1914 {
1915         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1916         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1917         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1918         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1919         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1920         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1921         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1922         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1923 }
1924
1925 static void
1926 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1927         uint32_t saddr, uint32_t length)
1928 {
1929         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1930         uint32_t midpoint, ilength;
1931         uint8_t data;
1932
1933         midpoint = length / 2;
1934
1935         WRT_REG_WORD(&reg->nvram, 0);
1936         RD_REG_WORD(&reg->nvram);
1937         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1938                 if (ilength == midpoint) {
1939                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1940                         RD_REG_WORD(&reg->nvram);
1941                 }
1942                 data = qla2x00_read_flash_byte(ha, saddr);
1943                 if (saddr % 100)
1944                         udelay(10);
1945                 *tmp_buf = data;
1946                 cond_resched();
1947         }
1948 }
1949
1950 static inline void
1951 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1952 {
1953         int cnt;
1954         unsigned long flags;
1955         struct qla_hw_data *ha = vha->hw;
1956         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1957
1958         /* Suspend HBA. */
1959         scsi_block_requests(vha->host);
1960         ha->isp_ops->disable_intrs(ha);
1961         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1962
1963         /* Pause RISC. */
1964         spin_lock_irqsave(&ha->hardware_lock, flags);
1965         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1966         RD_REG_WORD(&reg->hccr);
1967         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1968                 for (cnt = 0; cnt < 30000; cnt++) {
1969                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1970                                 break;
1971                         udelay(100);
1972                 }
1973         } else {
1974                 udelay(10);
1975         }
1976         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1977 }
1978
1979 static inline void
1980 qla2x00_resume_hba(struct scsi_qla_host *vha)
1981 {
1982         struct qla_hw_data *ha = vha->hw;
1983
1984         /* Resume HBA. */
1985         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1986         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1987         qla2xxx_wake_dpc(vha);
1988         qla2x00_wait_for_chip_reset(vha);
1989         scsi_unblock_requests(vha->host);
1990 }
1991
1992 uint8_t *
1993 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1994     uint32_t offset, uint32_t length)
1995 {
1996         uint32_t addr, midpoint;
1997         uint8_t *data;
1998         struct qla_hw_data *ha = vha->hw;
1999         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2000
2001         /* Suspend HBA. */
2002         qla2x00_suspend_hba(vha);
2003
2004         /* Go with read. */
2005         midpoint = ha->optrom_size / 2;
2006
2007         qla2x00_flash_enable(ha);
2008         WRT_REG_WORD(&reg->nvram, 0);
2009         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2010         for (addr = offset, data = buf; addr < length; addr++, data++) {
2011                 if (addr == midpoint) {
2012                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2013                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2014                 }
2015
2016                 *data = qla2x00_read_flash_byte(ha, addr);
2017         }
2018         qla2x00_flash_disable(ha);
2019
2020         /* Resume HBA. */
2021         qla2x00_resume_hba(vha);
2022
2023         return buf;
2024 }
2025
2026 int
2027 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2028     uint32_t offset, uint32_t length)
2029 {
2030
2031         int rval;
2032         uint8_t man_id, flash_id, sec_number, data;
2033         uint16_t wd;
2034         uint32_t addr, liter, sec_mask, rest_addr;
2035         struct qla_hw_data *ha = vha->hw;
2036         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2037
2038         /* Suspend HBA. */
2039         qla2x00_suspend_hba(vha);
2040
2041         rval = QLA_SUCCESS;
2042         sec_number = 0;
2043
2044         /* Reset ISP chip. */
2045         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2046         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2047
2048         /* Go with write. */
2049         qla2x00_flash_enable(ha);
2050         do {    /* Loop once to provide quick error exit */
2051                 /* Structure of flash memory based on manufacturer */
2052                 if (IS_OEM_001(ha)) {
2053                         /* OEM variant with special flash part. */
2054                         man_id = flash_id = 0;
2055                         rest_addr = 0xffff;
2056                         sec_mask   = 0x10000;
2057                         goto update_flash;
2058                 }
2059                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2060                 switch (man_id) {
2061                 case 0x20: /* ST flash. */
2062                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2063                                 /*
2064                                  * ST m29w008at part - 64kb sector size with
2065                                  * 32kb,8kb,8kb,16kb sectors at memory address
2066                                  * 0xf0000.
2067                                  */
2068                                 rest_addr = 0xffff;
2069                                 sec_mask = 0x10000;
2070                                 break;
2071                         }
2072                         /*
2073                          * ST m29w010b part - 16kb sector size
2074                          * Default to 16kb sectors
2075                          */
2076                         rest_addr = 0x3fff;
2077                         sec_mask = 0x1c000;
2078                         break;
2079                 case 0x40: /* Mostel flash. */
2080                         /* Mostel v29c51001 part - 512 byte sector size. */
2081                         rest_addr = 0x1ff;
2082                         sec_mask = 0x1fe00;
2083                         break;
2084                 case 0xbf: /* SST flash. */
2085                         /* SST39sf10 part - 4kb sector size. */
2086                         rest_addr = 0xfff;
2087                         sec_mask = 0x1f000;
2088                         break;
2089                 case 0xda: /* Winbond flash. */
2090                         /* Winbond W29EE011 part - 256 byte sector size. */
2091                         rest_addr = 0x7f;
2092                         sec_mask = 0x1ff80;
2093                         break;
2094                 case 0xc2: /* Macronix flash. */
2095                         /* 64k sector size. */
2096                         if (flash_id == 0x38 || flash_id == 0x4f) {
2097                                 rest_addr = 0xffff;
2098                                 sec_mask = 0x10000;
2099                                 break;
2100                         }
2101                         /* Fall through... */
2102
2103                 case 0x1f: /* Atmel flash. */
2104                         /* 512k sector size. */
2105                         if (flash_id == 0x13) {
2106                                 rest_addr = 0x7fffffff;
2107                                 sec_mask =   0x80000000;
2108                                 break;
2109                         }
2110                         /* Fall through... */
2111
2112                 case 0x01: /* AMD flash. */
2113                         if (flash_id == 0x38 || flash_id == 0x40 ||
2114                             flash_id == 0x4f) {
2115                                 /* Am29LV081 part - 64kb sector size. */
2116                                 /* Am29LV002BT part - 64kb sector size. */
2117                                 rest_addr = 0xffff;
2118                                 sec_mask = 0x10000;
2119                                 break;
2120                         } else if (flash_id == 0x3e) {
2121                                 /*
2122                                  * Am29LV008b part - 64kb sector size with
2123                                  * 32kb,8kb,8kb,16kb sector at memory address
2124                                  * h0xf0000.
2125                                  */
2126                                 rest_addr = 0xffff;
2127                                 sec_mask = 0x10000;
2128                                 break;
2129                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2130                                 /*
2131                                  * Am29LV010 part or AM29f010 - 16kb sector
2132                                  * size.
2133                                  */
2134                                 rest_addr = 0x3fff;
2135                                 sec_mask = 0x1c000;
2136                                 break;
2137                         } else if (flash_id == 0x6d) {
2138                                 /* Am29LV001 part - 8kb sector size. */
2139                                 rest_addr = 0x1fff;
2140                                 sec_mask = 0x1e000;
2141                                 break;
2142                         }
2143                 default:
2144                         /* Default to 16 kb sector size. */
2145                         rest_addr = 0x3fff;
2146                         sec_mask = 0x1c000;
2147                         break;
2148                 }
2149
2150 update_flash:
2151                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2152                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2153                                 rval = QLA_FUNCTION_FAILED;
2154                                 break;
2155                         }
2156                 }
2157
2158                 for (addr = offset, liter = 0; liter < length; liter++,
2159                     addr++) {
2160                         data = buf[liter];
2161                         /* Are we at the beginning of a sector? */
2162                         if ((addr & rest_addr) == 0) {
2163                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2164                                         if (addr >= 0x10000UL) {
2165                                                 if (((addr >> 12) & 0xf0) &&
2166                                                     ((man_id == 0x01 &&
2167                                                         flash_id == 0x3e) ||
2168                                                      (man_id == 0x20 &&
2169                                                          flash_id == 0xd2))) {
2170                                                         sec_number++;
2171                                                         if (sec_number == 1) {
2172                                                                 rest_addr =
2173                                                                     0x7fff;
2174                                                                 sec_mask =
2175                                                                     0x18000;
2176                                                         } else if (
2177                                                             sec_number == 2 ||
2178                                                             sec_number == 3) {
2179                                                                 rest_addr =
2180                                                                     0x1fff;
2181                                                                 sec_mask =
2182                                                                     0x1e000;
2183                                                         } else if (
2184                                                             sec_number == 4) {
2185                                                                 rest_addr =
2186                                                                     0x3fff;
2187                                                                 sec_mask =
2188                                                                     0x1c000;
2189                                                         }
2190                                                 }
2191                                         }
2192                                 } else if (addr == ha->optrom_size / 2) {
2193                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2194                                         RD_REG_WORD(&reg->nvram);
2195                                 }
2196
2197                                 if (flash_id == 0xda && man_id == 0xc1) {
2198                                         qla2x00_write_flash_byte(ha, 0x5555,
2199                                             0xaa);
2200                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2201                                             0x55);
2202                                         qla2x00_write_flash_byte(ha, 0x5555,
2203                                             0xa0);
2204                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2205                                         /* Then erase it */
2206                                         if (qla2x00_erase_flash_sector(ha,
2207                                             addr, sec_mask, man_id,
2208                                             flash_id)) {
2209                                                 rval = QLA_FUNCTION_FAILED;
2210                                                 break;
2211                                         }
2212                                         if (man_id == 0x01 && flash_id == 0x6d)
2213                                                 sec_number++;
2214                                 }
2215                         }
2216
2217                         if (man_id == 0x01 && flash_id == 0x6d) {
2218                                 if (sec_number == 1 &&
2219                                     addr == (rest_addr - 1)) {
2220                                         rest_addr = 0x0fff;
2221                                         sec_mask   = 0x1f000;
2222                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2223                                         rest_addr = 0x3fff;
2224                                         sec_mask   = 0x1c000;
2225                                 }
2226                         }
2227
2228                         if (qla2x00_program_flash_address(ha, addr, data,
2229                             man_id, flash_id)) {
2230                                 rval = QLA_FUNCTION_FAILED;
2231                                 break;
2232                         }
2233                         cond_resched();
2234                 }
2235         } while (0);
2236         qla2x00_flash_disable(ha);
2237
2238         /* Resume HBA. */
2239         qla2x00_resume_hba(vha);
2240
2241         return rval;
2242 }
2243
2244 uint8_t *
2245 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2246     uint32_t offset, uint32_t length)
2247 {
2248         struct qla_hw_data *ha = vha->hw;
2249
2250         /* Suspend HBA. */
2251         scsi_block_requests(vha->host);
2252         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2253
2254         /* Go with read. */
2255         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2256
2257         /* Resume HBA. */
2258         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2259         scsi_unblock_requests(vha->host);
2260
2261         return buf;
2262 }
2263
2264 int
2265 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2266     uint32_t offset, uint32_t length)
2267 {
2268         int rval;
2269         struct qla_hw_data *ha = vha->hw;
2270
2271         /* Suspend HBA. */
2272         scsi_block_requests(vha->host);
2273         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2274
2275         /* Go with write. */
2276         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2277             length >> 2);
2278
2279         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2280         scsi_unblock_requests(vha->host);
2281
2282         return rval;
2283 }
2284
2285 uint8_t *
2286 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2287     uint32_t offset, uint32_t length)
2288 {
2289         int rval;
2290         dma_addr_t optrom_dma;
2291         void *optrom;
2292         uint8_t *pbuf;
2293         uint32_t faddr, left, burst;
2294         struct qla_hw_data *ha = vha->hw;
2295
2296         if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2297                 goto try_fast;
2298         if (offset & 0xfff)
2299                 goto slow_read;
2300         if (length < OPTROM_BURST_SIZE)
2301                 goto slow_read;
2302
2303 try_fast:
2304         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2305             &optrom_dma, GFP_KERNEL);
2306         if (!optrom) {
2307                 qla_printk(KERN_DEBUG, ha,
2308                     "Unable to allocate memory for optrom burst read "
2309                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2310
2311                 goto slow_read;
2312         }
2313
2314         pbuf = buf;
2315         faddr = offset >> 2;
2316         left = length >> 2;
2317         burst = OPTROM_BURST_DWORDS;
2318         while (left != 0) {
2319                 if (burst > left)
2320                         burst = left;
2321
2322                 rval = qla2x00_dump_ram(vha, optrom_dma,
2323                     flash_data_addr(ha, faddr), burst);
2324                 if (rval) {
2325                         qla_printk(KERN_WARNING, ha,
2326                             "Unable to burst-read optrom segment "
2327                             "(%x/%x/%llx).\n", rval,
2328                             flash_data_addr(ha, faddr),
2329                             (unsigned long long)optrom_dma);
2330                         qla_printk(KERN_WARNING, ha,
2331                             "Reverting to slow-read.\n");
2332
2333                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2334                             optrom, optrom_dma);
2335                         goto slow_read;
2336                 }
2337
2338                 memcpy(pbuf, optrom, burst * 4);
2339
2340                 left -= burst;
2341                 faddr += burst;
2342                 pbuf += burst * 4;
2343         }
2344
2345         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2346             optrom_dma);
2347
2348         return buf;
2349
2350 slow_read:
2351     return qla24xx_read_optrom_data(vha, buf, offset, length);
2352 }
2353
2354 /**
2355  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2356  * @ha: HA context
2357  * @pcids: Pointer to the FCODE PCI data structure
2358  *
2359  * The process of retrieving the FCODE version information is at best
2360  * described as interesting.
2361  *
2362  * Within the first 100h bytes of the image an ASCII string is present
2363  * which contains several pieces of information including the FCODE
2364  * version.  Unfortunately it seems the only reliable way to retrieve
2365  * the version is by scanning for another sentinel within the string,
2366  * the FCODE build date:
2367  *
2368  *      ... 2.00.02 10/17/02 ...
2369  *
2370  * Returns QLA_SUCCESS on successful retrieval of version.
2371  */
2372 static void
2373 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2374 {
2375         int ret = QLA_FUNCTION_FAILED;
2376         uint32_t istart, iend, iter, vend;
2377         uint8_t do_next, rbyte, *vbyte;
2378
2379         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2380
2381         /* Skip the PCI data structure. */
2382         istart = pcids +
2383             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2384                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2385         iend = istart + 0x100;
2386         do {
2387                 /* Scan for the sentinel date string...eeewww. */
2388                 do_next = 0;
2389                 iter = istart;
2390                 while ((iter < iend) && !do_next) {
2391                         iter++;
2392                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2393                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2394                                     '/')
2395                                         do_next++;
2396                                 else if (qla2x00_read_flash_byte(ha,
2397                                     iter + 3) == '/')
2398                                         do_next++;
2399                         }
2400                 }
2401                 if (!do_next)
2402                         break;
2403
2404                 /* Backtrack to previous ' ' (space). */
2405                 do_next = 0;
2406                 while ((iter > istart) && !do_next) {
2407                         iter--;
2408                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2409                                 do_next++;
2410                 }
2411                 if (!do_next)
2412                         break;
2413
2414                 /*
2415                  * Mark end of version tag, and find previous ' ' (space) or
2416                  * string length (recent FCODE images -- major hack ahead!!!).
2417                  */
2418                 vend = iter - 1;
2419                 do_next = 0;
2420                 while ((iter > istart) && !do_next) {
2421                         iter--;
2422                         rbyte = qla2x00_read_flash_byte(ha, iter);
2423                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2424                                 do_next++;
2425                 }
2426                 if (!do_next)
2427                         break;
2428
2429                 /* Mark beginning of version tag, and copy data. */
2430                 iter++;
2431                 if ((vend - iter) &&
2432                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2433                         vbyte = ha->fcode_revision;
2434                         while (iter <= vend) {
2435                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2436                                 iter++;
2437                         }
2438                         ret = QLA_SUCCESS;
2439                 }
2440         } while (0);
2441
2442         if (ret != QLA_SUCCESS)
2443                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2444 }
2445
2446 int
2447 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2448 {
2449         int ret = QLA_SUCCESS;
2450         uint8_t code_type, last_image;
2451         uint32_t pcihdr, pcids;
2452         uint8_t *dbyte;
2453         uint16_t *dcode;
2454         struct qla_hw_data *ha = vha->hw;
2455
2456         if (!ha->pio_address || !mbuf)
2457                 return QLA_FUNCTION_FAILED;
2458
2459         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2460         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2461         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2462         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2463
2464         qla2x00_flash_enable(ha);
2465
2466         /* Begin with first PCI expansion ROM header. */
2467         pcihdr = 0;
2468         last_image = 1;
2469         do {
2470                 /* Verify PCI expansion ROM header. */
2471                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2472                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2473                         /* No signature */
2474                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2475                             "signature.\n"));
2476                         ret = QLA_FUNCTION_FAILED;
2477                         break;
2478                 }
2479
2480                 /* Locate PCI data structure. */
2481                 pcids = pcihdr +
2482                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2483                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2484
2485                 /* Validate signature of PCI data structure. */
2486                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2487                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2488                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2489                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2490                         /* Incorrect header. */
2491                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2492                             "found pcir_adr=%x.\n", pcids));
2493                         ret = QLA_FUNCTION_FAILED;
2494                         break;
2495                 }
2496
2497                 /* Read version */
2498                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2499                 switch (code_type) {
2500                 case ROM_CODE_TYPE_BIOS:
2501                         /* Intel x86, PC-AT compatible. */
2502                         ha->bios_revision[0] =
2503                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2504                         ha->bios_revision[1] =
2505                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2506                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2507                             ha->bios_revision[1], ha->bios_revision[0]));
2508                         break;
2509                 case ROM_CODE_TYPE_FCODE:
2510                         /* Open Firmware standard for PCI (FCode). */
2511                         /* Eeeewww... */
2512                         qla2x00_get_fcode_version(ha, pcids);
2513                         break;
2514                 case ROM_CODE_TYPE_EFI:
2515                         /* Extensible Firmware Interface (EFI). */
2516                         ha->efi_revision[0] =
2517                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2518                         ha->efi_revision[1] =
2519                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2520                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2521                             ha->efi_revision[1], ha->efi_revision[0]));
2522                         break;
2523                 default:
2524                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2525                             "type %x at pcids %x.\n", code_type, pcids));
2526                         break;
2527                 }
2528
2529                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2530
2531                 /* Locate next PCI expansion ROM. */
2532                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2533                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2534         } while (!last_image);
2535
2536         if (IS_QLA2322(ha)) {
2537                 /* Read firmware image information. */
2538                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2539                 dbyte = mbuf;
2540                 memset(dbyte, 0, 8);
2541                 dcode = (uint16_t *)dbyte;
2542
2543                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2544                     8);
2545                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2546                     "flash:\n"));
2547                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2548
2549                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2550                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2551                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2552                     dcode[3] == 0)) {
2553                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2554                             "revision at %x.\n", ha->flt_region_fw * 4));
2555                 } else {
2556                         /* values are in big endian */
2557                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2558                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2559                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2560                 }
2561         }
2562
2563         qla2x00_flash_disable(ha);
2564
2565         return ret;
2566 }
2567
2568 int
2569 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2570 {
2571         int ret = QLA_SUCCESS;
2572         uint32_t pcihdr, pcids;
2573         uint32_t *dcode;
2574         uint8_t *bcode;
2575         uint8_t code_type, last_image;
2576         int i;
2577         struct qla_hw_data *ha = vha->hw;
2578
2579         if (!mbuf)
2580                 return QLA_FUNCTION_FAILED;
2581
2582         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2583         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2584         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2585         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2586
2587         dcode = mbuf;
2588
2589         /* Begin with first PCI expansion ROM header. */
2590         pcihdr = ha->flt_region_boot << 2;
2591         last_image = 1;
2592         do {
2593                 /* Verify PCI expansion ROM header. */
2594                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2595                 bcode = mbuf + (pcihdr % 4);
2596                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2597                         /* No signature */
2598                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2599                             "signature.\n"));
2600                         ret = QLA_FUNCTION_FAILED;
2601                         break;
2602                 }
2603
2604                 /* Locate PCI data structure. */
2605                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2606
2607                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2608                 bcode = mbuf + (pcihdr % 4);
2609
2610                 /* Validate signature of PCI data structure. */
2611                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2612                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2613                         /* Incorrect header. */
2614                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2615                             "found pcir_adr=%x.\n", pcids));
2616                         ret = QLA_FUNCTION_FAILED;
2617                         break;
2618                 }
2619
2620                 /* Read version */
2621                 code_type = bcode[0x14];
2622                 switch (code_type) {
2623                 case ROM_CODE_TYPE_BIOS:
2624                         /* Intel x86, PC-AT compatible. */
2625                         ha->bios_revision[0] = bcode[0x12];
2626                         ha->bios_revision[1] = bcode[0x13];
2627                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2628                             ha->bios_revision[1], ha->bios_revision[0]));
2629                         break;
2630                 case ROM_CODE_TYPE_FCODE:
2631                         /* Open Firmware standard for PCI (FCode). */
2632                         ha->fcode_revision[0] = bcode[0x12];
2633                         ha->fcode_revision[1] = bcode[0x13];
2634                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2635                             ha->fcode_revision[1], ha->fcode_revision[0]));
2636                         break;
2637                 case ROM_CODE_TYPE_EFI:
2638                         /* Extensible Firmware Interface (EFI). */
2639                         ha->efi_revision[0] = bcode[0x12];
2640                         ha->efi_revision[1] = bcode[0x13];
2641                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2642                             ha->efi_revision[1], ha->efi_revision[0]));
2643                         break;
2644                 default:
2645                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2646                             "type %x at pcids %x.\n", code_type, pcids));
2647                         break;
2648                 }
2649
2650                 last_image = bcode[0x15] & BIT_7;
2651
2652                 /* Locate next PCI expansion ROM. */
2653                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2654         } while (!last_image);
2655
2656         /* Read firmware image information. */
2657         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2658         dcode = mbuf;
2659
2660         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2661         for (i = 0; i < 4; i++)
2662                 dcode[i] = be32_to_cpu(dcode[i]);
2663
2664         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2665             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2666             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2667             dcode[3] == 0)) {
2668                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2669                     "revision at %x.\n", ha->flt_region_fw * 4));
2670         } else {
2671                 ha->fw_revision[0] = dcode[0];
2672                 ha->fw_revision[1] = dcode[1];
2673                 ha->fw_revision[2] = dcode[2];
2674                 ha->fw_revision[3] = dcode[3];
2675         }
2676
2677         return ret;
2678 }
2679
2680 static int
2681 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2682 {
2683         if (pos >= end || *pos != 0x82)
2684                 return 0;
2685
2686         pos += 3 + pos[1];
2687         if (pos >= end || *pos != 0x90)
2688                 return 0;
2689
2690         pos += 3 + pos[1];
2691         if (pos >= end || *pos != 0x78)
2692                 return 0;
2693
2694         return 1;
2695 }
2696
2697 int
2698 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2699 {
2700         struct qla_hw_data *ha = vha->hw;
2701         uint8_t *pos = ha->vpd;
2702         uint8_t *end = pos + ha->vpd_size;
2703         int len = 0;
2704
2705         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2706                 return 0;
2707
2708         while (pos < end && *pos != 0x78) {
2709                 len = (*pos == 0x82) ? pos[1] : pos[2];
2710
2711                 if (!strncmp(pos, key, strlen(key)))
2712                         break;
2713
2714                 if (*pos != 0x90 && *pos != 0x91)
2715                         pos += len;
2716
2717                 pos += 3;
2718         }
2719
2720         if (pos < end - len && *pos != 0x78)
2721                 return snprintf(str, size, "%.*s", len, pos + 3);
2722
2723         return 0;
2724 }