drivers/scsi/mvsas/mv_init.c

   1 /*
   2  * Marvell 88SE64xx/88SE94xx pci init
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   7  *
   8  * This file is licensed under GPLv2.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; version 2 of the
  13  * License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23  * USA
  24 */
  25
  26
  27 #include "mv_sas.h"
  28
  29 static int lldd_max_execute_num = 1;
  30 module_param_named(collector, lldd_max_execute_num, int, S_IRUGO);
  31 MODULE_PARM_DESC(collector, "\n"
  32         "\tIf greater than one, tells the SAS Layer to run in Task Collector\n"
  33         "\tMode.  If 1 or 0, tells the SAS Layer to run in Direct Mode.\n"
  34         "\tThe mvsas SAS LLDD supports both modes.\n"
  35         "\tDefault: 1 (Direct Mode).\n");
  36
  37 int interrupt_coalescing = 0x80;
  38
  39 static struct scsi_transport_template *mvs_stt;
  40 struct kmem_cache *mvs_task_list_cache;
  41 static const struct mvs_chip_info mvs_chips[] = {
  42         [chip_6320] =   { 1, 2, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },
  43         [chip_6440] =   { 1, 4, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },
  44         [chip_6485] =   { 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, },
  45         [chip_9180] =   { 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },
  46         [chip_9480] =   { 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },
  47         [chip_9445] =   { 1, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
  48         [chip_9485] =   { 2, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
  49         [chip_1300] =   { 1, 4, 0x400, 17, 16,  9, &mvs_64xx_dispatch, },
  50         [chip_1320] =   { 2, 4, 0x800, 17, 64,  9, &mvs_94xx_dispatch, },
  51 };
  52
  53 struct device_attribute *mvst_host_attrs[];
  54
  55 #define SOC_SAS_NUM 2
  56 #define SG_MX 64
  57
  58 static struct scsi_host_template mvs_sht = {
  59         .module                 = THIS_MODULE,
  60         .name                   = DRV_NAME,
  61         .queuecommand           = sas_queuecommand,
  62         .target_alloc           = sas_target_alloc,
  63         .slave_configure        = mvs_slave_configure,
  64         .slave_destroy          = sas_slave_destroy,
  65         .scan_finished          = mvs_scan_finished,
  66         .scan_start             = mvs_scan_start,
  67         .change_queue_depth     = sas_change_queue_depth,
  68         .change_queue_type      = sas_change_queue_type,
  69         .bios_param             = sas_bios_param,
  70         .can_queue              = 1,
  71         .cmd_per_lun            = 1,
  72         .this_id                = -1,
  73         .sg_tablesize           = SG_MX,
  74         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  75         .use_clustering         = ENABLE_CLUSTERING,
  76         .eh_device_reset_handler = sas_eh_device_reset_handler,
  77         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  78         .slave_alloc            = mvs_slave_alloc,
  79         .target_destroy         = sas_target_destroy,
  80         .ioctl                  = sas_ioctl,
  81         .shost_attrs            = mvst_host_attrs,
  82 };
  83
  84 static struct sas_domain_function_template mvs_transport_ops = {
  85         .lldd_dev_found         = mvs_dev_found,
  86         .lldd_dev_gone          = mvs_dev_gone,
  87         .lldd_execute_task      = mvs_queue_command,
  88         .lldd_control_phy       = mvs_phy_control,
  89
  90         .lldd_abort_task        = mvs_abort_task,
  91         .lldd_abort_task_set    = mvs_abort_task_set,
  92         .lldd_clear_aca         = mvs_clear_aca,
  93         .lldd_clear_task_set    = mvs_clear_task_set,
  94         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
  95         .lldd_lu_reset          = mvs_lu_reset,
  96         .lldd_query_task        = mvs_query_task,
  97         .lldd_port_formed       = mvs_port_formed,
  98         .lldd_port_deformed     = mvs_port_deformed,
  99
 100 };
 101
 102 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
 103 {
 104         struct mvs_phy *phy = &mvi->phy[phy_id];
 105         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 106
 107         phy->mvi = mvi;
 108         init_timer(&phy->timer);
 109         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
 110         sas_phy->class = SAS;
 111         sas_phy->iproto = SAS_PROTOCOL_ALL;
 112         sas_phy->tproto = 0;
 113         sas_phy->type = PHY_TYPE_PHYSICAL;
 114         sas_phy->role = PHY_ROLE_INITIATOR;
 115         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 116         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 117
 118         sas_phy->id = phy_id;
 119         sas_phy->sas_addr = &mvi->sas_addr[0];
 120         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 121         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
 122         sas_phy->lldd_phy = phy;
 123 }
 124
 125 static void mvs_free(struct mvs_info *mvi)
 126 {
 127         struct mvs_wq *mwq;
 128         int slot_nr;
 129
 130         if (!mvi)
 131                 return;
 132
 133         if (mvi->flags & MVF_FLAG_SOC)
 134                 slot_nr = MVS_SOC_SLOTS;
 135         else
 136                 slot_nr = MVS_SLOTS;
 137
 138         if (mvi->dma_pool)
 139                 pci_pool_destroy(mvi->dma_pool);
 140
 141         if (mvi->tx)
 142                 dma_free_coherent(mvi->dev,
 143                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 144                                   mvi->tx, mvi->tx_dma);
 145         if (mvi->rx_fis)
 146                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
 147                                   mvi->rx_fis, mvi->rx_fis_dma);
 148         if (mvi->rx)
 149                 dma_free_coherent(mvi->dev,
 150                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 151                                   mvi->rx, mvi->rx_dma);
 152         if (mvi->slot)
 153                 dma_free_coherent(mvi->dev,
 154                                   sizeof(*mvi->slot) * slot_nr,
 155                                   mvi->slot, mvi->slot_dma);
 156
 157         if (mvi->bulk_buffer)
 158                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 159                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
 160         if (mvi->bulk_buffer1)
 161                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 162                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
 163
 164         MVS_CHIP_DISP->chip_iounmap(mvi);
 165         if (mvi->shost)
 166                 scsi_host_put(mvi->shost);
 167         list_for_each_entry(mwq, &mvi->wq_list, entry)
 168                 cancel_delayed_work(&mwq->work_q);
 169         kfree(mvi);
 170 }
 171
 172 #ifdef MVS_USE_TASKLET
 173 struct tasklet_struct   mv_tasklet;
 174 static void mvs_tasklet(unsigned long opaque)
 175 {
 176         unsigned long flags;
 177         u32 stat;
 178         u16 core_nr, i = 0;
 179
 180         struct mvs_info *mvi;
 181         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
 182
 183         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 184         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 185
 186         if (unlikely(!mvi))
 187                 BUG_ON(1);
 188
 189         for (i = 0; i < core_nr; i++) {
 190                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 191                 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->irq);
 192                 if (stat)
 193                         MVS_CHIP_DISP->isr(mvi, mvi->irq, stat);
 194         }
 195
 196 }
 197 #endif
 198
 199 static irqreturn_t mvs_interrupt(int irq, void *opaque)
 200 {
 201         u32 core_nr, i = 0;
 202         u32 stat;
 203         struct mvs_info *mvi;
 204         struct sas_ha_struct *sha = opaque;
 205
 206         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 207         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 208
 209         if (unlikely(!mvi))
 210                 return IRQ_NONE;
 211
 212         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
 213         if (!stat)
 214                 return IRQ_NONE;
 215
 216 #ifdef MVS_USE_TASKLET
 217         tasklet_schedule(&mv_tasklet);
 218 #else
 219         for (i = 0; i < core_nr; i++) {
 220                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 221                 MVS_CHIP_DISP->isr(mvi, irq, stat);
 222         }
 223 #endif
 224         return IRQ_HANDLED;
 225 }
 226
 227 static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
 228 {
 229         int i = 0, slot_nr;
 230         char pool_name[32];
 231
 232         if (mvi->flags & MVF_FLAG_SOC)
 233                 slot_nr = MVS_SOC_SLOTS;
 234         else
 235                 slot_nr = MVS_SLOTS;
 236
 237         spin_lock_init(&mvi->lock);
 238         for (i = 0; i < mvi->chip->n_phy; i++) {
 239                 mvs_phy_init(mvi, i);
 240                 mvi->port[i].wide_port_phymap = 0;
 241                 mvi->port[i].port_attached = 0;
 242                 INIT_LIST_HEAD(&mvi->port[i].list);
 243         }
 244         for (i = 0; i < MVS_MAX_DEVICES; i++) {
 245                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
 246                 mvi->devices[i].dev_type = NO_DEVICE;
 247                 mvi->devices[i].device_id = i;
 248                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
 249                 init_timer(&mvi->devices[i].timer);
 250         }
 251
 252         /*
 253          * alloc and init our DMA areas
 254          */
 255         mvi->tx = dma_alloc_coherent(mvi->dev,
 256                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 257                                      &mvi->tx_dma, GFP_KERNEL);
 258         if (!mvi->tx)
 259                 goto err_out;
 260         memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
 261         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
 262                                          &mvi->rx_fis_dma, GFP_KERNEL);
 263         if (!mvi->rx_fis)
 264                 goto err_out;
 265         memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
 266
 267         mvi->rx = dma_alloc_coherent(mvi->dev,
 268                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 269                                      &mvi->rx_dma, GFP_KERNEL);
 270         if (!mvi->rx)
 271                 goto err_out;
 272         memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
 273         mvi->rx[0] = cpu_to_le32(0xfff);
 274         mvi->rx_cons = 0xfff;
 275
 276         mvi->slot = dma_alloc_coherent(mvi->dev,
 277                                        sizeof(*mvi->slot) * slot_nr,
 278                                        &mvi->slot_dma, GFP_KERNEL);
 279         if (!mvi->slot)
 280                 goto err_out;
 281         memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
 282
 283         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
 284                                        TRASH_BUCKET_SIZE,
 285                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
 286         if (!mvi->bulk_buffer)
 287                 goto err_out;
 288
 289         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
 290                                        TRASH_BUCKET_SIZE,
 291                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
 292         if (!mvi->bulk_buffer1)
 293                 goto err_out;
 294
 295         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
 296         mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
 297         if (!mvi->dma_pool) {
 298                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
 299                         goto err_out;
 300         }
 301         mvi->tags_num = slot_nr;
 302
 303         /* Initialize tags */
 304         mvs_tag_init(mvi);
 305         return 0;
 306 err_out:
 307         return 1;
 308 }
 309
 310
 311 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
 312 {
 313         unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
 314         struct pci_dev *pdev = mvi->pdev;
 315         if (bar_ex != -1) {
 316                 /*
 317                  * ioremap main and peripheral registers
 318                  */
 319                 res_start = pci_resource_start(pdev, bar_ex);
 320                 res_len = pci_resource_len(pdev, bar_ex);
 321                 if (!res_start || !res_len)
 322                         goto err_out;
 323
 324                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
 325                 if (res_flag_ex & IORESOURCE_MEM) {
 326                         if (res_flag_ex & IORESOURCE_CACHEABLE)
 327                                 mvi->regs_ex = ioremap(res_start, res_len);
 328                         else
 329                                 mvi->regs_ex = ioremap_nocache(res_start,
 330                                                 res_len);
 331                 } else
 332                         mvi->regs_ex = (void *)res_start;
 333                 if (!mvi->regs_ex)
 334                         goto err_out;
 335         }
 336
 337         res_start = pci_resource_start(pdev, bar);
 338         res_len = pci_resource_len(pdev, bar);
 339         if (!res_start || !res_len)
 340                 goto err_out;
 341
 342         res_flag = pci_resource_flags(pdev, bar);
 343         if (res_flag & IORESOURCE_CACHEABLE)
 344                 mvi->regs = ioremap(res_start, res_len);
 345         else
 346                 mvi->regs = ioremap_nocache(res_start, res_len);
 347
 348         if (!mvi->regs) {
 349                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
 350                         iounmap(mvi->regs_ex);
 351                 mvi->regs_ex = NULL;
 352                 goto err_out;
 353         }
 354
 355         return 0;
 356 err_out:
 357         return -1;
 358 }
 359
 360 void mvs_iounmap(void __iomem *regs)
 361 {
 362         iounmap(regs);
 363 }
 364
 365 static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev,
 366                                 const struct pci_device_id *ent,
 367                                 struct Scsi_Host *shost, unsigned int id)
 368 {
 369         struct mvs_info *mvi;
 370         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 371
 372         mvi = kzalloc(sizeof(*mvi) + MVS_SLOTS * sizeof(struct mvs_slot_info),
 373                         GFP_KERNEL);
 374         if (!mvi)
 375                 return NULL;
 376
 377         mvi->pdev = pdev;
 378         mvi->dev = &pdev->dev;
 379         mvi->chip_id = ent->driver_data;
 380         mvi->chip = &mvs_chips[mvi->chip_id];
 381         INIT_LIST_HEAD(&mvi->wq_list);
 382         mvi->irq = pdev->irq;
 383
 384         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
 385         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
 386
 387         mvi->id = id;
 388         mvi->sas = sha;
 389         mvi->shost = shost;
 390 #ifdef MVS_USE_TASKLET
 391         tasklet_init(&mv_tasklet, mvs_tasklet, (unsigned long)sha);
 392 #endif
 393
 394         if (MVS_CHIP_DISP->chip_ioremap(mvi))
 395                 goto err_out;
 396         if (!mvs_alloc(mvi, shost))
 397                 return mvi;
 398 err_out:
 399         mvs_free(mvi);
 400         return NULL;
 401 }
 402
 403 /* move to PCI layer or libata core? */
 404 static int pci_go_64(struct pci_dev *pdev)
 405 {
 406         int rc;
 407
 408         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 409                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 410                 if (rc) {
 411                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 412                         if (rc) {
 413                                 dev_printk(KERN_ERR, &pdev->dev,
 414                                            "64-bit DMA enable failed\n");
 415                                 return rc;
 416                         }
 417                 }
 418         } else {
 419                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 420                 if (rc) {
 421                         dev_printk(KERN_ERR, &pdev->dev,
 422                                    "32-bit DMA enable failed\n");
 423                         return rc;
 424                 }
 425                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 426                 if (rc) {
 427                         dev_printk(KERN_ERR, &pdev->dev,
 428                                    "32-bit consistent DMA enable failed\n");
 429                         return rc;
 430                 }
 431         }
 432
 433         return rc;
 434 }
 435
 436 static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost,
 437                                 const struct mvs_chip_info *chip_info)
 438 {
 439         int phy_nr, port_nr; unsigned short core_nr;
 440         struct asd_sas_phy **arr_phy;
 441         struct asd_sas_port **arr_port;
 442         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 443
 444         core_nr = chip_info->n_host;
 445         phy_nr  = core_nr * chip_info->n_phy;
 446         port_nr = phy_nr;
 447
 448         memset(sha, 0x00, sizeof(struct sas_ha_struct));
 449         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 450         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 451         if (!arr_phy || !arr_port)
 452                 goto exit_free;
 453
 454         sha->sas_phy = arr_phy;
 455         sha->sas_port = arr_port;
 456         sha->core.shost = shost;
 457
 458         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
 459         if (!sha->lldd_ha)
 460                 goto exit_free;
 461
 462         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
 463
 464         shost->transportt = mvs_stt;
 465         shost->max_id = 128;
 466         shost->max_lun = ~0;
 467         shost->max_channel = 1;
 468         shost->max_cmd_len = 16;
 469
 470         return 0;
 471 exit_free:
 472         kfree(arr_phy);
 473         kfree(arr_port);
 474         return -1;
 475
 476 }
 477
 478 static void  __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost,
 479                         const struct mvs_chip_info *chip_info)
 480 {
 481         int can_queue, i = 0, j = 0;
 482         struct mvs_info *mvi = NULL;
 483         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 484         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 485
 486         for (j = 0; j < nr_core; j++) {
 487                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
 488                 for (i = 0; i < chip_info->n_phy; i++) {
 489                         sha->sas_phy[j * chip_info->n_phy  + i] =
 490                                 &mvi->phy[i].sas_phy;
 491                         sha->sas_port[j * chip_info->n_phy + i] =
 492                                 &mvi->port[i].sas_port;
 493                 }
 494         }
 495
 496         sha->sas_ha_name = DRV_NAME;
 497         sha->dev = mvi->dev;
 498         sha->lldd_module = THIS_MODULE;
 499         sha->sas_addr = &mvi->sas_addr[0];
 500
 501         sha->num_phys = nr_core * chip_info->n_phy;
 502
 503         sha->lldd_max_execute_num = lldd_max_execute_num;
 504
 505         if (mvi->flags & MVF_FLAG_SOC)
 506                 can_queue = MVS_SOC_CAN_QUEUE;
 507         else
 508                 can_queue = MVS_CAN_QUEUE;
 509
 510         sha->lldd_queue_size = can_queue;
 511         shost->can_queue = can_queue;
 512         mvi->shost->cmd_per_lun = MVS_SLOTS/sha->num_phys;
 513         sha->core.shost = mvi->shost;
 514 }
 515
 516 static void mvs_init_sas_add(struct mvs_info *mvi)
 517 {
 518         u8 i;
 519         for (i = 0; i < mvi->chip->n_phy; i++) {
 520                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
 521                 mvi->phy[i].dev_sas_addr =
 522                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
 523         }
 524
 525         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
 526 }
 527
 528 static int __devinit mvs_pci_init(struct pci_dev *pdev,
 529                                   const struct pci_device_id *ent)
 530 {
 531         unsigned int rc, nhost = 0;
 532         struct mvs_info *mvi;
 533         irq_handler_t irq_handler = mvs_interrupt;
 534         struct Scsi_Host *shost = NULL;
 535         const struct mvs_chip_info *chip;
 536
 537         dev_printk(KERN_INFO, &pdev->dev,
 538                 "mvsas: driver version %s\n", DRV_VERSION);
 539         rc = pci_enable_device(pdev);
 540         if (rc)
 541                 goto err_out_enable;
 542
 543         pci_set_master(pdev);
 544
 545         rc = pci_request_regions(pdev, DRV_NAME);
 546         if (rc)
 547                 goto err_out_disable;
 548
 549         rc = pci_go_64(pdev);
 550         if (rc)
 551                 goto err_out_regions;
 552
 553         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
 554         if (!shost) {
 555                 rc = -ENOMEM;
 556                 goto err_out_regions;
 557         }
 558
 559         chip = &mvs_chips[ent->driver_data];
 560         SHOST_TO_SAS_HA(shost) =
 561                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
 562         if (!SHOST_TO_SAS_HA(shost)) {
 563                 kfree(shost);
 564                 rc = -ENOMEM;
 565                 goto err_out_regions;
 566         }
 567
 568         rc = mvs_prep_sas_ha_init(shost, chip);
 569         if (rc) {
 570                 kfree(shost);
 571                 rc = -ENOMEM;
 572                 goto err_out_regions;
 573         }
 574
 575         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 576
 577         do {
 578                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
 579                 if (!mvi) {
 580                         rc = -ENOMEM;
 581                         goto err_out_regions;
 582                 }
 583
 584                 memset(&mvi->hba_info_param, 0xFF,
 585                         sizeof(struct hba_info_page));
 586
 587                 mvs_init_sas_add(mvi);
 588
 589                 mvi->instance = nhost;
 590                 rc = MVS_CHIP_DISP->chip_init(mvi);
 591                 if (rc) {
 592                         mvs_free(mvi);
 593                         goto err_out_regions;
 594                 }
 595                 nhost++;
 596         } while (nhost < chip->n_host);
 597 #ifdef MVS_USE_TASKLET
 598         tasklet_init(&mv_tasklet, mvs_tasklet,
 599                      (unsigned long)SHOST_TO_SAS_HA(shost));
 600 #endif
 601
 602         mvs_post_sas_ha_init(shost, chip);
 603
 604         rc = scsi_add_host(shost, &pdev->dev);
 605         if (rc)
 606                 goto err_out_shost;
 607
 608         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 609         if (rc)
 610                 goto err_out_shost;
 611         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
 612                 DRV_NAME, SHOST_TO_SAS_HA(shost));
 613         if (rc)
 614                 goto err_not_sas;
 615
 616         MVS_CHIP_DISP->interrupt_enable(mvi);
 617
 618         scsi_scan_host(mvi->shost);
 619
 620         return 0;
 621
 622 err_not_sas:
 623         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
 624 err_out_shost:
 625         scsi_remove_host(mvi->shost);
 626 err_out_regions:
 627         pci_release_regions(pdev);
 628 err_out_disable:
 629         pci_disable_device(pdev);
 630 err_out_enable:
 631         return rc;
 632 }
 633
 634 static void __devexit mvs_pci_remove(struct pci_dev *pdev)
 635 {
 636         unsigned short core_nr, i = 0;
 637         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 638         struct mvs_info *mvi = NULL;
 639
 640         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 641         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 642
 643 #ifdef MVS_USE_TASKLET
 644         tasklet_kill(&mv_tasklet);
 645 #endif
 646
 647         pci_set_drvdata(pdev, NULL);
 648         sas_unregister_ha(sha);
 649         sas_remove_host(mvi->shost);
 650         scsi_remove_host(mvi->shost);
 651
 652         MVS_CHIP_DISP->interrupt_disable(mvi);
 653         free_irq(mvi->irq, sha);
 654         for (i = 0; i < core_nr; i++) {
 655                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 656                 mvs_free(mvi);
 657         }
 658         kfree(sha->sas_phy);
 659         kfree(sha->sas_port);
 660         kfree(sha);
 661         pci_release_regions(pdev);
 662         pci_disable_device(pdev);
 663         return;
 664 }
 665
 666 static struct pci_device_id __devinitdata mvs_pci_table[] = {
 667         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
 668         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
 669         {
 670                 .vendor         = PCI_VENDOR_ID_MARVELL,
 671                 .device         = 0x6440,
 672                 .subvendor      = PCI_ANY_ID,
 673                 .subdevice      = 0x6480,
 674                 .class          = 0,
 675                 .class_mask     = 0,
 676                 .driver_data    = chip_6485,
 677         },
 678         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
 679         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
 680         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
 681         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
 682         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
 683         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
 684         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
 685         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
 686         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
 687         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
 688         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
 689         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
 690         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
 691         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
 692         {
 693                 .vendor         = 0x1b4b,
 694                 .device         = 0x9445,
 695                 .subvendor      = PCI_ANY_ID,
 696                 .subdevice      = 0x9480,
 697                 .class          = 0,
 698                 .class_mask     = 0,
 699                 .driver_data    = chip_9445,
 700         },
 701         {
 702                 .vendor         = 0x1b4b,
 703                 .device         = 0x9485,
 704                 .subvendor      = PCI_ANY_ID,
 705                 .subdevice      = 0x9480,
 706                 .class          = 0,
 707                 .class_mask     = 0,
 708                 .driver_data    = chip_9485,
 709         },
 710
 711         { }     /* terminate list */
 712 };
 713
 714 static struct pci_driver mvs_pci_driver = {
 715         .name           = DRV_NAME,
 716         .id_table       = mvs_pci_table,
 717         .probe          = mvs_pci_init,
 718         .remove         = __devexit_p(mvs_pci_remove),
 719 };
 720
 721 static ssize_t
 722 mvs_show_driver_version(struct device *cdev,
 723                 struct device_attribute *attr,  char *buffer)
 724 {
 725         return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
 726 }
 727
 728 static DEVICE_ATTR(driver_version,
 729                          S_IRUGO,
 730                          mvs_show_driver_version,
 731                          NULL);
 732
 733 static ssize_t
 734 mvs_store_interrupt_coalescing(struct device *cdev,
 735                         struct device_attribute *attr,
 736                         const char *buffer, size_t size)
 737 {
 738         int val = 0;
 739         struct mvs_info *mvi = NULL;
 740         struct Scsi_Host *shost = class_to_shost(cdev);
 741         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 742         u8 i, core_nr;
 743         if (buffer == NULL)
 744                 return size;
 745
 746         if (sscanf(buffer, "%d", &val) != 1)
 747                 return -EINVAL;
 748
 749         if (val >= 0x10000) {
 750                 mv_dprintk("interrupt coalescing timer %d us is"
 751                         "too long\n", val);
 752                 return strlen(buffer);
 753         }
 754
 755         interrupt_coalescing = val;
 756
 757         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 758         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 759
 760         if (unlikely(!mvi))
 761                 return -EINVAL;
 762
 763         for (i = 0; i < core_nr; i++) {
 764                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 765                 if (MVS_CHIP_DISP->tune_interrupt)
 766                         MVS_CHIP_DISP->tune_interrupt(mvi,
 767                                 interrupt_coalescing);
 768         }
 769         mv_dprintk("set interrupt coalescing time to %d us\n",
 770                 interrupt_coalescing);
 771         return strlen(buffer);
 772 }
 773
 774 static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
 775                         struct device_attribute *attr, char *buffer)
 776 {
 777         return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
 778 }
 779
 780 static DEVICE_ATTR(interrupt_coalescing,
 781                          S_IRUGO|S_IWUSR,
 782                          mvs_show_interrupt_coalescing,
 783                          mvs_store_interrupt_coalescing);
 784
 785 /* task handler */
 786 struct task_struct *mvs_th;
 787 static int __init mvs_init(void)
 788 {
 789         int rc;
 790         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
 791         if (!mvs_stt)
 792                 return -ENOMEM;
 793
 794         mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list),
 795                                                          0, SLAB_HWCACHE_ALIGN, NULL);
 796         if (!mvs_task_list_cache) {
 797                 rc = -ENOMEM;
 798                 mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__);
 799                 goto err_out;
 800         }
 801
 802         rc = pci_register_driver(&mvs_pci_driver);
 803
 804         if (rc)
 805                 goto err_out;
 806
 807         return 0;
 808
 809 err_out:
 810         sas_release_transport(mvs_stt);
 811         return rc;
 812 }
 813
 814 static void __exit mvs_exit(void)
 815 {
 816         pci_unregister_driver(&mvs_pci_driver);
 817         sas_release_transport(mvs_stt);
 818         kmem_cache_destroy(mvs_task_list_cache);
 819 }
 820
 821 struct device_attribute *mvst_host_attrs[] = {
 822         &dev_attr_driver_version,
 823         &dev_attr_interrupt_coalescing,
 824         NULL,
 825 };
 826
 827 module_init(mvs_init);
 828 module_exit(mvs_exit);
 829
 830 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
 831 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
 832 MODULE_VERSION(DRV_VERSION);
 833 MODULE_LICENSE("GPL");
 834 #ifdef CONFIG_PCI
 835 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
 836 #endif