2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
20 #include "bfi_cbreg.h"
23 BFA_TRC_FILE(CNA, IOC_CB);
26 * forward declarations
28 static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
29 static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
30 static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
31 static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
32 static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
33 static void bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc);
34 static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
36 static struct bfa_ioc_hwif_s hwif_cb;
39 * Called from bfa_ioc_attach() to map asic specific calls.
42 bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
44 hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
45 hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
46 hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
47 hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
48 hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
49 hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
50 hwif_cb.ioc_notify_hbfail = bfa_ioc_cb_notify_hbfail;
51 hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
53 ioc->ioc_hwif = &hwif_cb;
57 * Return true if firmware of current driver matches the running firmware.
60 bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
66 bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
71 * Notify other functions on HB failure.
74 bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc)
76 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
77 readl(ioc->ioc_regs.err_set);
81 * Host to LPU mailbox message addresses
83 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
84 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
85 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
89 * Host <-> LPU mailbox command/status registers
91 static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
93 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
94 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
98 bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
101 int pcifn = bfa_ioc_pcifn(ioc);
103 rb = bfa_ioc_bar0(ioc);
105 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
106 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
107 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
109 if (ioc->port_id == 0) {
110 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
111 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
113 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
114 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
118 * Host <-> LPU mailbox command/status registers
120 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
121 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
124 * PSS control registers
126 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
127 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
128 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG);
129 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG);
132 * IOC semaphore registers and serialization
134 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
135 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
140 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
141 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
144 * err set reg : for notification of hb failure
146 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
150 * Initialize IOC to port mapping.
154 bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
157 * For crossbow, port id is same as pci function.
159 ioc->port_id = bfa_ioc_pcifn(ioc);
161 bfa_trc(ioc, ioc->port_id);
165 * Set interrupt mode for a function: INTX or MSIX
168 bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
173 * Cleanup hw semaphore and usecnt registers
176 bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
180 * Read the hw sem reg to make sure that it is locked
181 * before we clear it. If it is not locked, writing 1
182 * will lock it instead of clearing it.
184 readl(ioc->ioc_regs.ioc_sem_reg);
185 writel(1, ioc->ioc_regs.ioc_sem_reg);
191 bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
193 u32 pll_sclk, pll_fclk;
195 pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN |
196 __APP_PLL_212_P0_1(3U) |
197 __APP_PLL_212_JITLMT0_1(3U) |
198 __APP_PLL_212_CNTLMT0_1(3U);
199 pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN |
200 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
201 __APP_PLL_400_JITLMT0_1(3U) |
202 __APP_PLL_400_CNTLMT0_1(3U);
203 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
204 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
205 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
206 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
207 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
208 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
209 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
210 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
211 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
212 writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET,
213 rb + APP_PLL_212_CTL_REG);
214 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
215 writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET,
216 rb + APP_PLL_400_CTL_REG);
218 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
219 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
220 writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET,
221 rb + APP_PLL_212_CTL_REG);
222 writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET,
223 rb + APP_PLL_400_CTL_REG);
225 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
226 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
227 writel(pll_sclk, (rb + APP_PLL_212_CTL_REG));
228 writel(pll_fclk, (rb + APP_PLL_400_CTL_REG));
230 return BFA_STATUS_OK;