drivers/scsi/atp870u.c

   1 /*
   2  *  Copyright (C) 1997  Wu Ching Chen
   3  *  2.1.x update (C) 1998  Krzysztof G. Baranowski
   4  *  2.5.x update (C) 2002  Red Hat
   5  *  2.6.x update (C) 2004  Red Hat
   6  *
   7  * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
   8  *
   9  * Wu Ching Chen : NULL pointer fixes  2000/06/02
  10  *                 support atp876 chip
  11  *                 enable 32 bit fifo transfer
  12  *                 support cdrom & remove device run ultra speed
  13  *                 fix disconnect bug  2000/12/21
  14  *                 support atp880 chip lvd u160 2001/05/15
  15  *                 fix prd table bug 2001/09/12 (7.1)
  16  *
  17  * atp885 support add by ACARD Hao Ping Lian 2005/01/05
  18  */
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/string.h>
  25 #include <linux/ioport.h>
  26 #include <linux/delay.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/pci.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #include <asm/system.h>
  34 #include <asm/io.h>
  35
  36 #include <scsi/scsi.h>
  37 #include <scsi/scsi_cmnd.h>
  38 #include <scsi/scsi_device.h>
  39 #include <scsi/scsi_host.h>
  40
  41 #include "atp870u.h"
  42
  43 static struct scsi_host_template atp870u_template;
  44 static void send_s870(struct atp_unit *dev,unsigned char c);
  45 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c);
  46 static void tscam_885(void);
  47
  48 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
  49 {
  50         unsigned long flags;
  51         unsigned short int tmpcip, id;
  52         unsigned char i, j, c, target_id, lun,cmdp;
  53         unsigned char *prd;
  54         struct scsi_cmnd *workreq;
  55         unsigned int workport, tmport, tmport1;
  56         unsigned long adrcnt, k;
  57 #ifdef ED_DBGP
  58         unsigned long l;
  59 #endif
  60         int errstus;
  61         struct Scsi_Host *host = dev_id;
  62         struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  63
  64         for (c = 0; c < 2; c++) {
  65                 tmport = dev->ioport[c] + 0x1f;
  66                 j = inb(tmport);
  67                 if ((j & 0x80) != 0)
  68                 {
  69                         goto ch_sel;
  70                 }
  71                 dev->in_int[c] = 0;
  72         }
  73         return IRQ_NONE;
  74 ch_sel:
  75 #ifdef ED_DBGP
  76         printk("atp870u_intr_handle enter\n");
  77 #endif
  78         dev->in_int[c] = 1;
  79         cmdp = inb(dev->ioport[c] + 0x10);
  80         workport = dev->ioport[c];
  81         if (dev->working[c] != 0) {
  82                 if (dev->dev_id == ATP885_DEVID) {
  83                         tmport1 = workport + 0x16;
  84                         if ((inb(tmport1) & 0x80) == 0)
  85                                 outb((inb(tmport1) | 0x80), tmport1);
  86                 }
  87                 tmpcip = dev->pciport[c];
  88                 if ((inb(tmpcip) & 0x08) != 0)
  89                 {
  90                         tmpcip += 0x2;
  91                         for (k=0; k < 1000; k++) {
  92                                 if ((inb(tmpcip) & 0x08) == 0) {
  93                                         goto stop_dma;
  94                                 }
  95                                 if ((inb(tmpcip) & 0x01) == 0) {
  96                                         goto stop_dma;
  97                                 }
  98                         }
  99                 }
 100 stop_dma:
 101                 tmpcip = dev->pciport[c];
 102                 outb(0x00, tmpcip);
 103                 tmport -= 0x08;
 104
 105                 i = inb(tmport);
 106
 107                 if (dev->dev_id == ATP885_DEVID) {
 108                         tmpcip += 2;
 109                         outb(0x06, tmpcip);
 110                         tmpcip -= 2;
 111                 }
 112
 113                 tmport -= 0x02;
 114                 target_id = inb(tmport);
 115                 tmport += 0x02;
 116
 117                 /*
 118                  *      Remap wide devices onto id numbers
 119                  */
 120
 121                 if ((target_id & 0x40) != 0) {
 122                         target_id = (target_id & 0x07) | 0x08;
 123                 } else {
 124                         target_id &= 0x07;
 125                 }
 126
 127                 if ((j & 0x40) != 0) {
 128                      if (dev->last_cmd[c] == 0xff) {
 129                         dev->last_cmd[c] = target_id;
 130                      }
 131                      dev->last_cmd[c] |= 0x40;
 132                 }
 133                 if (dev->dev_id == ATP885_DEVID)
 134                         dev->r1f[c][target_id] |= j;
 135 #ifdef ED_DBGP
 136                 printk("atp870u_intr_handle status = %x\n",i);
 137 #endif
 138                 if (i == 0x85) {
 139                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 140                            dev->last_cmd[c] = 0xff;
 141                         }
 142                         if (dev->dev_id == ATP885_DEVID) {
 143                                 tmport -= 0x05;
 144                                 adrcnt = 0;
 145                                 ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 146                                 ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 147                                 ((unsigned char *) &adrcnt)[0] = inb(tmport);
 148                                 if (dev->id[c][target_id].last_len != adrcnt)
 149                                 {
 150                                         k = dev->id[c][target_id].last_len;
 151                                         k -= adrcnt;
 152                                         dev->id[c][target_id].tran_len = k;
 153                                 dev->id[c][target_id].last_len = adrcnt;
 154                                 }
 155 #ifdef ED_DBGP
 156                                 printk("tmport = %x dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",tmport,dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
 157 #endif
 158                         }
 159
 160                         /*
 161                          *      Flip wide
 162                          */
 163                         if (dev->wide_id[c] != 0) {
 164                                 tmport = workport + 0x1b;
 165                                 outb(0x01, tmport);
 166                                 while ((inb(tmport) & 0x01) != 0x01) {
 167                                         outb(0x01, tmport);
 168                                 }
 169                         }
 170                         /*
 171                          *      Issue more commands
 172                          */
 173                         spin_lock_irqsave(dev->host->host_lock, flags);
 174                         if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
 175                             (dev->in_snd[c] == 0)) {
 176 #ifdef ED_DBGP
 177                                 printk("Call sent_s870\n");
 178 #endif
 179                                 send_s870(dev,c);
 180                         }
 181                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 182                         /*
 183                          *      Done
 184                          */
 185                         dev->in_int[c] = 0;
 186 #ifdef ED_DBGP
 187                                 printk("Status 0x85 return\n");
 188 #endif
 189                         goto handled;
 190                 }
 191
 192                 if (i == 0x40) {
 193                      dev->last_cmd[c] |= 0x40;
 194                      dev->in_int[c] = 0;
 195                      goto handled;
 196                 }
 197
 198                 if (i == 0x21) {
 199                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 200                            dev->last_cmd[c] = 0xff;
 201                         }
 202                         tmport -= 0x05;
 203                         adrcnt = 0;
 204                         ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 205                         ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 206                         ((unsigned char *) &adrcnt)[0] = inb(tmport);
 207                         k = dev->id[c][target_id].last_len;
 208                         k -= adrcnt;
 209                         dev->id[c][target_id].tran_len = k;
 210                         dev->id[c][target_id].last_len = adrcnt;
 211                         tmport -= 0x04;
 212                         outb(0x41, tmport);
 213                         tmport += 0x08;
 214                         outb(0x08, tmport);
 215                         dev->in_int[c] = 0;
 216                         goto handled;
 217                 }
 218
 219                 if (dev->dev_id == ATP885_DEVID) {
 220                         if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
 221                                 if ((i == 0x4c) || (i == 0x8c))
 222                                         i=0x48;
 223                                 else
 224                                         i=0x49;
 225                         }
 226
 227                 }
 228                 if ((i == 0x80) || (i == 0x8f)) {
 229 #ifdef ED_DBGP
 230                         printk(KERN_DEBUG "Device reselect\n");
 231 #endif
 232                         lun = 0;
 233                         tmport -= 0x07;
 234                         if (cmdp == 0x44 || i==0x80) {
 235                                 tmport += 0x0d;
 236                                 lun = inb(tmport) & 0x07;
 237                         } else {
 238                                 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 239                                    dev->last_cmd[c] = 0xff;
 240                                 }
 241                                 if (cmdp == 0x41) {
 242 #ifdef ED_DBGP
 243                                         printk("cmdp = 0x41\n");
 244 #endif
 245                                         tmport += 0x02;
 246                                         adrcnt = 0;
 247                                         ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 248                                         ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 249                                         ((unsigned char *) &adrcnt)[0] = inb(tmport);
 250                                         k = dev->id[c][target_id].last_len;
 251                                         k -= adrcnt;
 252                                         dev->id[c][target_id].tran_len = k;
 253                                         dev->id[c][target_id].last_len = adrcnt;
 254                                         tmport += 0x04;
 255                                         outb(0x08, tmport);
 256                                         dev->in_int[c] = 0;
 257                                         goto handled;
 258                                 } else {
 259 #ifdef ED_DBGP
 260                                         printk("cmdp != 0x41\n");
 261 #endif
 262                                         outb(0x46, tmport);
 263                                         dev->id[c][target_id].dirct = 0x00;
 264                                         tmport += 0x02;
 265                                         outb(0x00, tmport++);
 266                                         outb(0x00, tmport++);
 267                                         outb(0x00, tmport++);
 268                                         tmport += 0x03;
 269                                         outb(0x08, tmport);
 270                                         dev->in_int[c] = 0;
 271                                         goto handled;
 272                                 }
 273                         }
 274                         if (dev->last_cmd[c] != 0xff) {
 275                            dev->last_cmd[c] |= 0x40;
 276                         }
 277                         if (dev->dev_id == ATP885_DEVID) {
 278                                 j = inb(dev->baseport + 0x29) & 0xfe;
 279                                 outb(j, dev->baseport + 0x29);
 280                                 tmport = workport + 0x16;
 281                         } else {
 282                                 tmport = workport + 0x10;
 283                                 outb(0x45, tmport);
 284                                 tmport += 0x06;
 285                         }
 286
 287                         target_id = inb(tmport);
 288                         /*
 289                          *      Remap wide identifiers
 290                          */
 291                         if ((target_id & 0x10) != 0) {
 292                                 target_id = (target_id & 0x07) | 0x08;
 293                         } else {
 294                                 target_id &= 0x07;
 295                         }
 296                         if (dev->dev_id == ATP885_DEVID) {
 297                                 tmport = workport + 0x10;
 298                                 outb(0x45, tmport);
 299                         }
 300                         workreq = dev->id[c][target_id].curr_req;
 301 #ifdef ED_DBGP
 302                         scmd_printk(KERN_DEBUG, workreq, "CDB");
 303                         for (l = 0; l < workreq->cmd_len; l++)
 304                                 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
 305                         printk("\n");
 306 #endif
 307
 308                         tmport = workport + 0x0f;
 309                         outb(lun, tmport);
 310                         tmport += 0x02;
 311                         outb(dev->id[c][target_id].devsp, tmport++);
 312                         adrcnt = dev->id[c][target_id].tran_len;
 313                         k = dev->id[c][target_id].last_len;
 314
 315                         outb(((unsigned char *) &k)[2], tmport++);
 316                         outb(((unsigned char *) &k)[1], tmport++);
 317                         outb(((unsigned char *) &k)[0], tmport++);
 318 #ifdef ED_DBGP
 319                         printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, inb(tmport-1), inb(tmport-2), inb(tmport-3));
 320 #endif
 321                         /* Remap wide */
 322                         j = target_id;
 323                         if (target_id > 7) {
 324                                 j = (j & 0x07) | 0x40;
 325                         }
 326                         /* Add direction */
 327                         j |= dev->id[c][target_id].dirct;
 328                         outb(j, tmport++);
 329                         outb(0x80,tmport);
 330
 331                         /* enable 32 bit fifo transfer */
 332                         if (dev->dev_id == ATP885_DEVID) {
 333                                 tmpcip = dev->pciport[c] + 1;
 334                                 i=inb(tmpcip) & 0xf3;
 335                                 //j=workreq->cmnd[0];
 336                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 337                                    i |= 0x0c;
 338                                 }
 339                                 outb(i,tmpcip);
 340                         } else if ((dev->dev_id == ATP880_DEVID1) ||
 341                                    (dev->dev_id == ATP880_DEVID2) ) {
 342                                 tmport = workport - 0x05;
 343                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 344                                         outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport);
 345                                 } else {
 346                                         outb((unsigned char) (inb(tmport) & 0x3f), tmport);
 347                                 }
 348                         } else {
 349                                 tmport = workport + 0x3a;
 350                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 351                                         outb((unsigned char) ((inb(tmport) & 0xf3) | 0x08), tmport);
 352                                 } else {
 353                                         outb((unsigned char) (inb(tmport) & 0xf3), tmport);
 354                                 }
 355                         }
 356                         tmport = workport + 0x1b;
 357                         j = 0;
 358                         id = 1;
 359                         id = id << target_id;
 360                         /*
 361                          *      Is this a wide device
 362                          */
 363                         if ((id & dev->wide_id[c]) != 0) {
 364                                 j |= 0x01;
 365                         }
 366                         outb(j, tmport);
 367                         while ((inb(tmport) & 0x01) != j) {
 368                                 outb(j,tmport);
 369                         }
 370                         if (dev->id[c][target_id].last_len == 0) {
 371                                 tmport = workport + 0x18;
 372                                 outb(0x08, tmport);
 373                                 dev->in_int[c] = 0;
 374 #ifdef ED_DBGP
 375                                 printk("dev->id[c][target_id].last_len = 0\n");
 376 #endif
 377                                 goto handled;
 378                         }
 379 #ifdef ED_DBGP
 380                         printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
 381 #endif
 382                         prd = dev->id[c][target_id].prd_pos;
 383                         while (adrcnt != 0) {
 384                                 id = ((unsigned short int *)prd)[2];
 385                                 if (id == 0) {
 386                                         k = 0x10000;
 387                                 } else {
 388                                         k = id;
 389                                 }
 390                                 if (k > adrcnt) {
 391                                         ((unsigned short int *)prd)[2] = (unsigned short int)
 392                                             (k - adrcnt);
 393                                         ((unsigned long *)prd)[0] += adrcnt;
 394                                         adrcnt = 0;
 395                                         dev->id[c][target_id].prd_pos = prd;
 396                                 } else {
 397                                         adrcnt -= k;
 398                                         dev->id[c][target_id].prdaddr += 0x08;
 399                                         prd += 0x08;
 400                                         if (adrcnt == 0) {
 401                                                 dev->id[c][target_id].prd_pos = prd;
 402                                         }
 403                                 }
 404                         }
 405                         tmpcip = dev->pciport[c] + 0x04;
 406                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 407 #ifdef ED_DBGP
 408                         printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
 409 #endif
 410                         if (dev->dev_id == ATP885_DEVID) {
 411                                 tmpcip -= 0x04;
 412                         } else {
 413                                 tmpcip -= 0x02;
 414                                 outb(0x06, tmpcip);
 415                                 outb(0x00, tmpcip);
 416                                 tmpcip -= 0x02;
 417                         }
 418                         tmport = workport + 0x18;
 419                         /*
 420                          *      Check transfer direction
 421                          */
 422                         if (dev->id[c][target_id].dirct != 0) {
 423                                 outb(0x08, tmport);
 424                                 outb(0x01, tmpcip);
 425                                 dev->in_int[c] = 0;
 426 #ifdef ED_DBGP
 427                                 printk("status 0x80 return dirct != 0\n");
 428 #endif
 429                                 goto handled;
 430                         }
 431                         outb(0x08, tmport);
 432                         outb(0x09, tmpcip);
 433                         dev->in_int[c] = 0;
 434 #ifdef ED_DBGP
 435                         printk("status 0x80 return dirct = 0\n");
 436 #endif
 437                         goto handled;
 438                 }
 439
 440                 /*
 441                  *      Current scsi request on this target
 442                  */
 443
 444                 workreq = dev->id[c][target_id].curr_req;
 445
 446                 if (i == 0x42) {
 447                         if ((dev->last_cmd[c] & 0xf0) != 0x40)
 448                         {
 449                            dev->last_cmd[c] = 0xff;
 450                         }
 451                         errstus = 0x02;
 452                         workreq->result = errstus;
 453                         goto go_42;
 454                 }
 455                 if (i == 0x16) {
 456                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 457                            dev->last_cmd[c] = 0xff;
 458                         }
 459                         errstus = 0;
 460                         tmport -= 0x08;
 461                         errstus = inb(tmport);
 462                         if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
 463                            printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
 464                            errstus = 0x02;
 465                         }
 466                         workreq->result = errstus;
 467 go_42:
 468                         if (dev->dev_id == ATP885_DEVID) {
 469                                 j = inb(dev->baseport + 0x29) | 0x01;
 470                                 outb(j, dev->baseport + 0x29);
 471                         }
 472                         /*
 473                          *      Complete the command
 474                          */
 475                         scsi_dma_unmap(workreq);
 476
 477                         spin_lock_irqsave(dev->host->host_lock, flags);
 478                         (*workreq->scsi_done) (workreq);
 479 #ifdef ED_DBGP
 480                            printk("workreq->scsi_done\n");
 481 #endif
 482                         /*
 483                          *      Clear it off the queue
 484                          */
 485                         dev->id[c][target_id].curr_req = NULL;
 486                         dev->working[c]--;
 487                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 488                         /*
 489                          *      Take it back wide
 490                          */
 491                         if (dev->wide_id[c] != 0) {
 492                                 tmport = workport + 0x1b;
 493                                 outb(0x01, tmport);
 494                                 while ((inb(tmport) & 0x01) != 0x01) {
 495                                         outb(0x01, tmport);
 496                                 }
 497                         }
 498                         /*
 499                          *      If there is stuff to send and nothing going then send it
 500                          */
 501                         spin_lock_irqsave(dev->host->host_lock, flags);
 502                         if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
 503                             (dev->in_snd[c] == 0)) {
 504 #ifdef ED_DBGP
 505                            printk("Call sent_s870(scsi_done)\n");
 506 #endif
 507                            send_s870(dev,c);
 508                         }
 509                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 510                         dev->in_int[c] = 0;
 511                         goto handled;
 512                 }
 513                 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 514                    dev->last_cmd[c] = 0xff;
 515                 }
 516                 if (i == 0x4f) {
 517                         i = 0x89;
 518                 }
 519                 i &= 0x0f;
 520                 if (i == 0x09) {
 521                         tmpcip += 4;
 522                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 523                         tmpcip = tmpcip - 2;
 524                         outb(0x06, tmpcip);
 525                         outb(0x00, tmpcip);
 526                         tmpcip = tmpcip - 2;
 527                         tmport = workport + 0x10;
 528                         outb(0x41, tmport);
 529                         if (dev->dev_id == ATP885_DEVID) {
 530                                 tmport += 2;
 531                                 k = dev->id[c][target_id].last_len;
 532                                 outb((unsigned char) (((unsigned char *) (&k))[2]), tmport++);
 533                                 outb((unsigned char) (((unsigned char *) (&k))[1]), tmport++);
 534                                 outb((unsigned char) (((unsigned char *) (&k))[0]), tmport);
 535                                 dev->id[c][target_id].dirct = 0x00;
 536                                 tmport += 0x04;
 537                         } else {
 538                                 dev->id[c][target_id].dirct = 0x00;
 539                                 tmport += 0x08;
 540                         }
 541                         outb(0x08, tmport);
 542                         outb(0x09, tmpcip);
 543                         dev->in_int[c] = 0;
 544                         goto handled;
 545                 }
 546                 if (i == 0x08) {
 547                         tmpcip += 4;
 548                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 549                         tmpcip = tmpcip - 2;
 550                         outb(0x06, tmpcip);
 551                         outb(0x00, tmpcip);
 552                         tmpcip = tmpcip - 2;
 553                         tmport = workport + 0x10;
 554                         outb(0x41, tmport);
 555                         if (dev->dev_id == ATP885_DEVID) {
 556                                 tmport += 2;
 557                                 k = dev->id[c][target_id].last_len;
 558                                 outb((unsigned char) (((unsigned char *) (&k))[2]), tmport++);
 559                                 outb((unsigned char) (((unsigned char *) (&k))[1]), tmport++);
 560                                 outb((unsigned char) (((unsigned char *) (&k))[0]), tmport++);
 561                         } else {
 562                                 tmport += 5;
 563                         }
 564                         outb((unsigned char) (inb(tmport) | 0x20), tmport);
 565                         dev->id[c][target_id].dirct = 0x20;
 566                         tmport += 0x03;
 567                         outb(0x08, tmport);
 568                         outb(0x01, tmpcip);
 569                         dev->in_int[c] = 0;
 570                         goto handled;
 571                 }
 572                 tmport -= 0x07;
 573                 if (i == 0x0a) {
 574                         outb(0x30, tmport);
 575                 } else {
 576                         outb(0x46, tmport);
 577                 }
 578                 dev->id[c][target_id].dirct = 0x00;
 579                 tmport += 0x02;
 580                 outb(0x00, tmport++);
 581                 outb(0x00, tmport++);
 582                 outb(0x00, tmport++);
 583                 tmport += 0x03;
 584                 outb(0x08, tmport);
 585                 dev->in_int[c] = 0;
 586                 goto handled;
 587         } else {
 588 //              tmport = workport + 0x17;
 589 //              inb(tmport);
 590 //              dev->working[c] = 0;
 591                 dev->in_int[c] = 0;
 592                 goto handled;
 593         }
 594
 595 handled:
 596 #ifdef ED_DBGP
 597         printk("atp870u_intr_handle exit\n");
 598 #endif
 599         return IRQ_HANDLED;
 600 }
 601 /**
 602  *      atp870u_queuecommand    -       Queue SCSI command
 603  *      @req_p: request block
 604  *      @done: completion function
 605  *
 606  *      Queue a command to the ATP queue. Called with the host lock held.
 607  */
 608 static int atp870u_queuecommand(struct scsi_cmnd * req_p,
 609                          void (*done) (struct scsi_cmnd *))
 610 {
 611         unsigned char c;
 612         unsigned int tmport,m;
 613         struct atp_unit *dev;
 614         struct Scsi_Host *host;
 615
 616         c = scmd_channel(req_p);
 617         req_p->sense_buffer[0]=0;
 618         scsi_set_resid(req_p, 0);
 619         if (scmd_channel(req_p) > 1) {
 620                 req_p->result = 0x00040000;
 621                 done(req_p);
 622 #ifdef ED_DBGP
 623                 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
 624 #endif
 625                 return 0;
 626         }
 627
 628         host = req_p->device->host;
 629         dev = (struct atp_unit *)&host->hostdata;
 630
 631
 632
 633         m = 1;
 634         m = m << scmd_id(req_p);
 635
 636         /*
 637          *      Fake a timeout for missing targets
 638          */
 639
 640         if ((m & dev->active_id[c]) == 0) {
 641                 req_p->result = 0x00040000;
 642                 done(req_p);
 643                 return 0;
 644         }
 645
 646         if (done) {
 647                 req_p->scsi_done = done;
 648         } else {
 649 #ifdef ED_DBGP
 650                 printk( "atp870u_queuecommand: done can't be NULL\n");
 651 #endif
 652                 req_p->result = 0;
 653                 done(req_p);
 654                 return 0;
 655         }
 656
 657         /*
 658          *      Count new command
 659          */
 660         dev->quend[c]++;
 661         if (dev->quend[c] >= qcnt) {
 662                 dev->quend[c] = 0;
 663         }
 664
 665         /*
 666          *      Check queue state
 667          */
 668         if (dev->quhd[c] == dev->quend[c]) {
 669                 if (dev->quend[c] == 0) {
 670                         dev->quend[c] = qcnt;
 671                 }
 672 #ifdef ED_DBGP
 673                 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
 674 #endif
 675                 dev->quend[c]--;
 676                 req_p->result = 0x00020000;
 677                 done(req_p);
 678                 return 0;
 679         }
 680         dev->quereq[c][dev->quend[c]] = req_p;
 681         tmport = dev->ioport[c] + 0x1c;
 682 #ifdef ED_DBGP
 683         printk("dev->ioport[c] = %x inb(tmport) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],inb(tmport),c,dev->in_int[c],c,dev->in_snd[c]);
 684 #endif
 685         if ((inb(tmport) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
 686 #ifdef ED_DBGP
 687                 printk("Call sent_s870(atp870u_queuecommand)\n");
 688 #endif
 689                 send_s870(dev,c);
 690         }
 691 #ifdef ED_DBGP
 692         printk("atp870u_queuecommand : exit\n");
 693 #endif
 694         return 0;
 695 }
 696
 697 /**
 698  *      send_s870       -       send a command to the controller
 699  *      @host: host
 700  *
 701  *      On entry there is work queued to be done. We move some of that work to the
 702  *      controller itself.
 703  *
 704  *      Caller holds the host lock.
 705  */
 706 static void send_s870(struct atp_unit *dev,unsigned char c)
 707 {
 708         unsigned int tmport;
 709         struct scsi_cmnd *workreq;
 710         unsigned int i;//,k;
 711         unsigned char  j, target_id;
 712         unsigned char *prd;
 713         unsigned short int tmpcip, w;
 714         unsigned long l, bttl = 0;
 715         unsigned int workport;
 716         unsigned long  sg_count;
 717
 718         if (dev->in_snd[c] != 0) {
 719 #ifdef ED_DBGP
 720                 printk("cmnd in_snd\n");
 721 #endif
 722                 return;
 723         }
 724 #ifdef ED_DBGP
 725         printk("Sent_s870 enter\n");
 726 #endif
 727         dev->in_snd[c] = 1;
 728         if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
 729                 dev->last_cmd[c] &= 0x0f;
 730                 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
 731                 if (workreq != NULL) {  /* check NULL pointer */
 732                    goto cmd_subp;
 733                 }
 734                 dev->last_cmd[c] = 0xff;
 735                 if (dev->quhd[c] == dev->quend[c]) {
 736                         dev->in_snd[c] = 0;
 737                         return ;
 738                 }
 739         }
 740         if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
 741                 dev->in_snd[c] = 0;
 742                 return ;
 743         }
 744         dev->working[c]++;
 745         j = dev->quhd[c];
 746         dev->quhd[c]++;
 747         if (dev->quhd[c] >= qcnt) {
 748                 dev->quhd[c] = 0;
 749         }
 750         workreq = dev->quereq[c][dev->quhd[c]];
 751         if (dev->id[c][scmd_id(workreq)].curr_req == NULL) {
 752                 dev->id[c][scmd_id(workreq)].curr_req = workreq;
 753                 dev->last_cmd[c] = scmd_id(workreq);
 754                 goto cmd_subp;
 755         }
 756         dev->quhd[c] = j;
 757         dev->working[c]--;
 758         dev->in_snd[c] = 0;
 759         return;
 760 cmd_subp:
 761         workport = dev->ioport[c];
 762         tmport = workport + 0x1f;
 763         if ((inb(tmport) & 0xb0) != 0) {
 764                 goto abortsnd;
 765         }
 766         tmport = workport + 0x1c;
 767         if (inb(tmport) == 0) {
 768                 goto oktosend;
 769         }
 770 abortsnd:
 771 #ifdef ED_DBGP
 772         printk("Abort to Send\n");
 773 #endif
 774         dev->last_cmd[c] |= 0x40;
 775         dev->in_snd[c] = 0;
 776         return;
 777 oktosend:
 778 #ifdef ED_DBGP
 779         printk("OK to Send\n");
 780         scmd_printk(KERN_DEBUG, workreq, "CDB");
 781         for(i=0;i<workreq->cmd_len;i++) {
 782                 printk(" %x",workreq->cmnd[i]);
 783         }
 784         printk("\n");
 785 #endif
 786         l = scsi_bufflen(workreq);
 787
 788         if (dev->dev_id == ATP885_DEVID) {
 789                 j = inb(dev->baseport + 0x29) & 0xfe;
 790                 outb(j, dev->baseport + 0x29);
 791                 dev->r1f[c][scmd_id(workreq)] = 0;
 792         }
 793
 794         if (workreq->cmnd[0] == READ_CAPACITY) {
 795                 if (l > 8)
 796                         l = 8;
 797         }
 798         if (workreq->cmnd[0] == 0x00) {
 799                 l = 0;
 800         }
 801
 802         tmport = workport + 0x1b;
 803         j = 0;
 804         target_id = scmd_id(workreq);
 805
 806         /*
 807          *      Wide ?
 808          */
 809         w = 1;
 810         w = w << target_id;
 811         if ((w & dev->wide_id[c]) != 0) {
 812                 j |= 0x01;
 813         }
 814         outb(j, tmport);
 815         while ((inb(tmport) & 0x01) != j) {
 816                 outb(j,tmport);
 817 #ifdef ED_DBGP
 818                 printk("send_s870 while loop 1\n");
 819 #endif
 820         }
 821         /*
 822          *      Write the command
 823          */
 824
 825         tmport = workport;
 826         outb(workreq->cmd_len, tmport++);
 827         outb(0x2c, tmport++);
 828         if (dev->dev_id == ATP885_DEVID) {
 829                 outb(0x7f, tmport++);
 830         } else {
 831                 outb(0xcf, tmport++);
 832         }
 833         for (i = 0; i < workreq->cmd_len; i++) {
 834                 outb(workreq->cmnd[i], tmport++);
 835         }
 836         tmport = workport + 0x0f;
 837         outb(workreq->device->lun, tmport);
 838         tmport += 0x02;
 839         /*
 840          *      Write the target
 841          */
 842         outb(dev->id[c][target_id].devsp, tmport++);
 843 #ifdef ED_DBGP
 844         printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
 845 #endif
 846
 847         sg_count = scsi_dma_map(workreq);
 848         /*
 849          *      Write transfer size
 850          */
 851         outb((unsigned char) (((unsigned char *) (&l))[2]), tmport++);
 852         outb((unsigned char) (((unsigned char *) (&l))[1]), tmport++);
 853         outb((unsigned char) (((unsigned char *) (&l))[0]), tmport++);
 854         j = target_id;
 855         dev->id[c][j].last_len = l;
 856         dev->id[c][j].tran_len = 0;
 857 #ifdef ED_DBGP
 858         printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
 859 #endif
 860         /*
 861          *      Flip the wide bits
 862          */
 863         if ((j & 0x08) != 0) {
 864                 j = (j & 0x07) | 0x40;
 865         }
 866         /*
 867          *      Check transfer direction
 868          */
 869         if (workreq->sc_data_direction == DMA_TO_DEVICE) {
 870                 outb((unsigned char) (j | 0x20), tmport++);
 871         } else {
 872                 outb(j, tmport++);
 873         }
 874         outb((unsigned char) (inb(tmport) | 0x80), tmport);
 875         outb(0x80, tmport);
 876         tmport = workport + 0x1c;
 877         dev->id[c][target_id].dirct = 0;
 878         if (l == 0) {
 879                 if (inb(tmport) == 0) {
 880                         tmport = workport + 0x18;
 881 #ifdef ED_DBGP
 882                         printk("change SCSI_CMD_REG 0x08\n");
 883 #endif
 884                         outb(0x08, tmport);
 885                 } else {
 886                         dev->last_cmd[c] |= 0x40;
 887                 }
 888                 dev->in_snd[c] = 0;
 889                 return;
 890         }
 891         tmpcip = dev->pciport[c];
 892         prd = dev->id[c][target_id].prd_table;
 893         dev->id[c][target_id].prd_pos = prd;
 894
 895         /*
 896          *      Now write the request list. Either as scatter/gather or as
 897          *      a linear chain.
 898          */
 899
 900         if (l) {
 901                 struct scatterlist *sgpnt;
 902                 i = 0;
 903                 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
 904                         bttl = sg_dma_address(sgpnt);
 905                         l=sg_dma_len(sgpnt);
 906 #ifdef ED_DBGP
 907                         printk("1. bttl %x, l %x\n",bttl, l);
 908 #endif
 909                         while (l > 0x10000) {
 910                                 (((u16 *) (prd))[i + 3]) = 0x0000;
 911                                 (((u16 *) (prd))[i + 2]) = 0x0000;
 912                                 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
 913                                 l -= 0x10000;
 914                                 bttl += 0x10000;
 915                                 i += 0x04;
 916                         }
 917                         (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
 918                         (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
 919                         (((u16 *) (prd))[i + 3]) = 0;
 920                         i += 0x04;
 921                 }
 922                 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
 923 #ifdef ED_DBGP
 924                 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
 925                 printk("2. bttl %x, l %x\n",bttl, l);
 926 #endif
 927         }
 928         tmpcip += 4;
 929 #ifdef ED_DBGP
 930         printk("send_s870: prdaddr_2 0x%8x tmpcip %x target_id %d\n", dev->id[c][target_id].prdaddr,tmpcip,target_id);
 931 #endif
 932         dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
 933         outl(dev->id[c][target_id].prdaddr, tmpcip);
 934         tmpcip = tmpcip - 2;
 935         outb(0x06, tmpcip);
 936         outb(0x00, tmpcip);
 937         if (dev->dev_id == ATP885_DEVID) {
 938                 tmpcip--;
 939                 j=inb(tmpcip) & 0xf3;
 940                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
 941                 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 942                         j |= 0x0c;
 943                 }
 944                 outb(j,tmpcip);
 945                 tmpcip--;
 946         } else if ((dev->dev_id == ATP880_DEVID1) ||
 947                    (dev->dev_id == ATP880_DEVID2)) {
 948                 tmpcip =tmpcip -2;
 949                 tmport = workport - 0x05;
 950                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 951                         outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport);
 952                 } else {
 953                         outb((unsigned char) (inb(tmport) & 0x3f), tmport);
 954                 }
 955         } else {
 956                 tmpcip =tmpcip -2;
 957                 tmport = workport + 0x3a;
 958                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 959                         outb((inb(tmport) & 0xf3) | 0x08, tmport);
 960                 } else {
 961                         outb(inb(tmport) & 0xf3, tmport);
 962                 }
 963         }
 964         tmport = workport + 0x1c;
 965
 966         if(workreq->sc_data_direction == DMA_TO_DEVICE) {
 967                 dev->id[c][target_id].dirct = 0x20;
 968                 if (inb(tmport) == 0) {
 969                         tmport = workport + 0x18;
 970                         outb(0x08, tmport);
 971                         outb(0x01, tmpcip);
 972 #ifdef ED_DBGP
 973                 printk( "start DMA(to target)\n");
 974 #endif
 975                 } else {
 976                         dev->last_cmd[c] |= 0x40;
 977                 }
 978                 dev->in_snd[c] = 0;
 979                 return;
 980         }
 981         if (inb(tmport) == 0) {
 982                 tmport = workport + 0x18;
 983                 outb(0x08, tmport);
 984                 outb(0x09, tmpcip);
 985 #ifdef ED_DBGP
 986                 printk( "start DMA(to host)\n");
 987 #endif
 988         } else {
 989                 dev->last_cmd[c] |= 0x40;
 990         }
 991         dev->in_snd[c] = 0;
 992         return;
 993
 994 }
 995
 996 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
 997 {
 998         unsigned int tmport;
 999         unsigned short int i, k;
1000         unsigned char j;
1001
1002         tmport = dev->ioport[0] + 0x1c;
1003         outw(*val, tmport);
1004 FUN_D7:
1005         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns)  */
1006                 k = inw(tmport);
1007                 j = (unsigned char) (k >> 8);
1008                 if ((k & 0x8000) != 0) {        /* DB7 all release?    */
1009                         goto FUN_D7;
1010                 }
1011         }
1012         *val |= 0x4000;         /* assert DB6           */
1013         outw(*val, tmport);
1014         *val &= 0xdfff;         /* assert DB5           */
1015         outw(*val, tmport);
1016 FUN_D5:
1017         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns) */
1018                 if ((inw(tmport) & 0x2000) != 0) {      /* DB5 all release?       */
1019                         goto FUN_D5;
1020                 }
1021         }
1022         *val |= 0x8000;         /* no DB4-0, assert DB7    */
1023         *val &= 0xe0ff;
1024         outw(*val, tmport);
1025         *val &= 0xbfff;         /* release DB6             */
1026         outw(*val, tmport);
1027 FUN_D6:
1028         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns)  */
1029                 if ((inw(tmport) & 0x4000) != 0) {      /* DB6 all release?  */
1030                         goto FUN_D6;
1031                 }
1032         }
1033
1034         return j;
1035 }
1036
1037 static void tscam(struct Scsi_Host *host)
1038 {
1039
1040         unsigned int tmport;
1041         unsigned char i, j, k;
1042         unsigned long n;
1043         unsigned short int m, assignid_map, val;
1044         unsigned char mbuf[33], quintet[2];
1045         struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
1046         static unsigned char g2q_tab[8] = {
1047                 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
1048         };
1049
1050 /*  I can't believe we need this before we've even done anything.  Remove it
1051  *  and see if anyone bitches.
1052         for (i = 0; i < 0x10; i++) {
1053                 udelay(0xffff);
1054         }
1055  */
1056
1057         tmport = dev->ioport[0] + 1;
1058         outb(0x08, tmport++);
1059         outb(0x7f, tmport);
1060         tmport = dev->ioport[0] + 0x11;
1061         outb(0x20, tmport);
1062
1063         if ((dev->scam_on & 0x40) == 0) {
1064                 return;
1065         }
1066         m = 1;
1067         m <<= dev->host_id[0];
1068         j = 16;
1069         if (dev->chip_ver < 4) {
1070                 m |= 0xff00;
1071                 j = 8;
1072         }
1073         assignid_map = m;
1074         tmport = dev->ioport[0] + 0x02;
1075         outb(0x02, tmport++);   /* 2*2=4ms,3EH 2/32*3E=3.9ms */
1076         outb(0, tmport++);
1077         outb(0, tmport++);
1078         outb(0, tmport++);
1079         outb(0, tmport++);
1080         outb(0, tmport++);
1081         outb(0, tmport++);
1082
1083         for (i = 0; i < j; i++) {
1084                 m = 1;
1085                 m = m << i;
1086                 if ((m & assignid_map) != 0) {
1087                         continue;
1088                 }
1089                 tmport = dev->ioport[0] + 0x0f;
1090                 outb(0, tmport++);
1091                 tmport += 0x02;
1092                 outb(0, tmport++);
1093                 outb(0, tmport++);
1094                 outb(0, tmport++);
1095                 if (i > 7) {
1096                         k = (i & 0x07) | 0x40;
1097                 } else {
1098                         k = i;
1099                 }
1100                 outb(k, tmport++);
1101                 tmport = dev->ioport[0] + 0x1b;
1102                 if (dev->chip_ver == 4) {
1103                         outb(0x01, tmport);
1104                 } else {
1105                         outb(0x00, tmport);
1106                 }
1107 wait_rdyok:
1108                 tmport = dev->ioport[0] + 0x18;
1109                 outb(0x09, tmport);
1110                 tmport += 0x07;
1111
1112                 while ((inb(tmport) & 0x80) == 0x00)
1113                         cpu_relax();
1114                 tmport -= 0x08;
1115                 k = inb(tmport);
1116                 if (k != 0x16) {
1117                         if ((k == 0x85) || (k == 0x42)) {
1118                                 continue;
1119                         }
1120                         tmport = dev->ioport[0] + 0x10;
1121                         outb(0x41, tmport);
1122                         goto wait_rdyok;
1123                 }
1124                 assignid_map |= m;
1125
1126         }
1127         tmport = dev->ioport[0] + 0x02;
1128         outb(0x7f, tmport);
1129         tmport = dev->ioport[0] + 0x1b;
1130         outb(0x02, tmport);
1131
1132         outb(0, 0x80);
1133
1134         val = 0x0080;           /* bsy  */
1135         tmport = dev->ioport[0] + 0x1c;
1136         outw(val, tmport);
1137         val |= 0x0040;          /* sel  */
1138         outw(val, tmport);
1139         val |= 0x0004;          /* msg  */
1140         outw(val, tmport);
1141         inb(0x80);              /* 2 deskew delay(45ns*2=90ns) */
1142         val &= 0x007f;          /* no bsy  */
1143         outw(val, tmport);
1144         mdelay(128);
1145         val &= 0x00fb;          /* after 1ms no msg */
1146         outw(val, tmport);
1147 wait_nomsg:
1148         if ((inb(tmport) & 0x04) != 0) {
1149                 goto wait_nomsg;
1150         }
1151         outb(1, 0x80);
1152         udelay(100);
1153         for (n = 0; n < 0x30000; n++) {
1154                 if ((inb(tmport) & 0x80) != 0) {        /* bsy ? */
1155                         goto wait_io;
1156                 }
1157         }
1158         goto TCM_SYNC;
1159 wait_io:
1160         for (n = 0; n < 0x30000; n++) {
1161                 if ((inb(tmport) & 0x81) == 0x0081) {
1162                         goto wait_io1;
1163                 }
1164         }
1165         goto TCM_SYNC;
1166 wait_io1:
1167         inb(0x80);
1168         val |= 0x8003;          /* io,cd,db7  */
1169         outw(val, tmport);
1170         inb(0x80);
1171         val &= 0x00bf;          /* no sel     */
1172         outw(val, tmport);
1173         outb(2, 0x80);
1174 TCM_SYNC:
1175         udelay(0x800);
1176         if ((inb(tmport) & 0x80) == 0x00) {     /* bsy ? */
1177                 outw(0, tmport--);
1178                 outb(0, tmport);
1179                 tmport = dev->ioport[0] + 0x15;
1180                 outb(0, tmport);
1181                 tmport += 0x03;
1182                 outb(0x09, tmport);
1183                 tmport += 0x07;
1184                 while ((inb(tmport) & 0x80) == 0)
1185                         cpu_relax();
1186                 tmport -= 0x08;
1187                 inb(tmport);
1188                 return;
1189         }
1190         val &= 0x00ff;          /* synchronization  */
1191         val |= 0x3f00;
1192         fun_scam(dev, &val);
1193         outb(3, 0x80);
1194         val &= 0x00ff;          /* isolation        */
1195         val |= 0x2000;
1196         fun_scam(dev, &val);
1197         outb(4, 0x80);
1198         i = 8;
1199         j = 0;
1200 TCM_ID:
1201         if ((inw(tmport) & 0x2000) == 0) {
1202                 goto TCM_ID;
1203         }
1204         outb(5, 0x80);
1205         val &= 0x00ff;          /* get ID_STRING */
1206         val |= 0x2000;
1207         k = fun_scam(dev, &val);
1208         if ((k & 0x03) == 0) {
1209                 goto TCM_5;
1210         }
1211         mbuf[j] <<= 0x01;
1212         mbuf[j] &= 0xfe;
1213         if ((k & 0x02) != 0) {
1214                 mbuf[j] |= 0x01;
1215         }
1216         i--;
1217         if (i > 0) {
1218                 goto TCM_ID;
1219         }
1220         j++;
1221         i = 8;
1222         goto TCM_ID;
1223
1224 TCM_5:                  /* isolation complete..  */
1225 /*    mbuf[32]=0;
1226         printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1227         i = 15;
1228         j = mbuf[0];
1229         if ((j & 0x20) != 0) {  /* bit5=1:ID upto 7      */
1230                 i = 7;
1231         }
1232         if ((j & 0x06) == 0) {  /* IDvalid?             */
1233                 goto G2Q5;
1234         }
1235         k = mbuf[1];
1236 small_id:
1237         m = 1;
1238         m <<= k;
1239         if ((m & assignid_map) == 0) {
1240                 goto G2Q_QUIN;
1241         }
1242         if (k > 0) {
1243                 k--;
1244                 goto small_id;
1245         }
1246 G2Q5:                   /* srch from max acceptable ID#  */
1247         k = i;                  /* max acceptable ID#            */
1248 G2Q_LP:
1249         m = 1;
1250         m <<= k;
1251         if ((m & assignid_map) == 0) {
1252                 goto G2Q_QUIN;
1253         }
1254         if (k > 0) {
1255                 k--;
1256                 goto G2Q_LP;
1257         }
1258 G2Q_QUIN:               /* k=binID#,       */
1259         assignid_map |= m;
1260         if (k < 8) {
1261                 quintet[0] = 0x38;      /* 1st dft ID<8    */
1262         } else {
1263                 quintet[0] = 0x31;      /* 1st  ID>=8      */
1264         }
1265         k &= 0x07;
1266         quintet[1] = g2q_tab[k];
1267
1268         val &= 0x00ff;          /* AssignID 1stQuintet,AH=001xxxxx  */
1269         m = quintet[0] << 8;
1270         val |= m;
1271         fun_scam(dev, &val);
1272         val &= 0x00ff;          /* AssignID 2ndQuintet,AH=001xxxxx */
1273         m = quintet[1] << 8;
1274         val |= m;
1275         fun_scam(dev, &val);
1276
1277         goto TCM_SYNC;
1278
1279 }
1280
1281 static void is870(struct atp_unit *dev, unsigned int wkport)
1282 {
1283         unsigned int tmport;
1284         unsigned char i, j, k, rmb, n;
1285         unsigned short int m;
1286         static unsigned char mbuf[512];
1287         static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1288         static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1289         static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1290         static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1291         static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1292         static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1293
1294         tmport = wkport + 0x3a;
1295         outb((unsigned char) (inb(tmport) | 0x10), tmport);
1296
1297         for (i = 0; i < 16; i++) {
1298                 if ((dev->chip_ver != 4) && (i > 7)) {
1299                         break;
1300                 }
1301                 m = 1;
1302                 m = m << i;
1303                 if ((m & dev->active_id[0]) != 0) {
1304                         continue;
1305                 }
1306                 if (i == dev->host_id[0]) {
1307                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[0]);
1308                         continue;
1309                 }
1310                 tmport = wkport + 0x1b;
1311                 if (dev->chip_ver == 4) {
1312                         outb(0x01, tmport);
1313                 } else {
1314                         outb(0x00, tmport);
1315                 }
1316                 tmport = wkport + 1;
1317                 outb(0x08, tmport++);
1318                 outb(0x7f, tmport++);
1319                 outb(satn[0], tmport++);
1320                 outb(satn[1], tmport++);
1321                 outb(satn[2], tmport++);
1322                 outb(satn[3], tmport++);
1323                 outb(satn[4], tmport++);
1324                 outb(satn[5], tmport++);
1325                 tmport += 0x06;
1326                 outb(0, tmport);
1327                 tmport += 0x02;
1328                 outb(dev->id[0][i].devsp, tmport++);
1329                 outb(0, tmport++);
1330                 outb(satn[6], tmport++);
1331                 outb(satn[7], tmport++);
1332                 j = i;
1333                 if ((j & 0x08) != 0) {
1334                         j = (j & 0x07) | 0x40;
1335                 }
1336                 outb(j, tmport);
1337                 tmport += 0x03;
1338                 outb(satn[8], tmport);
1339                 tmport += 0x07;
1340
1341                 while ((inb(tmport) & 0x80) == 0x00)
1342                         cpu_relax();
1343
1344                 tmport -= 0x08;
1345                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1346                         continue;
1347
1348                 while (inb(tmport) != 0x8e)
1349                         cpu_relax();
1350
1351                 dev->active_id[0] |= m;
1352
1353                 tmport = wkport + 0x10;
1354                 outb(0x30, tmport);
1355                 tmport = wkport + 0x04;
1356                 outb(0x00, tmport);
1357
1358 phase_cmd:
1359                 tmport = wkport + 0x18;
1360                 outb(0x08, tmport);
1361                 tmport += 0x07;
1362                 while ((inb(tmport) & 0x80) == 0x00)
1363                         cpu_relax();
1364                 tmport -= 0x08;
1365                 j = inb(tmport);
1366                 if (j != 0x16) {
1367                         tmport = wkport + 0x10;
1368                         outb(0x41, tmport);
1369                         goto phase_cmd;
1370                 }
1371 sel_ok:
1372                 tmport = wkport + 3;
1373                 outb(inqd[0], tmport++);
1374                 outb(inqd[1], tmport++);
1375                 outb(inqd[2], tmport++);
1376                 outb(inqd[3], tmport++);
1377                 outb(inqd[4], tmport++);
1378                 outb(inqd[5], tmport);
1379                 tmport += 0x07;
1380                 outb(0, tmport);
1381                 tmport += 0x02;
1382                 outb(dev->id[0][i].devsp, tmport++);
1383                 outb(0, tmport++);
1384                 outb(inqd[6], tmport++);
1385                 outb(inqd[7], tmport++);
1386                 tmport += 0x03;
1387                 outb(inqd[8], tmport);
1388                 tmport += 0x07;
1389
1390                 while ((inb(tmport) & 0x80) == 0x00)
1391                         cpu_relax();
1392
1393                 tmport -= 0x08;
1394                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1395                         continue;
1396
1397                 while (inb(tmport) != 0x8e)
1398                         cpu_relax();
1399
1400                 tmport = wkport + 0x1b;
1401                 if (dev->chip_ver == 4)
1402                         outb(0x00, tmport);
1403
1404                 tmport = wkport + 0x18;
1405                 outb(0x08, tmport);
1406                 tmport += 0x07;
1407                 j = 0;
1408 rd_inq_data:
1409                 k = inb(tmport);
1410                 if ((k & 0x01) != 0) {
1411                         tmport -= 0x06;
1412                         mbuf[j++] = inb(tmport);
1413                         tmport += 0x06;
1414                         goto rd_inq_data;
1415                 }
1416                 if ((k & 0x80) == 0) {
1417                         goto rd_inq_data;
1418                 }
1419                 tmport -= 0x08;
1420                 j = inb(tmport);
1421                 if (j == 0x16) {
1422                         goto inq_ok;
1423                 }
1424                 tmport = wkport + 0x10;
1425                 outb(0x46, tmport);
1426                 tmport += 0x02;
1427                 outb(0, tmport++);
1428                 outb(0, tmport++);
1429                 outb(0, tmport++);
1430                 tmport += 0x03;
1431                 outb(0x08, tmport);
1432                 tmport += 0x07;
1433
1434                 while ((inb(tmport) & 0x80) == 0x00)
1435                         cpu_relax();
1436
1437                 tmport -= 0x08;
1438                 if (inb(tmport) != 0x16) {
1439                         goto sel_ok;
1440                 }
1441 inq_ok:
1442                 mbuf[36] = 0;
1443                 printk(KERN_INFO "         ID: %2d  %s\n", i, &mbuf[8]);
1444                 dev->id[0][i].devtype = mbuf[0];
1445                 rmb = mbuf[1];
1446                 n = mbuf[7];
1447                 if (dev->chip_ver != 4) {
1448                         goto not_wide;
1449                 }
1450                 if ((mbuf[7] & 0x60) == 0) {
1451                         goto not_wide;
1452                 }
1453                 if ((dev->global_map[0] & 0x20) == 0) {
1454                         goto not_wide;
1455                 }
1456                 tmport = wkport + 0x1b;
1457                 outb(0x01, tmport);
1458                 tmport = wkport + 3;
1459                 outb(satn[0], tmport++);
1460                 outb(satn[1], tmport++);
1461                 outb(satn[2], tmport++);
1462                 outb(satn[3], tmport++);
1463                 outb(satn[4], tmport++);
1464                 outb(satn[5], tmport++);
1465                 tmport += 0x06;
1466                 outb(0, tmport);
1467                 tmport += 0x02;
1468                 outb(dev->id[0][i].devsp, tmport++);
1469                 outb(0, tmport++);
1470                 outb(satn[6], tmport++);
1471                 outb(satn[7], tmport++);
1472                 tmport += 0x03;
1473                 outb(satn[8], tmport);
1474                 tmport += 0x07;
1475
1476                 while ((inb(tmport) & 0x80) == 0x00)
1477                         cpu_relax();
1478
1479                 tmport -= 0x08;
1480                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1481                         continue;
1482
1483                 while (inb(tmport) != 0x8e)
1484                         cpu_relax();
1485
1486 try_wide:
1487                 j = 0;
1488                 tmport = wkport + 0x14;
1489                 outb(0x05, tmport);
1490                 tmport += 0x04;
1491                 outb(0x20, tmport);
1492                 tmport += 0x07;
1493
1494                 while ((inb(tmport) & 0x80) == 0) {
1495                         if ((inb(tmport) & 0x01) != 0) {
1496                                 tmport -= 0x06;
1497                                 outb(wide[j++], tmport);
1498                                 tmport += 0x06;
1499                         }
1500                 }
1501                 tmport -= 0x08;
1502
1503                 while ((inb(tmport) & 0x80) == 0x00)
1504                         cpu_relax();
1505
1506                 j = inb(tmport) & 0x0f;
1507                 if (j == 0x0f) {
1508                         goto widep_in;
1509                 }
1510                 if (j == 0x0a) {
1511                         goto widep_cmd;
1512                 }
1513                 if (j == 0x0e) {
1514                         goto try_wide;
1515                 }
1516                 continue;
1517 widep_out:
1518                 tmport = wkport + 0x18;
1519                 outb(0x20, tmport);
1520                 tmport += 0x07;
1521                 while ((inb(tmport) & 0x80) == 0) {
1522                         if ((inb(tmport) & 0x01) != 0) {
1523                                 tmport -= 0x06;
1524                                 outb(0, tmport);
1525                                 tmport += 0x06;
1526                         }
1527                 }
1528                 tmport -= 0x08;
1529                 j = inb(tmport) & 0x0f;
1530                 if (j == 0x0f) {
1531                         goto widep_in;
1532                 }
1533                 if (j == 0x0a) {
1534                         goto widep_cmd;
1535                 }
1536                 if (j == 0x0e) {
1537                         goto widep_out;
1538                 }
1539                 continue;
1540 widep_in:
1541                 tmport = wkport + 0x14;
1542                 outb(0xff, tmport);
1543                 tmport += 0x04;
1544                 outb(0x20, tmport);
1545                 tmport += 0x07;
1546                 k = 0;
1547 widep_in1:
1548                 j = inb(tmport);
1549                 if ((j & 0x01) != 0) {
1550                         tmport -= 0x06;
1551                         mbuf[k++] = inb(tmport);
1552                         tmport += 0x06;
1553                         goto widep_in1;
1554                 }
1555                 if ((j & 0x80) == 0x00) {
1556                         goto widep_in1;
1557                 }
1558                 tmport -= 0x08;
1559                 j = inb(tmport) & 0x0f;
1560                 if (j == 0x0f) {
1561                         goto widep_in;
1562                 }
1563                 if (j == 0x0a) {
1564                         goto widep_cmd;
1565                 }
1566                 if (j == 0x0e) {
1567                         goto widep_out;
1568                 }
1569                 continue;
1570 widep_cmd:
1571                 tmport = wkport + 0x10;
1572                 outb(0x30, tmport);
1573                 tmport = wkport + 0x14;
1574                 outb(0x00, tmport);
1575                 tmport += 0x04;
1576                 outb(0x08, tmport);
1577                 tmport += 0x07;
1578
1579                 while ((inb(tmport) & 0x80) == 0x00)
1580                         cpu_relax();
1581
1582                 tmport -= 0x08;
1583                 j = inb(tmport);
1584                 if (j != 0x16) {
1585                         if (j == 0x4e) {
1586                                 goto widep_out;
1587                         }
1588                         continue;
1589                 }
1590                 if (mbuf[0] != 0x01) {
1591                         goto not_wide;
1592                 }
1593                 if (mbuf[1] != 0x02) {
1594                         goto not_wide;
1595                 }
1596                 if (mbuf[2] != 0x03) {
1597                         goto not_wide;
1598                 }
1599                 if (mbuf[3] != 0x01) {
1600                         goto not_wide;
1601                 }
1602                 m = 1;
1603                 m = m << i;
1604                 dev->wide_id[0] |= m;
1605 not_wide:
1606                 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1607                         goto set_sync;
1608                 }
1609                 continue;
1610 set_sync:
1611                 tmport = wkport + 0x1b;
1612                 j = 0;
1613                 if ((m & dev->wide_id[0]) != 0) {
1614                         j |= 0x01;
1615                 }
1616                 outb(j, tmport);
1617                 tmport = wkport + 3;
1618                 outb(satn[0], tmport++);
1619                 outb(satn[1], tmport++);
1620                 outb(satn[2], tmport++);
1621                 outb(satn[3], tmport++);
1622                 outb(satn[4], tmport++);
1623                 outb(satn[5], tmport++);
1624                 tmport += 0x06;
1625                 outb(0, tmport);
1626                 tmport += 0x02;
1627                 outb(dev->id[0][i].devsp, tmport++);
1628                 outb(0, tmport++);
1629                 outb(satn[6], tmport++);
1630                 outb(satn[7], tmport++);
1631                 tmport += 0x03;
1632                 outb(satn[8], tmport);
1633                 tmport += 0x07;
1634
1635                 while ((inb(tmport) & 0x80) == 0x00)
1636                         cpu_relax();
1637
1638                 tmport -= 0x08;
1639                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1640                         continue;
1641
1642                 while (inb(tmport) != 0x8e)
1643                         cpu_relax();
1644
1645 try_sync:
1646                 j = 0;
1647                 tmport = wkport + 0x14;
1648                 outb(0x06, tmport);
1649                 tmport += 0x04;
1650                 outb(0x20, tmport);
1651                 tmport += 0x07;
1652
1653                 while ((inb(tmport) & 0x80) == 0) {
1654                         if ((inb(tmport) & 0x01) != 0) {
1655                                 tmport -= 0x06;
1656                                 if ((m & dev->wide_id[0]) != 0) {
1657                                         outb(synw[j++], tmport);
1658                                 } else {
1659                                         if ((m & dev->ultra_map[0]) != 0) {
1660                                                 outb(synu[j++], tmport);
1661                                         } else {
1662                                                 outb(synn[j++], tmport);
1663                                         }
1664                                 }
1665                                 tmport += 0x06;
1666                         }
1667                 }
1668                 tmport -= 0x08;
1669
1670                 while ((inb(tmport) & 0x80) == 0x00)
1671                         cpu_relax();
1672
1673                 j = inb(tmport) & 0x0f;
1674                 if (j == 0x0f) {
1675                         goto phase_ins;
1676                 }
1677                 if (j == 0x0a) {
1678                         goto phase_cmds;
1679                 }
1680                 if (j == 0x0e) {
1681                         goto try_sync;
1682                 }
1683                 continue;
1684 phase_outs:
1685                 tmport = wkport + 0x18;
1686                 outb(0x20, tmport);
1687                 tmport += 0x07;
1688                 while ((inb(tmport) & 0x80) == 0x00) {
1689                         if ((inb(tmport) & 0x01) != 0x00) {
1690                                 tmport -= 0x06;
1691                                 outb(0x00, tmport);
1692                                 tmport += 0x06;
1693                         }
1694                 }
1695                 tmport -= 0x08;
1696                 j = inb(tmport);
1697                 if (j == 0x85) {
1698                         goto tar_dcons;
1699                 }
1700                 j &= 0x0f;
1701                 if (j == 0x0f) {
1702                         goto phase_ins;
1703                 }
1704                 if (j == 0x0a) {
1705                         goto phase_cmds;
1706                 }
1707                 if (j == 0x0e) {
1708                         goto phase_outs;
1709                 }
1710                 continue;
1711 phase_ins:
1712                 tmport = wkport + 0x14;
1713                 outb(0xff, tmport);
1714                 tmport += 0x04;
1715                 outb(0x20, tmport);
1716                 tmport += 0x07;
1717                 k = 0;
1718 phase_ins1:
1719                 j = inb(tmport);
1720                 if ((j & 0x01) != 0x00) {
1721                         tmport -= 0x06;
1722                         mbuf[k++] = inb(tmport);
1723                         tmport += 0x06;
1724                         goto phase_ins1;
1725                 }
1726                 if ((j & 0x80) == 0x00) {
1727                         goto phase_ins1;
1728                 }
1729                 tmport -= 0x08;
1730
1731                 while ((inb(tmport) & 0x80) == 0x00)
1732                         cpu_relax();
1733
1734                 j = inb(tmport);
1735                 if (j == 0x85) {
1736                         goto tar_dcons;
1737                 }
1738                 j &= 0x0f;
1739                 if (j == 0x0f) {
1740                         goto phase_ins;
1741                 }
1742                 if (j == 0x0a) {
1743                         goto phase_cmds;
1744                 }
1745                 if (j == 0x0e) {
1746                         goto phase_outs;
1747                 }
1748                 continue;
1749 phase_cmds:
1750                 tmport = wkport + 0x10;
1751                 outb(0x30, tmport);
1752 tar_dcons:
1753                 tmport = wkport + 0x14;
1754                 outb(0x00, tmport);
1755                 tmport += 0x04;
1756                 outb(0x08, tmport);
1757                 tmport += 0x07;
1758
1759                 while ((inb(tmport) & 0x80) == 0x00)
1760                         cpu_relax();
1761
1762                 tmport -= 0x08;
1763                 j = inb(tmport);
1764                 if (j != 0x16) {
1765                         continue;
1766                 }
1767                 if (mbuf[0] != 0x01) {
1768                         continue;
1769                 }
1770                 if (mbuf[1] != 0x03) {
1771                         continue;
1772                 }
1773                 if (mbuf[4] == 0x00) {
1774                         continue;
1775                 }
1776                 if (mbuf[3] > 0x64) {
1777                         continue;
1778                 }
1779                 if (mbuf[4] > 0x0c) {
1780                         mbuf[4] = 0x0c;
1781                 }
1782                 dev->id[0][i].devsp = mbuf[4];
1783                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1784                         j = 0xa0;
1785                         goto set_syn_ok;
1786                 }
1787                 if (mbuf[3] < 0x1a) {
1788                         j = 0x20;
1789                         goto set_syn_ok;
1790                 }
1791                 if (mbuf[3] < 0x33) {
1792                         j = 0x40;
1793                         goto set_syn_ok;
1794                 }
1795                 if (mbuf[3] < 0x4c) {
1796                         j = 0x50;
1797                         goto set_syn_ok;
1798                 }
1799                 j = 0x60;
1800 set_syn_ok:
1801                 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
1802         }
1803         tmport = wkport + 0x3a;
1804         outb((unsigned char) (inb(tmport) & 0xef), tmport);
1805 }
1806
1807 static void is880(struct atp_unit *dev, unsigned int wkport)
1808 {
1809         unsigned int tmport;
1810         unsigned char i, j, k, rmb, n, lvdmode;
1811         unsigned short int m;
1812         static unsigned char mbuf[512];
1813         static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1814         static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1815         static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1816         unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1817         static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1818         unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1819         static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1820         static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1821
1822         lvdmode = inb(wkport + 0x3f) & 0x40;
1823
1824         for (i = 0; i < 16; i++) {
1825                 m = 1;
1826                 m = m << i;
1827                 if ((m & dev->active_id[0]) != 0) {
1828                         continue;
1829                 }
1830                 if (i == dev->host_id[0]) {
1831                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[0]);
1832                         continue;
1833                 }
1834                 tmport = wkport + 0x5b;
1835                 outb(0x01, tmport);
1836                 tmport = wkport + 0x41;
1837                 outb(0x08, tmport++);
1838                 outb(0x7f, tmport++);
1839                 outb(satn[0], tmport++);
1840                 outb(satn[1], tmport++);
1841                 outb(satn[2], tmport++);
1842                 outb(satn[3], tmport++);
1843                 outb(satn[4], tmport++);
1844                 outb(satn[5], tmport++);
1845                 tmport += 0x06;
1846                 outb(0, tmport);
1847                 tmport += 0x02;
1848                 outb(dev->id[0][i].devsp, tmport++);
1849                 outb(0, tmport++);
1850                 outb(satn[6], tmport++);
1851                 outb(satn[7], tmport++);
1852                 j = i;
1853                 if ((j & 0x08) != 0) {
1854                         j = (j & 0x07) | 0x40;
1855                 }
1856                 outb(j, tmport);
1857                 tmport += 0x03;
1858                 outb(satn[8], tmport);
1859                 tmport += 0x07;
1860
1861                 while ((inb(tmport) & 0x80) == 0x00)
1862                         cpu_relax();
1863
1864                 tmport -= 0x08;
1865                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1866                         continue;
1867
1868                 while (inb(tmport) != 0x8e)
1869                         cpu_relax();
1870
1871                 dev->active_id[0] |= m;
1872
1873                 tmport = wkport + 0x50;
1874                 outb(0x30, tmport);
1875                 tmport = wkport + 0x54;
1876                 outb(0x00, tmport);
1877
1878 phase_cmd:
1879                 tmport = wkport + 0x58;
1880                 outb(0x08, tmport);
1881                 tmport += 0x07;
1882
1883                 while ((inb(tmport) & 0x80) == 0x00)
1884                         cpu_relax();
1885
1886                 tmport -= 0x08;
1887                 j = inb(tmport);
1888                 if (j != 0x16) {
1889                         tmport = wkport + 0x50;
1890                         outb(0x41, tmport);
1891                         goto phase_cmd;
1892                 }
1893 sel_ok:
1894                 tmport = wkport + 0x43;
1895                 outb(inqd[0], tmport++);
1896                 outb(inqd[1], tmport++);
1897                 outb(inqd[2], tmport++);
1898                 outb(inqd[3], tmport++);
1899                 outb(inqd[4], tmport++);
1900                 outb(inqd[5], tmport);
1901                 tmport += 0x07;
1902                 outb(0, tmport);
1903                 tmport += 0x02;
1904                 outb(dev->id[0][i].devsp, tmport++);
1905                 outb(0, tmport++);
1906                 outb(inqd[6], tmport++);
1907                 outb(inqd[7], tmport++);
1908                 tmport += 0x03;
1909                 outb(inqd[8], tmport);
1910                 tmport += 0x07;
1911
1912                 while ((inb(tmport) & 0x80) == 0x00)
1913                         cpu_relax();
1914
1915                 tmport -= 0x08;
1916                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1917                         continue;
1918
1919                 while (inb(tmport) != 0x8e)
1920                         cpu_relax();
1921
1922                 tmport = wkport + 0x5b;
1923                 outb(0x00, tmport);
1924                 tmport = wkport + 0x58;
1925                 outb(0x08, tmport);
1926                 tmport += 0x07;
1927                 j = 0;
1928 rd_inq_data:
1929                 k = inb(tmport);
1930                 if ((k & 0x01) != 0) {
1931                         tmport -= 0x06;
1932                         mbuf[j++] = inb(tmport);
1933                         tmport += 0x06;
1934                         goto rd_inq_data;
1935                 }
1936                 if ((k & 0x80) == 0) {
1937                         goto rd_inq_data;
1938                 }
1939                 tmport -= 0x08;
1940                 j = inb(tmport);
1941                 if (j == 0x16) {
1942                         goto inq_ok;
1943                 }
1944                 tmport = wkport + 0x50;
1945                 outb(0x46, tmport);
1946                 tmport += 0x02;
1947                 outb(0, tmport++);
1948                 outb(0, tmport++);
1949                 outb(0, tmport++);
1950                 tmport += 0x03;
1951                 outb(0x08, tmport);
1952                 tmport += 0x07;
1953                 while ((inb(tmport) & 0x80) == 0x00)
1954                         cpu_relax();
1955
1956                 tmport -= 0x08;
1957                 if (inb(tmport) != 0x16)
1958                         goto sel_ok;
1959
1960 inq_ok:
1961                 mbuf[36] = 0;
1962                 printk(KERN_INFO "         ID: %2d  %s\n", i, &mbuf[8]);
1963                 dev->id[0][i].devtype = mbuf[0];
1964                 rmb = mbuf[1];
1965                 n = mbuf[7];
1966                 if ((mbuf[7] & 0x60) == 0) {
1967                         goto not_wide;
1968                 }
1969                 if ((i < 8) && ((dev->global_map[0] & 0x20) == 0)) {
1970                         goto not_wide;
1971                 }
1972                 if (lvdmode == 0) {
1973                         goto chg_wide;
1974                 }
1975                 if (dev->sp[0][i] != 0x04)      // force u2
1976                 {
1977                         goto chg_wide;
1978                 }
1979
1980                 tmport = wkport + 0x5b;
1981                 outb(0x01, tmport);
1982                 tmport = wkport + 0x43;
1983                 outb(satn[0], tmport++);
1984                 outb(satn[1], tmport++);
1985                 outb(satn[2], tmport++);
1986                 outb(satn[3], tmport++);
1987                 outb(satn[4], tmport++);
1988                 outb(satn[5], tmport++);
1989                 tmport += 0x06;
1990                 outb(0, tmport);
1991                 tmport += 0x02;
1992                 outb(dev->id[0][i].devsp, tmport++);
1993                 outb(0, tmport++);
1994                 outb(satn[6], tmport++);
1995                 outb(satn[7], tmport++);
1996                 tmport += 0x03;
1997                 outb(satn[8], tmport);
1998                 tmport += 0x07;
1999
2000                 while ((inb(tmport) & 0x80) == 0x00)
2001                         cpu_relax();
2002
2003                 tmport -= 0x08;
2004
2005                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
2006                         continue;
2007
2008                 while (inb(tmport) != 0x8e)
2009                         cpu_relax();
2010
2011 try_u3:
2012                 j = 0;
2013                 tmport = wkport + 0x54;
2014                 outb(0x09, tmport);
2015                 tmport += 0x04;
2016                 outb(0x20, tmport);
2017                 tmport += 0x07;
2018
2019                 while ((inb(tmport) & 0x80) == 0) {
2020                         if ((inb(tmport) & 0x01) != 0) {
2021                                 tmport -= 0x06;
2022                                 outb(u3[j++], tmport);
2023                                 tmport += 0x06;
2024                         }
2025                 }
2026                 tmport -= 0x08;
2027
2028                 while ((inb(tmport) & 0x80) == 0x00)
2029                         cpu_relax();
2030
2031                 j = inb(tmport) & 0x0f;
2032                 if (j == 0x0f) {
2033                         goto u3p_in;
2034                 }
2035                 if (j == 0x0a) {
2036                         goto u3p_cmd;
2037                 }
2038                 if (j == 0x0e) {
2039                         goto try_u3;
2040                 }
2041                 continue;
2042 u3p_out:
2043                 tmport = wkport + 0x58;
2044                 outb(0x20, tmport);
2045                 tmport += 0x07;
2046                 while ((inb(tmport) & 0x80) == 0) {
2047                         if ((inb(tmport) & 0x01) != 0) {
2048                                 tmport -= 0x06;
2049                                 outb(0, tmport);
2050                                 tmport += 0x06;
2051                         }
2052                 }
2053                 tmport -= 0x08;
2054                 j = inb(tmport) & 0x0f;
2055                 if (j == 0x0f) {
2056                         goto u3p_in;
2057                 }
2058                 if (j == 0x0a) {
2059                         goto u3p_cmd;
2060                 }
2061                 if (j == 0x0e) {
2062                         goto u3p_out;
2063                 }
2064                 continue;
2065 u3p_in:
2066                 tmport = wkport + 0x54;
2067                 outb(0x09, tmport);
2068                 tmport += 0x04;
2069                 outb(0x20, tmport);
2070                 tmport += 0x07;
2071                 k = 0;
2072 u3p_in1:
2073                 j = inb(tmport);
2074                 if ((j & 0x01) != 0) {
2075                         tmport -= 0x06;
2076                         mbuf[k++] = inb(tmport);
2077                         tmport += 0x06;
2078                         goto u3p_in1;
2079                 }
2080                 if ((j & 0x80) == 0x00) {
2081                         goto u3p_in1;
2082                 }
2083                 tmport -= 0x08;
2084                 j = inb(tmport) & 0x0f;
2085                 if (j == 0x0f) {
2086                         goto u3p_in;
2087                 }
2088                 if (j == 0x0a) {
2089                         goto u3p_cmd;
2090                 }
2091                 if (j == 0x0e) {
2092                         goto u3p_out;
2093                 }
2094                 continue;
2095 u3p_cmd:
2096                 tmport = wkport + 0x50;
2097                 outb(0x30, tmport);
2098                 tmport = wkport + 0x54;
2099                 outb(0x00, tmport);
2100                 tmport += 0x04;
2101                 outb(0x08, tmport);
2102                 tmport += 0x07;
2103
2104                 while ((inb(tmport) & 0x80) == 0x00)
2105                         cpu_relax();
2106
2107                 tmport -= 0x08;
2108                 j = inb(tmport);
2109                 if (j != 0x16) {
2110                         if (j == 0x4e) {
2111                                 goto u3p_out;
2112                         }
2113                         continue;
2114                 }
2115                 if (mbuf[0] != 0x01) {
2116                         goto chg_wide;
2117                 }
2118                 if (mbuf[1] != 0x06) {
2119                         goto chg_wide;
2120                 }
2121                 if (mbuf[2] != 0x04) {
2122                         goto chg_wide;
2123                 }
2124                 if (mbuf[3] == 0x09) {
2125                         m = 1;
2126                         m = m << i;
2127                         dev->wide_id[0] |= m;
2128                         dev->id[0][i].devsp = 0xce;
2129                         continue;
2130                 }
2131 chg_wide:
2132                 tmport = wkport + 0x5b;
2133                 outb(0x01, tmport);
2134                 tmport = wkport + 0x43;
2135                 outb(satn[0], tmport++);
2136                 outb(satn[1], tmport++);
2137                 outb(satn[2], tmport++);
2138                 outb(satn[3], tmport++);
2139                 outb(satn[4], tmport++);
2140                 outb(satn[5], tmport++);
2141                 tmport += 0x06;
2142                 outb(0, tmport);
2143                 tmport += 0x02;
2144                 outb(dev->id[0][i].devsp, tmport++);
2145                 outb(0, tmport++);
2146                 outb(satn[6], tmport++);
2147                 outb(satn[7], tmport++);
2148                 tmport += 0x03;
2149                 outb(satn[8], tmport);
2150                 tmport += 0x07;
2151
2152                 while ((inb(tmport) & 0x80) == 0x00)
2153                         cpu_relax();
2154
2155                 tmport -= 0x08;
2156                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
2157                         continue;
2158
2159                 while (inb(tmport) != 0x8e)
2160                         cpu_relax();
2161
2162 try_wide:
2163                 j = 0;
2164                 tmport = wkport + 0x54;
2165                 outb(0x05, tmport);
2166                 tmport += 0x04;
2167                 outb(0x20, tmport);
2168                 tmport += 0x07;
2169
2170                 while ((inb(tmport) & 0x80) == 0) {
2171                         if ((inb(tmport) & 0x01) != 0) {
2172                                 tmport -= 0x06;
2173                                 outb(wide[j++], tmport);
2174                                 tmport += 0x06;
2175                         }
2176                 }
2177                 tmport -= 0x08;
2178                 while ((inb(tmport) & 0x80) == 0x00)
2179                         cpu_relax();
2180
2181                 j = inb(tmport) & 0x0f;
2182                 if (j == 0x0f) {
2183                         goto widep_in;
2184                 }
2185                 if (j == 0x0a) {
2186                         goto widep_cmd;
2187                 }
2188                 if (j == 0x0e) {
2189                         goto try_wide;
2190                 }
2191                 continue;
2192 widep_out:
2193                 tmport = wkport + 0x58;
2194                 outb(0x20, tmport);
2195                 tmport += 0x07;
2196                 while ((inb(tmport) & 0x80) == 0) {
2197                         if ((inb(tmport) & 0x01) != 0) {
2198                                 tmport -= 0x06;
2199                                 outb(0, tmport);
2200                                 tmport += 0x06;
2201                         }
2202                 }
2203                 tmport -= 0x08;
2204                 j = inb(tmport) & 0x0f;
2205                 if (j == 0x0f) {
2206                         goto widep_in;
2207                 }
2208                 if (j == 0x0a) {
2209                         goto widep_cmd;
2210                 }
2211                 if (j == 0x0e) {
2212                         goto widep_out;
2213                 }
2214                 continue;
2215 widep_in:
2216                 tmport = wkport + 0x54;
2217                 outb(0xff, tmport);
2218                 tmport += 0x04;
2219                 outb(0x20, tmport);
2220                 tmport += 0x07;
2221                 k = 0;
2222 widep_in1:
2223                 j = inb(tmport);
2224                 if ((j & 0x01) != 0) {
2225                         tmport -= 0x06;
2226                         mbuf[k++] = inb(tmport);
2227                         tmport += 0x06;
2228                         goto widep_in1;
2229                 }
2230                 if ((j & 0x80) == 0x00) {
2231                         goto widep_in1;
2232                 }
2233                 tmport -= 0x08;
2234                 j = inb(tmport) & 0x0f;
2235                 if (j == 0x0f) {
2236                         goto widep_in;
2237                 }
2238                 if (j == 0x0a) {
2239                         goto widep_cmd;
2240                 }
2241                 if (j == 0x0e) {
2242                         goto widep_out;
2243                 }
2244                 continue;
2245 widep_cmd:
2246                 tmport = wkport + 0x50;
2247                 outb(0x30, tmport);
2248                 tmport = wkport + 0x54;
2249                 outb(0x00, tmport);
2250                 tmport += 0x04;
2251                 outb(0x08, tmport);
2252                 tmport += 0x07;
2253
2254                 while ((inb(tmport) & 0x80) == 0x00)
2255                         cpu_relax();
2256
2257                 tmport -= 0x08;
2258                 j = inb(tmport);
2259                 if (j != 0x16) {
2260                         if (j == 0x4e) {
2261                                 goto widep_out;
2262                         }
2263                         continue;
2264                 }
2265                 if (mbuf[0] != 0x01) {
2266                         goto not_wide;
2267                 }
2268                 if (mbuf[1] != 0x02) {
2269                         goto not_wide;
2270                 }
2271                 if (mbuf[2] != 0x03) {
2272                         goto not_wide;
2273                 }
2274                 if (mbuf[3] != 0x01) {
2275                         goto not_wide;
2276                 }
2277                 m = 1;
2278                 m = m << i;
2279                 dev->wide_id[0] |= m;
2280 not_wide:
2281                 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
2282                         m = 1;
2283                         m = m << i;
2284                         if ((dev->async[0] & m) != 0) {
2285                                 goto set_sync;
2286                         }
2287                 }
2288                 continue;
2289 set_sync:
2290                 if (dev->sp[0][i] == 0x02) {
2291                         synu[4] = 0x0c;
2292                         synuw[4] = 0x0c;
2293                 } else {
2294                         if (dev->sp[0][i] >= 0x03) {
2295                                 synu[4] = 0x0a;
2296                                 synuw[4] = 0x0a;
2297                         }
2298                 }
2299                 tmport = wkport + 0x5b;
2300                 j = 0;
2301                 if ((m & dev->wide_id[0]) != 0) {
2302                         j |= 0x01;
2303                 }
2304                 outb(j, tmport);
2305                 tmport = wkport + 0x43;
2306                 outb(satn[0], tmport++);
2307                 outb(satn[1], tmport++);
2308                 outb(satn[2], tmport++);
2309                 outb(satn[3], tmport++);
2310                 outb(satn[4], tmport++);
2311                 outb(satn[5], tmport++);
2312                 tmport += 0x06;
2313                 outb(0, tmport);
2314                 tmport += 0x02;
2315                 outb(dev->id[0][i].devsp, tmport++);
2316                 outb(0, tmport++);
2317                 outb(satn[6], tmport++);
2318                 outb(satn[7], tmport++);
2319                 tmport += 0x03;
2320                 outb(satn[8], tmport);
2321                 tmport += 0x07;
2322
2323                 while ((inb(tmport) & 0x80) == 0x00)
2324                         cpu_relax();
2325
2326                 tmport -= 0x08;
2327                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
2328                         continue;
2329                 }
2330                 while (inb(tmport) != 0x8e)
2331                         cpu_relax();
2332
2333 try_sync:
2334                 j = 0;
2335                 tmport = wkport + 0x54;
2336                 outb(0x06, tmport);
2337                 tmport += 0x04;
2338                 outb(0x20, tmport);
2339                 tmport += 0x07;
2340
2341                 while ((inb(tmport) & 0x80) == 0) {
2342                         if ((inb(tmport) & 0x01) != 0) {
2343                                 tmport -= 0x06;
2344                                 if ((m & dev->wide_id[0]) != 0) {
2345                                         if ((m & dev->ultra_map[0]) != 0) {
2346                                                 outb(synuw[j++], tmport);
2347                                         } else {
2348                                                 outb(synw[j++], tmport);
2349                                         }
2350                                 } else {
2351                                         if ((m & dev->ultra_map[0]) != 0) {
2352                                                 outb(synu[j++], tmport);
2353                                         } else {
2354                                                 outb(synn[j++], tmport);
2355                                         }
2356                                 }
2357                                 tmport += 0x06;
2358                         }
2359                 }
2360                 tmport -= 0x08;
2361
2362                 while ((inb(tmport) & 0x80) == 0x00)
2363                         cpu_relax();
2364
2365                 j = inb(tmport) & 0x0f;
2366                 if (j == 0x0f) {
2367                         goto phase_ins;
2368                 }
2369                 if (j == 0x0a) {
2370                         goto phase_cmds;
2371                 }
2372                 if (j == 0x0e) {
2373                         goto try_sync;
2374                 }
2375                 continue;
2376 phase_outs:
2377                 tmport = wkport + 0x58;
2378                 outb(0x20, tmport);
2379                 tmport += 0x07;
2380                 while ((inb(tmport) & 0x80) == 0x00) {
2381                         if ((inb(tmport) & 0x01) != 0x00) {
2382                                 tmport -= 0x06;
2383                                 outb(0x00, tmport);
2384                                 tmport += 0x06;
2385                         }
2386                 }
2387                 tmport -= 0x08;
2388                 j = inb(tmport);
2389                 if (j == 0x85) {
2390                         goto tar_dcons;
2391                 }
2392                 j &= 0x0f;
2393                 if (j == 0x0f) {
2394                         goto phase_ins;
2395                 }
2396                 if (j == 0x0a) {
2397                         goto phase_cmds;
2398                 }
2399                 if (j == 0x0e) {
2400                         goto phase_outs;
2401                 }
2402                 continue;
2403 phase_ins:
2404                 tmport = wkport + 0x54;
2405                 outb(0x06, tmport);
2406                 tmport += 0x04;
2407                 outb(0x20, tmport);
2408                 tmport += 0x07;
2409                 k = 0;
2410 phase_ins1:
2411                 j = inb(tmport);
2412                 if ((j & 0x01) != 0x00) {
2413                         tmport -= 0x06;
2414                         mbuf[k++] = inb(tmport);
2415                         tmport += 0x06;
2416                         goto phase_ins1;
2417                 }
2418                 if ((j & 0x80) == 0x00) {
2419                         goto phase_ins1;
2420                 }
2421                 tmport -= 0x08;
2422
2423                 while ((inb(tmport) & 0x80) == 0x00)
2424                         cpu_relax();
2425
2426                 j = inb(tmport);
2427                 if (j == 0x85) {
2428                         goto tar_dcons;
2429                 }
2430                 j &= 0x0f;
2431                 if (j == 0x0f) {
2432                         goto phase_ins;
2433                 }
2434                 if (j == 0x0a) {
2435                         goto phase_cmds;
2436                 }
2437                 if (j == 0x0e) {
2438                         goto phase_outs;
2439                 }
2440                 continue;
2441 phase_cmds:
2442                 tmport = wkport + 0x50;
2443                 outb(0x30, tmport);
2444 tar_dcons:
2445                 tmport = wkport + 0x54;
2446                 outb(0x00, tmport);
2447                 tmport += 0x04;
2448                 outb(0x08, tmport);
2449                 tmport += 0x07;
2450
2451                 while ((inb(tmport) & 0x80) == 0x00)
2452                         cpu_relax();
2453
2454                 tmport -= 0x08;
2455                 j = inb(tmport);
2456                 if (j != 0x16) {
2457                         continue;
2458                 }
2459                 if (mbuf[0] != 0x01) {
2460                         continue;
2461                 }
2462                 if (mbuf[1] != 0x03) {
2463                         continue;
2464                 }
2465                 if (mbuf[4] == 0x00) {
2466                         continue;
2467                 }
2468                 if (mbuf[3] > 0x64) {
2469                         continue;
2470                 }
2471                 if (mbuf[4] > 0x0e) {
2472                         mbuf[4] = 0x0e;
2473                 }
2474                 dev->id[0][i].devsp = mbuf[4];
2475                 if (mbuf[3] < 0x0c) {
2476                         j = 0xb0;
2477                         goto set_syn_ok;
2478                 }
2479                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2480                         j = 0xa0;
2481                         goto set_syn_ok;
2482                 }
2483                 if (mbuf[3] < 0x1a) {
2484                         j = 0x20;
2485                         goto set_syn_ok;
2486                 }
2487                 if (mbuf[3] < 0x33) {
2488                         j = 0x40;
2489                         goto set_syn_ok;
2490                 }
2491                 if (mbuf[3] < 0x4c) {
2492                         j = 0x50;
2493                         goto set_syn_ok;
2494                 }
2495                 j = 0x60;
2496 set_syn_ok:
2497                 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
2498         }
2499 }
2500
2501 static void atp870u_free_tables(struct Scsi_Host *host)
2502 {
2503         struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2504         int j, k;
2505         for (j=0; j < 2; j++) {
2506                 for (k = 0; k < 16; k++) {
2507                         if (!atp_dev->id[j][k].prd_table)
2508                                 continue;
2509                         pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
2510                         atp_dev->id[j][k].prd_table = NULL;
2511                 }
2512         }
2513 }
2514
2515 static int atp870u_init_tables(struct Scsi_Host *host)
2516 {
2517         struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2518         int c,k;
2519         for(c=0;c < 2;c++) {
2520                 for(k=0;k<16;k++) {
2521                                 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
2522                                 if (!atp_dev->id[c][k].prd_table) {
2523                                         printk("atp870u_init_tables fail\n");
2524                                 atp870u_free_tables(host);
2525                                 return -ENOMEM;
2526                         }
2527                         atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
2528                         atp_dev->id[c][k].devsp=0x20;
2529                         atp_dev->id[c][k].devtype = 0x7f;
2530                         atp_dev->id[c][k].curr_req = NULL;
2531                 }
2532
2533                 atp_dev->active_id[c] = 0;
2534                 atp_dev->wide_id[c] = 0;
2535                 atp_dev->host_id[c] = 0x07;
2536                 atp_dev->quhd[c] = 0;
2537                 atp_dev->quend[c] = 0;
2538                 atp_dev->last_cmd[c] = 0xff;
2539                 atp_dev->in_snd[c] = 0;
2540                 atp_dev->in_int[c] = 0;
2541
2542                 for (k = 0; k < qcnt; k++) {
2543                           atp_dev->quereq[c][k] = NULL;
2544                 }
2545                 for (k = 0; k < 16; k++) {
2546                            atp_dev->id[c][k].curr_req = NULL;
2547                            atp_dev->sp[c][k] = 0x04;
2548                 }
2549         }
2550         return 0;
2551 }
2552
2553 /* return non-zero on detection */
2554 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2555 {
2556         unsigned char k, m, c;
2557         unsigned long flags;
2558         unsigned int base_io, tmport, error,n;
2559         unsigned char host_id;
2560         struct Scsi_Host *shpnt = NULL;
2561         struct atp_unit *atpdev, *p;
2562         unsigned char setupdata[2][16];
2563         int count = 0;
2564
2565         atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2566         if (!atpdev)
2567                 return -ENOMEM;
2568
2569         if (pci_enable_device(pdev))
2570                 goto err_eio;
2571
2572         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2573                 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2574         } else {
2575                 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
2576                 goto err_eio;
2577         }
2578
2579         /*
2580          * It's probably easier to weed out some revisions like
2581          * this than via the PCI device table
2582          */
2583         if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
2584                 error = pci_read_config_byte(pdev, PCI_CLASS_REVISION, &atpdev->chip_ver);
2585                 if (atpdev->chip_ver < 2)
2586                         goto err_eio;
2587         }
2588
2589         switch (ent->device) {
2590         case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2591         case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2592         case ATP880_DEVID1:
2593         case ATP880_DEVID2:
2594         case ATP885_DEVID:
2595                 atpdev->chip_ver = 0x04;
2596         default:
2597                 break;
2598         }
2599         base_io = pci_resource_start(pdev, 0);
2600         base_io &= 0xfffffff8;
2601
2602         if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
2603                 error = pci_read_config_byte(pdev, PCI_CLASS_REVISION, &atpdev->chip_ver);
2604                 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2605
2606                 host_id = inb(base_io + 0x39);
2607                 host_id >>= 0x04;
2608
2609                 printk(KERN_INFO "   ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2610                         "    IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2611                 atpdev->ioport[0] = base_io + 0x40;
2612                 atpdev->pciport[0] = base_io + 0x28;
2613                 atpdev->dev_id = ent->device;
2614                 atpdev->host_id[0] = host_id;
2615
2616                 tmport = base_io + 0x22;
2617                 atpdev->scam_on = inb(tmport);
2618                 tmport += 0x13;
2619                 atpdev->global_map[0] = inb(tmport);
2620                 tmport += 0x07;
2621                 atpdev->ultra_map[0] = inw(tmport);
2622
2623                 n = 0x3f09;
2624 next_fblk_880:
2625                 if (n >= 0x4000)
2626                         goto flash_ok_880;
2627
2628                 m = 0;
2629                 outw(n, base_io + 0x34);
2630                 n += 0x0002;
2631                 if (inb(base_io + 0x30) == 0xff)
2632                         goto flash_ok_880;
2633
2634                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2635                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2636                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2637                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2638                 outw(n, base_io + 0x34);
2639                 n += 0x0002;
2640                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2641                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2642                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2643                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2644                 outw(n, base_io + 0x34);
2645                 n += 0x0002;
2646                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2647                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2648                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2649                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2650                 outw(n, base_io + 0x34);
2651                 n += 0x0002;
2652                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2653                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2654                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2655                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2656                 n += 0x0018;
2657                 goto next_fblk_880;
2658 flash_ok_880:
2659                 outw(0, base_io + 0x34);
2660                 atpdev->ultra_map[0] = 0;
2661                 atpdev->async[0] = 0;
2662                 for (k = 0; k < 16; k++) {
2663                         n = 1;
2664                         n = n << k;
2665                         if (atpdev->sp[0][k] > 1) {
2666                                 atpdev->ultra_map[0] |= n;
2667                         } else {
2668                                 if (atpdev->sp[0][k] == 0)
2669                                         atpdev->async[0] |= n;
2670                         }
2671                 }
2672                 atpdev->async[0] = ~(atpdev->async[0]);
2673                 outb(atpdev->global_map[0], base_io + 0x35);
2674
2675                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2676                 if (!shpnt)
2677                         goto err_nomem;
2678
2679                 p = (struct atp_unit *)&shpnt->hostdata;
2680
2681                 atpdev->host = shpnt;
2682                 atpdev->pdev = pdev;
2683                 pci_set_drvdata(pdev, p);
2684                 memcpy(p, atpdev, sizeof(*atpdev));
2685                 if (atp870u_init_tables(shpnt) < 0) {
2686                         printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2687                         goto unregister;
2688                 }
2689
2690                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
2691                         printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2692                         goto free_tables;
2693                 }
2694
2695                 spin_lock_irqsave(shpnt->host_lock, flags);
2696                 tmport = base_io + 0x38;
2697                 k = inb(tmport) & 0x80;
2698                 outb(k, tmport);
2699                 tmport += 0x03;
2700                 outb(0x20, tmport);
2701                 mdelay(32);
2702                 outb(0, tmport);
2703                 mdelay(32);
2704                 tmport = base_io + 0x5b;
2705                 inb(tmport);
2706                 tmport -= 0x04;
2707                 inb(tmport);
2708                 tmport = base_io + 0x40;
2709                 outb((host_id | 0x08), tmport);
2710                 tmport += 0x18;
2711                 outb(0, tmport);
2712                 tmport += 0x07;
2713                 while ((inb(tmport) & 0x80) == 0)
2714                         mdelay(1);
2715                 tmport -= 0x08;
2716                 inb(tmport);
2717                 tmport = base_io + 0x41;
2718                 outb(8, tmport++);
2719                 outb(0x7f, tmport);
2720                 tmport = base_io + 0x51;
2721                 outb(0x20, tmport);
2722
2723                 tscam(shpnt);
2724                 is880(p, base_io);
2725                 tmport = base_io + 0x38;
2726                 outb(0xb0, tmport);
2727                 shpnt->max_id = 16;
2728                 shpnt->this_id = host_id;
2729                 shpnt->unique_id = base_io;
2730                 shpnt->io_port = base_io;
2731                 shpnt->n_io_port = 0x60;        /* Number of bytes of I/O space used */
2732                 shpnt->irq = pdev->irq;
2733         } else if (ent->device == ATP885_DEVID) {
2734                         printk(KERN_INFO "   ACARD AEC-67162 PCI Ultra3 LVD Host Adapter:  IO:%x, IRQ:%d.\n"
2735                                , base_io, pdev->irq);
2736
2737                 atpdev->pdev = pdev;
2738                 atpdev->dev_id  = ent->device;
2739                 atpdev->baseport = base_io;
2740                 atpdev->ioport[0] = base_io + 0x80;
2741                 atpdev->ioport[1] = base_io + 0xc0;
2742                 atpdev->pciport[0] = base_io + 0x40;
2743                 atpdev->pciport[1] = base_io + 0x50;
2744
2745                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2746                 if (!shpnt)
2747                         goto err_nomem;
2748
2749                 p = (struct atp_unit *)&shpnt->hostdata;
2750
2751                 atpdev->host = shpnt;
2752                 atpdev->pdev = pdev;
2753                 pci_set_drvdata(pdev, p);
2754                 memcpy(p, atpdev, sizeof(struct atp_unit));
2755                 if (atp870u_init_tables(shpnt) < 0)
2756                         goto unregister;
2757
2758 #ifdef ED_DBGP
2759         printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2760 #endif
2761                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
2762                                 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2763                         goto free_tables;
2764                 }
2765
2766                 spin_lock_irqsave(shpnt->host_lock, flags);
2767
2768                 c=inb(base_io + 0x29);
2769                 outb((c | 0x04),base_io + 0x29);
2770
2771                 n=0x1f80;
2772 next_fblk_885:
2773                 if (n >= 0x2000) {
2774                    goto flash_ok_885;
2775                 }
2776                 outw(n,base_io + 0x3c);
2777                 if (inl(base_io + 0x38) == 0xffffffff) {
2778                    goto flash_ok_885;
2779                 }
2780                 for (m=0; m < 2; m++) {
2781                     p->global_map[m]= 0;
2782                     for (k=0; k < 4; k++) {
2783                         outw(n++,base_io + 0x3c);
2784                         ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2785                     }
2786                     for (k=0; k < 4; k++) {
2787                         outw(n++,base_io + 0x3c);
2788                         ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2789                     }
2790                     n += 8;
2791                 }
2792                 goto next_fblk_885;
2793 flash_ok_885:
2794 #ifdef ED_DBGP
2795                 printk( "Flash Read OK\n");
2796 #endif
2797                 c=inb(base_io + 0x29);
2798                 outb((c & 0xfb),base_io + 0x29);
2799                 for (c=0;c < 2;c++) {
2800                     p->ultra_map[c]=0;
2801                     p->async[c] = 0;
2802                     for (k=0; k < 16; k++) {
2803                         n=1;
2804                         n = n << k;
2805                         if (p->sp[c][k] > 1) {
2806                            p->ultra_map[c] |= n;
2807                         } else {
2808                            if (p->sp[c][k] == 0) {
2809                               p->async[c] |= n;
2810                            }
2811                         }
2812                     }
2813                     p->async[c] = ~(p->async[c]);
2814
2815                     if (p->global_map[c] == 0) {
2816                        k=setupdata[c][1];
2817                        if ((k & 0x40) != 0)
2818                           p->global_map[c] |= 0x20;
2819                        k &= 0x07;
2820                        p->global_map[c] |= k;
2821                        if ((setupdata[c][2] & 0x04) != 0)
2822                           p->global_map[c] |= 0x08;
2823                        p->host_id[c] = setupdata[c][0] & 0x07;
2824                     }
2825                 }
2826
2827                 k = inb(base_io + 0x28) & 0x8f;
2828                 k |= 0x10;
2829                 outb(k, base_io + 0x28);
2830                 outb(0x80, base_io + 0x41);
2831                 outb(0x80, base_io + 0x51);
2832                 mdelay(100);
2833                 outb(0, base_io + 0x41);
2834                 outb(0, base_io + 0x51);
2835                 mdelay(1000);
2836                 inb(base_io + 0x9b);
2837                 inb(base_io + 0x97);
2838                 inb(base_io + 0xdb);
2839                 inb(base_io + 0xd7);
2840                 tmport = base_io + 0x80;
2841                 k=p->host_id[0];
2842                 if (k > 7)
2843                    k = (k & 0x07) | 0x40;
2844                 k |= 0x08;
2845                 outb(k, tmport);
2846                 tmport += 0x18;
2847                 outb(0, tmport);
2848                 tmport += 0x07;
2849
2850                 while ((inb(tmport) & 0x80) == 0)
2851                         cpu_relax();
2852
2853                 tmport -= 0x08;
2854                 inb(tmport);
2855                 tmport = base_io + 0x81;
2856                 outb(8, tmport++);
2857                 outb(0x7f, tmport);
2858                 tmport = base_io + 0x91;
2859                 outb(0x20, tmport);
2860
2861                 tmport = base_io + 0xc0;
2862                 k=p->host_id[1];
2863                 if (k > 7)
2864                    k = (k & 0x07) | 0x40;
2865                 k |= 0x08;
2866                 outb(k, tmport);
2867                 tmport += 0x18;
2868                 outb(0, tmport);
2869                 tmport += 0x07;
2870
2871                 while ((inb(tmport) & 0x80) == 0)
2872                         cpu_relax();
2873
2874                 tmport -= 0x08;
2875                 inb(tmport);
2876                 tmport = base_io + 0xc1;
2877                 outb(8, tmport++);
2878                 outb(0x7f, tmport);
2879                 tmport = base_io + 0xd1;
2880                 outb(0x20, tmport);
2881
2882                 tscam_885();
2883                 printk(KERN_INFO "   Scanning Channel A SCSI Device ...\n");
2884                 is885(p, base_io + 0x80, 0);
2885                 printk(KERN_INFO "   Scanning Channel B SCSI Device ...\n");
2886                 is885(p, base_io + 0xc0, 1);
2887
2888                 k = inb(base_io + 0x28) & 0xcf;
2889                 k |= 0xc0;
2890                 outb(k, base_io + 0x28);
2891                 k = inb(base_io + 0x1f) | 0x80;
2892                 outb(k, base_io + 0x1f);
2893                 k = inb(base_io + 0x29) | 0x01;
2894                 outb(k, base_io + 0x29);
2895 #ifdef ED_DBGP
2896                 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2897 #endif
2898                 shpnt->max_id = 16;
2899                 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2900                 shpnt->max_channel = 1;
2901                 shpnt->this_id = p->host_id[0];
2902                 shpnt->unique_id = base_io;
2903                 shpnt->io_port = base_io;
2904                 shpnt->n_io_port = 0xff;        /* Number of bytes of I/O space used */
2905                 shpnt->irq = pdev->irq;
2906
2907         } else {
2908                 error = pci_read_config_byte(pdev, 0x49, &host_id);
2909
2910                 printk(KERN_INFO "   ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2911                         "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2912
2913                 atpdev->ioport[0] = base_io;
2914                 atpdev->pciport[0] = base_io + 0x20;
2915                 atpdev->dev_id = ent->device;
2916                 host_id &= 0x07;
2917                 atpdev->host_id[0] = host_id;
2918                 tmport = base_io + 0x22;
2919                 atpdev->scam_on = inb(tmport);
2920                 tmport += 0x0b;
2921                 atpdev->global_map[0] = inb(tmport++);
2922                 atpdev->ultra_map[0] = inw(tmport);
2923
2924                 if (atpdev->ultra_map[0] == 0) {
2925                         atpdev->scam_on = 0x00;
2926                         atpdev->global_map[0] = 0x20;
2927                         atpdev->ultra_map[0] = 0xffff;
2928                 }
2929
2930                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2931                 if (!shpnt)
2932                         goto err_nomem;
2933
2934                 p = (struct atp_unit *)&shpnt->hostdata;
2935
2936                 atpdev->host = shpnt;
2937                 atpdev->pdev = pdev;
2938                 pci_set_drvdata(pdev, p);
2939                 memcpy(p, atpdev, sizeof(*atpdev));
2940                 if (atp870u_init_tables(shpnt) < 0)
2941                         goto unregister;
2942
2943                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
2944                         printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2945                         goto free_tables;
2946                 }
2947
2948                 spin_lock_irqsave(shpnt->host_lock, flags);
2949                 if (atpdev->chip_ver > 0x07) {  /* check if atp876 chip then enable terminator */
2950                         tmport = base_io + 0x3e;
2951                         outb(0x00, tmport);
2952                 }
2953
2954                 tmport = base_io + 0x3a;
2955                 k = (inb(tmport) & 0xf3) | 0x10;
2956                 outb(k, tmport);
2957                 outb((k & 0xdf), tmport);
2958                 mdelay(32);
2959                 outb(k, tmport);
2960                 mdelay(32);
2961                 tmport = base_io;
2962                 outb((host_id | 0x08), tmport);
2963                 tmport += 0x18;
2964                 outb(0, tmport);
2965                 tmport += 0x07;
2966                 while ((inb(tmport) & 0x80) == 0)
2967                         mdelay(1);
2968
2969                 tmport -= 0x08;
2970                 inb(tmport);
2971                 tmport = base_io + 1;
2972                 outb(8, tmport++);
2973                 outb(0x7f, tmport);
2974                 tmport = base_io + 0x11;
2975                 outb(0x20, tmport);
2976
2977                 tscam(shpnt);
2978                 is870(p, base_io);
2979                 tmport = base_io + 0x3a;
2980                 outb((inb(tmport) & 0xef), tmport);
2981                 tmport++;
2982                 outb((inb(tmport) | 0x20), tmport);
2983                 if (atpdev->chip_ver == 4)
2984                         shpnt->max_id = 16;
2985                 else
2986                         shpnt->max_id = 8;
2987                 shpnt->this_id = host_id;
2988                 shpnt->unique_id = base_io;
2989                 shpnt->io_port = base_io;
2990                 shpnt->n_io_port = 0x40;        /* Number of bytes of I/O space used */
2991                 shpnt->irq = pdev->irq;
2992         }
2993                 spin_unlock_irqrestore(shpnt->host_lock, flags);
2994                 if(ent->device==ATP885_DEVID) {
2995                         if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
2996                                 goto request_io_fail;
2997                 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2998                         if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
2999                                 goto request_io_fail;
3000                 } else {
3001                         if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
3002                                 goto request_io_fail;
3003                 }
3004                 count++;
3005                 if (scsi_add_host(shpnt, &pdev->dev))
3006                         goto scsi_add_fail;
3007                 scsi_scan_host(shpnt);
3008 #ifdef ED_DBGP
3009                 printk("atp870u_prob : exit\n");
3010 #endif
3011                 return 0;
3012
3013 scsi_add_fail:
3014         printk("atp870u_prob:scsi_add_fail\n");
3015         if(ent->device==ATP885_DEVID) {
3016                 release_region(base_io, 0xff);
3017         } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
3018                 release_region(base_io, 0x60);
3019         } else {
3020                 release_region(base_io, 0x40);
3021         }
3022 request_io_fail:
3023         printk("atp870u_prob:request_io_fail\n");
3024         free_irq(pdev->irq, shpnt);
3025 free_tables:
3026         printk("atp870u_prob:free_table\n");
3027         atp870u_free_tables(shpnt);
3028 unregister:
3029         printk("atp870u_prob:unregister\n");
3030         scsi_host_put(shpnt);
3031         return -1;
3032 err_eio:
3033         kfree(atpdev);
3034         return -EIO;
3035 err_nomem:
3036         kfree(atpdev);
3037         return -ENOMEM;
3038 }
3039
3040 /* The abort command does not leave the device in a clean state where
3041    it is available to be used again.  Until this gets worked out, we will
3042    leave it commented out.  */
3043
3044 static int atp870u_abort(struct scsi_cmnd * SCpnt)
3045 {
3046         unsigned char  j, k, c;
3047         struct scsi_cmnd *workrequ;
3048         unsigned int tmport;
3049         struct atp_unit *dev;
3050         struct Scsi_Host *host;
3051         host = SCpnt->device->host;
3052
3053         dev = (struct atp_unit *)&host->hostdata;
3054         c = scmd_channel(SCpnt);
3055         printk(" atp870u: abort Channel = %x \n", c);
3056         printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
3057         printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
3058         tmport = dev->ioport[c];
3059         for (j = 0; j < 0x18; j++) {
3060                 printk(" r%2x=%2x", j, inb(tmport++));
3061         }
3062         tmport += 0x04;
3063         printk(" r1c=%2x", inb(tmport));
3064         tmport += 0x03;
3065         printk(" r1f=%2x in_snd=%2x ", inb(tmport), dev->in_snd[c]);
3066         tmport= dev->pciport[c];
3067         printk(" d00=%2x", inb(tmport));
3068         tmport += 0x02;
3069         printk(" d02=%2x", inb(tmport));
3070         for(j=0;j<16;j++) {
3071            if (dev->id[c][j].curr_req != NULL) {
3072                 workrequ = dev->id[c][j].curr_req;
3073                 printk("\n que cdb= ");
3074                 for (k=0; k < workrequ->cmd_len; k++) {
3075                     printk(" %2x ",workrequ->cmnd[k]);
3076                 }
3077                 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
3078            }
3079         }
3080         return SUCCESS;
3081 }
3082
3083 static const char *atp870u_info(struct Scsi_Host *notused)
3084 {
3085         static char buffer[128];
3086
3087         strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
3088
3089         return buffer;
3090 }
3091
3092 #define BLS buffer + len + size
3093 static int atp870u_proc_info(struct Scsi_Host *HBAptr, char *buffer,
3094                              char **start, off_t offset, int length, int inout)
3095 {
3096         static u8 buff[512];
3097         int size = 0;
3098         int len = 0;
3099         off_t begin = 0;
3100         off_t pos = 0;
3101
3102         if (inout)
3103                 return -EINVAL;
3104         if (offset == 0)
3105                 memset(buff, 0, sizeof(buff));
3106         size += sprintf(BLS, "ACARD AEC-671X Driver Version: 2.6+ac\n");
3107         len += size;
3108         pos = begin + len;
3109         size = 0;
3110
3111         size += sprintf(BLS, "\n");
3112         size += sprintf(BLS, "Adapter Configuration:\n");
3113         size += sprintf(BLS, "               Base IO: %#.4lx\n", HBAptr->io_port);
3114         size += sprintf(BLS, "                   IRQ: %d\n", HBAptr->irq);
3115         len += size;
3116         pos = begin + len;
3117
3118         *start = buffer + (offset - begin);     /* Start of wanted data */
3119         len -= (offset - begin);        /* Start slop */
3120         if (len > length) {
3121                 len = length;   /* Ending slop */
3122         }
3123         return (len);
3124 }
3125
3126
3127 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
3128                         sector_t capacity, int *ip)
3129 {
3130         int heads, sectors, cylinders;
3131
3132         heads = 64;
3133         sectors = 32;
3134         cylinders = (unsigned long)capacity / (heads * sectors);
3135         if (cylinders > 1024) {
3136                 heads = 255;
3137                 sectors = 63;
3138                 cylinders = (unsigned long)capacity / (heads * sectors);
3139         }
3140         ip[0] = heads;
3141         ip[1] = sectors;
3142         ip[2] = cylinders;
3143
3144         return 0;
3145 }
3146
3147 static void atp870u_remove (struct pci_dev *pdev)
3148 {
3149         struct atp_unit *devext = pci_get_drvdata(pdev);
3150         struct Scsi_Host *pshost = devext->host;
3151
3152
3153         scsi_remove_host(pshost);
3154         printk(KERN_INFO "free_irq : %d\n",pshost->irq);
3155         free_irq(pshost->irq, pshost);
3156         release_region(pshost->io_port, pshost->n_io_port);
3157         printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
3158         atp870u_free_tables(pshost);
3159         printk(KERN_INFO "scsi_host_put : %p\n",pshost);
3160         scsi_host_put(pshost);
3161         printk(KERN_INFO "pci_set_drvdata : %p\n",pdev);
3162         pci_set_drvdata(pdev, NULL);
3163 }
3164 MODULE_LICENSE("GPL");
3165
3166 static struct scsi_host_template atp870u_template = {
3167      .module                    = THIS_MODULE,
3168      .name                      = "atp870u"             /* name */,
3169      .proc_name                 = "atp870u",
3170      .proc_info                 = atp870u_proc_info,
3171      .info                      = atp870u_info          /* info */,
3172      .queuecommand              = atp870u_queuecommand  /* queuecommand */,
3173      .eh_abort_handler          = atp870u_abort         /* abort */,
3174      .bios_param                = atp870u_biosparam     /* biosparm */,
3175      .can_queue                 = qcnt                  /* can_queue */,
3176      .this_id                   = 7                     /* SCSI ID */,
3177      .sg_tablesize              = ATP870U_SCATTER       /*SG_ALL*/ /*SG_NONE*/,
3178      .cmd_per_lun               = ATP870U_CMDLUN                /* commands per lun */,
3179      .use_clustering            = ENABLE_CLUSTERING,
3180      .max_sectors               = ATP870U_MAX_SECTORS,
3181 };
3182
3183 static struct pci_device_id atp870u_id_table[] = {
3184         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID)                   },
3185         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1)                          },
3186         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2)                          },
3187         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610)    },
3188         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW)  },
3189         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U)   },
3190         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S)   },
3191         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D)   },
3192         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
3193         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060)       },
3194         { 0, },
3195 };
3196
3197 MODULE_DEVICE_TABLE(pci, atp870u_id_table);
3198
3199 static struct pci_driver atp870u_driver = {
3200         .id_table       = atp870u_id_table,
3201         .name           = "atp870u",
3202         .probe          = atp870u_probe,
3203         .remove         = __devexit_p(atp870u_remove),
3204 };
3205
3206 static int __init atp870u_init(void)
3207 {
3208 #ifdef ED_DBGP
3209         printk("atp870u_init: Entry\n");
3210 #endif
3211         return pci_register_driver(&atp870u_driver);
3212 }
3213
3214 static void __exit atp870u_exit(void)
3215 {
3216 #ifdef ED_DBGP
3217         printk("atp870u_exit: Entry\n");
3218 #endif
3219         pci_unregister_driver(&atp870u_driver);
3220 }
3221
3222 static void tscam_885(void)
3223 {
3224         unsigned char i;
3225
3226         for (i = 0; i < 0x2; i++) {
3227                 mdelay(300);
3228         }
3229         return;
3230 }
3231
3232
3233
3234 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c)
3235 {
3236         unsigned int tmport;
3237         unsigned char i, j, k, rmb, n, lvdmode;
3238         unsigned short int m;
3239         static unsigned char mbuf[512];
3240         static unsigned char satn[9] =  {0, 0, 0, 0, 0, 0, 0, 6, 6};
3241         static unsigned char inqd[9] =  {0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6};
3242         static unsigned char synn[6] =  {0x80, 1, 3, 1, 0x19, 0x0e};
3243         unsigned char synu[6] =  {0x80, 1, 3, 1, 0x0a, 0x0e};
3244         static unsigned char synw[6] =  {0x80, 1, 3, 1, 0x19, 0x0e};
3245         unsigned char synuw[6] =  {0x80, 1, 3, 1, 0x0a, 0x0e};
3246         static unsigned char wide[6] =  {0x80, 1, 2, 3, 1, 0};
3247         static unsigned char u3[9] = { 0x80,1,6,4,0x09,00,0x0e,0x01,0x02 };
3248
3249         lvdmode=inb(wkport + 0x1b) >> 7;
3250
3251         for (i = 0; i < 16; i++) {
3252                 m = 1;
3253                 m = m << i;
3254                 if ((m & dev->active_id[c]) != 0) {
3255                         continue;
3256                 }
3257                 if (i == dev->host_id[c]) {
3258                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[c]);
3259                         continue;
3260                 }
3261                 tmport = wkport + 0x1b;
3262                 outb(0x01, tmport);
3263                 tmport = wkport + 0x01;
3264                 outb(0x08, tmport++);
3265                 outb(0x7f, tmport++);
3266                 outb(satn[0], tmport++);
3267                 outb(satn[1], tmport++);
3268                 outb(satn[2], tmport++);
3269                 outb(satn[3], tmport++);
3270                 outb(satn[4], tmport++);
3271                 outb(satn[5], tmport++);
3272                 tmport += 0x06;
3273                 outb(0, tmport);
3274                 tmport += 0x02;
3275                 outb(dev->id[c][i].devsp, tmport++);
3276
3277                 outb(0, tmport++);
3278                 outb(satn[6], tmport++);
3279                 outb(satn[7], tmport++);
3280                 j = i;
3281                 if ((j & 0x08) != 0) {
3282                         j = (j & 0x07) | 0x40;
3283                 }
3284                 outb(j, tmport);
3285                 tmport += 0x03;
3286                 outb(satn[8], tmport);
3287                 tmport += 0x07;
3288
3289                 while ((inb(tmport) & 0x80) == 0x00)
3290                         cpu_relax();
3291                 tmport -= 0x08;
3292                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3293                         continue;
3294                 }
3295                 while (inb(tmport) != 0x8e)
3296                         cpu_relax();
3297                 dev->active_id[c] |= m;
3298
3299                 tmport = wkport + 0x10;
3300                 outb(0x30, tmport);
3301                 tmport = wkport + 0x14;
3302                 outb(0x00, tmport);
3303
3304 phase_cmd:
3305                 tmport = wkport + 0x18;
3306                 outb(0x08, tmport);
3307                 tmport += 0x07;
3308                 while ((inb(tmport) & 0x80) == 0x00)
3309                         cpu_relax();
3310                 tmport -= 0x08;
3311                 j = inb(tmport);
3312                 if (j != 0x16) {
3313                         tmport = wkport + 0x10;
3314                         outb(0x41, tmport);
3315                         goto phase_cmd;
3316                 }
3317 sel_ok:
3318                 tmport = wkport + 0x03;
3319                 outb(inqd[0], tmport++);
3320                 outb(inqd[1], tmport++);
3321                 outb(inqd[2], tmport++);
3322                 outb(inqd[3], tmport++);
3323                 outb(inqd[4], tmport++);
3324                 outb(inqd[5], tmport);
3325                 tmport += 0x07;
3326                 outb(0, tmport);
3327                 tmport += 0x02;
3328                 outb(dev->id[c][i].devsp, tmport++);
3329                 outb(0, tmport++);
3330                 outb(inqd[6], tmport++);
3331                 outb(inqd[7], tmport++);
3332                 tmport += 0x03;
3333                 outb(inqd[8], tmport);
3334                 tmport += 0x07;
3335                 while ((inb(tmport) & 0x80) == 0x00)
3336                         cpu_relax();
3337                 tmport -= 0x08;
3338                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3339                         continue;
3340                 }
3341                 while (inb(tmport) != 0x8e)
3342                         cpu_relax();
3343                 tmport = wkport + 0x1b;
3344                 outb(0x00, tmport);
3345                 tmport = wkport + 0x18;
3346                 outb(0x08, tmport);
3347                 tmport += 0x07;
3348                 j = 0;
3349 rd_inq_data:
3350                 k = inb(tmport);
3351                 if ((k & 0x01) != 0) {
3352                         tmport -= 0x06;
3353                         mbuf[j++] = inb(tmport);
3354                         tmport += 0x06;
3355                         goto rd_inq_data;
3356                 }
3357                 if ((k & 0x80) == 0) {
3358                         goto rd_inq_data;
3359                 }
3360                 tmport -= 0x08;
3361                 j = inb(tmport);
3362                 if (j == 0x16) {
3363                         goto inq_ok;
3364                 }
3365                 tmport = wkport + 0x10;
3366                 outb(0x46, tmport);
3367                 tmport += 0x02;
3368                 outb(0, tmport++);
3369                 outb(0, tmport++);
3370                 outb(0, tmport++);
3371                 tmport += 0x03;
3372                 outb(0x08, tmport);
3373                 tmport += 0x07;
3374                 while ((inb(tmport) & 0x80) == 0x00)
3375                         cpu_relax();
3376                 tmport -= 0x08;
3377                 if (inb(tmport) != 0x16) {
3378                         goto sel_ok;
3379                 }
3380 inq_ok:
3381                 mbuf[36] = 0;
3382                 printk( KERN_INFO"         ID: %2d  %s\n", i, &mbuf[8]);
3383                 dev->id[c][i].devtype = mbuf[0];
3384                 rmb = mbuf[1];
3385                 n = mbuf[7];
3386                 if ((mbuf[7] & 0x60) == 0) {
3387                         goto not_wide;
3388                 }
3389                 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
3390                         goto not_wide;
3391                 }
3392                 if (lvdmode == 0) {
3393                    goto chg_wide;
3394                 }
3395                 if (dev->sp[c][i] != 0x04) {    // force u2
3396                    goto chg_wide;
3397                 }
3398
3399                 tmport = wkport + 0x1b;
3400                 outb(0x01, tmport);
3401                 tmport = wkport + 0x03;
3402                 outb(satn[0], tmport++);
3403                 outb(satn[1], tmport++);
3404                 outb(satn[2], tmport++);
3405                 outb(satn[3], tmport++);
3406                 outb(satn[4], tmport++);
3407                 outb(satn[5], tmport++);
3408                 tmport += 0x06;
3409                 outb(0, tmport);
3410                 tmport += 0x02;
3411                 outb(dev->id[c][i].devsp, tmport++);
3412                 outb(0, tmport++);
3413                 outb(satn[6], tmport++);
3414                 outb(satn[7], tmport++);
3415                 tmport += 0x03;
3416                 outb(satn[8], tmport);
3417                 tmport += 0x07;
3418
3419                 while ((inb(tmport) & 0x80) == 0x00)
3420                         cpu_relax();
3421                 tmport -= 0x08;
3422                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3423                         continue;
3424                 }
3425                 while (inb(tmport) != 0x8e)
3426                         cpu_relax();
3427 try_u3:
3428                 j = 0;
3429                 tmport = wkport + 0x14;
3430                 outb(0x09, tmport);
3431                 tmport += 0x04;
3432                 outb(0x20, tmport);
3433                 tmport += 0x07;
3434
3435                 while ((inb(tmport) & 0x80) == 0) {
3436                         if ((inb(tmport) & 0x01) != 0) {
3437                                 tmport -= 0x06;
3438                                 outb(u3[j++], tmport);
3439                                 tmport += 0x06;
3440                         }
3441                         cpu_relax();
3442                 }
3443                 tmport -= 0x08;
3444                 while ((inb(tmport) & 0x80) == 0x00)
3445                         cpu_relax();
3446                 j = inb(tmport) & 0x0f;
3447                 if (j == 0x0f) {
3448                         goto u3p_in;
3449                 }
3450                 if (j == 0x0a) {
3451                         goto u3p_cmd;
3452                 }
3453                 if (j == 0x0e) {
3454                         goto try_u3;
3455                 }
3456                 continue;
3457 u3p_out:
3458                 tmport = wkport + 0x18;
3459                 outb(0x20, tmport);
3460                 tmport += 0x07;
3461                 while ((inb(tmport) & 0x80) == 0) {
3462                         if ((inb(tmport) & 0x01) != 0) {
3463                                 tmport -= 0x06;
3464                                 outb(0, tmport);
3465                                 tmport += 0x06;
3466                         }
3467                         cpu_relax();
3468                 }
3469                 tmport -= 0x08;
3470                 j = inb(tmport) & 0x0f;
3471                 if (j == 0x0f) {
3472                         goto u3p_in;
3473                 }
3474                 if (j == 0x0a) {
3475                         goto u3p_cmd;
3476                 }
3477                 if (j == 0x0e) {
3478                         goto u3p_out;
3479                 }
3480                 continue;
3481 u3p_in:
3482                 tmport = wkport + 0x14;
3483                 outb(0x09, tmport);
3484                 tmport += 0x04;
3485                 outb(0x20, tmport);
3486                 tmport += 0x07;
3487                 k = 0;
3488 u3p_in1:
3489                 j = inb(tmport);
3490                 if ((j & 0x01) != 0) {
3491                         tmport -= 0x06;
3492                         mbuf[k++] = inb(tmport);
3493                         tmport += 0x06;
3494                         goto u3p_in1;
3495                 }
3496                 if ((j & 0x80) == 0x00) {
3497                         goto u3p_in1;
3498                 }
3499                 tmport -= 0x08;
3500                 j = inb(tmport) & 0x0f;
3501                 if (j == 0x0f) {
3502                         goto u3p_in;
3503                 }
3504                 if (j == 0x0a) {
3505                         goto u3p_cmd;
3506                 }
3507                 if (j == 0x0e) {
3508                         goto u3p_out;
3509                 }
3510                 continue;
3511 u3p_cmd:
3512                 tmport = wkport + 0x10;
3513                 outb(0x30, tmport);
3514                 tmport = wkport + 0x14;
3515                 outb(0x00, tmport);
3516                 tmport += 0x04;
3517                 outb(0x08, tmport);
3518                 tmport += 0x07;
3519                 while ((inb(tmport) & 0x80) == 0x00);
3520                 tmport -= 0x08;
3521                 j = inb(tmport);
3522                 if (j != 0x16) {
3523                         if (j == 0x4e) {
3524                                 goto u3p_out;
3525                         }
3526                         continue;
3527                 }
3528                 if (mbuf[0] != 0x01) {
3529                         goto chg_wide;
3530                 }
3531                 if (mbuf[1] != 0x06) {
3532                         goto chg_wide;
3533                 }
3534                 if (mbuf[2] != 0x04) {
3535                         goto chg_wide;
3536                 }
3537                 if (mbuf[3] == 0x09) {
3538                         m = 1;
3539                         m = m << i;
3540                         dev->wide_id[c] |= m;
3541                         dev->id[c][i].devsp = 0xce;
3542 #ifdef ED_DBGP
3543                         printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3544 #endif
3545                         continue;
3546                 }
3547 chg_wide:
3548                 tmport = wkport + 0x1b;
3549                 outb(0x01, tmport);
3550                 tmport = wkport + 0x03;
3551                 outb(satn[0], tmport++);
3552                 outb(satn[1], tmport++);
3553                 outb(satn[2], tmport++);
3554                 outb(satn[3], tmport++);
3555                 outb(satn[4], tmport++);
3556                 outb(satn[5], tmport++);
3557                 tmport += 0x06;
3558                 outb(0, tmport);
3559                 tmport += 0x02;
3560                 outb(dev->id[c][i].devsp, tmport++);
3561                 outb(0, tmport++);
3562                 outb(satn[6], tmport++);
3563                 outb(satn[7], tmport++);
3564                 tmport += 0x03;
3565                 outb(satn[8], tmport);
3566                 tmport += 0x07;
3567
3568                 while ((inb(tmport) & 0x80) == 0x00)
3569                         cpu_relax();
3570                 tmport -= 0x08;
3571                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3572                         continue;
3573                 }
3574                 while (inb(tmport) != 0x8e)
3575                         cpu_relax();
3576 try_wide:
3577                 j = 0;
3578                 tmport = wkport + 0x14;
3579                 outb(0x05, tmport);
3580                 tmport += 0x04;
3581                 outb(0x20, tmport);
3582                 tmport += 0x07;
3583
3584                 while ((inb(tmport) & 0x80) == 0) {
3585                         if ((inb(tmport) & 0x01) != 0) {
3586                                 tmport -= 0x06;
3587                                 outb(wide[j++], tmport);
3588                                 tmport += 0x06;
3589                         }
3590                         cpu_relax();
3591                 }
3592                 tmport -= 0x08;
3593                 while ((inb(tmport) & 0x80) == 0x00)
3594                         cpu_relax();
3595                 j = inb(tmport) & 0x0f;
3596                 if (j == 0x0f) {
3597                         goto widep_in;
3598                 }
3599                 if (j == 0x0a) {
3600                         goto widep_cmd;
3601                 }
3602                 if (j == 0x0e) {
3603                         goto try_wide;
3604                 }
3605                 continue;
3606 widep_out:
3607                 tmport = wkport + 0x18;
3608                 outb(0x20, tmport);
3609                 tmport += 0x07;
3610                 while ((inb(tmport) & 0x80) == 0) {
3611                         if ((inb(tmport) & 0x01) != 0) {
3612                                 tmport -= 0x06;
3613                                 outb(0, tmport);
3614                                 tmport += 0x06;
3615                         }
3616                         cpu_relax();
3617                 }
3618                 tmport -= 0x08;
3619                 j = inb(tmport) & 0x0f;
3620                 if (j == 0x0f) {
3621                         goto widep_in;
3622                 }
3623                 if (j == 0x0a) {
3624                         goto widep_cmd;
3625                 }
3626                 if (j == 0x0e) {
3627                         goto widep_out;
3628                 }
3629                 continue;
3630 widep_in:
3631                 tmport = wkport + 0x14;
3632                 outb(0xff, tmport);
3633                 tmport += 0x04;
3634                 outb(0x20, tmport);
3635                 tmport += 0x07;
3636                 k = 0;
3637 widep_in1:
3638                 j = inb(tmport);
3639                 if ((j & 0x01) != 0) {
3640                         tmport -= 0x06;
3641                         mbuf[k++] = inb(tmport);
3642                         tmport += 0x06;
3643                         goto widep_in1;
3644                 }
3645                 if ((j & 0x80) == 0x00) {
3646                         goto widep_in1;
3647                 }
3648                 tmport -= 0x08;
3649                 j = inb(tmport) & 0x0f;
3650                 if (j == 0x0f) {
3651                         goto widep_in;
3652                 }
3653                 if (j == 0x0a) {
3654                         goto widep_cmd;
3655                 }
3656                 if (j == 0x0e) {
3657                         goto widep_out;
3658                 }
3659                 continue;
3660 widep_cmd:
3661                 tmport = wkport + 0x10;
3662                 outb(0x30, tmport);
3663                 tmport = wkport + 0x14;
3664                 outb(0x00, tmport);
3665                 tmport += 0x04;
3666                 outb(0x08, tmport);
3667                 tmport += 0x07;
3668                 while ((inb(tmport) & 0x80) == 0x00)
3669                         cpu_relax();
3670                 tmport -= 0x08;
3671                 j = inb(tmport);
3672                 if (j != 0x16) {
3673                         if (j == 0x4e) {
3674                                 goto widep_out;
3675                         }
3676                         continue;
3677                 }
3678                 if (mbuf[0] != 0x01) {
3679                         goto not_wide;
3680                 }
3681                 if (mbuf[1] != 0x02) {
3682                         goto not_wide;
3683                 }
3684                 if (mbuf[2] != 0x03) {
3685                         goto not_wide;
3686                 }
3687                 if (mbuf[3] != 0x01) {
3688                         goto not_wide;
3689                 }
3690                 m = 1;
3691                 m = m << i;
3692                 dev->wide_id[c] |= m;
3693 not_wide:
3694                 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) ||
3695                     ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3696                         m = 1;
3697                         m = m << i;
3698                         if ((dev->async[c] & m) != 0) {
3699                            goto set_sync;
3700                         }
3701                 }
3702                 continue;
3703 set_sync:
3704                 if (dev->sp[c][i] == 0x02) {
3705                    synu[4]=0x0c;
3706                    synuw[4]=0x0c;
3707                 } else {
3708                    if (dev->sp[c][i] >= 0x03) {
3709                       synu[4]=0x0a;
3710                       synuw[4]=0x0a;
3711                    }
3712                 }
3713                 tmport = wkport + 0x1b;
3714                 j = 0;
3715                 if ((m & dev->wide_id[c]) != 0) {
3716                         j |= 0x01;
3717                 }
3718                 outb(j, tmport);
3719                 tmport = wkport + 0x03;
3720                 outb(satn[0], tmport++);
3721                 outb(satn[1], tmport++);
3722                 outb(satn[2], tmport++);
3723                 outb(satn[3], tmport++);
3724                 outb(satn[4], tmport++);
3725                 outb(satn[5], tmport++);
3726                 tmport += 0x06;
3727                 outb(0, tmport);
3728                 tmport += 0x02;
3729                 outb(dev->id[c][i].devsp, tmport++);
3730                 outb(0, tmport++);
3731                 outb(satn[6], tmport++);
3732                 outb(satn[7], tmport++);
3733                 tmport += 0x03;
3734                 outb(satn[8], tmport);
3735                 tmport += 0x07;
3736
3737                 while ((inb(tmport) & 0x80) == 0x00)
3738                         cpu_relax();
3739                 tmport -= 0x08;
3740                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3741                         continue;
3742                 }
3743                 while (inb(tmport) != 0x8e)
3744                         cpu_relax();
3745 try_sync:
3746                 j = 0;
3747                 tmport = wkport + 0x14;
3748                 outb(0x06, tmport);
3749                 tmport += 0x04;
3750                 outb(0x20, tmport);
3751                 tmport += 0x07;
3752
3753                 while ((inb(tmport) & 0x80) == 0) {
3754                         if ((inb(tmport) & 0x01) != 0) {
3755                                 tmport -= 0x06;
3756                                 if ((m & dev->wide_id[c]) != 0) {
3757                                         if ((m & dev->ultra_map[c]) != 0) {
3758                                                 outb(synuw[j++], tmport);
3759                                         } else {
3760                                                 outb(synw[j++], tmport);
3761                                         }
3762                                 } else {
3763                                         if ((m & dev->ultra_map[c]) != 0) {
3764                                                 outb(synu[j++], tmport);
3765                                         } else {
3766                                                 outb(synn[j++], tmport);
3767                                         }
3768                                 }
3769                                 tmport += 0x06;
3770                         }
3771                 }
3772                 tmport -= 0x08;
3773                 while ((inb(tmport) & 0x80) == 0x00)
3774                         cpu_relax();
3775                 j = inb(tmport) & 0x0f;
3776                 if (j == 0x0f) {
3777                         goto phase_ins;
3778                 }
3779                 if (j == 0x0a) {
3780                         goto phase_cmds;
3781                 }
3782                 if (j == 0x0e) {
3783                         goto try_sync;
3784                 }
3785                 continue;
3786 phase_outs:
3787                 tmport = wkport + 0x18;
3788                 outb(0x20, tmport);
3789                 tmport += 0x07;
3790                 while ((inb(tmport) & 0x80) == 0x00) {
3791                         if ((inb(tmport) & 0x01) != 0x00) {
3792                                 tmport -= 0x06;
3793                                 outb(0x00, tmport);
3794                                 tmport += 0x06;
3795                         }
3796                         cpu_relax();
3797                 }
3798                 tmport -= 0x08;
3799                 j = inb(tmport);
3800                 if (j == 0x85) {
3801                         goto tar_dcons;
3802                 }
3803                 j &= 0x0f;
3804                 if (j == 0x0f) {
3805                         goto phase_ins;
3806                 }
3807                 if (j == 0x0a) {
3808                         goto phase_cmds;
3809                 }
3810                 if (j == 0x0e) {
3811                         goto phase_outs;
3812                 }
3813                 continue;
3814 phase_ins:
3815                 tmport = wkport + 0x14;
3816                 outb(0x06, tmport);
3817                 tmport += 0x04;
3818                 outb(0x20, tmport);
3819                 tmport += 0x07;
3820                 k = 0;
3821 phase_ins1:
3822                 j = inb(tmport);
3823                 if ((j & 0x01) != 0x00) {
3824                         tmport -= 0x06;
3825                         mbuf[k++] = inb(tmport);
3826                         tmport += 0x06;
3827                         goto phase_ins1;
3828                 }
3829                 if ((j & 0x80) == 0x00) {
3830                         goto phase_ins1;
3831                 }
3832                 tmport -= 0x08;
3833                 while ((inb(tmport) & 0x80) == 0x00);
3834                 j = inb(tmport);
3835                 if (j == 0x85) {
3836                         goto tar_dcons;
3837                 }
3838                 j &= 0x0f;
3839                 if (j == 0x0f) {
3840                         goto phase_ins;
3841                 }
3842                 if (j == 0x0a) {
3843                         goto phase_cmds;
3844                 }
3845                 if (j == 0x0e) {
3846                         goto phase_outs;
3847                 }
3848                 continue;
3849 phase_cmds:
3850                 tmport = wkport + 0x10;
3851                 outb(0x30, tmport);
3852 tar_dcons:
3853                 tmport = wkport + 0x14;
3854                 outb(0x00, tmport);
3855                 tmport += 0x04;
3856                 outb(0x08, tmport);
3857                 tmport += 0x07;
3858                 while ((inb(tmport) & 0x80) == 0x00)
3859                         cpu_relax();
3860                 tmport -= 0x08;
3861                 j = inb(tmport);
3862                 if (j != 0x16) {
3863                         continue;
3864                 }
3865                 if (mbuf[0] != 0x01) {
3866                         continue;
3867                 }
3868                 if (mbuf[1] != 0x03) {
3869                         continue;
3870                 }
3871                 if (mbuf[4] == 0x00) {
3872                         continue;
3873                 }
3874                 if (mbuf[3] > 0x64) {
3875                         continue;
3876                 }
3877                 if (mbuf[4] > 0x0e) {
3878                         mbuf[4] = 0x0e;
3879                 }
3880                 dev->id[c][i].devsp = mbuf[4];
3881                 if (mbuf[3] < 0x0c){
3882                         j = 0xb0;
3883                         goto set_syn_ok;
3884                 }
3885                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3886                         j = 0xa0;
3887                         goto set_syn_ok;
3888                 }
3889                 if (mbuf[3] < 0x1a) {
3890                         j = 0x20;
3891                         goto set_syn_ok;
3892                 }
3893                 if (mbuf[3] < 0x33) {
3894                         j = 0x40;
3895                         goto set_syn_ok;
3896                 }
3897                 if (mbuf[3] < 0x4c) {
3898                         j = 0x50;
3899                         goto set_syn_ok;
3900                 }
3901                 j = 0x60;
3902               set_syn_ok:
3903                 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3904 #ifdef ED_DBGP
3905                 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3906 #endif
3907         }
3908         tmport = wkport + 0x16;
3909         outb(0x80, tmport);
3910 }
3911
3912 module_init(atp870u_init);
3913 module_exit(atp870u_exit);
3914