drivers/scsi/atp870u.c

   1 /*
   2  *  Copyright (C) 1997  Wu Ching Chen
   3  *  2.1.x update (C) 1998  Krzysztof G. Baranowski
   4  *  2.5.x update (C) 2002  Red Hat
   5  *  2.6.x update (C) 2004  Red Hat
   6  *
   7  * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
   8  *
   9  * Wu Ching Chen : NULL pointer fixes  2000/06/02
  10  *                 support atp876 chip
  11  *                 enable 32 bit fifo transfer
  12  *                 support cdrom & remove device run ultra speed
  13  *                 fix disconnect bug  2000/12/21
  14  *                 support atp880 chip lvd u160 2001/05/15
  15  *                 fix prd table bug 2001/09/12 (7.1)
  16  *
  17  * atp885 support add by ACARD Hao Ping Lian 2005/01/05
  18  */
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/string.h>
  25 #include <linux/ioport.h>
  26 #include <linux/delay.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/pci.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #include <asm/system.h>
  34 #include <asm/io.h>
  35
  36 #include <scsi/scsi.h>
  37 #include <scsi/scsi_cmnd.h>
  38 #include <scsi/scsi_device.h>
  39 #include <scsi/scsi_host.h>
  40
  41 #include "atp870u.h"
  42
  43 static struct scsi_host_template atp870u_template;
  44 static void send_s870(struct atp_unit *dev,unsigned char c);
  45 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c);
  46 static void tscam_885(void);
  47
  48 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
  49 {
  50         unsigned long flags;
  51         unsigned short int tmpcip, id;
  52         unsigned char i, j, c, target_id, lun,cmdp;
  53         unsigned char *prd;
  54         struct scsi_cmnd *workreq;
  55         unsigned int workport, tmport, tmport1;
  56         unsigned long adrcnt, k;
  57 #ifdef ED_DBGP
  58         unsigned long l;
  59 #endif
  60         int errstus;
  61         struct Scsi_Host *host = dev_id;
  62         struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
  63
  64         for (c = 0; c < 2; c++) {
  65                 tmport = dev->ioport[c] + 0x1f;
  66                 j = inb(tmport);
  67                 if ((j & 0x80) != 0)
  68                 {
  69                         goto ch_sel;
  70                 }
  71                 dev->in_int[c] = 0;
  72         }
  73         return IRQ_NONE;
  74 ch_sel:
  75 #ifdef ED_DBGP
  76         printk("atp870u_intr_handle enter\n");
  77 #endif
  78         dev->in_int[c] = 1;
  79         cmdp = inb(dev->ioport[c] + 0x10);
  80         workport = dev->ioport[c];
  81         if (dev->working[c] != 0) {
  82                 if (dev->dev_id == ATP885_DEVID) {
  83                         tmport1 = workport + 0x16;
  84                         if ((inb(tmport1) & 0x80) == 0)
  85                                 outb((inb(tmport1) | 0x80), tmport1);
  86                 }
  87                 tmpcip = dev->pciport[c];
  88                 if ((inb(tmpcip) & 0x08) != 0)
  89                 {
  90                         tmpcip += 0x2;
  91                         for (k=0; k < 1000; k++) {
  92                                 if ((inb(tmpcip) & 0x08) == 0) {
  93                                         goto stop_dma;
  94                                 }
  95                                 if ((inb(tmpcip) & 0x01) == 0) {
  96                                         goto stop_dma;
  97                                 }
  98                         }
  99                 }
 100 stop_dma:
 101                 tmpcip = dev->pciport[c];
 102                 outb(0x00, tmpcip);
 103                 tmport -= 0x08;
 104
 105                 i = inb(tmport);
 106
 107                 if (dev->dev_id == ATP885_DEVID) {
 108                         tmpcip += 2;
 109                         outb(0x06, tmpcip);
 110                         tmpcip -= 2;
 111                 }
 112
 113                 tmport -= 0x02;
 114                 target_id = inb(tmport);
 115                 tmport += 0x02;
 116
 117                 /*
 118                  *      Remap wide devices onto id numbers
 119                  */
 120
 121                 if ((target_id & 0x40) != 0) {
 122                         target_id = (target_id & 0x07) | 0x08;
 123                 } else {
 124                         target_id &= 0x07;
 125                 }
 126
 127                 if ((j & 0x40) != 0) {
 128                      if (dev->last_cmd[c] == 0xff) {
 129                         dev->last_cmd[c] = target_id;
 130                      }
 131                      dev->last_cmd[c] |= 0x40;
 132                 }
 133                 if (dev->dev_id == ATP885_DEVID)
 134                         dev->r1f[c][target_id] |= j;
 135 #ifdef ED_DBGP
 136                 printk("atp870u_intr_handle status = %x\n",i);
 137 #endif
 138                 if (i == 0x85) {
 139                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 140                            dev->last_cmd[c] = 0xff;
 141                         }
 142                         if (dev->dev_id == ATP885_DEVID) {
 143                                 tmport -= 0x05;
 144                                 adrcnt = 0;
 145                                 ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 146                                 ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 147                                 ((unsigned char *) &adrcnt)[0] = inb(tmport);
 148                                 if (dev->id[c][target_id].last_len != adrcnt)
 149                                 {
 150                                         k = dev->id[c][target_id].last_len;
 151                                         k -= adrcnt;
 152                                         dev->id[c][target_id].tran_len = k;
 153                                 dev->id[c][target_id].last_len = adrcnt;
 154                                 }
 155 #ifdef ED_DBGP
 156                                 printk("tmport = %x dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",tmport,dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
 157 #endif
 158                         }
 159
 160                         /*
 161                          *      Flip wide
 162                          */
 163                         if (dev->wide_id[c] != 0) {
 164                                 tmport = workport + 0x1b;
 165                                 outb(0x01, tmport);
 166                                 while ((inb(tmport) & 0x01) != 0x01) {
 167                                         outb(0x01, tmport);
 168                                 }
 169                         }
 170                         /*
 171                          *      Issue more commands
 172                          */
 173                         spin_lock_irqsave(dev->host->host_lock, flags);
 174                         if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
 175                             (dev->in_snd[c] == 0)) {
 176 #ifdef ED_DBGP
 177                                 printk("Call sent_s870\n");
 178 #endif
 179                                 send_s870(dev,c);
 180                         }
 181                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 182                         /*
 183                          *      Done
 184                          */
 185                         dev->in_int[c] = 0;
 186 #ifdef ED_DBGP
 187                                 printk("Status 0x85 return\n");
 188 #endif
 189                         goto handled;
 190                 }
 191
 192                 if (i == 0x40) {
 193                      dev->last_cmd[c] |= 0x40;
 194                      dev->in_int[c] = 0;
 195                      goto handled;
 196                 }
 197
 198                 if (i == 0x21) {
 199                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 200                            dev->last_cmd[c] = 0xff;
 201                         }
 202                         tmport -= 0x05;
 203                         adrcnt = 0;
 204                         ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 205                         ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 206                         ((unsigned char *) &adrcnt)[0] = inb(tmport);
 207                         k = dev->id[c][target_id].last_len;
 208                         k -= adrcnt;
 209                         dev->id[c][target_id].tran_len = k;
 210                         dev->id[c][target_id].last_len = adrcnt;
 211                         tmport -= 0x04;
 212                         outb(0x41, tmport);
 213                         tmport += 0x08;
 214                         outb(0x08, tmport);
 215                         dev->in_int[c] = 0;
 216                         goto handled;
 217                 }
 218
 219                 if (dev->dev_id == ATP885_DEVID) {
 220                         if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
 221                                 if ((i == 0x4c) || (i == 0x8c))
 222                                         i=0x48;
 223                                 else
 224                                         i=0x49;
 225                         }
 226
 227                 }
 228                 if ((i == 0x80) || (i == 0x8f)) {
 229 #ifdef ED_DBGP
 230                         printk(KERN_DEBUG "Device reselect\n");
 231 #endif
 232                         lun = 0;
 233                         tmport -= 0x07;
 234                         if (cmdp == 0x44 || i==0x80) {
 235                                 tmport += 0x0d;
 236                                 lun = inb(tmport) & 0x07;
 237                         } else {
 238                                 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 239                                    dev->last_cmd[c] = 0xff;
 240                                 }
 241                                 if (cmdp == 0x41) {
 242 #ifdef ED_DBGP
 243                                         printk("cmdp = 0x41\n");
 244 #endif
 245                                         tmport += 0x02;
 246                                         adrcnt = 0;
 247                                         ((unsigned char *) &adrcnt)[2] = inb(tmport++);
 248                                         ((unsigned char *) &adrcnt)[1] = inb(tmport++);
 249                                         ((unsigned char *) &adrcnt)[0] = inb(tmport);
 250                                         k = dev->id[c][target_id].last_len;
 251                                         k -= adrcnt;
 252                                         dev->id[c][target_id].tran_len = k;
 253                                         dev->id[c][target_id].last_len = adrcnt;
 254                                         tmport += 0x04;
 255                                         outb(0x08, tmport);
 256                                         dev->in_int[c] = 0;
 257                                         goto handled;
 258                                 } else {
 259 #ifdef ED_DBGP
 260                                         printk("cmdp != 0x41\n");
 261 #endif
 262                                         outb(0x46, tmport);
 263                                         dev->id[c][target_id].dirct = 0x00;
 264                                         tmport += 0x02;
 265                                         outb(0x00, tmport++);
 266                                         outb(0x00, tmport++);
 267                                         outb(0x00, tmport++);
 268                                         tmport += 0x03;
 269                                         outb(0x08, tmport);
 270                                         dev->in_int[c] = 0;
 271                                         goto handled;
 272                                 }
 273                         }
 274                         if (dev->last_cmd[c] != 0xff) {
 275                            dev->last_cmd[c] |= 0x40;
 276                         }
 277                         if (dev->dev_id == ATP885_DEVID) {
 278                                 j = inb(dev->baseport + 0x29) & 0xfe;
 279                                 outb(j, dev->baseport + 0x29);
 280                                 tmport = workport + 0x16;
 281                         } else {
 282                                 tmport = workport + 0x10;
 283                                 outb(0x45, tmport);
 284                                 tmport += 0x06;
 285                         }
 286
 287                         target_id = inb(tmport);
 288                         /*
 289                          *      Remap wide identifiers
 290                          */
 291                         if ((target_id & 0x10) != 0) {
 292                                 target_id = (target_id & 0x07) | 0x08;
 293                         } else {
 294                                 target_id &= 0x07;
 295                         }
 296                         if (dev->dev_id == ATP885_DEVID) {
 297                                 tmport = workport + 0x10;
 298                                 outb(0x45, tmport);
 299                         }
 300                         workreq = dev->id[c][target_id].curr_req;
 301 #ifdef ED_DBGP
 302                         scmd_printk(KERN_DEBUG, workreq, "CDB");
 303                         for (l = 0; l < workreq->cmd_len; l++)
 304                                 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
 305                         printk("\n");
 306 #endif
 307
 308                         tmport = workport + 0x0f;
 309                         outb(lun, tmport);
 310                         tmport += 0x02;
 311                         outb(dev->id[c][target_id].devsp, tmport++);
 312                         adrcnt = dev->id[c][target_id].tran_len;
 313                         k = dev->id[c][target_id].last_len;
 314
 315                         outb(((unsigned char *) &k)[2], tmport++);
 316                         outb(((unsigned char *) &k)[1], tmport++);
 317                         outb(((unsigned char *) &k)[0], tmport++);
 318 #ifdef ED_DBGP
 319                         printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, inb(tmport-1), inb(tmport-2), inb(tmport-3));
 320 #endif
 321                         /* Remap wide */
 322                         j = target_id;
 323                         if (target_id > 7) {
 324                                 j = (j & 0x07) | 0x40;
 325                         }
 326                         /* Add direction */
 327                         j |= dev->id[c][target_id].dirct;
 328                         outb(j, tmport++);
 329                         outb(0x80,tmport);
 330
 331                         /* enable 32 bit fifo transfer */
 332                         if (dev->dev_id == ATP885_DEVID) {
 333                                 tmpcip = dev->pciport[c] + 1;
 334                                 i=inb(tmpcip) & 0xf3;
 335                                 //j=workreq->cmnd[0];
 336                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 337                                    i |= 0x0c;
 338                                 }
 339                                 outb(i,tmpcip);
 340                         } else if ((dev->dev_id == ATP880_DEVID1) ||
 341                                    (dev->dev_id == ATP880_DEVID2) ) {
 342                                 tmport = workport - 0x05;
 343                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 344                                         outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport);
 345                                 } else {
 346                                         outb((unsigned char) (inb(tmport) & 0x3f), tmport);
 347                                 }
 348                         } else {
 349                                 tmport = workport + 0x3a;
 350                                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 351                                         outb((unsigned char) ((inb(tmport) & 0xf3) | 0x08), tmport);
 352                                 } else {
 353                                         outb((unsigned char) (inb(tmport) & 0xf3), tmport);
 354                                 }
 355                         }
 356                         tmport = workport + 0x1b;
 357                         j = 0;
 358                         id = 1;
 359                         id = id << target_id;
 360                         /*
 361                          *      Is this a wide device
 362                          */
 363                         if ((id & dev->wide_id[c]) != 0) {
 364                                 j |= 0x01;
 365                         }
 366                         outb(j, tmport);
 367                         while ((inb(tmport) & 0x01) != j) {
 368                                 outb(j,tmport);
 369                         }
 370                         if (dev->id[c][target_id].last_len == 0) {
 371                                 tmport = workport + 0x18;
 372                                 outb(0x08, tmport);
 373                                 dev->in_int[c] = 0;
 374 #ifdef ED_DBGP
 375                                 printk("dev->id[c][target_id].last_len = 0\n");
 376 #endif
 377                                 goto handled;
 378                         }
 379 #ifdef ED_DBGP
 380                         printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
 381 #endif
 382                         prd = dev->id[c][target_id].prd_pos;
 383                         while (adrcnt != 0) {
 384                                 id = ((unsigned short int *)prd)[2];
 385                                 if (id == 0) {
 386                                         k = 0x10000;
 387                                 } else {
 388                                         k = id;
 389                                 }
 390                                 if (k > adrcnt) {
 391                                         ((unsigned short int *)prd)[2] = (unsigned short int)
 392                                             (k - adrcnt);
 393                                         ((unsigned long *)prd)[0] += adrcnt;
 394                                         adrcnt = 0;
 395                                         dev->id[c][target_id].prd_pos = prd;
 396                                 } else {
 397                                         adrcnt -= k;
 398                                         dev->id[c][target_id].prdaddr += 0x08;
 399                                         prd += 0x08;
 400                                         if (adrcnt == 0) {
 401                                                 dev->id[c][target_id].prd_pos = prd;
 402                                         }
 403                                 }
 404                         }
 405                         tmpcip = dev->pciport[c] + 0x04;
 406                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 407 #ifdef ED_DBGP
 408                         printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
 409 #endif
 410                         if (dev->dev_id == ATP885_DEVID) {
 411                                 tmpcip -= 0x04;
 412                         } else {
 413                                 tmpcip -= 0x02;
 414                                 outb(0x06, tmpcip);
 415                                 outb(0x00, tmpcip);
 416                                 tmpcip -= 0x02;
 417                         }
 418                         tmport = workport + 0x18;
 419                         /*
 420                          *      Check transfer direction
 421                          */
 422                         if (dev->id[c][target_id].dirct != 0) {
 423                                 outb(0x08, tmport);
 424                                 outb(0x01, tmpcip);
 425                                 dev->in_int[c] = 0;
 426 #ifdef ED_DBGP
 427                                 printk("status 0x80 return dirct != 0\n");
 428 #endif
 429                                 goto handled;
 430                         }
 431                         outb(0x08, tmport);
 432                         outb(0x09, tmpcip);
 433                         dev->in_int[c] = 0;
 434 #ifdef ED_DBGP
 435                         printk("status 0x80 return dirct = 0\n");
 436 #endif
 437                         goto handled;
 438                 }
 439
 440                 /*
 441                  *      Current scsi request on this target
 442                  */
 443
 444                 workreq = dev->id[c][target_id].curr_req;
 445
 446                 if (i == 0x42) {
 447                         if ((dev->last_cmd[c] & 0xf0) != 0x40)
 448                         {
 449                            dev->last_cmd[c] = 0xff;
 450                         }
 451                         errstus = 0x02;
 452                         workreq->result = errstus;
 453                         goto go_42;
 454                 }
 455                 if (i == 0x16) {
 456                         if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 457                            dev->last_cmd[c] = 0xff;
 458                         }
 459                         errstus = 0;
 460                         tmport -= 0x08;
 461                         errstus = inb(tmport);
 462                         if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
 463                            printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
 464                            errstus = 0x02;
 465                         }
 466                         workreq->result = errstus;
 467 go_42:
 468                         if (dev->dev_id == ATP885_DEVID) {
 469                                 j = inb(dev->baseport + 0x29) | 0x01;
 470                                 outb(j, dev->baseport + 0x29);
 471                         }
 472                         /*
 473                          *      Complete the command
 474                          */
 475                         scsi_dma_unmap(workreq);
 476
 477                         spin_lock_irqsave(dev->host->host_lock, flags);
 478                         (*workreq->scsi_done) (workreq);
 479 #ifdef ED_DBGP
 480                            printk("workreq->scsi_done\n");
 481 #endif
 482                         /*
 483                          *      Clear it off the queue
 484                          */
 485                         dev->id[c][target_id].curr_req = NULL;
 486                         dev->working[c]--;
 487                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 488                         /*
 489                          *      Take it back wide
 490                          */
 491                         if (dev->wide_id[c] != 0) {
 492                                 tmport = workport + 0x1b;
 493                                 outb(0x01, tmport);
 494                                 while ((inb(tmport) & 0x01) != 0x01) {
 495                                         outb(0x01, tmport);
 496                                 }
 497                         }
 498                         /*
 499                          *      If there is stuff to send and nothing going then send it
 500                          */
 501                         spin_lock_irqsave(dev->host->host_lock, flags);
 502                         if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
 503                             (dev->in_snd[c] == 0)) {
 504 #ifdef ED_DBGP
 505                            printk("Call sent_s870(scsi_done)\n");
 506 #endif
 507                            send_s870(dev,c);
 508                         }
 509                         spin_unlock_irqrestore(dev->host->host_lock, flags);
 510                         dev->in_int[c] = 0;
 511                         goto handled;
 512                 }
 513                 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
 514                    dev->last_cmd[c] = 0xff;
 515                 }
 516                 if (i == 0x4f) {
 517                         i = 0x89;
 518                 }
 519                 i &= 0x0f;
 520                 if (i == 0x09) {
 521                         tmpcip += 4;
 522                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 523                         tmpcip = tmpcip - 2;
 524                         outb(0x06, tmpcip);
 525                         outb(0x00, tmpcip);
 526                         tmpcip = tmpcip - 2;
 527                         tmport = workport + 0x10;
 528                         outb(0x41, tmport);
 529                         if (dev->dev_id == ATP885_DEVID) {
 530                                 tmport += 2;
 531                                 k = dev->id[c][target_id].last_len;
 532                                 outb((unsigned char) (((unsigned char *) (&k))[2]), tmport++);
 533                                 outb((unsigned char) (((unsigned char *) (&k))[1]), tmport++);
 534                                 outb((unsigned char) (((unsigned char *) (&k))[0]), tmport);
 535                                 dev->id[c][target_id].dirct = 0x00;
 536                                 tmport += 0x04;
 537                         } else {
 538                                 dev->id[c][target_id].dirct = 0x00;
 539                                 tmport += 0x08;
 540                         }
 541                         outb(0x08, tmport);
 542                         outb(0x09, tmpcip);
 543                         dev->in_int[c] = 0;
 544                         goto handled;
 545                 }
 546                 if (i == 0x08) {
 547                         tmpcip += 4;
 548                         outl(dev->id[c][target_id].prdaddr, tmpcip);
 549                         tmpcip = tmpcip - 2;
 550                         outb(0x06, tmpcip);
 551                         outb(0x00, tmpcip);
 552                         tmpcip = tmpcip - 2;
 553                         tmport = workport + 0x10;
 554                         outb(0x41, tmport);
 555                         if (dev->dev_id == ATP885_DEVID) {
 556                                 tmport += 2;
 557                                 k = dev->id[c][target_id].last_len;
 558                                 outb((unsigned char) (((unsigned char *) (&k))[2]), tmport++);
 559                                 outb((unsigned char) (((unsigned char *) (&k))[1]), tmport++);
 560                                 outb((unsigned char) (((unsigned char *) (&k))[0]), tmport++);
 561                         } else {
 562                                 tmport += 5;
 563                         }
 564                         outb((unsigned char) (inb(tmport) | 0x20), tmport);
 565                         dev->id[c][target_id].dirct = 0x20;
 566                         tmport += 0x03;
 567                         outb(0x08, tmport);
 568                         outb(0x01, tmpcip);
 569                         dev->in_int[c] = 0;
 570                         goto handled;
 571                 }
 572                 tmport -= 0x07;
 573                 if (i == 0x0a) {
 574                         outb(0x30, tmport);
 575                 } else {
 576                         outb(0x46, tmport);
 577                 }
 578                 dev->id[c][target_id].dirct = 0x00;
 579                 tmport += 0x02;
 580                 outb(0x00, tmport++);
 581                 outb(0x00, tmport++);
 582                 outb(0x00, tmport++);
 583                 tmport += 0x03;
 584                 outb(0x08, tmport);
 585                 dev->in_int[c] = 0;
 586                 goto handled;
 587         } else {
 588 //              tmport = workport + 0x17;
 589 //              inb(tmport);
 590 //              dev->working[c] = 0;
 591                 dev->in_int[c] = 0;
 592                 goto handled;
 593         }
 594
 595 handled:
 596 #ifdef ED_DBGP
 597         printk("atp870u_intr_handle exit\n");
 598 #endif
 599         return IRQ_HANDLED;
 600 }
 601 /**
 602  *      atp870u_queuecommand    -       Queue SCSI command
 603  *      @req_p: request block
 604  *      @done: completion function
 605  *
 606  *      Queue a command to the ATP queue. Called with the host lock held.
 607  */
 608 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
 609                          void (*done) (struct scsi_cmnd *))
 610 {
 611         unsigned char c;
 612         unsigned int tmport,m;
 613         struct atp_unit *dev;
 614         struct Scsi_Host *host;
 615
 616         c = scmd_channel(req_p);
 617         req_p->sense_buffer[0]=0;
 618         scsi_set_resid(req_p, 0);
 619         if (scmd_channel(req_p) > 1) {
 620                 req_p->result = 0x00040000;
 621                 done(req_p);
 622 #ifdef ED_DBGP
 623                 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
 624 #endif
 625                 return 0;
 626         }
 627
 628         host = req_p->device->host;
 629         dev = (struct atp_unit *)&host->hostdata;
 630
 631
 632
 633         m = 1;
 634         m = m << scmd_id(req_p);
 635
 636         /*
 637          *      Fake a timeout for missing targets
 638          */
 639
 640         if ((m & dev->active_id[c]) == 0) {
 641                 req_p->result = 0x00040000;
 642                 done(req_p);
 643                 return 0;
 644         }
 645
 646         if (done) {
 647                 req_p->scsi_done = done;
 648         } else {
 649 #ifdef ED_DBGP
 650                 printk( "atp870u_queuecommand: done can't be NULL\n");
 651 #endif
 652                 req_p->result = 0;
 653                 done(req_p);
 654                 return 0;
 655         }
 656
 657         /*
 658          *      Count new command
 659          */
 660         dev->quend[c]++;
 661         if (dev->quend[c] >= qcnt) {
 662                 dev->quend[c] = 0;
 663         }
 664
 665         /*
 666          *      Check queue state
 667          */
 668         if (dev->quhd[c] == dev->quend[c]) {
 669                 if (dev->quend[c] == 0) {
 670                         dev->quend[c] = qcnt;
 671                 }
 672 #ifdef ED_DBGP
 673                 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
 674 #endif
 675                 dev->quend[c]--;
 676                 req_p->result = 0x00020000;
 677                 done(req_p);
 678                 return 0;
 679         }
 680         dev->quereq[c][dev->quend[c]] = req_p;
 681         tmport = dev->ioport[c] + 0x1c;
 682 #ifdef ED_DBGP
 683         printk("dev->ioport[c] = %x inb(tmport) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],inb(tmport),c,dev->in_int[c],c,dev->in_snd[c]);
 684 #endif
 685         if ((inb(tmport) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
 686 #ifdef ED_DBGP
 687                 printk("Call sent_s870(atp870u_queuecommand)\n");
 688 #endif
 689                 send_s870(dev,c);
 690         }
 691 #ifdef ED_DBGP
 692         printk("atp870u_queuecommand : exit\n");
 693 #endif
 694         return 0;
 695 }
 696
 697 static DEF_SCSI_QCMD(atp870u_queuecommand)
 698
 699 /**
 700  *      send_s870       -       send a command to the controller
 701  *      @host: host
 702  *
 703  *      On entry there is work queued to be done. We move some of that work to the
 704  *      controller itself.
 705  *
 706  *      Caller holds the host lock.
 707  */
 708 static void send_s870(struct atp_unit *dev,unsigned char c)
 709 {
 710         unsigned int tmport;
 711         struct scsi_cmnd *workreq;
 712         unsigned int i;//,k;
 713         unsigned char  j, target_id;
 714         unsigned char *prd;
 715         unsigned short int tmpcip, w;
 716         unsigned long l, bttl = 0;
 717         unsigned int workport;
 718         unsigned long  sg_count;
 719
 720         if (dev->in_snd[c] != 0) {
 721 #ifdef ED_DBGP
 722                 printk("cmnd in_snd\n");
 723 #endif
 724                 return;
 725         }
 726 #ifdef ED_DBGP
 727         printk("Sent_s870 enter\n");
 728 #endif
 729         dev->in_snd[c] = 1;
 730         if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
 731                 dev->last_cmd[c] &= 0x0f;
 732                 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
 733                 if (workreq != NULL) {  /* check NULL pointer */
 734                    goto cmd_subp;
 735                 }
 736                 dev->last_cmd[c] = 0xff;
 737                 if (dev->quhd[c] == dev->quend[c]) {
 738                         dev->in_snd[c] = 0;
 739                         return ;
 740                 }
 741         }
 742         if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
 743                 dev->in_snd[c] = 0;
 744                 return ;
 745         }
 746         dev->working[c]++;
 747         j = dev->quhd[c];
 748         dev->quhd[c]++;
 749         if (dev->quhd[c] >= qcnt) {
 750                 dev->quhd[c] = 0;
 751         }
 752         workreq = dev->quereq[c][dev->quhd[c]];
 753         if (dev->id[c][scmd_id(workreq)].curr_req == NULL) {
 754                 dev->id[c][scmd_id(workreq)].curr_req = workreq;
 755                 dev->last_cmd[c] = scmd_id(workreq);
 756                 goto cmd_subp;
 757         }
 758         dev->quhd[c] = j;
 759         dev->working[c]--;
 760         dev->in_snd[c] = 0;
 761         return;
 762 cmd_subp:
 763         workport = dev->ioport[c];
 764         tmport = workport + 0x1f;
 765         if ((inb(tmport) & 0xb0) != 0) {
 766                 goto abortsnd;
 767         }
 768         tmport = workport + 0x1c;
 769         if (inb(tmport) == 0) {
 770                 goto oktosend;
 771         }
 772 abortsnd:
 773 #ifdef ED_DBGP
 774         printk("Abort to Send\n");
 775 #endif
 776         dev->last_cmd[c] |= 0x40;
 777         dev->in_snd[c] = 0;
 778         return;
 779 oktosend:
 780 #ifdef ED_DBGP
 781         printk("OK to Send\n");
 782         scmd_printk(KERN_DEBUG, workreq, "CDB");
 783         for(i=0;i<workreq->cmd_len;i++) {
 784                 printk(" %x",workreq->cmnd[i]);
 785         }
 786         printk("\n");
 787 #endif
 788         l = scsi_bufflen(workreq);
 789
 790         if (dev->dev_id == ATP885_DEVID) {
 791                 j = inb(dev->baseport + 0x29) & 0xfe;
 792                 outb(j, dev->baseport + 0x29);
 793                 dev->r1f[c][scmd_id(workreq)] = 0;
 794         }
 795
 796         if (workreq->cmnd[0] == READ_CAPACITY) {
 797                 if (l > 8)
 798                         l = 8;
 799         }
 800         if (workreq->cmnd[0] == 0x00) {
 801                 l = 0;
 802         }
 803
 804         tmport = workport + 0x1b;
 805         j = 0;
 806         target_id = scmd_id(workreq);
 807
 808         /*
 809          *      Wide ?
 810          */
 811         w = 1;
 812         w = w << target_id;
 813         if ((w & dev->wide_id[c]) != 0) {
 814                 j |= 0x01;
 815         }
 816         outb(j, tmport);
 817         while ((inb(tmport) & 0x01) != j) {
 818                 outb(j,tmport);
 819 #ifdef ED_DBGP
 820                 printk("send_s870 while loop 1\n");
 821 #endif
 822         }
 823         /*
 824          *      Write the command
 825          */
 826
 827         tmport = workport;
 828         outb(workreq->cmd_len, tmport++);
 829         outb(0x2c, tmport++);
 830         if (dev->dev_id == ATP885_DEVID) {
 831                 outb(0x7f, tmport++);
 832         } else {
 833                 outb(0xcf, tmport++);
 834         }
 835         for (i = 0; i < workreq->cmd_len; i++) {
 836                 outb(workreq->cmnd[i], tmport++);
 837         }
 838         tmport = workport + 0x0f;
 839         outb(workreq->device->lun, tmport);
 840         tmport += 0x02;
 841         /*
 842          *      Write the target
 843          */
 844         outb(dev->id[c][target_id].devsp, tmport++);
 845 #ifdef ED_DBGP
 846         printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
 847 #endif
 848
 849         sg_count = scsi_dma_map(workreq);
 850         /*
 851          *      Write transfer size
 852          */
 853         outb((unsigned char) (((unsigned char *) (&l))[2]), tmport++);
 854         outb((unsigned char) (((unsigned char *) (&l))[1]), tmport++);
 855         outb((unsigned char) (((unsigned char *) (&l))[0]), tmport++);
 856         j = target_id;
 857         dev->id[c][j].last_len = l;
 858         dev->id[c][j].tran_len = 0;
 859 #ifdef ED_DBGP
 860         printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
 861 #endif
 862         /*
 863          *      Flip the wide bits
 864          */
 865         if ((j & 0x08) != 0) {
 866                 j = (j & 0x07) | 0x40;
 867         }
 868         /*
 869          *      Check transfer direction
 870          */
 871         if (workreq->sc_data_direction == DMA_TO_DEVICE) {
 872                 outb((unsigned char) (j | 0x20), tmport++);
 873         } else {
 874                 outb(j, tmport++);
 875         }
 876         outb((unsigned char) (inb(tmport) | 0x80), tmport);
 877         outb(0x80, tmport);
 878         tmport = workport + 0x1c;
 879         dev->id[c][target_id].dirct = 0;
 880         if (l == 0) {
 881                 if (inb(tmport) == 0) {
 882                         tmport = workport + 0x18;
 883 #ifdef ED_DBGP
 884                         printk("change SCSI_CMD_REG 0x08\n");
 885 #endif
 886                         outb(0x08, tmport);
 887                 } else {
 888                         dev->last_cmd[c] |= 0x40;
 889                 }
 890                 dev->in_snd[c] = 0;
 891                 return;
 892         }
 893         tmpcip = dev->pciport[c];
 894         prd = dev->id[c][target_id].prd_table;
 895         dev->id[c][target_id].prd_pos = prd;
 896
 897         /*
 898          *      Now write the request list. Either as scatter/gather or as
 899          *      a linear chain.
 900          */
 901
 902         if (l) {
 903                 struct scatterlist *sgpnt;
 904                 i = 0;
 905                 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
 906                         bttl = sg_dma_address(sgpnt);
 907                         l=sg_dma_len(sgpnt);
 908 #ifdef ED_DBGP
 909                         printk("1. bttl %x, l %x\n",bttl, l);
 910 #endif
 911                         while (l > 0x10000) {
 912                                 (((u16 *) (prd))[i + 3]) = 0x0000;
 913                                 (((u16 *) (prd))[i + 2]) = 0x0000;
 914                                 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
 915                                 l -= 0x10000;
 916                                 bttl += 0x10000;
 917                                 i += 0x04;
 918                         }
 919                         (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
 920                         (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
 921                         (((u16 *) (prd))[i + 3]) = 0;
 922                         i += 0x04;
 923                 }
 924                 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
 925 #ifdef ED_DBGP
 926                 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
 927                 printk("2. bttl %x, l %x\n",bttl, l);
 928 #endif
 929         }
 930         tmpcip += 4;
 931 #ifdef ED_DBGP
 932         printk("send_s870: prdaddr_2 0x%8x tmpcip %x target_id %d\n", dev->id[c][target_id].prdaddr,tmpcip,target_id);
 933 #endif
 934         dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
 935         outl(dev->id[c][target_id].prdaddr, tmpcip);
 936         tmpcip = tmpcip - 2;
 937         outb(0x06, tmpcip);
 938         outb(0x00, tmpcip);
 939         if (dev->dev_id == ATP885_DEVID) {
 940                 tmpcip--;
 941                 j=inb(tmpcip) & 0xf3;
 942                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
 943                 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 944                         j |= 0x0c;
 945                 }
 946                 outb(j,tmpcip);
 947                 tmpcip--;
 948         } else if ((dev->dev_id == ATP880_DEVID1) ||
 949                    (dev->dev_id == ATP880_DEVID2)) {
 950                 tmpcip =tmpcip -2;
 951                 tmport = workport - 0x05;
 952                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 953                         outb((unsigned char) ((inb(tmport) & 0x3f) | 0xc0), tmport);
 954                 } else {
 955                         outb((unsigned char) (inb(tmport) & 0x3f), tmport);
 956                 }
 957         } else {
 958                 tmpcip =tmpcip -2;
 959                 tmport = workport + 0x3a;
 960                 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
 961                         outb((inb(tmport) & 0xf3) | 0x08, tmport);
 962                 } else {
 963                         outb(inb(tmport) & 0xf3, tmport);
 964                 }
 965         }
 966         tmport = workport + 0x1c;
 967
 968         if(workreq->sc_data_direction == DMA_TO_DEVICE) {
 969                 dev->id[c][target_id].dirct = 0x20;
 970                 if (inb(tmport) == 0) {
 971                         tmport = workport + 0x18;
 972                         outb(0x08, tmport);
 973                         outb(0x01, tmpcip);
 974 #ifdef ED_DBGP
 975                 printk( "start DMA(to target)\n");
 976 #endif
 977                 } else {
 978                         dev->last_cmd[c] |= 0x40;
 979                 }
 980                 dev->in_snd[c] = 0;
 981                 return;
 982         }
 983         if (inb(tmport) == 0) {
 984                 tmport = workport + 0x18;
 985                 outb(0x08, tmport);
 986                 outb(0x09, tmpcip);
 987 #ifdef ED_DBGP
 988                 printk( "start DMA(to host)\n");
 989 #endif
 990         } else {
 991                 dev->last_cmd[c] |= 0x40;
 992         }
 993         dev->in_snd[c] = 0;
 994         return;
 995
 996 }
 997
 998 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
 999 {
1000         unsigned int tmport;
1001         unsigned short int i, k;
1002         unsigned char j;
1003
1004         tmport = dev->ioport[0] + 0x1c;
1005         outw(*val, tmport);
1006 FUN_D7:
1007         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns)  */
1008                 k = inw(tmport);
1009                 j = (unsigned char) (k >> 8);
1010                 if ((k & 0x8000) != 0) {        /* DB7 all release?    */
1011                         goto FUN_D7;
1012                 }
1013         }
1014         *val |= 0x4000;         /* assert DB6           */
1015         outw(*val, tmport);
1016         *val &= 0xdfff;         /* assert DB5           */
1017         outw(*val, tmport);
1018 FUN_D5:
1019         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns) */
1020                 if ((inw(tmport) & 0x2000) != 0) {      /* DB5 all release?       */
1021                         goto FUN_D5;
1022                 }
1023         }
1024         *val |= 0x8000;         /* no DB4-0, assert DB7    */
1025         *val &= 0xe0ff;
1026         outw(*val, tmport);
1027         *val &= 0xbfff;         /* release DB6             */
1028         outw(*val, tmport);
1029 FUN_D6:
1030         for (i = 0; i < 10; i++) {      /* stable >= bus settle delay(400 ns)  */
1031                 if ((inw(tmport) & 0x4000) != 0) {      /* DB6 all release?  */
1032                         goto FUN_D6;
1033                 }
1034         }
1035
1036         return j;
1037 }
1038
1039 static void tscam(struct Scsi_Host *host)
1040 {
1041
1042         unsigned int tmport;
1043         unsigned char i, j, k;
1044         unsigned long n;
1045         unsigned short int m, assignid_map, val;
1046         unsigned char mbuf[33], quintet[2];
1047         struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
1048         static unsigned char g2q_tab[8] = {
1049                 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
1050         };
1051
1052 /*  I can't believe we need this before we've even done anything.  Remove it
1053  *  and see if anyone bitches.
1054         for (i = 0; i < 0x10; i++) {
1055                 udelay(0xffff);
1056         }
1057  */
1058
1059         tmport = dev->ioport[0] + 1;
1060         outb(0x08, tmport++);
1061         outb(0x7f, tmport);
1062         tmport = dev->ioport[0] + 0x11;
1063         outb(0x20, tmport);
1064
1065         if ((dev->scam_on & 0x40) == 0) {
1066                 return;
1067         }
1068         m = 1;
1069         m <<= dev->host_id[0];
1070         j = 16;
1071         if (dev->chip_ver < 4) {
1072                 m |= 0xff00;
1073                 j = 8;
1074         }
1075         assignid_map = m;
1076         tmport = dev->ioport[0] + 0x02;
1077         outb(0x02, tmport++);   /* 2*2=4ms,3EH 2/32*3E=3.9ms */
1078         outb(0, tmport++);
1079         outb(0, tmport++);
1080         outb(0, tmport++);
1081         outb(0, tmport++);
1082         outb(0, tmport++);
1083         outb(0, tmport++);
1084
1085         for (i = 0; i < j; i++) {
1086                 m = 1;
1087                 m = m << i;
1088                 if ((m & assignid_map) != 0) {
1089                         continue;
1090                 }
1091                 tmport = dev->ioport[0] + 0x0f;
1092                 outb(0, tmport++);
1093                 tmport += 0x02;
1094                 outb(0, tmport++);
1095                 outb(0, tmport++);
1096                 outb(0, tmport++);
1097                 if (i > 7) {
1098                         k = (i & 0x07) | 0x40;
1099                 } else {
1100                         k = i;
1101                 }
1102                 outb(k, tmport++);
1103                 tmport = dev->ioport[0] + 0x1b;
1104                 if (dev->chip_ver == 4) {
1105                         outb(0x01, tmport);
1106                 } else {
1107                         outb(0x00, tmport);
1108                 }
1109 wait_rdyok:
1110                 tmport = dev->ioport[0] + 0x18;
1111                 outb(0x09, tmport);
1112                 tmport += 0x07;
1113
1114                 while ((inb(tmport) & 0x80) == 0x00)
1115                         cpu_relax();
1116                 tmport -= 0x08;
1117                 k = inb(tmport);
1118                 if (k != 0x16) {
1119                         if ((k == 0x85) || (k == 0x42)) {
1120                                 continue;
1121                         }
1122                         tmport = dev->ioport[0] + 0x10;
1123                         outb(0x41, tmport);
1124                         goto wait_rdyok;
1125                 }
1126                 assignid_map |= m;
1127
1128         }
1129         tmport = dev->ioport[0] + 0x02;
1130         outb(0x7f, tmport);
1131         tmport = dev->ioport[0] + 0x1b;
1132         outb(0x02, tmport);
1133
1134         outb(0, 0x80);
1135
1136         val = 0x0080;           /* bsy  */
1137         tmport = dev->ioport[0] + 0x1c;
1138         outw(val, tmport);
1139         val |= 0x0040;          /* sel  */
1140         outw(val, tmport);
1141         val |= 0x0004;          /* msg  */
1142         outw(val, tmport);
1143         inb(0x80);              /* 2 deskew delay(45ns*2=90ns) */
1144         val &= 0x007f;          /* no bsy  */
1145         outw(val, tmport);
1146         mdelay(128);
1147         val &= 0x00fb;          /* after 1ms no msg */
1148         outw(val, tmport);
1149 wait_nomsg:
1150         if ((inb(tmport) & 0x04) != 0) {
1151                 goto wait_nomsg;
1152         }
1153         outb(1, 0x80);
1154         udelay(100);
1155         for (n = 0; n < 0x30000; n++) {
1156                 if ((inb(tmport) & 0x80) != 0) {        /* bsy ? */
1157                         goto wait_io;
1158                 }
1159         }
1160         goto TCM_SYNC;
1161 wait_io:
1162         for (n = 0; n < 0x30000; n++) {
1163                 if ((inb(tmport) & 0x81) == 0x0081) {
1164                         goto wait_io1;
1165                 }
1166         }
1167         goto TCM_SYNC;
1168 wait_io1:
1169         inb(0x80);
1170         val |= 0x8003;          /* io,cd,db7  */
1171         outw(val, tmport);
1172         inb(0x80);
1173         val &= 0x00bf;          /* no sel     */
1174         outw(val, tmport);
1175         outb(2, 0x80);
1176 TCM_SYNC:
1177         /*
1178          * The funny division into multiple delays is to accomodate
1179          * arches like ARM where udelay() multiplies its argument by
1180          * a large number to initialize a loop counter.  To avoid
1181          * overflow, the maximum supported udelay is 2000 microseconds.
1182          *
1183          * XXX it would be more polite to find a way to use msleep()
1184          */
1185         mdelay(2);
1186         udelay(48);
1187         if ((inb(tmport) & 0x80) == 0x00) {     /* bsy ? */
1188                 outw(0, tmport--);
1189                 outb(0, tmport);
1190                 tmport = dev->ioport[0] + 0x15;
1191                 outb(0, tmport);
1192                 tmport += 0x03;
1193                 outb(0x09, tmport);
1194                 tmport += 0x07;
1195                 while ((inb(tmport) & 0x80) == 0)
1196                         cpu_relax();
1197                 tmport -= 0x08;
1198                 inb(tmport);
1199                 return;
1200         }
1201         val &= 0x00ff;          /* synchronization  */
1202         val |= 0x3f00;
1203         fun_scam(dev, &val);
1204         outb(3, 0x80);
1205         val &= 0x00ff;          /* isolation        */
1206         val |= 0x2000;
1207         fun_scam(dev, &val);
1208         outb(4, 0x80);
1209         i = 8;
1210         j = 0;
1211 TCM_ID:
1212         if ((inw(tmport) & 0x2000) == 0) {
1213                 goto TCM_ID;
1214         }
1215         outb(5, 0x80);
1216         val &= 0x00ff;          /* get ID_STRING */
1217         val |= 0x2000;
1218         k = fun_scam(dev, &val);
1219         if ((k & 0x03) == 0) {
1220                 goto TCM_5;
1221         }
1222         mbuf[j] <<= 0x01;
1223         mbuf[j] &= 0xfe;
1224         if ((k & 0x02) != 0) {
1225                 mbuf[j] |= 0x01;
1226         }
1227         i--;
1228         if (i > 0) {
1229                 goto TCM_ID;
1230         }
1231         j++;
1232         i = 8;
1233         goto TCM_ID;
1234
1235 TCM_5:                  /* isolation complete..  */
1236 /*    mbuf[32]=0;
1237         printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1238         i = 15;
1239         j = mbuf[0];
1240         if ((j & 0x20) != 0) {  /* bit5=1:ID up to 7      */
1241                 i = 7;
1242         }
1243         if ((j & 0x06) == 0) {  /* IDvalid?             */
1244                 goto G2Q5;
1245         }
1246         k = mbuf[1];
1247 small_id:
1248         m = 1;
1249         m <<= k;
1250         if ((m & assignid_map) == 0) {
1251                 goto G2Q_QUIN;
1252         }
1253         if (k > 0) {
1254                 k--;
1255                 goto small_id;
1256         }
1257 G2Q5:                   /* srch from max acceptable ID#  */
1258         k = i;                  /* max acceptable ID#            */
1259 G2Q_LP:
1260         m = 1;
1261         m <<= k;
1262         if ((m & assignid_map) == 0) {
1263                 goto G2Q_QUIN;
1264         }
1265         if (k > 0) {
1266                 k--;
1267                 goto G2Q_LP;
1268         }
1269 G2Q_QUIN:               /* k=binID#,       */
1270         assignid_map |= m;
1271         if (k < 8) {
1272                 quintet[0] = 0x38;      /* 1st dft ID<8    */
1273         } else {
1274                 quintet[0] = 0x31;      /* 1st  ID>=8      */
1275         }
1276         k &= 0x07;
1277         quintet[1] = g2q_tab[k];
1278
1279         val &= 0x00ff;          /* AssignID 1stQuintet,AH=001xxxxx  */
1280         m = quintet[0] << 8;
1281         val |= m;
1282         fun_scam(dev, &val);
1283         val &= 0x00ff;          /* AssignID 2ndQuintet,AH=001xxxxx */
1284         m = quintet[1] << 8;
1285         val |= m;
1286         fun_scam(dev, &val);
1287
1288         goto TCM_SYNC;
1289
1290 }
1291
1292 static void is870(struct atp_unit *dev, unsigned int wkport)
1293 {
1294         unsigned int tmport;
1295         unsigned char i, j, k, rmb, n;
1296         unsigned short int m;
1297         static unsigned char mbuf[512];
1298         static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1299         static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1300         static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1301         static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1302         static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1303         static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1304
1305         tmport = wkport + 0x3a;
1306         outb((unsigned char) (inb(tmport) | 0x10), tmport);
1307
1308         for (i = 0; i < 16; i++) {
1309                 if ((dev->chip_ver != 4) && (i > 7)) {
1310                         break;
1311                 }
1312                 m = 1;
1313                 m = m << i;
1314                 if ((m & dev->active_id[0]) != 0) {
1315                         continue;
1316                 }
1317                 if (i == dev->host_id[0]) {
1318                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[0]);
1319                         continue;
1320                 }
1321                 tmport = wkport + 0x1b;
1322                 if (dev->chip_ver == 4) {
1323                         outb(0x01, tmport);
1324                 } else {
1325                         outb(0x00, tmport);
1326                 }
1327                 tmport = wkport + 1;
1328                 outb(0x08, tmport++);
1329                 outb(0x7f, tmport++);
1330                 outb(satn[0], tmport++);
1331                 outb(satn[1], tmport++);
1332                 outb(satn[2], tmport++);
1333                 outb(satn[3], tmport++);
1334                 outb(satn[4], tmport++);
1335                 outb(satn[5], tmport++);
1336                 tmport += 0x06;
1337                 outb(0, tmport);
1338                 tmport += 0x02;
1339                 outb(dev->id[0][i].devsp, tmport++);
1340                 outb(0, tmport++);
1341                 outb(satn[6], tmport++);
1342                 outb(satn[7], tmport++);
1343                 j = i;
1344                 if ((j & 0x08) != 0) {
1345                         j = (j & 0x07) | 0x40;
1346                 }
1347                 outb(j, tmport);
1348                 tmport += 0x03;
1349                 outb(satn[8], tmport);
1350                 tmport += 0x07;
1351
1352                 while ((inb(tmport) & 0x80) == 0x00)
1353                         cpu_relax();
1354
1355                 tmport -= 0x08;
1356                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1357                         continue;
1358
1359                 while (inb(tmport) != 0x8e)
1360                         cpu_relax();
1361
1362                 dev->active_id[0] |= m;
1363
1364                 tmport = wkport + 0x10;
1365                 outb(0x30, tmport);
1366                 tmport = wkport + 0x04;
1367                 outb(0x00, tmport);
1368
1369 phase_cmd:
1370                 tmport = wkport + 0x18;
1371                 outb(0x08, tmport);
1372                 tmport += 0x07;
1373                 while ((inb(tmport) & 0x80) == 0x00)
1374                         cpu_relax();
1375                 tmport -= 0x08;
1376                 j = inb(tmport);
1377                 if (j != 0x16) {
1378                         tmport = wkport + 0x10;
1379                         outb(0x41, tmport);
1380                         goto phase_cmd;
1381                 }
1382 sel_ok:
1383                 tmport = wkport + 3;
1384                 outb(inqd[0], tmport++);
1385                 outb(inqd[1], tmport++);
1386                 outb(inqd[2], tmport++);
1387                 outb(inqd[3], tmport++);
1388                 outb(inqd[4], tmport++);
1389                 outb(inqd[5], tmport);
1390                 tmport += 0x07;
1391                 outb(0, tmport);
1392                 tmport += 0x02;
1393                 outb(dev->id[0][i].devsp, tmport++);
1394                 outb(0, tmport++);
1395                 outb(inqd[6], tmport++);
1396                 outb(inqd[7], tmport++);
1397                 tmport += 0x03;
1398                 outb(inqd[8], tmport);
1399                 tmport += 0x07;
1400
1401                 while ((inb(tmport) & 0x80) == 0x00)
1402                         cpu_relax();
1403
1404                 tmport -= 0x08;
1405                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1406                         continue;
1407
1408                 while (inb(tmport) != 0x8e)
1409                         cpu_relax();
1410
1411                 tmport = wkport + 0x1b;
1412                 if (dev->chip_ver == 4)
1413                         outb(0x00, tmport);
1414
1415                 tmport = wkport + 0x18;
1416                 outb(0x08, tmport);
1417                 tmport += 0x07;
1418                 j = 0;
1419 rd_inq_data:
1420                 k = inb(tmport);
1421                 if ((k & 0x01) != 0) {
1422                         tmport -= 0x06;
1423                         mbuf[j++] = inb(tmport);
1424                         tmport += 0x06;
1425                         goto rd_inq_data;
1426                 }
1427                 if ((k & 0x80) == 0) {
1428                         goto rd_inq_data;
1429                 }
1430                 tmport -= 0x08;
1431                 j = inb(tmport);
1432                 if (j == 0x16) {
1433                         goto inq_ok;
1434                 }
1435                 tmport = wkport + 0x10;
1436                 outb(0x46, tmport);
1437                 tmport += 0x02;
1438                 outb(0, tmport++);
1439                 outb(0, tmport++);
1440                 outb(0, tmport++);
1441                 tmport += 0x03;
1442                 outb(0x08, tmport);
1443                 tmport += 0x07;
1444
1445                 while ((inb(tmport) & 0x80) == 0x00)
1446                         cpu_relax();
1447
1448                 tmport -= 0x08;
1449                 if (inb(tmport) != 0x16) {
1450                         goto sel_ok;
1451                 }
1452 inq_ok:
1453                 mbuf[36] = 0;
1454                 printk(KERN_INFO "         ID: %2d  %s\n", i, &mbuf[8]);
1455                 dev->id[0][i].devtype = mbuf[0];
1456                 rmb = mbuf[1];
1457                 n = mbuf[7];
1458                 if (dev->chip_ver != 4) {
1459                         goto not_wide;
1460                 }
1461                 if ((mbuf[7] & 0x60) == 0) {
1462                         goto not_wide;
1463                 }
1464                 if ((dev->global_map[0] & 0x20) == 0) {
1465                         goto not_wide;
1466                 }
1467                 tmport = wkport + 0x1b;
1468                 outb(0x01, tmport);
1469                 tmport = wkport + 3;
1470                 outb(satn[0], tmport++);
1471                 outb(satn[1], tmport++);
1472                 outb(satn[2], tmport++);
1473                 outb(satn[3], tmport++);
1474                 outb(satn[4], tmport++);
1475                 outb(satn[5], tmport++);
1476                 tmport += 0x06;
1477                 outb(0, tmport);
1478                 tmport += 0x02;
1479                 outb(dev->id[0][i].devsp, tmport++);
1480                 outb(0, tmport++);
1481                 outb(satn[6], tmport++);
1482                 outb(satn[7], tmport++);
1483                 tmport += 0x03;
1484                 outb(satn[8], tmport);
1485                 tmport += 0x07;
1486
1487                 while ((inb(tmport) & 0x80) == 0x00)
1488                         cpu_relax();
1489
1490                 tmport -= 0x08;
1491                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1492                         continue;
1493
1494                 while (inb(tmport) != 0x8e)
1495                         cpu_relax();
1496
1497 try_wide:
1498                 j = 0;
1499                 tmport = wkport + 0x14;
1500                 outb(0x05, tmport);
1501                 tmport += 0x04;
1502                 outb(0x20, tmport);
1503                 tmport += 0x07;
1504
1505                 while ((inb(tmport) & 0x80) == 0) {
1506                         if ((inb(tmport) & 0x01) != 0) {
1507                                 tmport -= 0x06;
1508                                 outb(wide[j++], tmport);
1509                                 tmport += 0x06;
1510                         }
1511                 }
1512                 tmport -= 0x08;
1513
1514                 while ((inb(tmport) & 0x80) == 0x00)
1515                         cpu_relax();
1516
1517                 j = inb(tmport) & 0x0f;
1518                 if (j == 0x0f) {
1519                         goto widep_in;
1520                 }
1521                 if (j == 0x0a) {
1522                         goto widep_cmd;
1523                 }
1524                 if (j == 0x0e) {
1525                         goto try_wide;
1526                 }
1527                 continue;
1528 widep_out:
1529                 tmport = wkport + 0x18;
1530                 outb(0x20, tmport);
1531                 tmport += 0x07;
1532                 while ((inb(tmport) & 0x80) == 0) {
1533                         if ((inb(tmport) & 0x01) != 0) {
1534                                 tmport -= 0x06;
1535                                 outb(0, tmport);
1536                                 tmport += 0x06;
1537                         }
1538                 }
1539                 tmport -= 0x08;
1540                 j = inb(tmport) & 0x0f;
1541                 if (j == 0x0f) {
1542                         goto widep_in;
1543                 }
1544                 if (j == 0x0a) {
1545                         goto widep_cmd;
1546                 }
1547                 if (j == 0x0e) {
1548                         goto widep_out;
1549                 }
1550                 continue;
1551 widep_in:
1552                 tmport = wkport + 0x14;
1553                 outb(0xff, tmport);
1554                 tmport += 0x04;
1555                 outb(0x20, tmport);
1556                 tmport += 0x07;
1557                 k = 0;
1558 widep_in1:
1559                 j = inb(tmport);
1560                 if ((j & 0x01) != 0) {
1561                         tmport -= 0x06;
1562                         mbuf[k++] = inb(tmport);
1563                         tmport += 0x06;
1564                         goto widep_in1;
1565                 }
1566                 if ((j & 0x80) == 0x00) {
1567                         goto widep_in1;
1568                 }
1569                 tmport -= 0x08;
1570                 j = inb(tmport) & 0x0f;
1571                 if (j == 0x0f) {
1572                         goto widep_in;
1573                 }
1574                 if (j == 0x0a) {
1575                         goto widep_cmd;
1576                 }
1577                 if (j == 0x0e) {
1578                         goto widep_out;
1579                 }
1580                 continue;
1581 widep_cmd:
1582                 tmport = wkport + 0x10;
1583                 outb(0x30, tmport);
1584                 tmport = wkport + 0x14;
1585                 outb(0x00, tmport);
1586                 tmport += 0x04;
1587                 outb(0x08, tmport);
1588                 tmport += 0x07;
1589
1590                 while ((inb(tmport) & 0x80) == 0x00)
1591                         cpu_relax();
1592
1593                 tmport -= 0x08;
1594                 j = inb(tmport);
1595                 if (j != 0x16) {
1596                         if (j == 0x4e) {
1597                                 goto widep_out;
1598                         }
1599                         continue;
1600                 }
1601                 if (mbuf[0] != 0x01) {
1602                         goto not_wide;
1603                 }
1604                 if (mbuf[1] != 0x02) {
1605                         goto not_wide;
1606                 }
1607                 if (mbuf[2] != 0x03) {
1608                         goto not_wide;
1609                 }
1610                 if (mbuf[3] != 0x01) {
1611                         goto not_wide;
1612                 }
1613                 m = 1;
1614                 m = m << i;
1615                 dev->wide_id[0] |= m;
1616 not_wide:
1617                 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1618                         goto set_sync;
1619                 }
1620                 continue;
1621 set_sync:
1622                 tmport = wkport + 0x1b;
1623                 j = 0;
1624                 if ((m & dev->wide_id[0]) != 0) {
1625                         j |= 0x01;
1626                 }
1627                 outb(j, tmport);
1628                 tmport = wkport + 3;
1629                 outb(satn[0], tmport++);
1630                 outb(satn[1], tmport++);
1631                 outb(satn[2], tmport++);
1632                 outb(satn[3], tmport++);
1633                 outb(satn[4], tmport++);
1634                 outb(satn[5], tmport++);
1635                 tmport += 0x06;
1636                 outb(0, tmport);
1637                 tmport += 0x02;
1638                 outb(dev->id[0][i].devsp, tmport++);
1639                 outb(0, tmport++);
1640                 outb(satn[6], tmport++);
1641                 outb(satn[7], tmport++);
1642                 tmport += 0x03;
1643                 outb(satn[8], tmport);
1644                 tmport += 0x07;
1645
1646                 while ((inb(tmport) & 0x80) == 0x00)
1647                         cpu_relax();
1648
1649                 tmport -= 0x08;
1650                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1651                         continue;
1652
1653                 while (inb(tmport) != 0x8e)
1654                         cpu_relax();
1655
1656 try_sync:
1657                 j = 0;
1658                 tmport = wkport + 0x14;
1659                 outb(0x06, tmport);
1660                 tmport += 0x04;
1661                 outb(0x20, tmport);
1662                 tmport += 0x07;
1663
1664                 while ((inb(tmport) & 0x80) == 0) {
1665                         if ((inb(tmport) & 0x01) != 0) {
1666                                 tmport -= 0x06;
1667                                 if ((m & dev->wide_id[0]) != 0) {
1668                                         outb(synw[j++], tmport);
1669                                 } else {
1670                                         if ((m & dev->ultra_map[0]) != 0) {
1671                                                 outb(synu[j++], tmport);
1672                                         } else {
1673                                                 outb(synn[j++], tmport);
1674                                         }
1675                                 }
1676                                 tmport += 0x06;
1677                         }
1678                 }
1679                 tmport -= 0x08;
1680
1681                 while ((inb(tmport) & 0x80) == 0x00)
1682                         cpu_relax();
1683
1684                 j = inb(tmport) & 0x0f;
1685                 if (j == 0x0f) {
1686                         goto phase_ins;
1687                 }
1688                 if (j == 0x0a) {
1689                         goto phase_cmds;
1690                 }
1691                 if (j == 0x0e) {
1692                         goto try_sync;
1693                 }
1694                 continue;
1695 phase_outs:
1696                 tmport = wkport + 0x18;
1697                 outb(0x20, tmport);
1698                 tmport += 0x07;
1699                 while ((inb(tmport) & 0x80) == 0x00) {
1700                         if ((inb(tmport) & 0x01) != 0x00) {
1701                                 tmport -= 0x06;
1702                                 outb(0x00, tmport);
1703                                 tmport += 0x06;
1704                         }
1705                 }
1706                 tmport -= 0x08;
1707                 j = inb(tmport);
1708                 if (j == 0x85) {
1709                         goto tar_dcons;
1710                 }
1711                 j &= 0x0f;
1712                 if (j == 0x0f) {
1713                         goto phase_ins;
1714                 }
1715                 if (j == 0x0a) {
1716                         goto phase_cmds;
1717                 }
1718                 if (j == 0x0e) {
1719                         goto phase_outs;
1720                 }
1721                 continue;
1722 phase_ins:
1723                 tmport = wkport + 0x14;
1724                 outb(0xff, tmport);
1725                 tmport += 0x04;
1726                 outb(0x20, tmport);
1727                 tmport += 0x07;
1728                 k = 0;
1729 phase_ins1:
1730                 j = inb(tmport);
1731                 if ((j & 0x01) != 0x00) {
1732                         tmport -= 0x06;
1733                         mbuf[k++] = inb(tmport);
1734                         tmport += 0x06;
1735                         goto phase_ins1;
1736                 }
1737                 if ((j & 0x80) == 0x00) {
1738                         goto phase_ins1;
1739                 }
1740                 tmport -= 0x08;
1741
1742                 while ((inb(tmport) & 0x80) == 0x00)
1743                         cpu_relax();
1744
1745                 j = inb(tmport);
1746                 if (j == 0x85) {
1747                         goto tar_dcons;
1748                 }
1749                 j &= 0x0f;
1750                 if (j == 0x0f) {
1751                         goto phase_ins;
1752                 }
1753                 if (j == 0x0a) {
1754                         goto phase_cmds;
1755                 }
1756                 if (j == 0x0e) {
1757                         goto phase_outs;
1758                 }
1759                 continue;
1760 phase_cmds:
1761                 tmport = wkport + 0x10;
1762                 outb(0x30, tmport);
1763 tar_dcons:
1764                 tmport = wkport + 0x14;
1765                 outb(0x00, tmport);
1766                 tmport += 0x04;
1767                 outb(0x08, tmport);
1768                 tmport += 0x07;
1769
1770                 while ((inb(tmport) & 0x80) == 0x00)
1771                         cpu_relax();
1772
1773                 tmport -= 0x08;
1774                 j = inb(tmport);
1775                 if (j != 0x16) {
1776                         continue;
1777                 }
1778                 if (mbuf[0] != 0x01) {
1779                         continue;
1780                 }
1781                 if (mbuf[1] != 0x03) {
1782                         continue;
1783                 }
1784                 if (mbuf[4] == 0x00) {
1785                         continue;
1786                 }
1787                 if (mbuf[3] > 0x64) {
1788                         continue;
1789                 }
1790                 if (mbuf[4] > 0x0c) {
1791                         mbuf[4] = 0x0c;
1792                 }
1793                 dev->id[0][i].devsp = mbuf[4];
1794                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1795                         j = 0xa0;
1796                         goto set_syn_ok;
1797                 }
1798                 if (mbuf[3] < 0x1a) {
1799                         j = 0x20;
1800                         goto set_syn_ok;
1801                 }
1802                 if (mbuf[3] < 0x33) {
1803                         j = 0x40;
1804                         goto set_syn_ok;
1805                 }
1806                 if (mbuf[3] < 0x4c) {
1807                         j = 0x50;
1808                         goto set_syn_ok;
1809                 }
1810                 j = 0x60;
1811 set_syn_ok:
1812                 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
1813         }
1814         tmport = wkport + 0x3a;
1815         outb((unsigned char) (inb(tmport) & 0xef), tmport);
1816 }
1817
1818 static void is880(struct atp_unit *dev, unsigned int wkport)
1819 {
1820         unsigned int tmport;
1821         unsigned char i, j, k, rmb, n, lvdmode;
1822         unsigned short int m;
1823         static unsigned char mbuf[512];
1824         static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1825         static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1826         static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1827         unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1828         static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1829         unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1830         static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1831         static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1832
1833         lvdmode = inb(wkport + 0x3f) & 0x40;
1834
1835         for (i = 0; i < 16; i++) {
1836                 m = 1;
1837                 m = m << i;
1838                 if ((m & dev->active_id[0]) != 0) {
1839                         continue;
1840                 }
1841                 if (i == dev->host_id[0]) {
1842                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[0]);
1843                         continue;
1844                 }
1845                 tmport = wkport + 0x5b;
1846                 outb(0x01, tmport);
1847                 tmport = wkport + 0x41;
1848                 outb(0x08, tmport++);
1849                 outb(0x7f, tmport++);
1850                 outb(satn[0], tmport++);
1851                 outb(satn[1], tmport++);
1852                 outb(satn[2], tmport++);
1853                 outb(satn[3], tmport++);
1854                 outb(satn[4], tmport++);
1855                 outb(satn[5], tmport++);
1856                 tmport += 0x06;
1857                 outb(0, tmport);
1858                 tmport += 0x02;
1859                 outb(dev->id[0][i].devsp, tmport++);
1860                 outb(0, tmport++);
1861                 outb(satn[6], tmport++);
1862                 outb(satn[7], tmport++);
1863                 j = i;
1864                 if ((j & 0x08) != 0) {
1865                         j = (j & 0x07) | 0x40;
1866                 }
1867                 outb(j, tmport);
1868                 tmport += 0x03;
1869                 outb(satn[8], tmport);
1870                 tmport += 0x07;
1871
1872                 while ((inb(tmport) & 0x80) == 0x00)
1873                         cpu_relax();
1874
1875                 tmport -= 0x08;
1876                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1877                         continue;
1878
1879                 while (inb(tmport) != 0x8e)
1880                         cpu_relax();
1881
1882                 dev->active_id[0] |= m;
1883
1884                 tmport = wkport + 0x50;
1885                 outb(0x30, tmport);
1886                 tmport = wkport + 0x54;
1887                 outb(0x00, tmport);
1888
1889 phase_cmd:
1890                 tmport = wkport + 0x58;
1891                 outb(0x08, tmport);
1892                 tmport += 0x07;
1893
1894                 while ((inb(tmport) & 0x80) == 0x00)
1895                         cpu_relax();
1896
1897                 tmport -= 0x08;
1898                 j = inb(tmport);
1899                 if (j != 0x16) {
1900                         tmport = wkport + 0x50;
1901                         outb(0x41, tmport);
1902                         goto phase_cmd;
1903                 }
1904 sel_ok:
1905                 tmport = wkport + 0x43;
1906                 outb(inqd[0], tmport++);
1907                 outb(inqd[1], tmport++);
1908                 outb(inqd[2], tmport++);
1909                 outb(inqd[3], tmport++);
1910                 outb(inqd[4], tmport++);
1911                 outb(inqd[5], tmport);
1912                 tmport += 0x07;
1913                 outb(0, tmport);
1914                 tmport += 0x02;
1915                 outb(dev->id[0][i].devsp, tmport++);
1916                 outb(0, tmport++);
1917                 outb(inqd[6], tmport++);
1918                 outb(inqd[7], tmport++);
1919                 tmport += 0x03;
1920                 outb(inqd[8], tmport);
1921                 tmport += 0x07;
1922
1923                 while ((inb(tmport) & 0x80) == 0x00)
1924                         cpu_relax();
1925
1926                 tmport -= 0x08;
1927                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
1928                         continue;
1929
1930                 while (inb(tmport) != 0x8e)
1931                         cpu_relax();
1932
1933                 tmport = wkport + 0x5b;
1934                 outb(0x00, tmport);
1935                 tmport = wkport + 0x58;
1936                 outb(0x08, tmport);
1937                 tmport += 0x07;
1938                 j = 0;
1939 rd_inq_data:
1940                 k = inb(tmport);
1941                 if ((k & 0x01) != 0) {
1942                         tmport -= 0x06;
1943                         mbuf[j++] = inb(tmport);
1944                         tmport += 0x06;
1945                         goto rd_inq_data;
1946                 }
1947                 if ((k & 0x80) == 0) {
1948                         goto rd_inq_data;
1949                 }
1950                 tmport -= 0x08;
1951                 j = inb(tmport);
1952                 if (j == 0x16) {
1953                         goto inq_ok;
1954                 }
1955                 tmport = wkport + 0x50;
1956                 outb(0x46, tmport);
1957                 tmport += 0x02;
1958                 outb(0, tmport++);
1959                 outb(0, tmport++);
1960                 outb(0, tmport++);
1961                 tmport += 0x03;
1962                 outb(0x08, tmport);
1963                 tmport += 0x07;
1964                 while ((inb(tmport) & 0x80) == 0x00)
1965                         cpu_relax();
1966
1967                 tmport -= 0x08;
1968                 if (inb(tmport) != 0x16)
1969                         goto sel_ok;
1970
1971 inq_ok:
1972                 mbuf[36] = 0;
1973                 printk(KERN_INFO "         ID: %2d  %s\n", i, &mbuf[8]);
1974                 dev->id[0][i].devtype = mbuf[0];
1975                 rmb = mbuf[1];
1976                 n = mbuf[7];
1977                 if ((mbuf[7] & 0x60) == 0) {
1978                         goto not_wide;
1979                 }
1980                 if ((i < 8) && ((dev->global_map[0] & 0x20) == 0)) {
1981                         goto not_wide;
1982                 }
1983                 if (lvdmode == 0) {
1984                         goto chg_wide;
1985                 }
1986                 if (dev->sp[0][i] != 0x04)      // force u2
1987                 {
1988                         goto chg_wide;
1989                 }
1990
1991                 tmport = wkport + 0x5b;
1992                 outb(0x01, tmport);
1993                 tmport = wkport + 0x43;
1994                 outb(satn[0], tmport++);
1995                 outb(satn[1], tmport++);
1996                 outb(satn[2], tmport++);
1997                 outb(satn[3], tmport++);
1998                 outb(satn[4], tmport++);
1999                 outb(satn[5], tmport++);
2000                 tmport += 0x06;
2001                 outb(0, tmport);
2002                 tmport += 0x02;
2003                 outb(dev->id[0][i].devsp, tmport++);
2004                 outb(0, tmport++);
2005                 outb(satn[6], tmport++);
2006                 outb(satn[7], tmport++);
2007                 tmport += 0x03;
2008                 outb(satn[8], tmport);
2009                 tmport += 0x07;
2010
2011                 while ((inb(tmport) & 0x80) == 0x00)
2012                         cpu_relax();
2013
2014                 tmport -= 0x08;
2015
2016                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
2017                         continue;
2018
2019                 while (inb(tmport) != 0x8e)
2020                         cpu_relax();
2021
2022 try_u3:
2023                 j = 0;
2024                 tmport = wkport + 0x54;
2025                 outb(0x09, tmport);
2026                 tmport += 0x04;
2027                 outb(0x20, tmport);
2028                 tmport += 0x07;
2029
2030                 while ((inb(tmport) & 0x80) == 0) {
2031                         if ((inb(tmport) & 0x01) != 0) {
2032                                 tmport -= 0x06;
2033                                 outb(u3[j++], tmport);
2034                                 tmport += 0x06;
2035                         }
2036                 }
2037                 tmport -= 0x08;
2038
2039                 while ((inb(tmport) & 0x80) == 0x00)
2040                         cpu_relax();
2041
2042                 j = inb(tmport) & 0x0f;
2043                 if (j == 0x0f) {
2044                         goto u3p_in;
2045                 }
2046                 if (j == 0x0a) {
2047                         goto u3p_cmd;
2048                 }
2049                 if (j == 0x0e) {
2050                         goto try_u3;
2051                 }
2052                 continue;
2053 u3p_out:
2054                 tmport = wkport + 0x58;
2055                 outb(0x20, tmport);
2056                 tmport += 0x07;
2057                 while ((inb(tmport) & 0x80) == 0) {
2058                         if ((inb(tmport) & 0x01) != 0) {
2059                                 tmport -= 0x06;
2060                                 outb(0, tmport);
2061                                 tmport += 0x06;
2062                         }
2063                 }
2064                 tmport -= 0x08;
2065                 j = inb(tmport) & 0x0f;
2066                 if (j == 0x0f) {
2067                         goto u3p_in;
2068                 }
2069                 if (j == 0x0a) {
2070                         goto u3p_cmd;
2071                 }
2072                 if (j == 0x0e) {
2073                         goto u3p_out;
2074                 }
2075                 continue;
2076 u3p_in:
2077                 tmport = wkport + 0x54;
2078                 outb(0x09, tmport);
2079                 tmport += 0x04;
2080                 outb(0x20, tmport);
2081                 tmport += 0x07;
2082                 k = 0;
2083 u3p_in1:
2084                 j = inb(tmport);
2085                 if ((j & 0x01) != 0) {
2086                         tmport -= 0x06;
2087                         mbuf[k++] = inb(tmport);
2088                         tmport += 0x06;
2089                         goto u3p_in1;
2090                 }
2091                 if ((j & 0x80) == 0x00) {
2092                         goto u3p_in1;
2093                 }
2094                 tmport -= 0x08;
2095                 j = inb(tmport) & 0x0f;
2096                 if (j == 0x0f) {
2097                         goto u3p_in;
2098                 }
2099                 if (j == 0x0a) {
2100                         goto u3p_cmd;
2101                 }
2102                 if (j == 0x0e) {
2103                         goto u3p_out;
2104                 }
2105                 continue;
2106 u3p_cmd:
2107                 tmport = wkport + 0x50;
2108                 outb(0x30, tmport);
2109                 tmport = wkport + 0x54;
2110                 outb(0x00, tmport);
2111                 tmport += 0x04;
2112                 outb(0x08, tmport);
2113                 tmport += 0x07;
2114
2115                 while ((inb(tmport) & 0x80) == 0x00)
2116                         cpu_relax();
2117
2118                 tmport -= 0x08;
2119                 j = inb(tmport);
2120                 if (j != 0x16) {
2121                         if (j == 0x4e) {
2122                                 goto u3p_out;
2123                         }
2124                         continue;
2125                 }
2126                 if (mbuf[0] != 0x01) {
2127                         goto chg_wide;
2128                 }
2129                 if (mbuf[1] != 0x06) {
2130                         goto chg_wide;
2131                 }
2132                 if (mbuf[2] != 0x04) {
2133                         goto chg_wide;
2134                 }
2135                 if (mbuf[3] == 0x09) {
2136                         m = 1;
2137                         m = m << i;
2138                         dev->wide_id[0] |= m;
2139                         dev->id[0][i].devsp = 0xce;
2140                         continue;
2141                 }
2142 chg_wide:
2143                 tmport = wkport + 0x5b;
2144                 outb(0x01, tmport);
2145                 tmport = wkport + 0x43;
2146                 outb(satn[0], tmport++);
2147                 outb(satn[1], tmport++);
2148                 outb(satn[2], tmport++);
2149                 outb(satn[3], tmport++);
2150                 outb(satn[4], tmport++);
2151                 outb(satn[5], tmport++);
2152                 tmport += 0x06;
2153                 outb(0, tmport);
2154                 tmport += 0x02;
2155                 outb(dev->id[0][i].devsp, tmport++);
2156                 outb(0, tmport++);
2157                 outb(satn[6], tmport++);
2158                 outb(satn[7], tmport++);
2159                 tmport += 0x03;
2160                 outb(satn[8], tmport);
2161                 tmport += 0x07;
2162
2163                 while ((inb(tmport) & 0x80) == 0x00)
2164                         cpu_relax();
2165
2166                 tmport -= 0x08;
2167                 if (inb(tmport) != 0x11 && inb(tmport) != 0x8e)
2168                         continue;
2169
2170                 while (inb(tmport) != 0x8e)
2171                         cpu_relax();
2172
2173 try_wide:
2174                 j = 0;
2175                 tmport = wkport + 0x54;
2176                 outb(0x05, tmport);
2177                 tmport += 0x04;
2178                 outb(0x20, tmport);
2179                 tmport += 0x07;
2180
2181                 while ((inb(tmport) & 0x80) == 0) {
2182                         if ((inb(tmport) & 0x01) != 0) {
2183                                 tmport -= 0x06;
2184                                 outb(wide[j++], tmport);
2185                                 tmport += 0x06;
2186                         }
2187                 }
2188                 tmport -= 0x08;
2189                 while ((inb(tmport) & 0x80) == 0x00)
2190                         cpu_relax();
2191
2192                 j = inb(tmport) & 0x0f;
2193                 if (j == 0x0f) {
2194                         goto widep_in;
2195                 }
2196                 if (j == 0x0a) {
2197                         goto widep_cmd;
2198                 }
2199                 if (j == 0x0e) {
2200                         goto try_wide;
2201                 }
2202                 continue;
2203 widep_out:
2204                 tmport = wkport + 0x58;
2205                 outb(0x20, tmport);
2206                 tmport += 0x07;
2207                 while ((inb(tmport) & 0x80) == 0) {
2208                         if ((inb(tmport) & 0x01) != 0) {
2209                                 tmport -= 0x06;
2210                                 outb(0, tmport);
2211                                 tmport += 0x06;
2212                         }
2213                 }
2214                 tmport -= 0x08;
2215                 j = inb(tmport) & 0x0f;
2216                 if (j == 0x0f) {
2217                         goto widep_in;
2218                 }
2219                 if (j == 0x0a) {
2220                         goto widep_cmd;
2221                 }
2222                 if (j == 0x0e) {
2223                         goto widep_out;
2224                 }
2225                 continue;
2226 widep_in:
2227                 tmport = wkport + 0x54;
2228                 outb(0xff, tmport);
2229                 tmport += 0x04;
2230                 outb(0x20, tmport);
2231                 tmport += 0x07;
2232                 k = 0;
2233 widep_in1:
2234                 j = inb(tmport);
2235                 if ((j & 0x01) != 0) {
2236                         tmport -= 0x06;
2237                         mbuf[k++] = inb(tmport);
2238                         tmport += 0x06;
2239                         goto widep_in1;
2240                 }
2241                 if ((j & 0x80) == 0x00) {
2242                         goto widep_in1;
2243                 }
2244                 tmport -= 0x08;
2245                 j = inb(tmport) & 0x0f;
2246                 if (j == 0x0f) {
2247                         goto widep_in;
2248                 }
2249                 if (j == 0x0a) {
2250                         goto widep_cmd;
2251                 }
2252                 if (j == 0x0e) {
2253                         goto widep_out;
2254                 }
2255                 continue;
2256 widep_cmd:
2257                 tmport = wkport + 0x50;
2258                 outb(0x30, tmport);
2259                 tmport = wkport + 0x54;
2260                 outb(0x00, tmport);
2261                 tmport += 0x04;
2262                 outb(0x08, tmport);
2263                 tmport += 0x07;
2264
2265                 while ((inb(tmport) & 0x80) == 0x00)
2266                         cpu_relax();
2267
2268                 tmport -= 0x08;
2269                 j = inb(tmport);
2270                 if (j != 0x16) {
2271                         if (j == 0x4e) {
2272                                 goto widep_out;
2273                         }
2274                         continue;
2275                 }
2276                 if (mbuf[0] != 0x01) {
2277                         goto not_wide;
2278                 }
2279                 if (mbuf[1] != 0x02) {
2280                         goto not_wide;
2281                 }
2282                 if (mbuf[2] != 0x03) {
2283                         goto not_wide;
2284                 }
2285                 if (mbuf[3] != 0x01) {
2286                         goto not_wide;
2287                 }
2288                 m = 1;
2289                 m = m << i;
2290                 dev->wide_id[0] |= m;
2291 not_wide:
2292                 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
2293                         m = 1;
2294                         m = m << i;
2295                         if ((dev->async[0] & m) != 0) {
2296                                 goto set_sync;
2297                         }
2298                 }
2299                 continue;
2300 set_sync:
2301                 if (dev->sp[0][i] == 0x02) {
2302                         synu[4] = 0x0c;
2303                         synuw[4] = 0x0c;
2304                 } else {
2305                         if (dev->sp[0][i] >= 0x03) {
2306                                 synu[4] = 0x0a;
2307                                 synuw[4] = 0x0a;
2308                         }
2309                 }
2310                 tmport = wkport + 0x5b;
2311                 j = 0;
2312                 if ((m & dev->wide_id[0]) != 0) {
2313                         j |= 0x01;
2314                 }
2315                 outb(j, tmport);
2316                 tmport = wkport + 0x43;
2317                 outb(satn[0], tmport++);
2318                 outb(satn[1], tmport++);
2319                 outb(satn[2], tmport++);
2320                 outb(satn[3], tmport++);
2321                 outb(satn[4], tmport++);
2322                 outb(satn[5], tmport++);
2323                 tmport += 0x06;
2324                 outb(0, tmport);
2325                 tmport += 0x02;
2326                 outb(dev->id[0][i].devsp, tmport++);
2327                 outb(0, tmport++);
2328                 outb(satn[6], tmport++);
2329                 outb(satn[7], tmport++);
2330                 tmport += 0x03;
2331                 outb(satn[8], tmport);
2332                 tmport += 0x07;
2333
2334                 while ((inb(tmport) & 0x80) == 0x00)
2335                         cpu_relax();
2336
2337                 tmport -= 0x08;
2338                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
2339                         continue;
2340                 }
2341                 while (inb(tmport) != 0x8e)
2342                         cpu_relax();
2343
2344 try_sync:
2345                 j = 0;
2346                 tmport = wkport + 0x54;
2347                 outb(0x06, tmport);
2348                 tmport += 0x04;
2349                 outb(0x20, tmport);
2350                 tmport += 0x07;
2351
2352                 while ((inb(tmport) & 0x80) == 0) {
2353                         if ((inb(tmport) & 0x01) != 0) {
2354                                 tmport -= 0x06;
2355                                 if ((m & dev->wide_id[0]) != 0) {
2356                                         if ((m & dev->ultra_map[0]) != 0) {
2357                                                 outb(synuw[j++], tmport);
2358                                         } else {
2359                                                 outb(synw[j++], tmport);
2360                                         }
2361                                 } else {
2362                                         if ((m & dev->ultra_map[0]) != 0) {
2363                                                 outb(synu[j++], tmport);
2364                                         } else {
2365                                                 outb(synn[j++], tmport);
2366                                         }
2367                                 }
2368                                 tmport += 0x06;
2369                         }
2370                 }
2371                 tmport -= 0x08;
2372
2373                 while ((inb(tmport) & 0x80) == 0x00)
2374                         cpu_relax();
2375
2376                 j = inb(tmport) & 0x0f;
2377                 if (j == 0x0f) {
2378                         goto phase_ins;
2379                 }
2380                 if (j == 0x0a) {
2381                         goto phase_cmds;
2382                 }
2383                 if (j == 0x0e) {
2384                         goto try_sync;
2385                 }
2386                 continue;
2387 phase_outs:
2388                 tmport = wkport + 0x58;
2389                 outb(0x20, tmport);
2390                 tmport += 0x07;
2391                 while ((inb(tmport) & 0x80) == 0x00) {
2392                         if ((inb(tmport) & 0x01) != 0x00) {
2393                                 tmport -= 0x06;
2394                                 outb(0x00, tmport);
2395                                 tmport += 0x06;
2396                         }
2397                 }
2398                 tmport -= 0x08;
2399                 j = inb(tmport);
2400                 if (j == 0x85) {
2401                         goto tar_dcons;
2402                 }
2403                 j &= 0x0f;
2404                 if (j == 0x0f) {
2405                         goto phase_ins;
2406                 }
2407                 if (j == 0x0a) {
2408                         goto phase_cmds;
2409                 }
2410                 if (j == 0x0e) {
2411                         goto phase_outs;
2412                 }
2413                 continue;
2414 phase_ins:
2415                 tmport = wkport + 0x54;
2416                 outb(0x06, tmport);
2417                 tmport += 0x04;
2418                 outb(0x20, tmport);
2419                 tmport += 0x07;
2420                 k = 0;
2421 phase_ins1:
2422                 j = inb(tmport);
2423                 if ((j & 0x01) != 0x00) {
2424                         tmport -= 0x06;
2425                         mbuf[k++] = inb(tmport);
2426                         tmport += 0x06;
2427                         goto phase_ins1;
2428                 }
2429                 if ((j & 0x80) == 0x00) {
2430                         goto phase_ins1;
2431                 }
2432                 tmport -= 0x08;
2433
2434                 while ((inb(tmport) & 0x80) == 0x00)
2435                         cpu_relax();
2436
2437                 j = inb(tmport);
2438                 if (j == 0x85) {
2439                         goto tar_dcons;
2440                 }
2441                 j &= 0x0f;
2442                 if (j == 0x0f) {
2443                         goto phase_ins;
2444                 }
2445                 if (j == 0x0a) {
2446                         goto phase_cmds;
2447                 }
2448                 if (j == 0x0e) {
2449                         goto phase_outs;
2450                 }
2451                 continue;
2452 phase_cmds:
2453                 tmport = wkport + 0x50;
2454                 outb(0x30, tmport);
2455 tar_dcons:
2456                 tmport = wkport + 0x54;
2457                 outb(0x00, tmport);
2458                 tmport += 0x04;
2459                 outb(0x08, tmport);
2460                 tmport += 0x07;
2461
2462                 while ((inb(tmport) & 0x80) == 0x00)
2463                         cpu_relax();
2464
2465                 tmport -= 0x08;
2466                 j = inb(tmport);
2467                 if (j != 0x16) {
2468                         continue;
2469                 }
2470                 if (mbuf[0] != 0x01) {
2471                         continue;
2472                 }
2473                 if (mbuf[1] != 0x03) {
2474                         continue;
2475                 }
2476                 if (mbuf[4] == 0x00) {
2477                         continue;
2478                 }
2479                 if (mbuf[3] > 0x64) {
2480                         continue;
2481                 }
2482                 if (mbuf[4] > 0x0e) {
2483                         mbuf[4] = 0x0e;
2484                 }
2485                 dev->id[0][i].devsp = mbuf[4];
2486                 if (mbuf[3] < 0x0c) {
2487                         j = 0xb0;
2488                         goto set_syn_ok;
2489                 }
2490                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2491                         j = 0xa0;
2492                         goto set_syn_ok;
2493                 }
2494                 if (mbuf[3] < 0x1a) {
2495                         j = 0x20;
2496                         goto set_syn_ok;
2497                 }
2498                 if (mbuf[3] < 0x33) {
2499                         j = 0x40;
2500                         goto set_syn_ok;
2501                 }
2502                 if (mbuf[3] < 0x4c) {
2503                         j = 0x50;
2504                         goto set_syn_ok;
2505                 }
2506                 j = 0x60;
2507 set_syn_ok:
2508                 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
2509         }
2510 }
2511
2512 static void atp870u_free_tables(struct Scsi_Host *host)
2513 {
2514         struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2515         int j, k;
2516         for (j=0; j < 2; j++) {
2517                 for (k = 0; k < 16; k++) {
2518                         if (!atp_dev->id[j][k].prd_table)
2519                                 continue;
2520                         pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
2521                         atp_dev->id[j][k].prd_table = NULL;
2522                 }
2523         }
2524 }
2525
2526 static int atp870u_init_tables(struct Scsi_Host *host)
2527 {
2528         struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2529         int c,k;
2530         for(c=0;c < 2;c++) {
2531                 for(k=0;k<16;k++) {
2532                                 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
2533                                 if (!atp_dev->id[c][k].prd_table) {
2534                                         printk("atp870u_init_tables fail\n");
2535                                 atp870u_free_tables(host);
2536                                 return -ENOMEM;
2537                         }
2538                         atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
2539                         atp_dev->id[c][k].devsp=0x20;
2540                         atp_dev->id[c][k].devtype = 0x7f;
2541                         atp_dev->id[c][k].curr_req = NULL;
2542                 }
2543
2544                 atp_dev->active_id[c] = 0;
2545                 atp_dev->wide_id[c] = 0;
2546                 atp_dev->host_id[c] = 0x07;
2547                 atp_dev->quhd[c] = 0;
2548                 atp_dev->quend[c] = 0;
2549                 atp_dev->last_cmd[c] = 0xff;
2550                 atp_dev->in_snd[c] = 0;
2551                 atp_dev->in_int[c] = 0;
2552
2553                 for (k = 0; k < qcnt; k++) {
2554                           atp_dev->quereq[c][k] = NULL;
2555                 }
2556                 for (k = 0; k < 16; k++) {
2557                            atp_dev->id[c][k].curr_req = NULL;
2558                            atp_dev->sp[c][k] = 0x04;
2559                 }
2560         }
2561         return 0;
2562 }
2563
2564 /* return non-zero on detection */
2565 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2566 {
2567         unsigned char k, m, c;
2568         unsigned long flags;
2569         unsigned int base_io, tmport, error,n;
2570         unsigned char host_id;
2571         struct Scsi_Host *shpnt = NULL;
2572         struct atp_unit *atpdev, *p;
2573         unsigned char setupdata[2][16];
2574         int count = 0;
2575
2576         atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2577         if (!atpdev)
2578                 return -ENOMEM;
2579
2580         if (pci_enable_device(pdev))
2581                 goto err_eio;
2582
2583         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2584                 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2585         } else {
2586                 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
2587                 goto err_eio;
2588         }
2589
2590         /*
2591          * It's probably easier to weed out some revisions like
2592          * this than via the PCI device table
2593          */
2594         if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
2595                 error = pci_read_config_byte(pdev, PCI_CLASS_REVISION, &atpdev->chip_ver);
2596                 if (atpdev->chip_ver < 2)
2597                         goto err_eio;
2598         }
2599
2600         switch (ent->device) {
2601         case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2602         case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2603         case ATP880_DEVID1:
2604         case ATP880_DEVID2:
2605         case ATP885_DEVID:
2606                 atpdev->chip_ver = 0x04;
2607         default:
2608                 break;
2609         }
2610         base_io = pci_resource_start(pdev, 0);
2611         base_io &= 0xfffffff8;
2612
2613         if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
2614                 error = pci_read_config_byte(pdev, PCI_CLASS_REVISION, &atpdev->chip_ver);
2615                 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2616
2617                 host_id = inb(base_io + 0x39);
2618                 host_id >>= 0x04;
2619
2620                 printk(KERN_INFO "   ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2621                         "    IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2622                 atpdev->ioport[0] = base_io + 0x40;
2623                 atpdev->pciport[0] = base_io + 0x28;
2624                 atpdev->dev_id = ent->device;
2625                 atpdev->host_id[0] = host_id;
2626
2627                 tmport = base_io + 0x22;
2628                 atpdev->scam_on = inb(tmport);
2629                 tmport += 0x13;
2630                 atpdev->global_map[0] = inb(tmport);
2631                 tmport += 0x07;
2632                 atpdev->ultra_map[0] = inw(tmport);
2633
2634                 n = 0x3f09;
2635 next_fblk_880:
2636                 if (n >= 0x4000)
2637                         goto flash_ok_880;
2638
2639                 m = 0;
2640                 outw(n, base_io + 0x34);
2641                 n += 0x0002;
2642                 if (inb(base_io + 0x30) == 0xff)
2643                         goto flash_ok_880;
2644
2645                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2646                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2647                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2648                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2649                 outw(n, base_io + 0x34);
2650                 n += 0x0002;
2651                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2652                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2653                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2654                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2655                 outw(n, base_io + 0x34);
2656                 n += 0x0002;
2657                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2658                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2659                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2660                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2661                 outw(n, base_io + 0x34);
2662                 n += 0x0002;
2663                 atpdev->sp[0][m++] = inb(base_io + 0x30);
2664                 atpdev->sp[0][m++] = inb(base_io + 0x31);
2665                 atpdev->sp[0][m++] = inb(base_io + 0x32);
2666                 atpdev->sp[0][m++] = inb(base_io + 0x33);
2667                 n += 0x0018;
2668                 goto next_fblk_880;
2669 flash_ok_880:
2670                 outw(0, base_io + 0x34);
2671                 atpdev->ultra_map[0] = 0;
2672                 atpdev->async[0] = 0;
2673                 for (k = 0; k < 16; k++) {
2674                         n = 1;
2675                         n = n << k;
2676                         if (atpdev->sp[0][k] > 1) {
2677                                 atpdev->ultra_map[0] |= n;
2678                         } else {
2679                                 if (atpdev->sp[0][k] == 0)
2680                                         atpdev->async[0] |= n;
2681                         }
2682                 }
2683                 atpdev->async[0] = ~(atpdev->async[0]);
2684                 outb(atpdev->global_map[0], base_io + 0x35);
2685
2686                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2687                 if (!shpnt)
2688                         goto err_nomem;
2689
2690                 p = (struct atp_unit *)&shpnt->hostdata;
2691
2692                 atpdev->host = shpnt;
2693                 atpdev->pdev = pdev;
2694                 pci_set_drvdata(pdev, p);
2695                 memcpy(p, atpdev, sizeof(*atpdev));
2696                 if (atp870u_init_tables(shpnt) < 0) {
2697                         printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2698                         goto unregister;
2699                 }
2700
2701                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
2702                         printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2703                         goto free_tables;
2704                 }
2705
2706                 spin_lock_irqsave(shpnt->host_lock, flags);
2707                 tmport = base_io + 0x38;
2708                 k = inb(tmport) & 0x80;
2709                 outb(k, tmport);
2710                 tmport += 0x03;
2711                 outb(0x20, tmport);
2712                 mdelay(32);
2713                 outb(0, tmport);
2714                 mdelay(32);
2715                 tmport = base_io + 0x5b;
2716                 inb(tmport);
2717                 tmport -= 0x04;
2718                 inb(tmport);
2719                 tmport = base_io + 0x40;
2720                 outb((host_id | 0x08), tmport);
2721                 tmport += 0x18;
2722                 outb(0, tmport);
2723                 tmport += 0x07;
2724                 while ((inb(tmport) & 0x80) == 0)
2725                         mdelay(1);
2726                 tmport -= 0x08;
2727                 inb(tmport);
2728                 tmport = base_io + 0x41;
2729                 outb(8, tmport++);
2730                 outb(0x7f, tmport);
2731                 tmport = base_io + 0x51;
2732                 outb(0x20, tmport);
2733
2734                 tscam(shpnt);
2735                 is880(p, base_io);
2736                 tmport = base_io + 0x38;
2737                 outb(0xb0, tmport);
2738                 shpnt->max_id = 16;
2739                 shpnt->this_id = host_id;
2740                 shpnt->unique_id = base_io;
2741                 shpnt->io_port = base_io;
2742                 shpnt->n_io_port = 0x60;        /* Number of bytes of I/O space used */
2743                 shpnt->irq = pdev->irq;
2744         } else if (ent->device == ATP885_DEVID) {
2745                         printk(KERN_INFO "   ACARD AEC-67162 PCI Ultra3 LVD Host Adapter:  IO:%x, IRQ:%d.\n"
2746                                , base_io, pdev->irq);
2747
2748                 atpdev->pdev = pdev;
2749                 atpdev->dev_id  = ent->device;
2750                 atpdev->baseport = base_io;
2751                 atpdev->ioport[0] = base_io + 0x80;
2752                 atpdev->ioport[1] = base_io + 0xc0;
2753                 atpdev->pciport[0] = base_io + 0x40;
2754                 atpdev->pciport[1] = base_io + 0x50;
2755
2756                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2757                 if (!shpnt)
2758                         goto err_nomem;
2759
2760                 p = (struct atp_unit *)&shpnt->hostdata;
2761
2762                 atpdev->host = shpnt;
2763                 atpdev->pdev = pdev;
2764                 pci_set_drvdata(pdev, p);
2765                 memcpy(p, atpdev, sizeof(struct atp_unit));
2766                 if (atp870u_init_tables(shpnt) < 0)
2767                         goto unregister;
2768
2769 #ifdef ED_DBGP
2770         printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2771 #endif
2772                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
2773                                 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2774                         goto free_tables;
2775                 }
2776
2777                 spin_lock_irqsave(shpnt->host_lock, flags);
2778
2779                 c=inb(base_io + 0x29);
2780                 outb((c | 0x04),base_io + 0x29);
2781
2782                 n=0x1f80;
2783 next_fblk_885:
2784                 if (n >= 0x2000) {
2785                    goto flash_ok_885;
2786                 }
2787                 outw(n,base_io + 0x3c);
2788                 if (inl(base_io + 0x38) == 0xffffffff) {
2789                    goto flash_ok_885;
2790                 }
2791                 for (m=0; m < 2; m++) {
2792                     p->global_map[m]= 0;
2793                     for (k=0; k < 4; k++) {
2794                         outw(n++,base_io + 0x3c);
2795                         ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2796                     }
2797                     for (k=0; k < 4; k++) {
2798                         outw(n++,base_io + 0x3c);
2799                         ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2800                     }
2801                     n += 8;
2802                 }
2803                 goto next_fblk_885;
2804 flash_ok_885:
2805 #ifdef ED_DBGP
2806                 printk( "Flash Read OK\n");
2807 #endif
2808                 c=inb(base_io + 0x29);
2809                 outb((c & 0xfb),base_io + 0x29);
2810                 for (c=0;c < 2;c++) {
2811                     p->ultra_map[c]=0;
2812                     p->async[c] = 0;
2813                     for (k=0; k < 16; k++) {
2814                         n=1;
2815                         n = n << k;
2816                         if (p->sp[c][k] > 1) {
2817                            p->ultra_map[c] |= n;
2818                         } else {
2819                            if (p->sp[c][k] == 0) {
2820                               p->async[c] |= n;
2821                            }
2822                         }
2823                     }
2824                     p->async[c] = ~(p->async[c]);
2825
2826                     if (p->global_map[c] == 0) {
2827                        k=setupdata[c][1];
2828                        if ((k & 0x40) != 0)
2829                           p->global_map[c] |= 0x20;
2830                        k &= 0x07;
2831                        p->global_map[c] |= k;
2832                        if ((setupdata[c][2] & 0x04) != 0)
2833                           p->global_map[c] |= 0x08;
2834                        p->host_id[c] = setupdata[c][0] & 0x07;
2835                     }
2836                 }
2837
2838                 k = inb(base_io + 0x28) & 0x8f;
2839                 k |= 0x10;
2840                 outb(k, base_io + 0x28);
2841                 outb(0x80, base_io + 0x41);
2842                 outb(0x80, base_io + 0x51);
2843                 mdelay(100);
2844                 outb(0, base_io + 0x41);
2845                 outb(0, base_io + 0x51);
2846                 mdelay(1000);
2847                 inb(base_io + 0x9b);
2848                 inb(base_io + 0x97);
2849                 inb(base_io + 0xdb);
2850                 inb(base_io + 0xd7);
2851                 tmport = base_io + 0x80;
2852                 k=p->host_id[0];
2853                 if (k > 7)
2854                    k = (k & 0x07) | 0x40;
2855                 k |= 0x08;
2856                 outb(k, tmport);
2857                 tmport += 0x18;
2858                 outb(0, tmport);
2859                 tmport += 0x07;
2860
2861                 while ((inb(tmport) & 0x80) == 0)
2862                         cpu_relax();
2863
2864                 tmport -= 0x08;
2865                 inb(tmport);
2866                 tmport = base_io + 0x81;
2867                 outb(8, tmport++);
2868                 outb(0x7f, tmport);
2869                 tmport = base_io + 0x91;
2870                 outb(0x20, tmport);
2871
2872                 tmport = base_io + 0xc0;
2873                 k=p->host_id[1];
2874                 if (k > 7)
2875                    k = (k & 0x07) | 0x40;
2876                 k |= 0x08;
2877                 outb(k, tmport);
2878                 tmport += 0x18;
2879                 outb(0, tmport);
2880                 tmport += 0x07;
2881
2882                 while ((inb(tmport) & 0x80) == 0)
2883                         cpu_relax();
2884
2885                 tmport -= 0x08;
2886                 inb(tmport);
2887                 tmport = base_io + 0xc1;
2888                 outb(8, tmport++);
2889                 outb(0x7f, tmport);
2890                 tmport = base_io + 0xd1;
2891                 outb(0x20, tmport);
2892
2893                 tscam_885();
2894                 printk(KERN_INFO "   Scanning Channel A SCSI Device ...\n");
2895                 is885(p, base_io + 0x80, 0);
2896                 printk(KERN_INFO "   Scanning Channel B SCSI Device ...\n");
2897                 is885(p, base_io + 0xc0, 1);
2898
2899                 k = inb(base_io + 0x28) & 0xcf;
2900                 k |= 0xc0;
2901                 outb(k, base_io + 0x28);
2902                 k = inb(base_io + 0x1f) | 0x80;
2903                 outb(k, base_io + 0x1f);
2904                 k = inb(base_io + 0x29) | 0x01;
2905                 outb(k, base_io + 0x29);
2906 #ifdef ED_DBGP
2907                 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2908 #endif
2909                 shpnt->max_id = 16;
2910                 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2911                 shpnt->max_channel = 1;
2912                 shpnt->this_id = p->host_id[0];
2913                 shpnt->unique_id = base_io;
2914                 shpnt->io_port = base_io;
2915                 shpnt->n_io_port = 0xff;        /* Number of bytes of I/O space used */
2916                 shpnt->irq = pdev->irq;
2917
2918         } else {
2919                 error = pci_read_config_byte(pdev, 0x49, &host_id);
2920
2921                 printk(KERN_INFO "   ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2922                         "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2923
2924                 atpdev->ioport[0] = base_io;
2925                 atpdev->pciport[0] = base_io + 0x20;
2926                 atpdev->dev_id = ent->device;
2927                 host_id &= 0x07;
2928                 atpdev->host_id[0] = host_id;
2929                 tmport = base_io + 0x22;
2930                 atpdev->scam_on = inb(tmport);
2931                 tmport += 0x0b;
2932                 atpdev->global_map[0] = inb(tmport++);
2933                 atpdev->ultra_map[0] = inw(tmport);
2934
2935                 if (atpdev->ultra_map[0] == 0) {
2936                         atpdev->scam_on = 0x00;
2937                         atpdev->global_map[0] = 0x20;
2938                         atpdev->ultra_map[0] = 0xffff;
2939                 }
2940
2941                 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2942                 if (!shpnt)
2943                         goto err_nomem;
2944
2945                 p = (struct atp_unit *)&shpnt->hostdata;
2946
2947                 atpdev->host = shpnt;
2948                 atpdev->pdev = pdev;
2949                 pci_set_drvdata(pdev, p);
2950                 memcpy(p, atpdev, sizeof(*atpdev));
2951                 if (atp870u_init_tables(shpnt) < 0)
2952                         goto unregister;
2953
2954                 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
2955                         printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2956                         goto free_tables;
2957                 }
2958
2959                 spin_lock_irqsave(shpnt->host_lock, flags);
2960                 if (atpdev->chip_ver > 0x07) {  /* check if atp876 chip then enable terminator */
2961                         tmport = base_io + 0x3e;
2962                         outb(0x00, tmport);
2963                 }
2964
2965                 tmport = base_io + 0x3a;
2966                 k = (inb(tmport) & 0xf3) | 0x10;
2967                 outb(k, tmport);
2968                 outb((k & 0xdf), tmport);
2969                 mdelay(32);
2970                 outb(k, tmport);
2971                 mdelay(32);
2972                 tmport = base_io;
2973                 outb((host_id | 0x08), tmport);
2974                 tmport += 0x18;
2975                 outb(0, tmport);
2976                 tmport += 0x07;
2977                 while ((inb(tmport) & 0x80) == 0)
2978                         mdelay(1);
2979
2980                 tmport -= 0x08;
2981                 inb(tmport);
2982                 tmport = base_io + 1;
2983                 outb(8, tmport++);
2984                 outb(0x7f, tmport);
2985                 tmport = base_io + 0x11;
2986                 outb(0x20, tmport);
2987
2988                 tscam(shpnt);
2989                 is870(p, base_io);
2990                 tmport = base_io + 0x3a;
2991                 outb((inb(tmport) & 0xef), tmport);
2992                 tmport++;
2993                 outb((inb(tmport) | 0x20), tmport);
2994                 if (atpdev->chip_ver == 4)
2995                         shpnt->max_id = 16;
2996                 else
2997                         shpnt->max_id = 8;
2998                 shpnt->this_id = host_id;
2999                 shpnt->unique_id = base_io;
3000                 shpnt->io_port = base_io;
3001                 shpnt->n_io_port = 0x40;        /* Number of bytes of I/O space used */
3002                 shpnt->irq = pdev->irq;
3003         }
3004                 spin_unlock_irqrestore(shpnt->host_lock, flags);
3005                 if(ent->device==ATP885_DEVID) {
3006                         if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
3007                                 goto request_io_fail;
3008                 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
3009                         if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
3010                                 goto request_io_fail;
3011                 } else {
3012                         if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
3013                                 goto request_io_fail;
3014                 }
3015                 count++;
3016                 if (scsi_add_host(shpnt, &pdev->dev))
3017                         goto scsi_add_fail;
3018                 scsi_scan_host(shpnt);
3019 #ifdef ED_DBGP
3020                 printk("atp870u_prob : exit\n");
3021 #endif
3022                 return 0;
3023
3024 scsi_add_fail:
3025         printk("atp870u_prob:scsi_add_fail\n");
3026         if(ent->device==ATP885_DEVID) {
3027                 release_region(base_io, 0xff);
3028         } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
3029                 release_region(base_io, 0x60);
3030         } else {
3031                 release_region(base_io, 0x40);
3032         }
3033 request_io_fail:
3034         printk("atp870u_prob:request_io_fail\n");
3035         free_irq(pdev->irq, shpnt);
3036 free_tables:
3037         printk("atp870u_prob:free_table\n");
3038         atp870u_free_tables(shpnt);
3039 unregister:
3040         printk("atp870u_prob:unregister\n");
3041         scsi_host_put(shpnt);
3042         return -1;
3043 err_eio:
3044         kfree(atpdev);
3045         return -EIO;
3046 err_nomem:
3047         kfree(atpdev);
3048         return -ENOMEM;
3049 }
3050
3051 /* The abort command does not leave the device in a clean state where
3052    it is available to be used again.  Until this gets worked out, we will
3053    leave it commented out.  */
3054
3055 static int atp870u_abort(struct scsi_cmnd * SCpnt)
3056 {
3057         unsigned char  j, k, c;
3058         struct scsi_cmnd *workrequ;
3059         unsigned int tmport;
3060         struct atp_unit *dev;
3061         struct Scsi_Host *host;
3062         host = SCpnt->device->host;
3063
3064         dev = (struct atp_unit *)&host->hostdata;
3065         c = scmd_channel(SCpnt);
3066         printk(" atp870u: abort Channel = %x \n", c);
3067         printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
3068         printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
3069         tmport = dev->ioport[c];
3070         for (j = 0; j < 0x18; j++) {
3071                 printk(" r%2x=%2x", j, inb(tmport++));
3072         }
3073         tmport += 0x04;
3074         printk(" r1c=%2x", inb(tmport));
3075         tmport += 0x03;
3076         printk(" r1f=%2x in_snd=%2x ", inb(tmport), dev->in_snd[c]);
3077         tmport= dev->pciport[c];
3078         printk(" d00=%2x", inb(tmport));
3079         tmport += 0x02;
3080         printk(" d02=%2x", inb(tmport));
3081         for(j=0;j<16;j++) {
3082            if (dev->id[c][j].curr_req != NULL) {
3083                 workrequ = dev->id[c][j].curr_req;
3084                 printk("\n que cdb= ");
3085                 for (k=0; k < workrequ->cmd_len; k++) {
3086                     printk(" %2x ",workrequ->cmnd[k]);
3087                 }
3088                 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
3089            }
3090         }
3091         return SUCCESS;
3092 }
3093
3094 static const char *atp870u_info(struct Scsi_Host *notused)
3095 {
3096         static char buffer[128];
3097
3098         strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
3099
3100         return buffer;
3101 }
3102
3103 #define BLS buffer + len + size
3104 static int atp870u_proc_info(struct Scsi_Host *HBAptr, char *buffer,
3105                              char **start, off_t offset, int length, int inout)
3106 {
3107         static u8 buff[512];
3108         int size = 0;
3109         int len = 0;
3110         off_t begin = 0;
3111         off_t pos = 0;
3112
3113         if (inout)
3114                 return -EINVAL;
3115         if (offset == 0)
3116                 memset(buff, 0, sizeof(buff));
3117         size += sprintf(BLS, "ACARD AEC-671X Driver Version: 2.6+ac\n");
3118         len += size;
3119         pos = begin + len;
3120         size = 0;
3121
3122         size += sprintf(BLS, "\n");
3123         size += sprintf(BLS, "Adapter Configuration:\n");
3124         size += sprintf(BLS, "               Base IO: %#.4lx\n", HBAptr->io_port);
3125         size += sprintf(BLS, "                   IRQ: %d\n", HBAptr->irq);
3126         len += size;
3127         pos = begin + len;
3128
3129         *start = buffer + (offset - begin);     /* Start of wanted data */
3130         len -= (offset - begin);        /* Start slop */
3131         if (len > length) {
3132                 len = length;   /* Ending slop */
3133         }
3134         return (len);
3135 }
3136
3137
3138 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
3139                         sector_t capacity, int *ip)
3140 {
3141         int heads, sectors, cylinders;
3142
3143         heads = 64;
3144         sectors = 32;
3145         cylinders = (unsigned long)capacity / (heads * sectors);
3146         if (cylinders > 1024) {
3147                 heads = 255;
3148                 sectors = 63;
3149                 cylinders = (unsigned long)capacity / (heads * sectors);
3150         }
3151         ip[0] = heads;
3152         ip[1] = sectors;
3153         ip[2] = cylinders;
3154
3155         return 0;
3156 }
3157
3158 static void atp870u_remove (struct pci_dev *pdev)
3159 {
3160         struct atp_unit *devext = pci_get_drvdata(pdev);
3161         struct Scsi_Host *pshost = devext->host;
3162
3163
3164         scsi_remove_host(pshost);
3165         printk(KERN_INFO "free_irq : %d\n",pshost->irq);
3166         free_irq(pshost->irq, pshost);
3167         release_region(pshost->io_port, pshost->n_io_port);
3168         printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
3169         atp870u_free_tables(pshost);
3170         printk(KERN_INFO "scsi_host_put : %p\n",pshost);
3171         scsi_host_put(pshost);
3172         printk(KERN_INFO "pci_set_drvdata : %p\n",pdev);
3173         pci_set_drvdata(pdev, NULL);
3174 }
3175 MODULE_LICENSE("GPL");
3176
3177 static struct scsi_host_template atp870u_template = {
3178      .module                    = THIS_MODULE,
3179      .name                      = "atp870u"             /* name */,
3180      .proc_name                 = "atp870u",
3181      .proc_info                 = atp870u_proc_info,
3182      .info                      = atp870u_info          /* info */,
3183      .queuecommand              = atp870u_queuecommand  /* queuecommand */,
3184      .eh_abort_handler          = atp870u_abort         /* abort */,
3185      .bios_param                = atp870u_biosparam     /* biosparm */,
3186      .can_queue                 = qcnt                  /* can_queue */,
3187      .this_id                   = 7                     /* SCSI ID */,
3188      .sg_tablesize              = ATP870U_SCATTER       /*SG_ALL*/ /*SG_NONE*/,
3189      .cmd_per_lun               = ATP870U_CMDLUN                /* commands per lun */,
3190      .use_clustering            = ENABLE_CLUSTERING,
3191      .max_sectors               = ATP870U_MAX_SECTORS,
3192 };
3193
3194 static struct pci_device_id atp870u_id_table[] = {
3195         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID)                   },
3196         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1)                          },
3197         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2)                          },
3198         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610)    },
3199         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW)  },
3200         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U)   },
3201         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S)   },
3202         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D)   },
3203         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
3204         { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060)       },
3205         { 0, },
3206 };
3207
3208 MODULE_DEVICE_TABLE(pci, atp870u_id_table);
3209
3210 static struct pci_driver atp870u_driver = {
3211         .id_table       = atp870u_id_table,
3212         .name           = "atp870u",
3213         .probe          = atp870u_probe,
3214         .remove         = __devexit_p(atp870u_remove),
3215 };
3216
3217 static int __init atp870u_init(void)
3218 {
3219 #ifdef ED_DBGP
3220         printk("atp870u_init: Entry\n");
3221 #endif
3222         return pci_register_driver(&atp870u_driver);
3223 }
3224
3225 static void __exit atp870u_exit(void)
3226 {
3227 #ifdef ED_DBGP
3228         printk("atp870u_exit: Entry\n");
3229 #endif
3230         pci_unregister_driver(&atp870u_driver);
3231 }
3232
3233 static void tscam_885(void)
3234 {
3235         unsigned char i;
3236
3237         for (i = 0; i < 0x2; i++) {
3238                 mdelay(300);
3239         }
3240         return;
3241 }
3242
3243
3244
3245 static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c)
3246 {
3247         unsigned int tmport;
3248         unsigned char i, j, k, rmb, n, lvdmode;
3249         unsigned short int m;
3250         static unsigned char mbuf[512];
3251         static unsigned char satn[9] =  {0, 0, 0, 0, 0, 0, 0, 6, 6};
3252         static unsigned char inqd[9] =  {0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6};
3253         static unsigned char synn[6] =  {0x80, 1, 3, 1, 0x19, 0x0e};
3254         unsigned char synu[6] =  {0x80, 1, 3, 1, 0x0a, 0x0e};
3255         static unsigned char synw[6] =  {0x80, 1, 3, 1, 0x19, 0x0e};
3256         unsigned char synuw[6] =  {0x80, 1, 3, 1, 0x0a, 0x0e};
3257         static unsigned char wide[6] =  {0x80, 1, 2, 3, 1, 0};
3258         static unsigned char u3[9] = { 0x80,1,6,4,0x09,00,0x0e,0x01,0x02 };
3259
3260         lvdmode=inb(wkport + 0x1b) >> 7;
3261
3262         for (i = 0; i < 16; i++) {
3263                 m = 1;
3264                 m = m << i;
3265                 if ((m & dev->active_id[c]) != 0) {
3266                         continue;
3267                 }
3268                 if (i == dev->host_id[c]) {
3269                         printk(KERN_INFO "         ID: %2d  Host Adapter\n", dev->host_id[c]);
3270                         continue;
3271                 }
3272                 tmport = wkport + 0x1b;
3273                 outb(0x01, tmport);
3274                 tmport = wkport + 0x01;
3275                 outb(0x08, tmport++);
3276                 outb(0x7f, tmport++);
3277                 outb(satn[0], tmport++);
3278                 outb(satn[1], tmport++);
3279                 outb(satn[2], tmport++);
3280                 outb(satn[3], tmport++);
3281                 outb(satn[4], tmport++);
3282                 outb(satn[5], tmport++);
3283                 tmport += 0x06;
3284                 outb(0, tmport);
3285                 tmport += 0x02;
3286                 outb(dev->id[c][i].devsp, tmport++);
3287
3288                 outb(0, tmport++);
3289                 outb(satn[6], tmport++);
3290                 outb(satn[7], tmport++);
3291                 j = i;
3292                 if ((j & 0x08) != 0) {
3293                         j = (j & 0x07) | 0x40;
3294                 }
3295                 outb(j, tmport);
3296                 tmport += 0x03;
3297                 outb(satn[8], tmport);
3298                 tmport += 0x07;
3299
3300                 while ((inb(tmport) & 0x80) == 0x00)
3301                         cpu_relax();
3302                 tmport -= 0x08;
3303                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3304                         continue;
3305                 }
3306                 while (inb(tmport) != 0x8e)
3307                         cpu_relax();
3308                 dev->active_id[c] |= m;
3309
3310                 tmport = wkport + 0x10;
3311                 outb(0x30, tmport);
3312                 tmport = wkport + 0x14;
3313                 outb(0x00, tmport);
3314
3315 phase_cmd:
3316                 tmport = wkport + 0x18;
3317                 outb(0x08, tmport);
3318                 tmport += 0x07;
3319                 while ((inb(tmport) & 0x80) == 0x00)
3320                         cpu_relax();
3321                 tmport -= 0x08;
3322                 j = inb(tmport);
3323                 if (j != 0x16) {
3324                         tmport = wkport + 0x10;
3325                         outb(0x41, tmport);
3326                         goto phase_cmd;
3327                 }
3328 sel_ok:
3329                 tmport = wkport + 0x03;
3330                 outb(inqd[0], tmport++);
3331                 outb(inqd[1], tmport++);
3332                 outb(inqd[2], tmport++);
3333                 outb(inqd[3], tmport++);
3334                 outb(inqd[4], tmport++);
3335                 outb(inqd[5], tmport);
3336                 tmport += 0x07;
3337                 outb(0, tmport);
3338                 tmport += 0x02;
3339                 outb(dev->id[c][i].devsp, tmport++);
3340                 outb(0, tmport++);
3341                 outb(inqd[6], tmport++);
3342                 outb(inqd[7], tmport++);
3343                 tmport += 0x03;
3344                 outb(inqd[8], tmport);
3345                 tmport += 0x07;
3346                 while ((inb(tmport) & 0x80) == 0x00)
3347                         cpu_relax();
3348                 tmport -= 0x08;
3349                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3350                         continue;
3351                 }
3352                 while (inb(tmport) != 0x8e)
3353                         cpu_relax();
3354                 tmport = wkport + 0x1b;
3355                 outb(0x00, tmport);
3356                 tmport = wkport + 0x18;
3357                 outb(0x08, tmport);
3358                 tmport += 0x07;
3359                 j = 0;
3360 rd_inq_data:
3361                 k = inb(tmport);
3362                 if ((k & 0x01) != 0) {
3363                         tmport -= 0x06;
3364                         mbuf[j++] = inb(tmport);
3365                         tmport += 0x06;
3366                         goto rd_inq_data;
3367                 }
3368                 if ((k & 0x80) == 0) {
3369                         goto rd_inq_data;
3370                 }
3371                 tmport -= 0x08;
3372                 j = inb(tmport);
3373                 if (j == 0x16) {
3374                         goto inq_ok;
3375                 }
3376                 tmport = wkport + 0x10;
3377                 outb(0x46, tmport);
3378                 tmport += 0x02;
3379                 outb(0, tmport++);
3380                 outb(0, tmport++);
3381                 outb(0, tmport++);
3382                 tmport += 0x03;
3383                 outb(0x08, tmport);
3384                 tmport += 0x07;
3385                 while ((inb(tmport) & 0x80) == 0x00)
3386                         cpu_relax();
3387                 tmport -= 0x08;
3388                 if (inb(tmport) != 0x16) {
3389                         goto sel_ok;
3390                 }
3391 inq_ok:
3392                 mbuf[36] = 0;
3393                 printk( KERN_INFO"         ID: %2d  %s\n", i, &mbuf[8]);
3394                 dev->id[c][i].devtype = mbuf[0];
3395                 rmb = mbuf[1];
3396                 n = mbuf[7];
3397                 if ((mbuf[7] & 0x60) == 0) {
3398                         goto not_wide;
3399                 }
3400                 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
3401                         goto not_wide;
3402                 }
3403                 if (lvdmode == 0) {
3404                    goto chg_wide;
3405                 }
3406                 if (dev->sp[c][i] != 0x04) {    // force u2
3407                    goto chg_wide;
3408                 }
3409
3410                 tmport = wkport + 0x1b;
3411                 outb(0x01, tmport);
3412                 tmport = wkport + 0x03;
3413                 outb(satn[0], tmport++);
3414                 outb(satn[1], tmport++);
3415                 outb(satn[2], tmport++);
3416                 outb(satn[3], tmport++);
3417                 outb(satn[4], tmport++);
3418                 outb(satn[5], tmport++);
3419                 tmport += 0x06;
3420                 outb(0, tmport);
3421                 tmport += 0x02;
3422                 outb(dev->id[c][i].devsp, tmport++);
3423                 outb(0, tmport++);
3424                 outb(satn[6], tmport++);
3425                 outb(satn[7], tmport++);
3426                 tmport += 0x03;
3427                 outb(satn[8], tmport);
3428                 tmport += 0x07;
3429
3430                 while ((inb(tmport) & 0x80) == 0x00)
3431                         cpu_relax();
3432                 tmport -= 0x08;
3433                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3434                         continue;
3435                 }
3436                 while (inb(tmport) != 0x8e)
3437                         cpu_relax();
3438 try_u3:
3439                 j = 0;
3440                 tmport = wkport + 0x14;
3441                 outb(0x09, tmport);
3442                 tmport += 0x04;
3443                 outb(0x20, tmport);
3444                 tmport += 0x07;
3445
3446                 while ((inb(tmport) & 0x80) == 0) {
3447                         if ((inb(tmport) & 0x01) != 0) {
3448                                 tmport -= 0x06;
3449                                 outb(u3[j++], tmport);
3450                                 tmport += 0x06;
3451                         }
3452                         cpu_relax();
3453                 }
3454                 tmport -= 0x08;
3455                 while ((inb(tmport) & 0x80) == 0x00)
3456                         cpu_relax();
3457                 j = inb(tmport) & 0x0f;
3458                 if (j == 0x0f) {
3459                         goto u3p_in;
3460                 }
3461                 if (j == 0x0a) {
3462                         goto u3p_cmd;
3463                 }
3464                 if (j == 0x0e) {
3465                         goto try_u3;
3466                 }
3467                 continue;
3468 u3p_out:
3469                 tmport = wkport + 0x18;
3470                 outb(0x20, tmport);
3471                 tmport += 0x07;
3472                 while ((inb(tmport) & 0x80) == 0) {
3473                         if ((inb(tmport) & 0x01) != 0) {
3474                                 tmport -= 0x06;
3475                                 outb(0, tmport);
3476                                 tmport += 0x06;
3477                         }
3478                         cpu_relax();
3479                 }
3480                 tmport -= 0x08;
3481                 j = inb(tmport) & 0x0f;
3482                 if (j == 0x0f) {
3483                         goto u3p_in;
3484                 }
3485                 if (j == 0x0a) {
3486                         goto u3p_cmd;
3487                 }
3488                 if (j == 0x0e) {
3489                         goto u3p_out;
3490                 }
3491                 continue;
3492 u3p_in:
3493                 tmport = wkport + 0x14;
3494                 outb(0x09, tmport);
3495                 tmport += 0x04;
3496                 outb(0x20, tmport);
3497                 tmport += 0x07;
3498                 k = 0;
3499 u3p_in1:
3500                 j = inb(tmport);
3501                 if ((j & 0x01) != 0) {
3502                         tmport -= 0x06;
3503                         mbuf[k++] = inb(tmport);
3504                         tmport += 0x06;
3505                         goto u3p_in1;
3506                 }
3507                 if ((j & 0x80) == 0x00) {
3508                         goto u3p_in1;
3509                 }
3510                 tmport -= 0x08;
3511                 j = inb(tmport) & 0x0f;
3512                 if (j == 0x0f) {
3513                         goto u3p_in;
3514                 }
3515                 if (j == 0x0a) {
3516                         goto u3p_cmd;
3517                 }
3518                 if (j == 0x0e) {
3519                         goto u3p_out;
3520                 }
3521                 continue;
3522 u3p_cmd:
3523                 tmport = wkport + 0x10;
3524                 outb(0x30, tmport);
3525                 tmport = wkport + 0x14;
3526                 outb(0x00, tmport);
3527                 tmport += 0x04;
3528                 outb(0x08, tmport);
3529                 tmport += 0x07;
3530                 while ((inb(tmport) & 0x80) == 0x00);
3531                 tmport -= 0x08;
3532                 j = inb(tmport);
3533                 if (j != 0x16) {
3534                         if (j == 0x4e) {
3535                                 goto u3p_out;
3536                         }
3537                         continue;
3538                 }
3539                 if (mbuf[0] != 0x01) {
3540                         goto chg_wide;
3541                 }
3542                 if (mbuf[1] != 0x06) {
3543                         goto chg_wide;
3544                 }
3545                 if (mbuf[2] != 0x04) {
3546                         goto chg_wide;
3547                 }
3548                 if (mbuf[3] == 0x09) {
3549                         m = 1;
3550                         m = m << i;
3551                         dev->wide_id[c] |= m;
3552                         dev->id[c][i].devsp = 0xce;
3553 #ifdef ED_DBGP
3554                         printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3555 #endif
3556                         continue;
3557                 }
3558 chg_wide:
3559                 tmport = wkport + 0x1b;
3560                 outb(0x01, tmport);
3561                 tmport = wkport + 0x03;
3562                 outb(satn[0], tmport++);
3563                 outb(satn[1], tmport++);
3564                 outb(satn[2], tmport++);
3565                 outb(satn[3], tmport++);
3566                 outb(satn[4], tmport++);
3567                 outb(satn[5], tmport++);
3568                 tmport += 0x06;
3569                 outb(0, tmport);
3570                 tmport += 0x02;
3571                 outb(dev->id[c][i].devsp, tmport++);
3572                 outb(0, tmport++);
3573                 outb(satn[6], tmport++);
3574                 outb(satn[7], tmport++);
3575                 tmport += 0x03;
3576                 outb(satn[8], tmport);
3577                 tmport += 0x07;
3578
3579                 while ((inb(tmport) & 0x80) == 0x00)
3580                         cpu_relax();
3581                 tmport -= 0x08;
3582                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3583                         continue;
3584                 }
3585                 while (inb(tmport) != 0x8e)
3586                         cpu_relax();
3587 try_wide:
3588                 j = 0;
3589                 tmport = wkport + 0x14;
3590                 outb(0x05, tmport);
3591                 tmport += 0x04;
3592                 outb(0x20, tmport);
3593                 tmport += 0x07;
3594
3595                 while ((inb(tmport) & 0x80) == 0) {
3596                         if ((inb(tmport) & 0x01) != 0) {
3597                                 tmport -= 0x06;
3598                                 outb(wide[j++], tmport);
3599                                 tmport += 0x06;
3600                         }
3601                         cpu_relax();
3602                 }
3603                 tmport -= 0x08;
3604                 while ((inb(tmport) & 0x80) == 0x00)
3605                         cpu_relax();
3606                 j = inb(tmport) & 0x0f;
3607                 if (j == 0x0f) {
3608                         goto widep_in;
3609                 }
3610                 if (j == 0x0a) {
3611                         goto widep_cmd;
3612                 }
3613                 if (j == 0x0e) {
3614                         goto try_wide;
3615                 }
3616                 continue;
3617 widep_out:
3618                 tmport = wkport + 0x18;
3619                 outb(0x20, tmport);
3620                 tmport += 0x07;
3621                 while ((inb(tmport) & 0x80) == 0) {
3622                         if ((inb(tmport) & 0x01) != 0) {
3623                                 tmport -= 0x06;
3624                                 outb(0, tmport);
3625                                 tmport += 0x06;
3626                         }
3627                         cpu_relax();
3628                 }
3629                 tmport -= 0x08;
3630                 j = inb(tmport) & 0x0f;
3631                 if (j == 0x0f) {
3632                         goto widep_in;
3633                 }
3634                 if (j == 0x0a) {
3635                         goto widep_cmd;
3636                 }
3637                 if (j == 0x0e) {
3638                         goto widep_out;
3639                 }
3640                 continue;
3641 widep_in:
3642                 tmport = wkport + 0x14;
3643                 outb(0xff, tmport);
3644                 tmport += 0x04;
3645                 outb(0x20, tmport);
3646                 tmport += 0x07;
3647                 k = 0;
3648 widep_in1:
3649                 j = inb(tmport);
3650                 if ((j & 0x01) != 0) {
3651                         tmport -= 0x06;
3652                         mbuf[k++] = inb(tmport);
3653                         tmport += 0x06;
3654                         goto widep_in1;
3655                 }
3656                 if ((j & 0x80) == 0x00) {
3657                         goto widep_in1;
3658                 }
3659                 tmport -= 0x08;
3660                 j = inb(tmport) & 0x0f;
3661                 if (j == 0x0f) {
3662                         goto widep_in;
3663                 }
3664                 if (j == 0x0a) {
3665                         goto widep_cmd;
3666                 }
3667                 if (j == 0x0e) {
3668                         goto widep_out;
3669                 }
3670                 continue;
3671 widep_cmd:
3672                 tmport = wkport + 0x10;
3673                 outb(0x30, tmport);
3674                 tmport = wkport + 0x14;
3675                 outb(0x00, tmport);
3676                 tmport += 0x04;
3677                 outb(0x08, tmport);
3678                 tmport += 0x07;
3679                 while ((inb(tmport) & 0x80) == 0x00)
3680                         cpu_relax();
3681                 tmport -= 0x08;
3682                 j = inb(tmport);
3683                 if (j != 0x16) {
3684                         if (j == 0x4e) {
3685                                 goto widep_out;
3686                         }
3687                         continue;
3688                 }
3689                 if (mbuf[0] != 0x01) {
3690                         goto not_wide;
3691                 }
3692                 if (mbuf[1] != 0x02) {
3693                         goto not_wide;
3694                 }
3695                 if (mbuf[2] != 0x03) {
3696                         goto not_wide;
3697                 }
3698                 if (mbuf[3] != 0x01) {
3699                         goto not_wide;
3700                 }
3701                 m = 1;
3702                 m = m << i;
3703                 dev->wide_id[c] |= m;
3704 not_wide:
3705                 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) ||
3706                     ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3707                         m = 1;
3708                         m = m << i;
3709                         if ((dev->async[c] & m) != 0) {
3710                            goto set_sync;
3711                         }
3712                 }
3713                 continue;
3714 set_sync:
3715                 if (dev->sp[c][i] == 0x02) {
3716                    synu[4]=0x0c;
3717                    synuw[4]=0x0c;
3718                 } else {
3719                    if (dev->sp[c][i] >= 0x03) {
3720                       synu[4]=0x0a;
3721                       synuw[4]=0x0a;
3722                    }
3723                 }
3724                 tmport = wkport + 0x1b;
3725                 j = 0;
3726                 if ((m & dev->wide_id[c]) != 0) {
3727                         j |= 0x01;
3728                 }
3729                 outb(j, tmport);
3730                 tmport = wkport + 0x03;
3731                 outb(satn[0], tmport++);
3732                 outb(satn[1], tmport++);
3733                 outb(satn[2], tmport++);
3734                 outb(satn[3], tmport++);
3735                 outb(satn[4], tmport++);
3736                 outb(satn[5], tmport++);
3737                 tmport += 0x06;
3738                 outb(0, tmport);
3739                 tmport += 0x02;
3740                 outb(dev->id[c][i].devsp, tmport++);
3741                 outb(0, tmport++);
3742                 outb(satn[6], tmport++);
3743                 outb(satn[7], tmport++);
3744                 tmport += 0x03;
3745                 outb(satn[8], tmport);
3746                 tmport += 0x07;
3747
3748                 while ((inb(tmport) & 0x80) == 0x00)
3749                         cpu_relax();
3750                 tmport -= 0x08;
3751                 if ((inb(tmport) != 0x11) && (inb(tmport) != 0x8e)) {
3752                         continue;
3753                 }
3754                 while (inb(tmport) != 0x8e)
3755                         cpu_relax();
3756 try_sync:
3757                 j = 0;
3758                 tmport = wkport + 0x14;
3759                 outb(0x06, tmport);
3760                 tmport += 0x04;
3761                 outb(0x20, tmport);
3762                 tmport += 0x07;
3763
3764                 while ((inb(tmport) & 0x80) == 0) {
3765                         if ((inb(tmport) & 0x01) != 0) {
3766                                 tmport -= 0x06;
3767                                 if ((m & dev->wide_id[c]) != 0) {
3768                                         if ((m & dev->ultra_map[c]) != 0) {
3769                                                 outb(synuw[j++], tmport);
3770                                         } else {
3771                                                 outb(synw[j++], tmport);
3772                                         }
3773                                 } else {
3774                                         if ((m & dev->ultra_map[c]) != 0) {
3775                                                 outb(synu[j++], tmport);
3776                                         } else {
3777                                                 outb(synn[j++], tmport);
3778                                         }
3779                                 }
3780                                 tmport += 0x06;
3781                         }
3782                 }
3783                 tmport -= 0x08;
3784                 while ((inb(tmport) & 0x80) == 0x00)
3785                         cpu_relax();
3786                 j = inb(tmport) & 0x0f;
3787                 if (j == 0x0f) {
3788                         goto phase_ins;
3789                 }
3790                 if (j == 0x0a) {
3791                         goto phase_cmds;
3792                 }
3793                 if (j == 0x0e) {
3794                         goto try_sync;
3795                 }
3796                 continue;
3797 phase_outs:
3798                 tmport = wkport + 0x18;
3799                 outb(0x20, tmport);
3800                 tmport += 0x07;
3801                 while ((inb(tmport) & 0x80) == 0x00) {
3802                         if ((inb(tmport) & 0x01) != 0x00) {
3803                                 tmport -= 0x06;
3804                                 outb(0x00, tmport);
3805                                 tmport += 0x06;
3806                         }
3807                         cpu_relax();
3808                 }
3809                 tmport -= 0x08;
3810                 j = inb(tmport);
3811                 if (j == 0x85) {
3812                         goto tar_dcons;
3813                 }
3814                 j &= 0x0f;
3815                 if (j == 0x0f) {
3816                         goto phase_ins;
3817                 }
3818                 if (j == 0x0a) {
3819                         goto phase_cmds;
3820                 }
3821                 if (j == 0x0e) {
3822                         goto phase_outs;
3823                 }
3824                 continue;
3825 phase_ins:
3826                 tmport = wkport + 0x14;
3827                 outb(0x06, tmport);
3828                 tmport += 0x04;
3829                 outb(0x20, tmport);
3830                 tmport += 0x07;
3831                 k = 0;
3832 phase_ins1:
3833                 j = inb(tmport);
3834                 if ((j & 0x01) != 0x00) {
3835                         tmport -= 0x06;
3836                         mbuf[k++] = inb(tmport);
3837                         tmport += 0x06;
3838                         goto phase_ins1;
3839                 }
3840                 if ((j & 0x80) == 0x00) {
3841                         goto phase_ins1;
3842                 }
3843                 tmport -= 0x08;
3844                 while ((inb(tmport) & 0x80) == 0x00);
3845                 j = inb(tmport);
3846                 if (j == 0x85) {
3847                         goto tar_dcons;
3848                 }
3849                 j &= 0x0f;
3850                 if (j == 0x0f) {
3851                         goto phase_ins;
3852                 }
3853                 if (j == 0x0a) {
3854                         goto phase_cmds;
3855                 }
3856                 if (j == 0x0e) {
3857                         goto phase_outs;
3858                 }
3859                 continue;
3860 phase_cmds:
3861                 tmport = wkport + 0x10;
3862                 outb(0x30, tmport);
3863 tar_dcons:
3864                 tmport = wkport + 0x14;
3865                 outb(0x00, tmport);
3866                 tmport += 0x04;
3867                 outb(0x08, tmport);
3868                 tmport += 0x07;
3869                 while ((inb(tmport) & 0x80) == 0x00)
3870                         cpu_relax();
3871                 tmport -= 0x08;
3872                 j = inb(tmport);
3873                 if (j != 0x16) {
3874                         continue;
3875                 }
3876                 if (mbuf[0] != 0x01) {
3877                         continue;
3878                 }
3879                 if (mbuf[1] != 0x03) {
3880                         continue;
3881                 }
3882                 if (mbuf[4] == 0x00) {
3883                         continue;
3884                 }
3885                 if (mbuf[3] > 0x64) {
3886                         continue;
3887                 }
3888                 if (mbuf[4] > 0x0e) {
3889                         mbuf[4] = 0x0e;
3890                 }
3891                 dev->id[c][i].devsp = mbuf[4];
3892                 if (mbuf[3] < 0x0c){
3893                         j = 0xb0;
3894                         goto set_syn_ok;
3895                 }
3896                 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3897                         j = 0xa0;
3898                         goto set_syn_ok;
3899                 }
3900                 if (mbuf[3] < 0x1a) {
3901                         j = 0x20;
3902                         goto set_syn_ok;
3903                 }
3904                 if (mbuf[3] < 0x33) {
3905                         j = 0x40;
3906                         goto set_syn_ok;
3907                 }
3908                 if (mbuf[3] < 0x4c) {
3909                         j = 0x50;
3910                         goto set_syn_ok;
3911                 }
3912                 j = 0x60;
3913               set_syn_ok:
3914                 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3915 #ifdef ED_DBGP
3916                 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3917 #endif
3918         }
3919         tmport = wkport + 0x16;
3920         outb(0x80, tmport);
3921 }
3922
3923 module_init(atp870u_init);
3924 module_exit(atp870u_exit);
3925