drivers/platform/x86/intel_ips.c

   1 /*
   2  * Copyright (c) 2009-2010 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * The full GNU General Public License is included in this distribution in
  18  * the file called "COPYING".
  19  *
  20  * Authors:
  21  *      Jesse Barnes <jbarnes@virtuousgeek.org>
  22  */
  23
  24 /*
  25  * Some Intel Ibex Peak based platforms support so-called "intelligent
  26  * power sharing", which allows the CPU and GPU to cooperate to maximize
  27  * performance within a given TDP (thermal design point).  This driver
  28  * performs the coordination between the CPU and GPU, monitors thermal and
  29  * power statistics in the platform, and initializes power monitoring
  30  * hardware.  It also provides a few tunables to control behavior.  Its
  31  * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
  32  * by tracking power and thermal budget; secondarily it can boost turbo
  33  * performance by allocating more power or thermal budget to the CPU or GPU
  34  * based on available headroom and activity.
  35  *
  36  * The basic algorithm is driven by a 5s moving average of tempurature.  If
  37  * thermal headroom is available, the CPU and/or GPU power clamps may be
  38  * adjusted upwards.  If we hit the thermal ceiling or a thermal trigger,
  39  * we scale back the clamp.  Aside from trigger events (when we're critically
  40  * close or over our TDP) we don't adjust the clamps more than once every
  41  * five seconds.
  42  *
  43  * The thermal device (device 31, function 6) has a set of registers that
  44  * are updated by the ME firmware.  The ME should also take the clamp values
  45  * written to those registers and write them to the CPU, but we currently
  46  * bypass that functionality and write the CPU MSR directly.
  47  *
  48  * UNSUPPORTED:
  49  *   - dual MCP configs
  50  *
  51  * TODO:
  52  *   - handle CPU hotplug
  53  *   - provide turbo enable/disable api
  54  *
  55  * Related documents:
  56  *   - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
  57  *   - CDI 401376 - Ibex Peak EDS
  58  *   - ref 26037, 26641 - IPS BIOS spec
  59  *   - ref 26489 - Nehalem BIOS writer's guide
  60  *   - ref 26921 - Ibex Peak BIOS Specification
  61  */
  62
  63 #include <linux/debugfs.h>
  64 #include <linux/delay.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/kernel.h>
  67 #include <linux/kthread.h>
  68 #include <linux/module.h>
  69 #include <linux/pci.h>
  70 #include <linux/sched.h>
  71 #include <linux/seq_file.h>
  72 #include <linux/string.h>
  73 #include <linux/tick.h>
  74 #include <linux/timer.h>
  75 #include <drm/i915_drm.h>
  76 #include <asm/msr.h>
  77 #include <asm/processor.h>
  78 #include "intel_ips.h"
  79
  80 #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
  81
  82 /*
  83  * Package level MSRs for monitor/control
  84  */
  85 #define PLATFORM_INFO   0xce
  86 #define   PLATFORM_TDP          (1<<29)
  87 #define   PLATFORM_RATIO        (1<<28)
  88
  89 #define IA32_MISC_ENABLE        0x1a0
  90 #define   IA32_MISC_TURBO_EN    (1ULL<<38)
  91
  92 #define TURBO_POWER_CURRENT_LIMIT       0x1ac
  93 #define   TURBO_TDC_OVR_EN      (1UL<<31)
  94 #define   TURBO_TDC_MASK        (0x000000007fff0000UL)
  95 #define   TURBO_TDC_SHIFT       (16)
  96 #define   TURBO_TDP_OVR_EN      (1UL<<15)
  97 #define   TURBO_TDP_MASK        (0x0000000000003fffUL)
  98
  99 /*
 100  * Core/thread MSRs for monitoring
 101  */
 102 #define IA32_PERF_CTL           0x199
 103 #define   IA32_PERF_TURBO_DIS   (1ULL<<32)
 104
 105 /*
 106  * Thermal PCI device regs
 107  */
 108 #define THM_CFG_TBAR    0x10
 109 #define THM_CFG_TBAR_HI 0x14
 110
 111 #define THM_TSIU        0x00
 112 #define THM_TSE         0x01
 113 #define   TSE_EN        0xb8
 114 #define THM_TSS         0x02
 115 #define THM_TSTR        0x03
 116 #define THM_TSTTP       0x04
 117 #define THM_TSCO        0x08
 118 #define THM_TSES        0x0c
 119 #define THM_TSGPEN      0x0d
 120 #define   TSGPEN_HOT_LOHI       (1<<1)
 121 #define   TSGPEN_CRIT_LOHI      (1<<2)
 122 #define THM_TSPC        0x0e
 123 #define THM_PPEC        0x10
 124 #define THM_CTA         0x12
 125 #define THM_PTA         0x14
 126 #define   PTA_SLOPE_MASK        (0xff00)
 127 #define   PTA_SLOPE_SHIFT       8
 128 #define   PTA_OFFSET_MASK       (0x00ff)
 129 #define THM_MGTA        0x16
 130 #define   MGTA_SLOPE_MASK       (0xff00)
 131 #define   MGTA_SLOPE_SHIFT      8
 132 #define   MGTA_OFFSET_MASK      (0x00ff)
 133 #define THM_TRC         0x1a
 134 #define   TRC_CORE2_EN  (1<<15)
 135 #define   TRC_THM_EN    (1<<12)
 136 #define   TRC_C6_WAR    (1<<8)
 137 #define   TRC_CORE1_EN  (1<<7)
 138 #define   TRC_CORE_PWR  (1<<6)
 139 #define   TRC_PCH_EN    (1<<5)
 140 #define   TRC_MCH_EN    (1<<4)
 141 #define   TRC_DIMM4     (1<<3)
 142 #define   TRC_DIMM3     (1<<2)
 143 #define   TRC_DIMM2     (1<<1)
 144 #define   TRC_DIMM1     (1<<0)
 145 #define THM_TES         0x20
 146 #define THM_TEN         0x21
 147 #define   TEN_UPDATE_EN 1
 148 #define THM_PSC         0x24
 149 #define   PSC_NTG       (1<<0) /* No GFX turbo support */
 150 #define   PSC_NTPC      (1<<1) /* No CPU turbo support */
 151 #define   PSC_PP_DEF    (0<<2) /* Perf policy up to driver */
 152 #define   PSP_PP_PC     (1<<2) /* BIOS prefers CPU perf */
 153 #define   PSP_PP_BAL    (2<<2) /* BIOS wants balanced perf */
 154 #define   PSP_PP_GFX    (3<<2) /* BIOS prefers GFX perf */
 155 #define   PSP_PBRT      (1<<4) /* BIOS run time support */
 156 #define THM_CTV1        0x30
 157 #define   CTV_TEMP_ERROR (1<<15)
 158 #define   CTV_TEMP_MASK 0x3f
 159 #define   CTV_
 160 #define THM_CTV2        0x32
 161 #define THM_CEC         0x34 /* undocumented power accumulator in joules */
 162 #define THM_AE          0x3f
 163 #define THM_HTS         0x50 /* 32 bits */
 164 #define   HTS_PCPL_MASK (0x7fe00000)
 165 #define   HTS_PCPL_SHIFT 21
 166 #define   HTS_GPL_MASK  (0x001ff000)
 167 #define   HTS_GPL_SHIFT 12
 168 #define   HTS_PP_MASK   (0x00000c00)
 169 #define   HTS_PP_SHIFT  10
 170 #define   HTS_PP_DEF    0
 171 #define   HTS_PP_PROC   1
 172 #define   HTS_PP_BAL    2
 173 #define   HTS_PP_GFX    3
 174 #define   HTS_PCTD_DIS  (1<<9)
 175 #define   HTS_GTD_DIS   (1<<8)
 176 #define   HTS_PTL_MASK  (0x000000fe)
 177 #define   HTS_PTL_SHIFT 1
 178 #define   HTS_NVV       (1<<0)
 179 #define THM_HTSHI       0x54 /* 16 bits */
 180 #define   HTS2_PPL_MASK         (0x03ff)
 181 #define   HTS2_PRST_MASK        (0x3c00)
 182 #define   HTS2_PRST_SHIFT       10
 183 #define   HTS2_PRST_UNLOADED    0
 184 #define   HTS2_PRST_RUNNING     1
 185 #define   HTS2_PRST_TDISOP      2 /* turbo disabled due to power */
 186 #define   HTS2_PRST_TDISHT      3 /* turbo disabled due to high temp */
 187 #define   HTS2_PRST_TDISUSR     4 /* user disabled turbo */
 188 #define   HTS2_PRST_TDISPLAT    5 /* platform disabled turbo */
 189 #define   HTS2_PRST_TDISPM      6 /* power management disabled turbo */
 190 #define   HTS2_PRST_TDISERR     7 /* some kind of error disabled turbo */
 191 #define THM_PTL         0x56
 192 #define THM_MGTV        0x58
 193 #define   TV_MASK       0x000000000000ff00
 194 #define   TV_SHIFT      8
 195 #define THM_PTV         0x60
 196 #define   PTV_MASK      0x00ff
 197 #define THM_MMGPC       0x64
 198 #define THM_MPPC        0x66
 199 #define THM_MPCPC       0x68
 200 #define THM_TSPIEN      0x82
 201 #define   TSPIEN_AUX_LOHI       (1<<0)
 202 #define   TSPIEN_HOT_LOHI       (1<<1)
 203 #define   TSPIEN_CRIT_LOHI      (1<<2)
 204 #define   TSPIEN_AUX2_LOHI      (1<<3)
 205 #define THM_TSLOCK      0x83
 206 #define THM_ATR         0x84
 207 #define THM_TOF         0x87
 208 #define THM_STS         0x98
 209 #define   STS_PCPL_MASK         (0x7fe00000)
 210 #define   STS_PCPL_SHIFT        21
 211 #define   STS_GPL_MASK          (0x001ff000)
 212 #define   STS_GPL_SHIFT         12
 213 #define   STS_PP_MASK           (0x00000c00)
 214 #define   STS_PP_SHIFT          10
 215 #define   STS_PP_DEF            0
 216 #define   STS_PP_PROC           1
 217 #define   STS_PP_BAL            2
 218 #define   STS_PP_GFX            3
 219 #define   STS_PCTD_DIS          (1<<9)
 220 #define   STS_GTD_DIS           (1<<8)
 221 #define   STS_PTL_MASK          (0x000000fe)
 222 #define   STS_PTL_SHIFT         1
 223 #define   STS_NVV               (1<<0)
 224 #define THM_SEC         0x9c
 225 #define   SEC_ACK       (1<<0)
 226 #define THM_TC3         0xa4
 227 #define THM_TC1         0xa8
 228 #define   STS_PPL_MASK          (0x0003ff00)
 229 #define   STS_PPL_SHIFT         16
 230 #define THM_TC2         0xac
 231 #define THM_DTV         0xb0
 232 #define THM_ITV         0xd8
 233 #define   ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
 234 #define   ITV_ME_SEQNO_SHIFT (16)
 235 #define   ITV_MCH_TEMP_MASK 0x0000ff00
 236 #define   ITV_MCH_TEMP_SHIFT (8)
 237 #define   ITV_PCH_TEMP_MASK 0x000000ff
 238
 239 #define thm_readb(off) readb(ips->regmap + (off))
 240 #define thm_readw(off) readw(ips->regmap + (off))
 241 #define thm_readl(off) readl(ips->regmap + (off))
 242 #define thm_readq(off) readq(ips->regmap + (off))
 243
 244 #define thm_writeb(off, val) writeb((val), ips->regmap + (off))
 245 #define thm_writew(off, val) writew((val), ips->regmap + (off))
 246 #define thm_writel(off, val) writel((val), ips->regmap + (off))
 247
 248 static const int IPS_ADJUST_PERIOD = 5000; /* ms */
 249 static bool late_i915_load = false;
 250
 251 /* For initial average collection */
 252 static const int IPS_SAMPLE_PERIOD = 200; /* ms */
 253 static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */
 254 #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
 255
 256 /* Per-SKU limits */
 257 struct ips_mcp_limits {
 258         int cpu_family;
 259         int cpu_model; /* includes extended model... */
 260         int mcp_power_limit; /* mW units */
 261         int core_power_limit;
 262         int mch_power_limit;
 263         int core_temp_limit; /* degrees C */
 264         int mch_temp_limit;
 265 };
 266
 267 /* Max temps are -10 degrees C to avoid PROCHOT# */
 268
 269 struct ips_mcp_limits ips_sv_limits = {
 270         .mcp_power_limit = 35000,
 271         .core_power_limit = 29000,
 272         .mch_power_limit = 20000,
 273         .core_temp_limit = 95,
 274         .mch_temp_limit = 90
 275 };
 276
 277 struct ips_mcp_limits ips_lv_limits = {
 278         .mcp_power_limit = 25000,
 279         .core_power_limit = 21000,
 280         .mch_power_limit = 13000,
 281         .core_temp_limit = 95,
 282         .mch_temp_limit = 90
 283 };
 284
 285 struct ips_mcp_limits ips_ulv_limits = {
 286         .mcp_power_limit = 18000,
 287         .core_power_limit = 14000,
 288         .mch_power_limit = 11000,
 289         .core_temp_limit = 95,
 290         .mch_temp_limit = 90
 291 };
 292
 293 struct ips_driver {
 294         struct pci_dev *dev;
 295         void *regmap;
 296         struct task_struct *monitor;
 297         struct task_struct *adjust;
 298         struct dentry *debug_root;
 299
 300         /* Average CPU core temps (all averages in .01 degrees C for precision) */
 301         u16 ctv1_avg_temp;
 302         u16 ctv2_avg_temp;
 303         /* GMCH average */
 304         u16 mch_avg_temp;
 305         /* Average for the CPU (both cores?) */
 306         u16 mcp_avg_temp;
 307         /* Average power consumption (in mW) */
 308         u32 cpu_avg_power;
 309         u32 mch_avg_power;
 310
 311         /* Offset values */
 312         u16 cta_val;
 313         u16 pta_val;
 314         u16 mgta_val;
 315
 316         /* Maximums & prefs, protected by turbo status lock */
 317         spinlock_t turbo_status_lock;
 318         u16 mcp_temp_limit;
 319         u16 mcp_power_limit;
 320         u16 core_power_limit;
 321         u16 mch_power_limit;
 322         bool cpu_turbo_enabled;
 323         bool __cpu_turbo_on;
 324         bool gpu_turbo_enabled;
 325         bool __gpu_turbo_on;
 326         bool gpu_preferred;
 327         bool poll_turbo_status;
 328         bool second_cpu;
 329         bool turbo_toggle_allowed;
 330         struct ips_mcp_limits *limits;
 331
 332         /* Optional MCH interfaces for if i915 is in use */
 333         unsigned long (*read_mch_val)(void);
 334         bool (*gpu_raise)(void);
 335         bool (*gpu_lower)(void);
 336         bool (*gpu_busy)(void);
 337         bool (*gpu_turbo_disable)(void);
 338
 339         /* For restoration at unload */
 340         u64 orig_turbo_limit;
 341         u64 orig_turbo_ratios;
 342 };
 343
 344 static bool
 345 ips_gpu_turbo_enabled(struct ips_driver *ips);
 346
 347 /**
 348  * ips_cpu_busy - is CPU busy?
 349  * @ips: IPS driver struct
 350  *
 351  * Check CPU for load to see whether we should increase its thermal budget.
 352  *
 353  * RETURNS:
 354  * True if the CPU could use more power, false otherwise.
 355  */
 356 static bool ips_cpu_busy(struct ips_driver *ips)
 357 {
 358         if ((avenrun[0] >> FSHIFT) > 1)
 359                 return true;
 360
 361         return false;
 362 }
 363
 364 /**
 365  * ips_cpu_raise - raise CPU power clamp
 366  * @ips: IPS driver struct
 367  *
 368  * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
 369  * this platform.
 370  *
 371  * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
 372  * long as we haven't hit the TDP limit for the SKU).
 373  */
 374 static void ips_cpu_raise(struct ips_driver *ips)
 375 {
 376         u64 turbo_override;
 377         u16 cur_tdp_limit, new_tdp_limit;
 378
 379         if (!ips->cpu_turbo_enabled)
 380                 return;
 381
 382         rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 383
 384         cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
 385         new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
 386
 387         /* Clamp to SKU TDP limit */
 388         if (((new_tdp_limit * 10) / 8) > ips->core_power_limit)
 389                 new_tdp_limit = cur_tdp_limit;
 390
 391         thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8);
 392
 393         turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN;
 394         wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 395
 396         turbo_override &= ~TURBO_TDP_MASK;
 397         turbo_override |= new_tdp_limit;
 398
 399         wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 400 }
 401
 402 /**
 403  * ips_cpu_lower - lower CPU power clamp
 404  * @ips: IPS driver struct
 405  *
 406  * Lower CPU power clamp b %IPS_CPU_STEP if possible.
 407  *
 408  * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
 409  * as low as the platform limits will allow (though we could go lower there
 410  * wouldn't be much point).
 411  */
 412 static void ips_cpu_lower(struct ips_driver *ips)
 413 {
 414         u64 turbo_override;
 415         u16 cur_limit, new_limit;
 416
 417         rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 418
 419         cur_limit = turbo_override & TURBO_TDP_MASK;
 420         new_limit = cur_limit - 8; /* 1W decrease */
 421
 422         /* Clamp to SKU TDP limit */
 423         if (new_limit  < (ips->orig_turbo_limit & TURBO_TDP_MASK))
 424                 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK;
 425
 426         thm_writew(THM_MPCPC, (new_limit * 10) / 8);
 427
 428         turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN;
 429         wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 430
 431         turbo_override &= ~TURBO_TDP_MASK;
 432         turbo_override |= new_limit;
 433
 434         wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
 435 }
 436
 437 /**
 438  * do_enable_cpu_turbo - internal turbo enable function
 439  * @data: unused
 440  *
 441  * Internal function for actually updating MSRs.  When we enable/disable
 442  * turbo, we need to do it on each CPU; this function is the one called
 443  * by on_each_cpu() when needed.
 444  */
 445 static void do_enable_cpu_turbo(void *data)
 446 {
 447         u64 perf_ctl;
 448
 449         rdmsrl(IA32_PERF_CTL, perf_ctl);
 450         if (perf_ctl & IA32_PERF_TURBO_DIS) {
 451                 perf_ctl &= ~IA32_PERF_TURBO_DIS;
 452                 wrmsrl(IA32_PERF_CTL, perf_ctl);
 453         }
 454 }
 455
 456 /**
 457  * ips_enable_cpu_turbo - enable turbo mode on all CPUs
 458  * @ips: IPS driver struct
 459  *
 460  * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
 461  * all logical threads.
 462  */
 463 static void ips_enable_cpu_turbo(struct ips_driver *ips)
 464 {
 465         /* Already on, no need to mess with MSRs */
 466         if (ips->__cpu_turbo_on)
 467                 return;
 468
 469         if (ips->turbo_toggle_allowed)
 470                 on_each_cpu(do_enable_cpu_turbo, ips, 1);
 471
 472         ips->__cpu_turbo_on = true;
 473 }
 474
 475 /**
 476  * do_disable_cpu_turbo - internal turbo disable function
 477  * @data: unused
 478  *
 479  * Internal function for actually updating MSRs.  When we enable/disable
 480  * turbo, we need to do it on each CPU; this function is the one called
 481  * by on_each_cpu() when needed.
 482  */
 483 static void do_disable_cpu_turbo(void *data)
 484 {
 485         u64 perf_ctl;
 486
 487         rdmsrl(IA32_PERF_CTL, perf_ctl);
 488         if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
 489                 perf_ctl |= IA32_PERF_TURBO_DIS;
 490                 wrmsrl(IA32_PERF_CTL, perf_ctl);
 491         }
 492 }
 493
 494 /**
 495  * ips_disable_cpu_turbo - disable turbo mode on all CPUs
 496  * @ips: IPS driver struct
 497  *
 498  * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
 499  * all logical threads.
 500  */
 501 static void ips_disable_cpu_turbo(struct ips_driver *ips)
 502 {
 503         /* Already off, leave it */
 504         if (!ips->__cpu_turbo_on)
 505                 return;
 506
 507         if (ips->turbo_toggle_allowed)
 508                 on_each_cpu(do_disable_cpu_turbo, ips, 1);
 509
 510         ips->__cpu_turbo_on = false;
 511 }
 512
 513 /**
 514  * ips_gpu_busy - is GPU busy?
 515  * @ips: IPS driver struct
 516  *
 517  * Check GPU for load to see whether we should increase its thermal budget.
 518  * We need to call into the i915 driver in this case.
 519  *
 520  * RETURNS:
 521  * True if the GPU could use more power, false otherwise.
 522  */
 523 static bool ips_gpu_busy(struct ips_driver *ips)
 524 {
 525         if (!ips_gpu_turbo_enabled(ips))
 526                 return false;
 527
 528         return ips->gpu_busy();
 529 }
 530
 531 /**
 532  * ips_gpu_raise - raise GPU power clamp
 533  * @ips: IPS driver struct
 534  *
 535  * Raise the GPU frequency/power if possible.  We need to call into the
 536  * i915 driver in this case.
 537  */
 538 static void ips_gpu_raise(struct ips_driver *ips)
 539 {
 540         if (!ips_gpu_turbo_enabled(ips))
 541                 return;
 542
 543         if (!ips->gpu_raise())
 544                 ips->gpu_turbo_enabled = false;
 545
 546         return;
 547 }
 548
 549 /**
 550  * ips_gpu_lower - lower GPU power clamp
 551  * @ips: IPS driver struct
 552  *
 553  * Lower GPU frequency/power if possible.  Need to call i915.
 554  */
 555 static void ips_gpu_lower(struct ips_driver *ips)
 556 {
 557         if (!ips_gpu_turbo_enabled(ips))
 558                 return;
 559
 560         if (!ips->gpu_lower())
 561                 ips->gpu_turbo_enabled = false;
 562
 563         return;
 564 }
 565
 566 /**
 567  * ips_enable_gpu_turbo - notify the gfx driver turbo is available
 568  * @ips: IPS driver struct
 569  *
 570  * Call into the graphics driver indicating that it can safely use
 571  * turbo mode.
 572  */
 573 static void ips_enable_gpu_turbo(struct ips_driver *ips)
 574 {
 575         if (ips->__gpu_turbo_on)
 576                 return;
 577         ips->__gpu_turbo_on = true;
 578 }
 579
 580 /**
 581  * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
 582  * @ips: IPS driver struct
 583  *
 584  * Request that the graphics driver disable turbo mode.
 585  */
 586 static void ips_disable_gpu_turbo(struct ips_driver *ips)
 587 {
 588         /* Avoid calling i915 if turbo is already disabled */
 589         if (!ips->__gpu_turbo_on)
 590                 return;
 591
 592         if (!ips->gpu_turbo_disable())
 593                 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n");
 594         else
 595                 ips->__gpu_turbo_on = false;
 596 }
 597
 598 /**
 599  * mcp_exceeded - check whether we're outside our thermal & power limits
 600  * @ips: IPS driver struct
 601  *
 602  * Check whether the MCP is over its thermal or power budget.
 603  */
 604 static bool mcp_exceeded(struct ips_driver *ips)
 605 {
 606         unsigned long flags;
 607         bool ret = false;
 608         u32 temp_limit;
 609         u32 avg_power;
 610         const char *msg = "MCP limit exceeded: ";
 611
 612         spin_lock_irqsave(&ips->turbo_status_lock, flags);
 613
 614         temp_limit = ips->mcp_temp_limit * 100;
 615         if (ips->mcp_avg_temp > temp_limit) {
 616                 dev_info(&ips->dev->dev,
 617                         "%sAvg temp %u, limit %u\n", msg, ips->mcp_avg_temp,
 618                         temp_limit);
 619                 ret = true;
 620         }
 621
 622         avg_power = ips->cpu_avg_power + ips->mch_avg_power;
 623         if (avg_power > ips->mcp_power_limit) {
 624                 dev_info(&ips->dev->dev,
 625                         "%sAvg power %u, limit %u\n", msg, avg_power,
 626                         ips->mcp_power_limit);
 627                 ret = true;
 628         }
 629
 630         spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
 631
 632         return ret;
 633 }
 634
 635 /**
 636  * cpu_exceeded - check whether a CPU core is outside its limits
 637  * @ips: IPS driver struct
 638  * @cpu: CPU number to check
 639  *
 640  * Check a given CPU's average temp or power is over its limit.
 641  */
 642 static bool cpu_exceeded(struct ips_driver *ips, int cpu)
 643 {
 644         unsigned long flags;
 645         int avg;
 646         bool ret = false;
 647
 648         spin_lock_irqsave(&ips->turbo_status_lock, flags);
 649         avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp;
 650         if (avg > (ips->limits->core_temp_limit * 100))
 651                 ret = true;
 652         if (ips->cpu_avg_power > ips->core_power_limit * 100)
 653                 ret = true;
 654         spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
 655
 656         if (ret)
 657                 dev_info(&ips->dev->dev,
 658                          "CPU power or thermal limit exceeded\n");
 659
 660         return ret;
 661 }
 662
 663 /**
 664  * mch_exceeded - check whether the GPU is over budget
 665  * @ips: IPS driver struct
 666  *
 667  * Check the MCH temp & power against their maximums.
 668  */
 669 static bool mch_exceeded(struct ips_driver *ips)
 670 {
 671         unsigned long flags;
 672         bool ret = false;
 673
 674         spin_lock_irqsave(&ips->turbo_status_lock, flags);
 675         if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100))
 676                 ret = true;
 677         if (ips->mch_avg_power > ips->mch_power_limit)
 678                 ret = true;
 679         spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
 680
 681         return ret;
 682 }
 683
 684 /**
 685  * verify_limits - verify BIOS provided limits
 686  * @ips: IPS structure
 687  *
 688  * BIOS can optionally provide non-default limits for power and temp.  Check
 689  * them here and use the defaults if the BIOS values are not provided or
 690  * are otherwise unusable.
 691  */
 692 static void verify_limits(struct ips_driver *ips)
 693 {
 694         if (ips->mcp_power_limit < ips->limits->mcp_power_limit ||
 695             ips->mcp_power_limit > 35000)
 696                 ips->mcp_power_limit = ips->limits->mcp_power_limit;
 697
 698         if (ips->mcp_temp_limit < ips->limits->core_temp_limit ||
 699             ips->mcp_temp_limit < ips->limits->mch_temp_limit ||
 700             ips->mcp_temp_limit > 150)
 701                 ips->mcp_temp_limit = min(ips->limits->core_temp_limit,
 702                                           ips->limits->mch_temp_limit);
 703 }
 704
 705 /**
 706  * update_turbo_limits - get various limits & settings from regs
 707  * @ips: IPS driver struct
 708  *
 709  * Update the IPS power & temp limits, along with turbo enable flags,
 710  * based on latest register contents.
 711  *
 712  * Used at init time and for runtime BIOS support, which requires polling
 713  * the regs for updates (as a result of AC->DC transition for example).
 714  *
 715  * LOCKING:
 716  * Caller must hold turbo_status_lock (outside of init)
 717  */
 718 static void update_turbo_limits(struct ips_driver *ips)
 719 {
 720         u32 hts = thm_readl(THM_HTS);
 721
 722         ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS);
 723         /*
 724          * Disable turbo for now, until we can figure out why the power figures
 725          * are wrong
 726          */
 727         ips->cpu_turbo_enabled = false;
 728
 729         if (ips->gpu_busy)
 730                 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS);
 731
 732         ips->core_power_limit = thm_readw(THM_MPCPC);
 733         ips->mch_power_limit = thm_readw(THM_MMGPC);
 734         ips->mcp_temp_limit = thm_readw(THM_PTL);
 735         ips->mcp_power_limit = thm_readw(THM_MPPC);
 736
 737         verify_limits(ips);
 738         /* Ignore BIOS CPU vs GPU pref */
 739 }
 740
 741 /**
 742  * ips_adjust - adjust power clamp based on thermal state
 743  * @data: ips driver structure
 744  *
 745  * Wake up every 5s or so and check whether we should adjust the power clamp.
 746  * Check CPU and GPU load to determine which needs adjustment.  There are
 747  * several things to consider here:
 748  *   - do we need to adjust up or down?
 749  *   - is CPU busy?
 750  *   - is GPU busy?
 751  *   - is CPU in turbo?
 752  *   - is GPU in turbo?
 753  *   - is CPU or GPU preferred? (CPU is default)
 754  *
 755  * So, given the above, we do the following:
 756  *   - up (TDP available)
 757  *     - CPU not busy, GPU not busy - nothing
 758  *     - CPU busy, GPU not busy - adjust CPU up
 759  *     - CPU not busy, GPU busy - adjust GPU up
 760  *     - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
 761  *       non-preferred unit if necessary
 762  *   - down (at TDP limit)
 763  *     - adjust both CPU and GPU down if possible
 764  *
 765                 cpu+ gpu+       cpu+gpu-        cpu-gpu+        cpu-gpu-
 766 cpu < gpu <     cpu+gpu+        cpu+            gpu+            nothing
 767 cpu < gpu >=    cpu+gpu-(mcp<)  cpu+gpu-(mcp<)  gpu-            gpu-
 768 cpu >= gpu <    cpu-gpu+(mcp<)  cpu-            cpu-gpu+(mcp<)  cpu-
 769 cpu >= gpu >=   cpu-gpu-        cpu-gpu-        cpu-gpu-        cpu-gpu-
 770  *
 771  */
 772 static int ips_adjust(void *data)
 773 {
 774         struct ips_driver *ips = data;
 775         unsigned long flags;
 776
 777         dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n");
 778
 779         /*
 780          * Adjust CPU and GPU clamps every 5s if needed.  Doing it more
 781          * often isn't recommended due to ME interaction.
 782          */
 783         do {
 784                 bool cpu_busy = ips_cpu_busy(ips);
 785                 bool gpu_busy = ips_gpu_busy(ips);
 786
 787                 spin_lock_irqsave(&ips->turbo_status_lock, flags);
 788                 if (ips->poll_turbo_status)
 789                         update_turbo_limits(ips);
 790                 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
 791
 792                 /* Update turbo status if necessary */
 793                 if (ips->cpu_turbo_enabled)
 794                         ips_enable_cpu_turbo(ips);
 795                 else
 796                         ips_disable_cpu_turbo(ips);
 797
 798                 if (ips->gpu_turbo_enabled)
 799                         ips_enable_gpu_turbo(ips);
 800                 else
 801                         ips_disable_gpu_turbo(ips);
 802
 803                 /* We're outside our comfort zone, crank them down */
 804                 if (mcp_exceeded(ips)) {
 805                         ips_cpu_lower(ips);
 806                         ips_gpu_lower(ips);
 807                         goto sleep;
 808                 }
 809
 810                 if (!cpu_exceeded(ips, 0) && cpu_busy)
 811                         ips_cpu_raise(ips);
 812                 else
 813                         ips_cpu_lower(ips);
 814
 815                 if (!mch_exceeded(ips) && gpu_busy)
 816                         ips_gpu_raise(ips);
 817                 else
 818                         ips_gpu_lower(ips);
 819
 820 sleep:
 821                 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD));
 822         } while (!kthread_should_stop());
 823
 824         dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n");
 825
 826         return 0;
 827 }
 828
 829 /*
 830  * Helpers for reading out temp/power values and calculating their
 831  * averages for the decision making and monitoring functions.
 832  */
 833
 834 static u16 calc_avg_temp(struct ips_driver *ips, u16 *array)
 835 {
 836         u64 total = 0;
 837         int i;
 838         u16 avg;
 839
 840         for (i = 0; i < IPS_SAMPLE_COUNT; i++)
 841                 total += (u64)(array[i] * 100);
 842
 843         do_div(total, IPS_SAMPLE_COUNT);
 844
 845         avg = (u16)total;
 846
 847         return avg;
 848 }
 849
 850 static u16 read_mgtv(struct ips_driver *ips)
 851 {
 852         u16 ret;
 853         u64 slope, offset;
 854         u64 val;
 855
 856         val = thm_readq(THM_MGTV);
 857         val = (val & TV_MASK) >> TV_SHIFT;
 858
 859         slope = offset = thm_readw(THM_MGTA);
 860         slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT;
 861         offset = offset & MGTA_OFFSET_MASK;
 862
 863         ret = ((val * slope + 0x40) >> 7) + offset;
 864
 865         return 0; /* MCH temp reporting buggy */
 866 }
 867
 868 static u16 read_ptv(struct ips_driver *ips)
 869 {
 870         u16 val, slope, offset;
 871
 872         slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT;
 873         offset = ips->pta_val & PTA_OFFSET_MASK;
 874
 875         val = thm_readw(THM_PTV) & PTV_MASK;
 876
 877         return val;
 878 }
 879
 880 static u16 read_ctv(struct ips_driver *ips, int cpu)
 881 {
 882         int reg = cpu ? THM_CTV2 : THM_CTV1;
 883         u16 val;
 884
 885         val = thm_readw(reg);
 886         if (!(val & CTV_TEMP_ERROR))
 887                 val = (val) >> 6; /* discard fractional component */
 888         else
 889                 val = 0;
 890
 891         return val;
 892 }
 893
 894 static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period)
 895 {
 896         u32 val;
 897         u32 ret;
 898
 899         /*
 900          * CEC is in joules/65535.  Take difference over time to
 901          * get watts.
 902          */
 903         val = thm_readl(THM_CEC);
 904
 905         /* period is in ms and we want mW */
 906         ret = (((val - *last) * 1000) / period);
 907         ret = (ret * 1000) / 65535;
 908         *last = val;
 909
 910         return 0;
 911 }
 912
 913 static const u16 temp_decay_factor = 2;
 914 static u16 update_average_temp(u16 avg, u16 val)
 915 {
 916         u16 ret;
 917
 918         /* Multiply by 100 for extra precision */
 919         ret = (val * 100 / temp_decay_factor) +
 920                 (((temp_decay_factor - 1) * avg) / temp_decay_factor);
 921         return ret;
 922 }
 923
 924 static const u16 power_decay_factor = 2;
 925 static u16 update_average_power(u32 avg, u32 val)
 926 {
 927         u32 ret;
 928
 929         ret = (val / power_decay_factor) +
 930                 (((power_decay_factor - 1) * avg) / power_decay_factor);
 931
 932         return ret;
 933 }
 934
 935 static u32 calc_avg_power(struct ips_driver *ips, u32 *array)
 936 {
 937         u64 total = 0;
 938         u32 avg;
 939         int i;
 940
 941         for (i = 0; i < IPS_SAMPLE_COUNT; i++)
 942                 total += array[i];
 943
 944         do_div(total, IPS_SAMPLE_COUNT);
 945         avg = (u32)total;
 946
 947         return avg;
 948 }
 949
 950 static void monitor_timeout(unsigned long arg)
 951 {
 952         wake_up_process((struct task_struct *)arg);
 953 }
 954
 955 /**
 956  * ips_monitor - temp/power monitoring thread
 957  * @data: ips driver structure
 958  *
 959  * This is the main function for the IPS driver.  It monitors power and
 960  * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
 961  *
 962  * We keep a 5s moving average of power consumption and tempurature.  Using
 963  * that data, along with CPU vs GPU preference, we adjust the power clamps
 964  * up or down.
 965  */
 966 static int ips_monitor(void *data)
 967 {
 968         struct ips_driver *ips = data;
 969         struct timer_list timer;
 970         unsigned long seqno_timestamp, expire, last_msecs, last_sample_period;
 971         int i;
 972         u32 *cpu_samples, *mchp_samples, old_cpu_power;
 973         u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples;
 974         u8 cur_seqno, last_seqno;
 975
 976         mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 977         ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 978         ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 979         mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 980         cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 981         mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
 982         if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples ||
 983                         !cpu_samples || !mchp_samples) {
 984                 dev_err(&ips->dev->dev,
 985                         "failed to allocate sample array, ips disabled\n");
 986                 kfree(mcp_samples);
 987                 kfree(ctv1_samples);
 988                 kfree(ctv2_samples);
 989                 kfree(mch_samples);
 990                 kfree(cpu_samples);
 991                 kfree(mchp_samples);
 992                 return -ENOMEM;
 993         }
 994
 995         last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
 996                 ITV_ME_SEQNO_SHIFT;
 997         seqno_timestamp = get_jiffies_64();
 998
 999         old_cpu_power = thm_readl(THM_CEC);
1000         schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1001
1002         /* Collect an initial average */
1003         for (i = 0; i < IPS_SAMPLE_COUNT; i++) {
1004                 u32 mchp, cpu_power;
1005                 u16 val;
1006
1007                 mcp_samples[i] = read_ptv(ips);
1008
1009                 val = read_ctv(ips, 0);
1010                 ctv1_samples[i] = val;
1011
1012                 val = read_ctv(ips, 1);
1013                 ctv2_samples[i] = val;
1014
1015                 val = read_mgtv(ips);
1016                 mch_samples[i] = val;
1017
1018                 cpu_power = get_cpu_power(ips, &old_cpu_power,
1019                                           IPS_SAMPLE_PERIOD);
1020                 cpu_samples[i] = cpu_power;
1021
1022                 if (ips->read_mch_val) {
1023                         mchp = ips->read_mch_val();
1024                         mchp_samples[i] = mchp;
1025                 }
1026
1027                 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1028                 if (kthread_should_stop())
1029                         break;
1030         }
1031
1032         ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples);
1033         ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples);
1034         ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples);
1035         ips->mch_avg_temp = calc_avg_temp(ips, mch_samples);
1036         ips->cpu_avg_power = calc_avg_power(ips, cpu_samples);
1037         ips->mch_avg_power = calc_avg_power(ips, mchp_samples);
1038         kfree(mcp_samples);
1039         kfree(ctv1_samples);
1040         kfree(ctv2_samples);
1041         kfree(mch_samples);
1042         kfree(cpu_samples);
1043         kfree(mchp_samples);
1044
1045         /* Start the adjustment thread now that we have data */
1046         wake_up_process(ips->adjust);
1047
1048         /*
1049          * Ok, now we have an initial avg.  From here on out, we track the
1050          * running avg using a decaying average calculation.  This allows
1051          * us to reduce the sample frequency if the CPU and GPU are idle.
1052          */
1053         old_cpu_power = thm_readl(THM_CEC);
1054         schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1055         last_sample_period = IPS_SAMPLE_PERIOD;
1056
1057         setup_deferrable_timer_on_stack(&timer, monitor_timeout,
1058                                         (unsigned long)current);
1059         do {
1060                 u32 cpu_val, mch_val;
1061                 u16 val;
1062
1063                 /* MCP itself */
1064                 val = read_ptv(ips);
1065                 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val);
1066
1067                 /* Processor 0 */
1068                 val = read_ctv(ips, 0);
1069                 ips->ctv1_avg_temp =
1070                         update_average_temp(ips->ctv1_avg_temp, val);
1071                 /* Power */
1072                 cpu_val = get_cpu_power(ips, &old_cpu_power,
1073                                         last_sample_period);
1074                 ips->cpu_avg_power =
1075                         update_average_power(ips->cpu_avg_power, cpu_val);
1076
1077                 if (ips->second_cpu) {
1078                         /* Processor 1 */
1079                         val = read_ctv(ips, 1);
1080                         ips->ctv2_avg_temp =
1081                                 update_average_temp(ips->ctv2_avg_temp, val);
1082                 }
1083
1084                 /* MCH */
1085                 val = read_mgtv(ips);
1086                 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val);
1087                 /* Power */
1088                 if (ips->read_mch_val) {
1089                         mch_val = ips->read_mch_val();
1090                         ips->mch_avg_power =
1091                                 update_average_power(ips->mch_avg_power,
1092                                                      mch_val);
1093                 }
1094
1095                 /*
1096                  * Make sure ME is updating thermal regs.
1097                  * Note:
1098                  * If it's been more than a second since the last update,
1099                  * the ME is probably hung.
1100                  */
1101                 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1102                         ITV_ME_SEQNO_SHIFT;
1103                 if (cur_seqno == last_seqno &&
1104                     time_after(jiffies, seqno_timestamp + HZ)) {
1105                         dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n");
1106                 } else {
1107                         seqno_timestamp = get_jiffies_64();
1108                         last_seqno = cur_seqno;
1109                 }
1110
1111                 last_msecs = jiffies_to_msecs(jiffies);
1112                 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD);
1113
1114                 __set_current_state(TASK_UNINTERRUPTIBLE);
1115                 mod_timer(&timer, expire);
1116                 schedule();
1117
1118                 /* Calculate actual sample period for power averaging */
1119                 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs;
1120                 if (!last_sample_period)
1121                         last_sample_period = 1;
1122         } while (!kthread_should_stop());
1123
1124         del_timer_sync(&timer);
1125         destroy_timer_on_stack(&timer);
1126
1127         dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n");
1128
1129         return 0;
1130 }
1131
1132 #if 0
1133 #define THM_DUMPW(reg) \
1134         { \
1135         u16 val = thm_readw(reg); \
1136         dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1137         }
1138 #define THM_DUMPL(reg) \
1139         { \
1140         u32 val = thm_readl(reg); \
1141         dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1142         }
1143 #define THM_DUMPQ(reg) \
1144         { \
1145         u64 val = thm_readq(reg); \
1146         dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1147         }
1148
1149 static void dump_thermal_info(struct ips_driver *ips)
1150 {
1151         u16 ptl;
1152
1153         ptl = thm_readw(THM_PTL);
1154         dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl);
1155
1156         THM_DUMPW(THM_CTA);
1157         THM_DUMPW(THM_TRC);
1158         THM_DUMPW(THM_CTV1);
1159         THM_DUMPL(THM_STS);
1160         THM_DUMPW(THM_PTV);
1161         THM_DUMPQ(THM_MGTV);
1162 }
1163 #endif
1164
1165 /**
1166  * ips_irq_handler - handle temperature triggers and other IPS events
1167  * @irq: irq number
1168  * @arg: unused
1169  *
1170  * Handle temperature limit trigger events, generally by lowering the clamps.
1171  * If we're at a critical limit, we clamp back to the lowest possible value
1172  * to prevent emergency shutdown.
1173  */
1174 static irqreturn_t ips_irq_handler(int irq, void *arg)
1175 {
1176         struct ips_driver *ips = arg;
1177         u8 tses = thm_readb(THM_TSES);
1178         u8 tes = thm_readb(THM_TES);
1179
1180         if (!tses && !tes)
1181                 return IRQ_NONE;
1182
1183         dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses);
1184         dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes);
1185
1186         /* STS update from EC? */
1187         if (tes & 1) {
1188                 u32 sts, tc1;
1189
1190                 sts = thm_readl(THM_STS);
1191                 tc1 = thm_readl(THM_TC1);
1192
1193                 if (sts & STS_NVV) {
1194                         spin_lock(&ips->turbo_status_lock);
1195                         ips->core_power_limit = (sts & STS_PCPL_MASK) >>
1196                                 STS_PCPL_SHIFT;
1197                         ips->mch_power_limit = (sts & STS_GPL_MASK) >>
1198                                 STS_GPL_SHIFT;
1199                         /* ignore EC CPU vs GPU pref */
1200                         ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS);
1201                         /*
1202                          * Disable turbo for now, until we can figure
1203                          * out why the power figures are wrong
1204                          */
1205                         ips->cpu_turbo_enabled = false;
1206                         if (ips->gpu_busy)
1207                                 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS);
1208                         ips->mcp_temp_limit = (sts & STS_PTL_MASK) >>
1209                                 STS_PTL_SHIFT;
1210                         ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >>
1211                                 STS_PPL_SHIFT;
1212                         verify_limits(ips);
1213                         spin_unlock(&ips->turbo_status_lock);
1214
1215                         thm_writeb(THM_SEC, SEC_ACK);
1216                 }
1217                 thm_writeb(THM_TES, tes);
1218         }
1219
1220         /* Thermal trip */
1221         if (tses) {
1222                 dev_warn(&ips->dev->dev,
1223                          "thermal trip occurred, tses: 0x%04x\n", tses);
1224                 thm_writeb(THM_TSES, tses);
1225         }
1226
1227         return IRQ_HANDLED;
1228 }
1229
1230 #ifndef CONFIG_DEBUG_FS
1231 static void ips_debugfs_init(struct ips_driver *ips) { return; }
1232 static void ips_debugfs_cleanup(struct ips_driver *ips) { return; }
1233 #else
1234
1235 /* Expose current state and limits in debugfs if possible */
1236
1237 struct ips_debugfs_node {
1238         struct ips_driver *ips;
1239         char *name;
1240         int (*show)(struct seq_file *m, void *data);
1241 };
1242
1243 static int show_cpu_temp(struct seq_file *m, void *data)
1244 {
1245         struct ips_driver *ips = m->private;
1246
1247         seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100,
1248                    ips->ctv1_avg_temp % 100);
1249
1250         return 0;
1251 }
1252
1253 static int show_cpu_power(struct seq_file *m, void *data)
1254 {
1255         struct ips_driver *ips = m->private;
1256
1257         seq_printf(m, "%dmW\n", ips->cpu_avg_power);
1258
1259         return 0;
1260 }
1261
1262 static int show_cpu_clamp(struct seq_file *m, void *data)
1263 {
1264         u64 turbo_override;
1265         int tdp, tdc;
1266
1267         rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1268
1269         tdp = (int)(turbo_override & TURBO_TDP_MASK);
1270         tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
1271
1272         /* Convert to .1W/A units */
1273         tdp = tdp * 10 / 8;
1274         tdc = tdc * 10 / 8;
1275
1276         /* Watts Amperes */
1277         seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10,
1278                    tdc / 10, tdc % 10);
1279
1280         return 0;
1281 }
1282
1283 static int show_mch_temp(struct seq_file *m, void *data)
1284 {
1285         struct ips_driver *ips = m->private;
1286
1287         seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100,
1288                    ips->mch_avg_temp % 100);
1289
1290         return 0;
1291 }
1292
1293 static int show_mch_power(struct seq_file *m, void *data)
1294 {
1295         struct ips_driver *ips = m->private;
1296
1297         seq_printf(m, "%dmW\n", ips->mch_avg_power);
1298
1299         return 0;
1300 }
1301
1302 static struct ips_debugfs_node ips_debug_files[] = {
1303         { NULL, "cpu_temp", show_cpu_temp },
1304         { NULL, "cpu_power", show_cpu_power },
1305         { NULL, "cpu_clamp", show_cpu_clamp },
1306         { NULL, "mch_temp", show_mch_temp },
1307         { NULL, "mch_power", show_mch_power },
1308 };
1309
1310 static int ips_debugfs_open(struct inode *inode, struct file *file)
1311 {
1312         struct ips_debugfs_node *node = inode->i_private;
1313
1314         return single_open(file, node->show, node->ips);
1315 }
1316
1317 static const struct file_operations ips_debugfs_ops = {
1318         .owner = THIS_MODULE,
1319         .open = ips_debugfs_open,
1320         .read = seq_read,
1321         .llseek = seq_lseek,
1322         .release = single_release,
1323 };
1324
1325 static void ips_debugfs_cleanup(struct ips_driver *ips)
1326 {
1327         if (ips->debug_root)
1328                 debugfs_remove_recursive(ips->debug_root);
1329         return;
1330 }
1331
1332 static void ips_debugfs_init(struct ips_driver *ips)
1333 {
1334         int i;
1335
1336         ips->debug_root = debugfs_create_dir("ips", NULL);
1337         if (!ips->debug_root) {
1338                 dev_err(&ips->dev->dev,
1339                         "failed to create debugfs entries: %ld\n",
1340                         PTR_ERR(ips->debug_root));
1341                 return;
1342         }
1343
1344         for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) {
1345                 struct dentry *ent;
1346                 struct ips_debugfs_node *node = &ips_debug_files[i];
1347
1348                 node->ips = ips;
1349                 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO,
1350                                           ips->debug_root, node,
1351                                           &ips_debugfs_ops);
1352                 if (!ent) {
1353                         dev_err(&ips->dev->dev,
1354                                 "failed to create debug file: %ld\n",
1355                                 PTR_ERR(ent));
1356                         goto err_cleanup;
1357                 }
1358         }
1359
1360         return;
1361
1362 err_cleanup:
1363         ips_debugfs_cleanup(ips);
1364         return;
1365 }
1366 #endif /* CONFIG_DEBUG_FS */
1367
1368 /**
1369  * ips_detect_cpu - detect whether CPU supports IPS
1370  *
1371  * Walk our list and see if we're on a supported CPU.  If we find one,
1372  * return the limits for it.
1373  */
1374 static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
1375 {
1376         u64 turbo_power, misc_en;
1377         struct ips_mcp_limits *limits = NULL;
1378         u16 tdp;
1379
1380         if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) {
1381                 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n");
1382                 goto out;
1383         }
1384
1385         rdmsrl(IA32_MISC_ENABLE, misc_en);
1386         /*
1387          * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1388          * turbo manually or we'll get an illegal MSR access, even though
1389          * turbo will still be available.
1390          */
1391         if (misc_en & IA32_MISC_TURBO_EN)
1392                 ips->turbo_toggle_allowed = true;
1393         else
1394                 ips->turbo_toggle_allowed = false;
1395
1396         if (strstr(boot_cpu_data.x86_model_id, "CPU       M"))
1397                 limits = &ips_sv_limits;
1398         else if (strstr(boot_cpu_data.x86_model_id, "CPU       L"))
1399                 limits = &ips_lv_limits;
1400         else if (strstr(boot_cpu_data.x86_model_id, "CPU       U"))
1401                 limits = &ips_ulv_limits;
1402         else {
1403                 dev_info(&ips->dev->dev, "No CPUID match found.\n");
1404                 goto out;
1405         }
1406
1407         rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power);
1408         tdp = turbo_power & TURBO_TDP_MASK;
1409
1410         /* Sanity check TDP against CPU */
1411         if (limits->core_power_limit != (tdp / 8) * 1000) {
1412                 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1413                          tdp / 8, limits->core_power_limit / 1000);
1414                 limits->core_power_limit = (tdp / 8) * 1000;
1415         }
1416
1417 out:
1418         return limits;
1419 }
1420
1421 /**
1422  * ips_get_i915_syms - try to get GPU control methods from i915 driver
1423  * @ips: IPS driver
1424  *
1425  * The i915 driver exports several interfaces to allow the IPS driver to
1426  * monitor and control graphics turbo mode.  If we can find them, we can
1427  * enable graphics turbo, otherwise we must disable it to avoid exceeding
1428  * thermal and power limits in the MCP.
1429  */
1430 static bool ips_get_i915_syms(struct ips_driver *ips)
1431 {
1432         ips->read_mch_val = symbol_get(i915_read_mch_val);
1433         if (!ips->read_mch_val)
1434                 goto out_err;
1435         ips->gpu_raise = symbol_get(i915_gpu_raise);
1436         if (!ips->gpu_raise)
1437                 goto out_put_mch;
1438         ips->gpu_lower = symbol_get(i915_gpu_lower);
1439         if (!ips->gpu_lower)
1440                 goto out_put_raise;
1441         ips->gpu_busy = symbol_get(i915_gpu_busy);
1442         if (!ips->gpu_busy)
1443                 goto out_put_lower;
1444         ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
1445         if (!ips->gpu_turbo_disable)
1446                 goto out_put_busy;
1447
1448         return true;
1449
1450 out_put_busy:
1451         symbol_put(i915_gpu_busy);
1452 out_put_lower:
1453         symbol_put(i915_gpu_lower);
1454 out_put_raise:
1455         symbol_put(i915_gpu_raise);
1456 out_put_mch:
1457         symbol_put(i915_read_mch_val);
1458 out_err:
1459         return false;
1460 }
1461
1462 static bool
1463 ips_gpu_turbo_enabled(struct ips_driver *ips)
1464 {
1465         if (!ips->gpu_busy && late_i915_load) {
1466                 if (ips_get_i915_syms(ips)) {
1467                         dev_info(&ips->dev->dev,
1468                                  "i915 driver attached, reenabling gpu turbo\n");
1469                         ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS);
1470                 }
1471         }
1472
1473         return ips->gpu_turbo_enabled;
1474 }
1475
1476 void
1477 ips_link_to_i915_driver()
1478 {
1479         /* We can't cleanly get at the various ips_driver structs from
1480          * this caller (the i915 driver), so just set a flag saying
1481          * that it's time to try getting the symbols again.
1482          */
1483         late_i915_load = true;
1484 }
1485 EXPORT_SYMBOL_GPL(ips_link_to_i915_driver);
1486
1487 static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = {
1488         { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
1489                      PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), },
1490         { 0, }
1491 };
1492
1493 MODULE_DEVICE_TABLE(pci, ips_id_table);
1494
1495 static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
1496 {
1497         u64 platform_info;
1498         struct ips_driver *ips;
1499         u32 hts;
1500         int ret = 0;
1501         u16 htshi, trc, trc_required_mask;
1502         u8 tse;
1503
1504         ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL);
1505         if (!ips)
1506                 return -ENOMEM;
1507
1508         pci_set_drvdata(dev, ips);
1509         ips->dev = dev;
1510
1511         ips->limits = ips_detect_cpu(ips);
1512         if (!ips->limits) {
1513                 dev_info(&dev->dev, "IPS not supported on this CPU\n");
1514                 ret = -ENXIO;
1515                 goto error_free;
1516         }
1517
1518         spin_lock_init(&ips->turbo_status_lock);
1519
1520         ret = pci_enable_device(dev);
1521         if (ret) {
1522                 dev_err(&dev->dev, "can't enable PCI device, aborting\n");
1523                 goto error_free;
1524         }
1525
1526         if (!pci_resource_start(dev, 0)) {
1527                 dev_err(&dev->dev, "TBAR not assigned, aborting\n");
1528                 ret = -ENXIO;
1529                 goto error_free;
1530         }
1531
1532         ret = pci_request_regions(dev, "ips thermal sensor");
1533         if (ret) {
1534                 dev_err(&dev->dev, "thermal resource busy, aborting\n");
1535                 goto error_free;
1536         }
1537
1538
1539         ips->regmap = ioremap(pci_resource_start(dev, 0),
1540                               pci_resource_len(dev, 0));
1541         if (!ips->regmap) {
1542                 dev_err(&dev->dev, "failed to map thermal regs, aborting\n");
1543                 ret = -EBUSY;
1544                 goto error_release;
1545         }
1546
1547         tse = thm_readb(THM_TSE);
1548         if (tse != TSE_EN) {
1549                 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse);
1550                 ret = -ENXIO;
1551                 goto error_unmap;
1552         }
1553
1554         trc = thm_readw(THM_TRC);
1555         trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN;
1556         if ((trc & trc_required_mask) != trc_required_mask) {
1557                 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n");
1558                 ret = -ENXIO;
1559                 goto error_unmap;
1560         }
1561
1562         if (trc & TRC_CORE2_EN)
1563                 ips->second_cpu = true;
1564
1565         update_turbo_limits(ips);
1566         dev_dbg(&dev->dev, "max cpu power clamp: %dW\n",
1567                 ips->mcp_power_limit / 10);
1568         dev_dbg(&dev->dev, "max core power clamp: %dW\n",
1569                 ips->core_power_limit / 10);
1570         /* BIOS may update limits at runtime */
1571         if (thm_readl(THM_PSC) & PSP_PBRT)
1572                 ips->poll_turbo_status = true;
1573
1574         if (!ips_get_i915_syms(ips)) {
1575                 dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n");
1576                 ips->gpu_turbo_enabled = false;
1577         } else {
1578                 dev_dbg(&dev->dev, "graphics turbo enabled\n");
1579                 ips->gpu_turbo_enabled = true;
1580         }
1581
1582         /*
1583          * Check PLATFORM_INFO MSR to make sure this chip is
1584          * turbo capable.
1585          */
1586         rdmsrl(PLATFORM_INFO, platform_info);
1587         if (!(platform_info & PLATFORM_TDP)) {
1588                 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
1589                 ret = -ENODEV;
1590                 goto error_unmap;
1591         }
1592
1593         /*
1594          * IRQ handler for ME interaction
1595          * Note: don't use MSI here as the PCH has bugs.
1596          */
1597         pci_disable_msi(dev);
1598         ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips",
1599                           ips);
1600         if (ret) {
1601                 dev_err(&dev->dev, "request irq failed, aborting\n");
1602                 goto error_unmap;
1603         }
1604
1605         /* Enable aux, hot & critical interrupts */
1606         thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI |
1607                    TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI);
1608         thm_writeb(THM_TEN, TEN_UPDATE_EN);
1609
1610         /* Collect adjustment values */
1611         ips->cta_val = thm_readw(THM_CTA);
1612         ips->pta_val = thm_readw(THM_PTA);
1613         ips->mgta_val = thm_readw(THM_MGTA);
1614
1615         /* Save turbo limits & ratios */
1616         rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1617
1618         ips_disable_cpu_turbo(ips);
1619         ips->cpu_turbo_enabled = false;
1620
1621         /* Create thermal adjust thread */
1622         ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust");
1623         if (IS_ERR(ips->adjust)) {
1624                 dev_err(&dev->dev,
1625                         "failed to create thermal adjust thread, aborting\n");
1626                 ret = -ENOMEM;
1627                 goto error_free_irq;
1628
1629         }
1630
1631         /*
1632          * Set up the work queue and monitor thread. The monitor thread
1633          * will wake up ips_adjust thread.
1634          */
1635         ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor");
1636         if (IS_ERR(ips->monitor)) {
1637                 dev_err(&dev->dev,
1638                         "failed to create thermal monitor thread, aborting\n");
1639                 ret = -ENOMEM;
1640                 goto error_thread_cleanup;
1641         }
1642
1643         hts = (ips->core_power_limit << HTS_PCPL_SHIFT) |
1644                 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV;
1645         htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT;
1646
1647         thm_writew(THM_HTSHI, htshi);
1648         thm_writel(THM_HTS, hts);
1649
1650         ips_debugfs_init(ips);
1651
1652         dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n",
1653                  ips->mcp_temp_limit);
1654         return ret;
1655
1656 error_thread_cleanup:
1657         kthread_stop(ips->adjust);
1658 error_free_irq:
1659         free_irq(ips->dev->irq, ips);
1660 error_unmap:
1661         iounmap(ips->regmap);
1662 error_release:
1663         pci_release_regions(dev);
1664 error_free:
1665         kfree(ips);
1666         return ret;
1667 }
1668
1669 static void ips_remove(struct pci_dev *dev)
1670 {
1671         struct ips_driver *ips = pci_get_drvdata(dev);
1672         u64 turbo_override;
1673
1674         if (!ips)
1675                 return;
1676
1677         ips_debugfs_cleanup(ips);
1678
1679         /* Release i915 driver */
1680         if (ips->read_mch_val)
1681                 symbol_put(i915_read_mch_val);
1682         if (ips->gpu_raise)
1683                 symbol_put(i915_gpu_raise);
1684         if (ips->gpu_lower)
1685                 symbol_put(i915_gpu_lower);
1686         if (ips->gpu_busy)
1687                 symbol_put(i915_gpu_busy);
1688         if (ips->gpu_turbo_disable)
1689                 symbol_put(i915_gpu_turbo_disable);
1690
1691         rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1692         turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
1693         wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1694         wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1695
1696         free_irq(ips->dev->irq, ips);
1697         if (ips->adjust)
1698                 kthread_stop(ips->adjust);
1699         if (ips->monitor)
1700                 kthread_stop(ips->monitor);
1701         iounmap(ips->regmap);
1702         pci_release_regions(dev);
1703         kfree(ips);
1704         dev_dbg(&dev->dev, "IPS driver removed\n");
1705 }
1706
1707 #ifdef CONFIG_PM
1708 static int ips_suspend(struct pci_dev *dev, pm_message_t state)
1709 {
1710         return 0;
1711 }
1712
1713 static int ips_resume(struct pci_dev *dev)
1714 {
1715         return 0;
1716 }
1717 #else
1718 #define ips_suspend NULL
1719 #define ips_resume NULL
1720 #endif /* CONFIG_PM */
1721
1722 static void ips_shutdown(struct pci_dev *dev)
1723 {
1724 }
1725
1726 static struct pci_driver ips_pci_driver = {
1727         .name = "intel ips",
1728         .id_table = ips_id_table,
1729         .probe = ips_probe,
1730         .remove = ips_remove,
1731         .suspend = ips_suspend,
1732         .resume = ips_resume,
1733         .shutdown = ips_shutdown,
1734 };
1735
1736 static int __init ips_init(void)
1737 {
1738         return pci_register_driver(&ips_pci_driver);
1739 }
1740 module_init(ips_init);
1741
1742 static void ips_exit(void)
1743 {
1744         pci_unregister_driver(&ips_pci_driver);
1745         return;
1746 }
1747 module_exit(ips_exit);
1748
1749 MODULE_LICENSE("GPL");
1750 MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1751 MODULE_DESCRIPTION("Intelligent Power Sharing Driver");