2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/crc7.h>
27 #include <linux/spi/spi.h>
30 #include "wl12xx_80211.h"
34 #define OCP_CMD_LOOP 32
36 #define OCP_CMD_WRITE 0x1
37 #define OCP_CMD_READ 0x2
39 #define OCP_READY_MASK BIT(18)
40 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
42 #define OCP_STATUS_NO_RESP 0x00000
43 #define OCP_STATUS_OK 0x10000
44 #define OCP_STATUS_REQ_FAILED 0x20000
45 #define OCP_STATUS_RESP_ERROR 0x30000
47 bool wl1271_set_block_size(struct wl1271 *wl)
49 if (wl->if_ops->set_block_size) {
50 wl->if_ops->set_block_size(wl, WL12XX_BUS_BLOCK_SIZE);
57 void wl1271_disable_interrupts(struct wl1271 *wl)
59 wl->if_ops->disable_irq(wl);
62 void wl1271_enable_interrupts(struct wl1271 *wl)
64 wl->if_ops->enable_irq(wl);
67 /* Set the SPI partitions to access the chip addresses
69 * To simplify driver code, a fixed (virtual) memory map is defined for
70 * register and memory addresses. Because in the chipset, in different stages
71 * of operation, those addresses will move around, an address translation
72 * mechanism is required.
74 * There are four partitions (three memory and one register partition),
75 * which are mapped to two different areas of the hardware memory.
81 * ...+----+--> mem.start
82 * Physical address ... | |
83 * space ... | | [PART_0]
85 * 00000000 <--+----+... ...+----+--> mem.start + mem.size
89 * mem.size <--+----+... | | {unused area)
92 * mem.size | | ... | |
93 * + <--+----+... ...+----+--> reg.start
94 * reg.size | | ... | |
95 * |MEM2| ... | | [PART_1]
97 * ...+----+--> reg.start + reg.size
101 int wl1271_set_partition(struct wl1271 *wl,
102 struct wl1271_partition_set *p)
104 /* copy partition info */
105 memcpy(&wl->part, p, sizeof(*p));
107 wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
108 p->mem.start, p->mem.size);
109 wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
110 p->reg.start, p->reg.size);
111 wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
112 p->mem2.start, p->mem2.size);
113 wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
114 p->mem3.start, p->mem3.size);
116 /* write partition info to the chipset */
117 wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
118 wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
119 wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
120 wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
121 wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
122 wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
123 wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
127 EXPORT_SYMBOL_GPL(wl1271_set_partition);
129 void wl1271_io_reset(struct wl1271 *wl)
131 wl->if_ops->reset(wl);
134 void wl1271_io_init(struct wl1271 *wl)
136 wl->if_ops->init(wl);
139 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
141 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
142 addr = (addr >> 1) + 0x30000;
143 wl1271_write32(wl, OCP_POR_CTR, addr);
145 /* write value to OCP_POR_WDATA */
146 wl1271_write32(wl, OCP_DATA_WRITE, val);
148 /* write 1 to OCP_CMD */
149 wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
152 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
155 int timeout = OCP_CMD_LOOP;
157 /* write address >> 1 + 0x30000 to OCP_POR_CTR */
158 addr = (addr >> 1) + 0x30000;
159 wl1271_write32(wl, OCP_POR_CTR, addr);
161 /* write 2 to OCP_CMD */
162 wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
164 /* poll for data ready */
166 val = wl1271_read32(wl, OCP_DATA_READ);
167 } while (!(val & OCP_READY_MASK) && --timeout);
170 wl1271_warning("Top register access timed out.");
174 /* check data status and return if OK */
175 if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
178 wl1271_warning("Top register access returned error.");