drivers/net/wireless/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include "../wifi.h"
  33 #include "../efuse.h"
  34 #include "../base.h"
  35 #include "../regd.h"
  36 #include "../cam.h"
  37 #include "../ps.h"
  38 #include "../pci.h"
  39 #include "reg.h"
  40 #include "def.h"
  41 #include "phy.h"
  42 #include "dm.h"
  43 #include "fw.h"
  44 #include "led.h"
  45 #include "hw.h"
  46
  47 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  48 {
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  51         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  52
  53         switch (variable) {
  54         case HW_VAR_RCR: {
  55                         *((u32 *) (val)) = rtlpci->receive_config;
  56                         break;
  57                 }
  58         case HW_VAR_RF_STATE: {
  59                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  60                         break;
  61                 }
  62         case HW_VAR_FW_PSMODE_STATUS: {
  63                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  64                         break;
  65                 }
  66         case HW_VAR_CORRECT_TSF: {
  67                         u64 tsf;
  68                         u32 *ptsf_low = (u32 *)&tsf;
  69                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  70
  71                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  72                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  73
  74                         *((u64 *) (val)) = tsf;
  75
  76                         break;
  77                 }
  78         case HW_VAR_MRC: {
  79                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  80                         break;
  81                 }
  82         default: {
  83                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  84                                  ("switch case not process\n"));
  85                         break;
  86                 }
  87         }
  88 }
  89
  90 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  91 {
  92         struct rtl_priv *rtlpriv = rtl_priv(hw);
  93         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  94         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  95         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  96         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  97         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  98
  99         switch (variable) {
 100         case HW_VAR_ETHER_ADDR:{
 101                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 102                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 103                         break;
 104                 }
 105         case HW_VAR_BASIC_RATE:{
 106                         u16 rate_cfg = ((u16 *) val)[0];
 107                         u8 rate_index = 0;
 108
 109                         if (rtlhal->version == VERSION_8192S_ACUT)
 110                                 rate_cfg = rate_cfg & 0x150;
 111                         else
 112                                 rate_cfg = rate_cfg & 0x15f;
 113
 114                         rate_cfg |= 0x01;
 115
 116                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 117                         rtl_write_byte(rtlpriv, RRSR + 1,
 118                                        (rate_cfg >> 8) & 0xff);
 119
 120                         while (rate_cfg > 0x1) {
 121                                 rate_cfg = (rate_cfg >> 1);
 122                                 rate_index++;
 123                         }
 124                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 125
 126                         break;
 127                 }
 128         case HW_VAR_BSSID:{
 129                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 130                         rtl_write_word(rtlpriv, BSSIDR + 4,
 131                                        ((u16 *)(val + 4))[0]);
 132                         break;
 133                 }
 134         case HW_VAR_SIFS:{
 135                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 136                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 137                         break;
 138                 }
 139         case HW_VAR_SLOT_TIME:{
 140                         u8 e_aci;
 141
 142                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 143                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 144
 145                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 146
 147                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 148                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 149                                                 HW_VAR_AC_PARAM,
 150                                                 (u8 *)(&e_aci));
 151                         }
 152                         break;
 153                 }
 154         case HW_VAR_ACK_PREAMBLE:{
 155                         u8 reg_tmp;
 156                         u8 short_preamble = (bool) (*(u8 *) val);
 157                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 158                         if (short_preamble)
 159                                 reg_tmp |= 0x80;
 160
 161                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 162                         break;
 163                 }
 164         case HW_VAR_AMPDU_MIN_SPACE:{
 165                         u8 min_spacing_to_set;
 166                         u8 sec_min_space;
 167
 168                         min_spacing_to_set = *((u8 *)val);
 169                         if (min_spacing_to_set <= 7) {
 170                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 171                                     NO_ENCRYPTION)
 172                                         sec_min_space = 0;
 173                                 else
 174                                         sec_min_space = 1;
 175
 176                                 if (min_spacing_to_set < sec_min_space)
 177                                         min_spacing_to_set = sec_min_space;
 178                                 if (min_spacing_to_set > 5)
 179                                         min_spacing_to_set = 5;
 180
 181                                 mac->min_space_cfg =
 182                                                 ((mac->min_space_cfg & 0xf8) |
 183                                                 min_spacing_to_set);
 184
 185                                 *val = min_spacing_to_set;
 186
 187                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 188                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 189                                           mac->min_space_cfg));
 190
 191                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 192                                                mac->min_space_cfg);
 193                         }
 194                         break;
 195                 }
 196         case HW_VAR_SHORTGI_DENSITY:{
 197                         u8 density_to_set;
 198
 199                         density_to_set = *((u8 *) val);
 200                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 201                         mac->min_space_cfg |= (density_to_set << 3);
 202
 203                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 204                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 205                                   mac->min_space_cfg));
 206
 207                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 208                                        mac->min_space_cfg);
 209
 210                         break;
 211                 }
 212         case HW_VAR_AMPDU_FACTOR:{
 213                         u8 factor_toset;
 214                         u8 regtoset;
 215                         u8 factorlevel[18] = {
 216                                 2, 4, 4, 7, 7, 13, 13,
 217                                 13, 2, 7, 7, 13, 13,
 218                                 15, 15, 15, 15, 0};
 219                         u8 index = 0;
 220
 221                         factor_toset = *((u8 *) val);
 222                         if (factor_toset <= 3) {
 223                                 factor_toset = (1 << (factor_toset + 2));
 224                                 if (factor_toset > 0xf)
 225                                         factor_toset = 0xf;
 226
 227                                 for (index = 0; index < 17; index++) {
 228                                         if (factorlevel[index] > factor_toset)
 229                                                 factorlevel[index] =
 230                                                                  factor_toset;
 231                                 }
 232
 233                                 for (index = 0; index < 8; index++) {
 234                                         regtoset = ((factorlevel[index * 2]) |
 235                                                     (factorlevel[index *
 236                                                     2 + 1] << 4));
 237                                         rtl_write_byte(rtlpriv,
 238                                                        AGGLEN_LMT_L + index,
 239                                                        regtoset);
 240                                 }
 241
 242                                 regtoset = ((factorlevel[16]) |
 243                                             (factorlevel[17] << 4));
 244                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 245
 246                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 247                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 248                                           factor_toset));
 249                         }
 250                         break;
 251                 }
 252         case HW_VAR_AC_PARAM:{
 253                         u8 e_aci = *((u8 *) val);
 254                         rtl92s_dm_init_edca_turbo(hw);
 255
 256                         if (rtlpci->acm_method != eAcmWay2_SW)
 257                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 258                                                  HW_VAR_ACM_CTRL,
 259                                                  (u8 *)(&e_aci));
 260                         break;
 261                 }
 262         case HW_VAR_ACM_CTRL:{
 263                         u8 e_aci = *((u8 *) val);
 264                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 265                                                         mac->ac[0].aifs));
 266                         u8 acm = p_aci_aifsn->f.acm;
 267                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 268
 269                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 270                                    0x0 : 0x1);
 271
 272                         if (acm) {
 273                                 switch (e_aci) {
 274                                 case AC0_BE:
 275                                         acm_ctrl |= AcmHw_BeqEn;
 276                                         break;
 277                                 case AC2_VI:
 278                                         acm_ctrl |= AcmHw_ViqEn;
 279                                         break;
 280                                 case AC3_VO:
 281                                         acm_ctrl |= AcmHw_VoqEn;
 282                                         break;
 283                                 default:
 284                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 285                                                  ("HW_VAR_ACM_CTRL acm set "
 286                                                   "failed: eACI is %d\n", acm));
 287                                         break;
 288                                 }
 289                         } else {
 290                                 switch (e_aci) {
 291                                 case AC0_BE:
 292                                         acm_ctrl &= (~AcmHw_BeqEn);
 293                                         break;
 294                                 case AC2_VI:
 295                                         acm_ctrl &= (~AcmHw_ViqEn);
 296                                         break;
 297                                 case AC3_VO:
 298                                         acm_ctrl &= (~AcmHw_BeqEn);
 299                                         break;
 300                                 default:
 301                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 302                                                  ("switch case not process\n"));
 303                                         break;
 304                                 }
 305                         }
 306
 307                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 308                                  ("HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl));
 309                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 310                         break;
 311                 }
 312         case HW_VAR_RCR:{
 313                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 314                         rtlpci->receive_config = ((u32 *) (val))[0];
 315                         break;
 316                 }
 317         case HW_VAR_RETRY_LIMIT:{
 318                         u8 retry_limit = ((u8 *) (val))[0];
 319
 320                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 321                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 322                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 323                         break;
 324                 }
 325         case HW_VAR_DUAL_TSF_RST: {
 326                         break;
 327                 }
 328         case HW_VAR_EFUSE_BYTES: {
 329                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 330                         break;
 331                 }
 332         case HW_VAR_EFUSE_USAGE: {
 333                         rtlefuse->efuse_usedpercentage = *((u8 *) val);
 334                         break;
 335                 }
 336         case HW_VAR_IO_CMD: {
 337                         break;
 338                 }
 339         case HW_VAR_WPA_CONFIG: {
 340                         rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
 341                         break;
 342                 }
 343         case HW_VAR_SET_RPWM:{
 344                         break;
 345                 }
 346         case HW_VAR_H2C_FW_PWRMODE:{
 347                         break;
 348                 }
 349         case HW_VAR_FW_PSMODE_STATUS: {
 350                         ppsc->fw_current_inpsmode = *((bool *) val);
 351                         break;
 352                 }
 353         case HW_VAR_H2C_FW_JOINBSSRPT:{
 354                         break;
 355                 }
 356         case HW_VAR_AID:{
 357                         break;
 358                 }
 359         case HW_VAR_CORRECT_TSF:{
 360                         break;
 361                 }
 362         case HW_VAR_MRC: {
 363                         bool bmrc_toset = *((bool *)val);
 364                         u8 u1bdata = 0;
 365
 366                         if (bmrc_toset) {
 367                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 368                                               MASKBYTE0, 0x33);
 369                                 u1bdata = (u8)rtl_get_bbreg(hw,
 370                                                 ROFDM1_TRXPATHENABLE,
 371                                                 MASKBYTE0);
 372                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 373                                               MASKBYTE0,
 374                                               ((u1bdata & 0xf0) | 0x03));
 375                                 u1bdata = (u8)rtl_get_bbreg(hw,
 376                                                 ROFDM0_TRXPATHENABLE,
 377                                                 MASKBYTE1);
 378                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 379                                               MASKBYTE1,
 380                                               (u1bdata | 0x04));
 381
 382                                 /* Update current settings. */
 383                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 384                         } else {
 385                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 386                                               MASKBYTE0, 0x13);
 387                                 u1bdata = (u8)rtl_get_bbreg(hw,
 388                                                  ROFDM1_TRXPATHENABLE,
 389                                                  MASKBYTE0);
 390                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 391                                               MASKBYTE0,
 392                                               ((u1bdata & 0xf0) | 0x01));
 393                                 u1bdata = (u8)rtl_get_bbreg(hw,
 394                                                 ROFDM0_TRXPATHENABLE,
 395                                                 MASKBYTE1);
 396                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 397                                               MASKBYTE1, (u1bdata & 0xfb));
 398
 399                                 /* Update current settings. */
 400                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 401                         }
 402
 403                         break;
 404                 }
 405         default:
 406                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 407                          ("switch case not process\n"));
 408                 break;
 409         }
 410
 411 }
 412
 413 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 414 {
 415         struct rtl_priv *rtlpriv = rtl_priv(hw);
 416         u8 sec_reg_value = 0x0;
 417
 418         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("PairwiseEncAlgorithm = %d "
 419                  "GroupEncAlgorithm = %d\n",
 420                  rtlpriv->sec.pairwise_enc_algorithm,
 421                  rtlpriv->sec.group_enc_algorithm));
 422
 423         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 424                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 425                          ("not open hw encryption\n"));
 426                 return;
 427         }
 428
 429         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 430
 431         if (rtlpriv->sec.use_defaultkey) {
 432                 sec_reg_value |= SCR_TXUSEDK;
 433                 sec_reg_value |= SCR_RXUSEDK;
 434         }
 435
 436         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, ("The SECR-value %x\n",
 437                         sec_reg_value));
 438
 439         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 440
 441 }
 442
 443 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 444 {
 445         struct rtl_priv *rtlpriv = rtl_priv(hw);
 446         u8 waitcount = 100;
 447         bool bresult = false;
 448         u8 tmpvalue;
 449
 450         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 451
 452         /* Wait the MAC synchronized. */
 453         udelay(400);
 454
 455         /* Check if it is set ready. */
 456         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 457         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 458
 459         if ((data & (BIT(6) | BIT(7))) == false) {
 460                 waitcount = 100;
 461                 tmpvalue = 0;
 462
 463                 while (1) {
 464                         waitcount--;
 465
 466                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 467                         if ((tmpvalue & BIT(6)))
 468                                 break;
 469
 470                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 471                         if (waitcount == 0)
 472                                 break;
 473
 474                         udelay(10);
 475                 }
 476
 477                 if (waitcount == 0)
 478                         bresult = false;
 479                 else
 480                         bresult = true;
 481         }
 482
 483         return bresult;
 484 }
 485
 486 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 487 {
 488         struct rtl_priv *rtlpriv = rtl_priv(hw);
 489         u8 u1tmp;
 490
 491         /* The following config GPIO function */
 492         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 493         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 494
 495         /* config GPIO3 to input */
 496         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 497         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 498
 499 }
 500
 501 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 502 {
 503         struct rtl_priv *rtlpriv = rtl_priv(hw);
 504         u8 u1tmp;
 505         u8 retval = ERFON;
 506
 507         /* The following config GPIO function */
 508         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 509         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 510
 511         /* config GPIO3 to input */
 512         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 513         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 514
 515         /* On some of the platform, driver cannot read correct
 516          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 517         mdelay(10);
 518
 519         /* check GPIO3 */
 520         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 521         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 522
 523         return retval;
 524 }
 525
 526 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 527 {
 528         struct rtl_priv *rtlpriv = rtl_priv(hw);
 529         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 530         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 531
 532         u8 i;
 533         u8 tmpu1b;
 534         u16 tmpu2b;
 535         u8 pollingcnt = 20;
 536
 537         if (rtlpci->first_init) {
 538                 /* Reset PCIE Digital */
 539                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 540                 tmpu1b &= 0xFE;
 541                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 542                 udelay(1);
 543                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 544         }
 545
 546         /* Switch to SW IO control */
 547         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 548         if (tmpu1b & BIT(7)) {
 549                 tmpu1b &= ~(BIT(6) | BIT(7));
 550
 551                 /* Set failed, return to prevent hang. */
 552                 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 553                         return;
 554         }
 555
 556         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 557         udelay(50);
 558         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 559         udelay(50);
 560
 561         /* Clear FW RPWM for FW control LPS.*/
 562         rtl_write_byte(rtlpriv, RPWM, 0x0);
 563
 564         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 565         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 566         tmpu1b &= 0x73;
 567         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 568         /* wait for BIT 10/11/15 to pull high automatically!! */
 569         mdelay(1);
 570
 571         rtl_write_byte(rtlpriv, CMDR, 0);
 572         rtl_write_byte(rtlpriv, TCR, 0);
 573
 574         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 575         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 576         tmpu1b |= 0x08;
 577         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 578         tmpu1b &= ~(BIT(3));
 579         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 580
 581         /* Enable AFE clock source */
 582         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 583         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 584         /* Delay 1.5ms */
 585         mdelay(2);
 586         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 587         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 588
 589         /* Enable AFE Macro Block's Bandgap */
 590         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 591         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 592         mdelay(1);
 593
 594         /* Enable AFE Mbias */
 595         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 596         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 597         mdelay(1);
 598
 599         /* Enable LDOA15 block  */
 600         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 601         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 602
 603         /* Set Digital Vdd to Retention isolation Path. */
 604         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 605         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 606
 607         /* For warm reboot NIC disappera bug. */
 608         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 609         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 610
 611         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 612
 613         /* Enable AFE PLL Macro Block */
 614         /* We need to delay 100u before enabling PLL. */
 615         udelay(200);
 616         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 617         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 618
 619         /* for divider reset  */
 620         udelay(100);
 621         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 622                        BIT(4) | BIT(6)));
 623         udelay(10);
 624         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 625         udelay(10);
 626
 627         /* Enable MAC 80MHZ clock  */
 628         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 629         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 630         mdelay(1);
 631
 632         /* Release isolation AFE PLL & MD */
 633         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 634
 635         /* Enable MAC clock */
 636         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 637         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 638
 639         /* Enable Core digital and enable IOREG R/W */
 640         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 641         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 642
 643         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 644         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 645
 646         /* enable REG_EN */
 647         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 648
 649         /* Switch the control path. */
 650         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 651         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 652
 653         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 654         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 655         if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 656                 return; /* Set failed, return to prevent hang. */
 657
 658         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 659
 660         /* MH We must enable the section of code to prevent load IMEM fail. */
 661         /* Load MAC register from WMAc temporarily We simulate macreg. */
 662         /* txt HW will provide MAC txt later  */
 663         rtl_write_byte(rtlpriv, 0x6, 0x30);
 664         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 665
 666         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 667
 668         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 669
 670         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 671         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 672         rtl_write_byte(rtlpriv, 0xde, 0xff);
 673         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 674
 675         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 676         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 677
 678         for (i = 0; i < 32; i++)
 679                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 680
 681         rtl_write_byte(rtlpriv, 0x236, 0xff);
 682
 683         rtl_write_byte(rtlpriv, 0x503, 0x22);
 684
 685         if (ppsc->support_aspm && !ppsc->support_backdoor)
 686                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 687         else
 688                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 689
 690         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 691
 692         /* Set RX Desc Address */
 693         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 694         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 695
 696         /* Set TX Desc Address */
 697         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 698         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 699         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 700         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 701         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 702         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 703         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 704         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 705         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 706
 707         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 708
 709         /* To make sure that TxDMA can ready to download FW. */
 710         /* We should reset TxDMA if IMEM RPT was not ready. */
 711         do {
 712                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 713                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 714                         break;
 715
 716                 udelay(5);
 717         } while (pollingcnt--);
 718
 719         if (pollingcnt <= 0) {
 720                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 721                          ("Polling TXDMA_INIT_VALUE "
 722                          "timeout!! Current TCR(%#x)\n", tmpu1b));
 723                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 724                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 725                 udelay(2);
 726                 /* Reset TxDMA */
 727                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 728         }
 729
 730         /* After MACIO reset,we must refresh LED state. */
 731         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 732            (ppsc->rfoff_reason == 0)) {
 733                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 734                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 735                 enum rf_pwrstate rfpwr_state_toset;
 736                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 737
 738                 if (rfpwr_state_toset == ERFON)
 739                         rtl92se_sw_led_on(hw, pLed0);
 740         }
 741 }
 742
 743 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 744 {
 745         struct rtl_priv *rtlpriv = rtl_priv(hw);
 746         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 747         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 748         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 749         u8 i;
 750         u16 tmpu2b;
 751
 752         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 753
 754         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 755         /* Turn on 0x40 Command register */
 756         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 757                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 758                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 759
 760         /* Set TCR TX DMA pre 2 FULL enable bit */
 761         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 762                         TXDMAPRE2FULL);
 763
 764         /* Set RCR      */
 765         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 766
 767         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 768
 769         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 770         /* Set CCK/OFDM SIFS */
 771         /* CCK SIFS shall always be 10us. */
 772         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 773         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 774
 775         /* Set AckTimeout */
 776         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 777
 778         /* Beacon related */
 779         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 780         rtl_write_word(rtlpriv, ATIMWND, 2);
 781
 782         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 783         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 784         /* Firmware allocate now, associate with FW internal setting.!!! */
 785
 786         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 787         /* 5.3 Set driver info, we only accept PHY status now. */
 788         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 789         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 790
 791         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 792         /* Set RRSR to all legacy rate and HT rate
 793          * CCK rate is supported by default.
 794          * CCK rate will be filtered out only when associated
 795          * AP does not support it.
 796          * Only enable ACK rate to OFDM 24M
 797          * Disable RRSR for CCK rate in A-Cut   */
 798
 799         if (rtlhal->version == VERSION_8192S_ACUT)
 800                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 801         else if (rtlhal->version == VERSION_8192S_BCUT)
 802                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 803         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 804         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 805
 806         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 807         /* fallback to CCK rate */
 808         for (i = 0; i < 8; i++) {
 809                 /*Disable RRSR for CCK rate in A-Cut */
 810                 if (rtlhal->version == VERSION_8192S_ACUT)
 811                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 812         }
 813
 814         /* Different rate use different AMPDU size */
 815         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 816         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 817         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 818         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 819         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 820         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 821         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 822         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 823         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 824         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 825
 826         /* Set Data / Response auto rate fallack retry count */
 827         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 828         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 829         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 830         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 831
 832         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 833         /* Set all rate to support SG */
 834         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 835
 836         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 837         /* Set NAV protection length */
 838         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 839         /* CF-END Threshold */
 840         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 841         /* Set AMPDU minimum space */
 842         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 843         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 844         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 845
 846         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 847         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 848         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 849         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 850         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 851
 852         /* 14. Set driver info, we only accept PHY status now. */
 853         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 854
 855         /* 15. For EEPROM R/W Workaround */
 856         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 857         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 858         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 859         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 860         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 861
 862         /* 17. For EFUSE */
 863         /* We may R/W EFUSE in EEPROM mode */
 864         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 865                 u8      tempval;
 866
 867                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 868                 tempval &= 0xFE;
 869                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 870
 871                 /* Change Program timing */
 872                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 873                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("EFUSE CONFIG OK\n"));
 874         }
 875
 876         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
 877
 878 }
 879
 880 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 881 {
 882         struct rtl_priv *rtlpriv = rtl_priv(hw);
 883         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 884         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 885         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 886
 887         u8 reg_bw_opmode = 0;
 888         u32 reg_rrsr = 0;
 889         u8 regtmp = 0;
 890
 891         reg_bw_opmode = BW_OPMODE_20MHZ;
 892         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 893
 894         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 895         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 896         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 897         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 898
 899         /* Set Retry Limit here */
 900         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 901                         (u8 *)(&rtlpci->shortretry_limit));
 902
 903         rtl_write_byte(rtlpriv, MLT, 0x8f);
 904
 905         /* For Min Spacing configuration. */
 906         switch (rtlphy->rf_type) {
 907         case RF_1T2R:
 908         case RF_1T1R:
 909                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 910                 break;
 911         case RF_2T2R:
 912         case RF_2T2R_GREEN:
 913                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 914                 break;
 915         }
 916         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 917 }
 918
 919 int rtl92se_hw_init(struct ieee80211_hw *hw)
 920 {
 921         struct rtl_priv *rtlpriv = rtl_priv(hw);
 922         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 923         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 924         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 925         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 926         u8 tmp_byte = 0;
 927         unsigned long flags;
 928         bool rtstatus = true;
 929         u8 tmp_u1b;
 930         int err = false;
 931         u8 i;
 932         int wdcapra_add[] = {
 933                 EDCAPARA_BE, EDCAPARA_BK,
 934                 EDCAPARA_VI, EDCAPARA_VO};
 935         u8 secr_value = 0x0;
 936
 937         rtlpci->being_init_adapter = true;
 938
 939         /* As this function can take a very long time (up to 350 ms)
 940          * and can be called with irqs disabled, reenable the irqs
 941          * to let the other devices continue being serviced.
 942          *
 943          * It is safe doing so since our own interrupts will only be enabled
 944          * in a subsequent step.
 945          */
 946         local_save_flags(flags);
 947         local_irq_enable();
 948
 949         rtlpriv->intf_ops->disable_aspm(hw);
 950
 951         /* 1. MAC Initialize */
 952         /* Before FW download, we have to set some MAC register */
 953         _rtl92se_macconfig_before_fwdownload(hw);
 954
 955         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 956                         PMC_FSM) >> 16) & 0xF);
 957
 958         rtl8192se_gpiobit3_cfg_inputmode(hw);
 959
 960         /* 2. download firmware */
 961         rtstatus = rtl92s_download_fw(hw);
 962         if (!rtstatus) {
 963                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 964                          ("Failed to download FW. "
 965                          "Init HW without FW now.., Please copy FW into"
 966                          "/lib/firmware/rtlwifi\n"));
 967                 rtlhal->fw_ready = false;
 968         } else {
 969                 rtlhal->fw_ready = true;
 970         }
 971
 972         /* After FW download, we have to reset MAC register */
 973         _rtl92se_macconfig_after_fwdownload(hw);
 974
 975         /*Retrieve default FW Cmd IO map. */
 976         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 977         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 978
 979         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 980         if (rtl92s_phy_mac_config(hw) != true) {
 981                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("MAC Config failed\n"));
 982                 err = rtstatus;
 983                 goto exit;
 984         }
 985
 986         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 987         /* We must set flag avoid BB/RF config period later!! */
 988         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 989
 990         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 991         if (rtl92s_phy_bb_config(hw) != true) {
 992                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("BB Config failed\n"));
 993                 err = rtstatus;
 994                 goto exit;
 995         }
 996
 997         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
 998         /* Before initalizing RF. We can not use FW to do RF-R/W. */
 999
1000         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1001
1002         /* RF Power Save */
1003 #if 0
1004         /* H/W or S/W RF OFF before sleep. */
1005         if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
1006                 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
1007
1008                 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
1009                 rtlpriv->psc.rfpwr_state = ERFON;
1010                 /* FIXME: check spinlocks if this block is uncommented */
1011                 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
1012         } else {
1013                 /* gpio radio on/off is out of adapter start */
1014                 if (rtlpriv->psc.hwradiooff == false) {
1015                         rtlpriv->psc.rfpwr_state = ERFON;
1016                         rtlpriv->psc.rfoff_reason = 0;
1017                 }
1018         }
1019 #endif
1020
1021         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1022         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1023         if (rtlhal->version == VERSION_8192S_ACUT)
1024                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1025         else
1026                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1027
1028         if (rtl92s_phy_rf_config(hw) != true) {
1029                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("RF Config failed\n"));
1030                 err = rtstatus;
1031                 goto exit;
1032         }
1033
1034         /* After read predefined TXT, we must set BB/MAC/RF
1035          * register as our requirement */
1036
1037         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1038                                                            (enum radio_path)0,
1039                                                            RF_CHNLBW,
1040                                                            RFREG_OFFSET_MASK);
1041         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1042                                                            (enum radio_path)1,
1043                                                            RF_CHNLBW,
1044                                                            RFREG_OFFSET_MASK);
1045
1046         /*---- Set CCK and OFDM Block "ON"----*/
1047         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1048         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1049
1050         /*3 Set Hardware(Do nothing now) */
1051         _rtl92se_hw_configure(hw);
1052
1053         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1054         /* TX power index for different rate set. */
1055         /* Get original hw reg values */
1056         rtl92s_phy_get_hw_reg_originalvalue(hw);
1057         /* Write correct tx power index */
1058         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1059
1060         /* We must set MAC address after firmware download. */
1061         for (i = 0; i < 6; i++)
1062                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1063
1064         /* EEPROM R/W workaround */
1065         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1066         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1067
1068         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1069
1070         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1071                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1072                 tmp_byte = tmp_byte | BIT(5);
1073                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1074                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1075         }
1076
1077         /* We enable high power and RA related mechanism after NIC
1078          * initialized. */
1079         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1080
1081         /* Add to prevent ASPM bug. */
1082         /* Always enable hst and NIC clock request. */
1083         rtl92s_phy_switch_ephy_parameter(hw);
1084
1085         /* Security related
1086          * 1. Clear all H/W keys.
1087          * 2. Enable H/W encryption/decryption. */
1088         rtl_cam_reset_all_entry(hw);
1089         secr_value |= SCR_TXENCENABLE;
1090         secr_value |= SCR_RXENCENABLE;
1091         secr_value |= SCR_NOSKMC;
1092         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1093
1094         for (i = 0; i < 4; i++)
1095                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1096
1097         if (rtlphy->rf_type == RF_1T2R) {
1098                 bool mrc2set = true;
1099                 /* Turn on B-Path */
1100                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1101         }
1102
1103         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1104         rtl92s_dm_init(hw);
1105 exit:
1106         local_irq_restore(flags);
1107         rtlpci->being_init_adapter = false;
1108         return err;
1109 }
1110
1111 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1112 {
1113 }
1114
1115 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1116 {
1117         struct rtl_priv *rtlpriv = rtl_priv(hw);
1118         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1119         u32 reg_rcr = rtlpci->receive_config;
1120
1121         if (rtlpriv->psc.rfpwr_state != ERFON)
1122                 return;
1123
1124         if (check_bssid) {
1125                 reg_rcr |= (RCR_CBSSID);
1126                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1127         } else if (check_bssid == false) {
1128                 reg_rcr &= (~RCR_CBSSID);
1129                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1130         }
1131
1132 }
1133
1134 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1135                                      enum nl80211_iftype type)
1136 {
1137         struct rtl_priv *rtlpriv = rtl_priv(hw);
1138         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1139         u32 temp;
1140         bt_msr &= ~MSR_LINK_MASK;
1141
1142         switch (type) {
1143         case NL80211_IFTYPE_UNSPECIFIED:
1144                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1145                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1146                          ("Set Network type to NO LINK!\n"));
1147                 break;
1148         case NL80211_IFTYPE_ADHOC:
1149                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1150                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1151                          ("Set Network type to Ad Hoc!\n"));
1152                 break;
1153         case NL80211_IFTYPE_STATION:
1154                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1155                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1156                          ("Set Network type to STA!\n"));
1157                 break;
1158         case NL80211_IFTYPE_AP:
1159                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1161                          ("Set Network type to AP!\n"));
1162                 break;
1163         default:
1164                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1165                          ("Network type %d not support!\n", type));
1166                 return 1;
1167                 break;
1168
1169         }
1170
1171         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1172
1173         temp = rtl_read_dword(rtlpriv, TCR);
1174         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1175         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1176
1177
1178         return 0;
1179 }
1180
1181 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1182 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1183 {
1184         struct rtl_priv *rtlpriv = rtl_priv(hw);
1185
1186         if (_rtl92se_set_media_status(hw, type))
1187                 return -EOPNOTSUPP;
1188
1189         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1190                 if (type != NL80211_IFTYPE_AP)
1191                         rtl92se_set_check_bssid(hw, true);
1192         } else {
1193                 rtl92se_set_check_bssid(hw, false);
1194         }
1195
1196         return 0;
1197 }
1198
1199 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1200 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1201 {
1202         struct rtl_priv *rtlpriv = rtl_priv(hw);
1203         rtl92s_dm_init_edca_turbo(hw);
1204
1205         switch (aci) {
1206         case AC1_BK:
1207                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1208                 break;
1209         case AC0_BE:
1210                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1211                 break;
1212         case AC2_VI:
1213                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1214                 break;
1215         case AC3_VO:
1216                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1217                 break;
1218         default:
1219                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1220                 break;
1221         }
1222 }
1223
1224 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1225 {
1226         struct rtl_priv *rtlpriv = rtl_priv(hw);
1227         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1228
1229         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1230         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1231         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1232 }
1233
1234 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1235 {
1236         struct rtl_priv *rtlpriv = rtl_priv(hw);
1237         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1238
1239         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1240         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1241
1242         synchronize_irq(rtlpci->pdev->irq);
1243 }
1244
1245
1246 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1247 {
1248         struct rtl_priv *rtlpriv = rtl_priv(hw);
1249         u8 waitcnt = 100;
1250         bool result = false;
1251         u8 tmp;
1252
1253         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1254
1255         /* Wait the MAC synchronized. */
1256         udelay(400);
1257
1258         /* Check if it is set ready. */
1259         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1260         result = ((tmp & BIT(7)) == (data & BIT(7)));
1261
1262         if ((data & (BIT(6) | BIT(7))) == false) {
1263                 waitcnt = 100;
1264                 tmp = 0;
1265
1266                 while (1) {
1267                         waitcnt--;
1268                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1269
1270                         if ((tmp & BIT(6)))
1271                                 break;
1272
1273                         pr_err("wait for BIT(6) return value %x\n", tmp);
1274
1275                         if (waitcnt == 0)
1276                                 break;
1277                         udelay(10);
1278                 }
1279
1280                 if (waitcnt == 0)
1281                         result = false;
1282                 else
1283                         result = true;
1284         }
1285
1286         return result;
1287 }
1288
1289 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1290 {
1291         struct rtl_priv *rtlpriv = rtl_priv(hw);
1292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1293         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1294         u8 u1btmp;
1295
1296         if (rtlhal->driver_going2unload)
1297                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1298
1299         /* Power save for BB/RF */
1300         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1301         u1btmp |= BIT(0);
1302         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1303         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1304         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1305         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1306         udelay(100);
1307         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1308         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1309         udelay(10);
1310         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1311         udelay(10);
1312         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1313         udelay(10);
1314         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1315         rtl_write_word(rtlpriv, CMDR, 0x0000);
1316
1317         if (rtlhal->driver_going2unload) {
1318                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1319                 u1btmp &= ~(BIT(0));
1320                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1321         }
1322
1323         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1324
1325         /* Add description. After switch control path. register
1326          * after page1 will be invisible. We can not do any IO
1327          * for register>0x40. After resume&MACIO reset, we need
1328          * to remember previous reg content. */
1329         if (u1btmp & BIT(7)) {
1330                 u1btmp &= ~(BIT(6) | BIT(7));
1331                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1332                         pr_err("Switch ctrl path fail\n");
1333                         return;
1334                 }
1335         }
1336
1337         /* Power save for MAC */
1338         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1339                 !rtlhal->driver_going2unload) {
1340                 /* enable LED function */
1341                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1342         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1343         } else {
1344                 /* LED function disable. Power range is about 8mA now. */
1345                 /* if write 0xF1 disconnet_pci power
1346                  *       ifconfig wlan0 down power are both high 35:70 */
1347                 /* if write oxF9 disconnet_pci power
1348                  * ifconfig wlan0 down power are both low  12:45*/
1349                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1350         }
1351
1352         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1353         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1354         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1355         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1356         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1357         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1358
1359 }
1360
1361 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1362 {
1363         struct rtl_priv *rtlpriv = rtl_priv(hw);
1364         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1365         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1366         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1367
1368         if (rtlpci->up_first_time == 1)
1369                 return;
1370
1371         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1372                 rtl92se_sw_led_on(hw, pLed0);
1373         else
1374                 rtl92se_sw_led_off(hw, pLed0);
1375 }
1376
1377
1378 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1379 {
1380         struct rtl_priv *rtlpriv = rtl_priv(hw);
1381         u16 tmpu2b;
1382         u8 tmpu1b;
1383
1384         rtlpriv->psc.pwrdomain_protect = true;
1385
1386         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1387         if (tmpu1b & BIT(7)) {
1388                 tmpu1b &= ~(BIT(6) | BIT(7));
1389                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1390                         rtlpriv->psc.pwrdomain_protect = false;
1391                         return;
1392                 }
1393         }
1394
1395         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1396         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1397
1398         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1399         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1400
1401         /* If IPS we need to turn LED on. So we not
1402          * not disable BIT 3/7 of reg3. */
1403         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1404                 tmpu1b &= 0xFB;
1405         else
1406                 tmpu1b &= 0x73;
1407
1408         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1409         /* wait for BIT 10/11/15 to pull high automatically!! */
1410         mdelay(1);
1411
1412         rtl_write_byte(rtlpriv, CMDR, 0);
1413         rtl_write_byte(rtlpriv, TCR, 0);
1414
1415         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1416         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1417         tmpu1b |= 0x08;
1418         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1419         tmpu1b &= ~(BIT(3));
1420         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1421
1422         /* Enable AFE clock source */
1423         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1424         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1425         /* Delay 1.5ms */
1426         udelay(1500);
1427         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1428         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1429
1430         /* Enable AFE Macro Block's Bandgap */
1431         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1432         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1433         mdelay(1);
1434
1435         /* Enable AFE Mbias */
1436         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1437         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1438         mdelay(1);
1439
1440         /* Enable LDOA15 block */
1441         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1442         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1443
1444         /* Set Digital Vdd to Retention isolation Path. */
1445         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1446         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1447
1448
1449         /* For warm reboot NIC disappera bug. */
1450         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1451         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1452
1453         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1454
1455         /* Enable AFE PLL Macro Block */
1456         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1457         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1458         /* Enable MAC 80MHZ clock */
1459         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1460         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1461         mdelay(1);
1462
1463         /* Release isolation AFE PLL & MD */
1464         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1465
1466         /* Enable MAC clock */
1467         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1468         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1469
1470         /* Enable Core digital and enable IOREG R/W */
1471         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1472         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1473         /* enable REG_EN */
1474         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1475
1476         /* Switch the control path. */
1477         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1478         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1479
1480         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1481         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1482         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1483                 rtlpriv->psc.pwrdomain_protect = false;
1484                 return;
1485         }
1486
1487         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1488
1489         /* After MACIO reset,we must refresh LED state. */
1490         _rtl92se_gen_refreshledstate(hw);
1491
1492         rtlpriv->psc.pwrdomain_protect = false;
1493 }
1494
1495 void rtl92se_card_disable(struct ieee80211_hw *hw)
1496 {
1497         struct rtl_priv *rtlpriv = rtl_priv(hw);
1498         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1499         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1500         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1501         enum nl80211_iftype opmode;
1502         u8 wait = 30;
1503
1504         rtlpriv->intf_ops->enable_aspm(hw);
1505
1506         if (rtlpci->driver_is_goingto_unload ||
1507                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1508                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1509
1510         /* we should chnge GPIO to input mode
1511          * this will drop away current about 25mA*/
1512         rtl8192se_gpiobit3_cfg_inputmode(hw);
1513
1514         /* this is very important for ips power save */
1515         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1516                 if (rtlpriv->psc.pwrdomain_protect)
1517                         mdelay(20);
1518                 else
1519                         break;
1520         }
1521
1522         mac->link_state = MAC80211_NOLINK;
1523         opmode = NL80211_IFTYPE_UNSPECIFIED;
1524         _rtl92se_set_media_status(hw, opmode);
1525
1526         _rtl92s_phy_set_rfhalt(hw);
1527         udelay(100);
1528 }
1529
1530 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1531                              u32 *p_intb)
1532 {
1533         struct rtl_priv *rtlpriv = rtl_priv(hw);
1534         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1535
1536         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1537         rtl_write_dword(rtlpriv, ISR, *p_inta);
1538
1539         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1540         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1541 }
1542
1543 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1544 {
1545         struct rtl_priv *rtlpriv = rtl_priv(hw);
1546         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1547         u16 bcntime_cfg = 0;
1548         u16 bcn_cw = 6, bcn_ifs = 0xf;
1549         u16 atim_window = 2;
1550
1551         /* ATIM Window (in unit of TU). */
1552         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1553
1554         /* Beacon interval (in unit of TU). */
1555         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1556
1557         /* DrvErlyInt (in unit of TU). (Time to send
1558          * interrupt to notify driver to change
1559          * beacon content) */
1560         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1561
1562         /* BcnDMATIM(in unit of us). Indicates the
1563          * time before TBTT to perform beacon queue DMA  */
1564         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1565
1566         /* Force beacon frame transmission even
1567          * after receiving beacon frame from
1568          * other ad hoc STA */
1569         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1570
1571         /* Beacon Time Configuration */
1572         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1573                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1574
1575         /* TODO: bcn_ifs may required to be changed on ASIC */
1576         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1577
1578         /*for beacon changed */
1579         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1580 }
1581
1582 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1583 {
1584         struct rtl_priv *rtlpriv = rtl_priv(hw);
1585         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1586         u16 bcn_interval = mac->beacon_interval;
1587
1588         /* Beacon interval (in unit of TU). */
1589         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1590         /* 2008.10.24 added by tynli for beacon changed. */
1591         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1592 }
1593
1594 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1595                 u32 add_msr, u32 rm_msr)
1596 {
1597         struct rtl_priv *rtlpriv = rtl_priv(hw);
1598         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1599
1600         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1601                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1602
1603         if (add_msr)
1604                 rtlpci->irq_mask[0] |= add_msr;
1605
1606         if (rm_msr)
1607                 rtlpci->irq_mask[0] &= (~rm_msr);
1608
1609         rtl92se_disable_interrupt(hw);
1610         rtl92se_enable_interrupt(hw);
1611 }
1612
1613 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1614 {
1615         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1616         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1617         u8 efuse_id;
1618
1619         rtlhal->ic_class = IC_INFERIORITY_A;
1620
1621         /* Only retrieving while using EFUSE. */
1622         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1623                 !rtlefuse->autoload_failflag) {
1624                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1625
1626                 if (efuse_id == 0xfe)
1627                         rtlhal->ic_class = IC_INFERIORITY_B;
1628         }
1629 }
1630
1631 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1632 {
1633         struct rtl_priv *rtlpriv = rtl_priv(hw);
1634         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1635         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1636         u16 i, usvalue;
1637         u16     eeprom_id;
1638         u8 tempval;
1639         u8 hwinfo[HWSET_MAX_SIZE_92S];
1640         u8 rf_path, index;
1641
1642         if (rtlefuse->epromtype == EEPROM_93C46) {
1643                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1644                          ("RTL819X Not boot from eeprom, check it !!"));
1645         } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1646                 rtl_efuse_shadow_map_update(hw);
1647
1648                 memcpy((void *)hwinfo, (void *)
1649                         &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1650                         HWSET_MAX_SIZE_92S);
1651         }
1652
1653         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1654                       hwinfo, HWSET_MAX_SIZE_92S);
1655
1656         eeprom_id = *((u16 *)&hwinfo[0]);
1657         if (eeprom_id != RTL8190_EEPROM_ID) {
1658                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1659                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1660                 rtlefuse->autoload_failflag = true;
1661         } else {
1662                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1663                 rtlefuse->autoload_failflag = false;
1664         }
1665
1666         if (rtlefuse->autoload_failflag)
1667                 return;
1668
1669         _rtl8192se_get_IC_Inferiority(hw);
1670
1671         /* Read IC Version && Channel Plan */
1672         /* VID, DID      SE     0xA-D */
1673         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1674         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1675         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1676         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1677         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1678
1679         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1680                         ("EEPROMId = 0x%4x\n", eeprom_id));
1681         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1682                         ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1683         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1684                         ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1685         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1686                         ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1687         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1688                         ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1689
1690         for (i = 0; i < 6; i += 2) {
1691                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1692                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1693         }
1694
1695         for (i = 0; i < 6; i++)
1696                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1697
1698         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1699                  ("%pM\n", rtlefuse->dev_addr));
1700
1701         /* Get Tx Power Level by Channel */
1702         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1703         /* 92S suupport RF A & B */
1704         for (rf_path = 0; rf_path < 2; rf_path++) {
1705                 for (i = 0; i < 3; i++) {
1706                         /* Read CCK RF A & B Tx power  */
1707                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1708                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1709
1710                         /* Read OFDM RF A & B Tx power for 1T */
1711                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1712                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1713
1714                         /* Read OFDM RF A & B Tx power for 2T */
1715                         rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1716                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1717                                    rf_path * 3 + i];
1718                 }
1719         }
1720
1721         for (rf_path = 0; rf_path < 2; rf_path++)
1722                 for (i = 0; i < 3; i++)
1723                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1724                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1725                                 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1726                                         [rf_path][i]));
1727         for (rf_path = 0; rf_path < 2; rf_path++)
1728                 for (i = 0; i < 3; i++)
1729                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1730                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1731                                  rf_path, i,
1732                                  rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1733                                                 [rf_path][i]));
1734         for (rf_path = 0; rf_path < 2; rf_path++)
1735                 for (i = 0; i < 3; i++)
1736                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1737                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1738                                  rf_path, i,
1739                                  rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1740                                         [rf_path][i]));
1741
1742         for (rf_path = 0; rf_path < 2; rf_path++) {
1743
1744                 /* Assign dedicated channel tx power */
1745                 for (i = 0; i < 14; i++)        {
1746                         /* channel 1~3 use the same Tx Power Level. */
1747                         if (i < 3)
1748                                 index = 0;
1749                         /* Channel 4-8 */
1750                         else if (i < 8)
1751                                 index = 1;
1752                         /* Channel 9-14 */
1753                         else
1754                                 index = 2;
1755
1756                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1757                          * tx power */
1758                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1759                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1760                                                         [rf_path][index];
1761                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1762                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1763                                                         [rf_path][index];
1764                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1765                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1766                                                         [rf_path][index];
1767                 }
1768
1769                 for (i = 0; i < 14; i++) {
1770                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1771                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1772                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1773                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1774                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1775                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1776                 }
1777         }
1778
1779         for (rf_path = 0; rf_path < 2; rf_path++) {
1780                 for (i = 0; i < 3; i++) {
1781                         /* Read Power diff limit. */
1782                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1783                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1784                 }
1785         }
1786
1787         for (rf_path = 0; rf_path < 2; rf_path++) {
1788                 /* Fill Pwr group */
1789                 for (i = 0; i < 14; i++) {
1790                         /* Chanel 1-3 */
1791                         if (i < 3)
1792                                 index = 0;
1793                         /* Channel 4-8 */
1794                         else if (i < 8)
1795                                 index = 1;
1796                         /* Channel 9-13 */
1797                         else
1798                                 index = 2;
1799
1800                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1801                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1802                                 0xf);
1803                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1804                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1805                                 0xf0) >> 4);
1806
1807                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1808                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1809                                  rf_path, i,
1810                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1811                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1812                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1813                                  rf_path, i,
1814                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1815                         }
1816         }
1817
1818         for (i = 0; i < 14; i++) {
1819                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1820                 /* channel 1-3 */
1821                 if (i < 3)
1822                         index = 0;
1823                 /* Channel 4-8 */
1824                 else if (i < 8)
1825                         index = 1;
1826                 /* Channel 9-14 */
1827                 else
1828                         index = 2;
1829
1830                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1831                            index]) & 0xff;
1832                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1833                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1834                                                  ((tempval >> 4) & 0xF);
1835
1836                 /* Read OFDM<->HT tx power diff */
1837                 /* Channel 1-3 */
1838                 if (i < 3)
1839                         index = 0;
1840                 /* Channel 4-8 */
1841                 else if (i < 8)
1842                         index = 0x11;
1843                 /* Channel 9-14 */
1844                 else
1845                         index = 1;
1846
1847                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1848                                   & 0xff;
1849                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1850                                  (tempval & 0xF);
1851                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1852                                  ((tempval >> 4) & 0xF);
1853
1854                 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1855                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1856         }
1857
1858         rtlefuse->eeprom_regulatory = 0;
1859         if (rtlefuse->eeprom_version >= 2) {
1860                 /* BIT(0)~2 */
1861                 if (rtlefuse->eeprom_version >= 4)
1862                         rtlefuse->eeprom_regulatory =
1863                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1864                 else /* BIT(0) */
1865                         rtlefuse->eeprom_regulatory =
1866                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1867         }
1868         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1869                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1870
1871         for (i = 0; i < 14; i++)
1872                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1873                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1874                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1875         for (i = 0; i < 14; i++)
1876                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1877                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1878                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1879         for (i = 0; i < 14; i++)
1880                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1881                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1882                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1883         for (i = 0; i < 14; i++)
1884                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1885                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1886                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1887
1888         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n",
1889                 rtlefuse->txpwr_safetyflag));
1890
1891         /* Read RF-indication and Tx Power gain
1892          * index diff of legacy to HT OFDM rate. */
1893         tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1894         rtlefuse->eeprom_txpowerdiff = tempval;
1895         rtlefuse->legacy_httxpowerdiff =
1896                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1897
1898         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n",
1899                 rtlefuse->eeprom_txpowerdiff));
1900
1901         /* Get TSSI value for each path. */
1902         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1903         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1904         usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1905         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1906
1907         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1908                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1909                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1910
1911         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1912         /* and read ThermalMeter from EEPROM */
1913         tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1914         rtlefuse->eeprom_thermalmeter = tempval;
1915         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n",
1916                 rtlefuse->eeprom_thermalmeter));
1917
1918         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1919         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1920         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1921
1922         /* Read CrystalCap from EEPROM */
1923         tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1924         rtlefuse->eeprom_crystalcap = tempval;
1925         /* CrystalCap, BIT(12)~15 */
1926         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1927
1928         /* Read IC Version && Channel Plan */
1929         /* Version ID, Channel plan */
1930         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1931         rtlefuse->txpwr_fromeprom = true;
1932         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n",
1933                 rtlefuse->eeprom_channelplan));
1934
1935         /* Read Customer ID or Board Type!!! */
1936         tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1937         /* Change RF type definition */
1938         if (tempval == 0)
1939                 rtlphy->rf_type = RF_2T2R;
1940         else if (tempval == 1)
1941                 rtlphy->rf_type = RF_1T2R;
1942         else if (tempval == 2)
1943                 rtlphy->rf_type = RF_1T2R;
1944         else if (tempval == 3)
1945                 rtlphy->rf_type = RF_1T1R;
1946
1947         /* 1T2R but 1SS (1x1 receive combining) */
1948         rtlefuse->b1x1_recvcombine = false;
1949         if (rtlphy->rf_type == RF_1T2R) {
1950                 tempval = rtl_read_byte(rtlpriv, 0x07);
1951                 if (!(tempval & BIT(0))) {
1952                         rtlefuse->b1x1_recvcombine = true;
1953                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1954                                 ("RF_TYPE=1T2R but only 1SS\n"));
1955                 }
1956         }
1957         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1958         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1959
1960         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("EEPROM Customer ID: 0x%2x",
1961                         rtlefuse->eeprom_oemid));
1962
1963         /* set channel paln to world wide 13 */
1964         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1965 }
1966
1967 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1968 {
1969         struct rtl_priv *rtlpriv = rtl_priv(hw);
1970         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1971         u8 tmp_u1b = 0;
1972
1973         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1974
1975         if (tmp_u1b & BIT(4)) {
1976                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1977                 rtlefuse->epromtype = EEPROM_93C46;
1978         } else {
1979                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1980                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1981         }
1982
1983         if (tmp_u1b & BIT(5)) {
1984                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1985                 rtlefuse->autoload_failflag = false;
1986                 _rtl92se_read_adapter_info(hw);
1987         } else {
1988                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1989                 rtlefuse->autoload_failflag = true;
1990         }
1991 }
1992
1993 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1994                                           struct ieee80211_sta *sta)
1995 {
1996         struct rtl_priv *rtlpriv = rtl_priv(hw);
1997         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1998         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1999         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2000         u32 ratr_value;
2001         u8 ratr_index = 0;
2002         u8 nmode = mac->ht_enable;
2003         u8 mimo_ps = IEEE80211_SMPS_OFF;
2004         u16 shortgi_rate = 0;
2005         u32 tmp_ratr_value = 0;
2006         u8 curtxbw_40mhz = mac->bw_40;
2007         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2008                                 1 : 0;
2009         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2010                                 1 : 0;
2011         enum wireless_mode wirelessmode = mac->mode;
2012
2013         if (rtlhal->current_bandtype == BAND_ON_5G)
2014                 ratr_value = sta->supp_rates[1] << 4;
2015         else
2016                 ratr_value = sta->supp_rates[0];
2017         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2018                         sta->ht_cap.mcs.rx_mask[0] << 12);
2019         switch (wirelessmode) {
2020         case WIRELESS_MODE_B:
2021                 ratr_value &= 0x0000000D;
2022                 break;
2023         case WIRELESS_MODE_G:
2024                 ratr_value &= 0x00000FF5;
2025                 break;
2026         case WIRELESS_MODE_N_24G:
2027         case WIRELESS_MODE_N_5G:
2028                 nmode = 1;
2029                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2030                         ratr_value &= 0x0007F005;
2031                 } else {
2032                         u32 ratr_mask;
2033
2034                         if (get_rf_type(rtlphy) == RF_1T2R ||
2035                             get_rf_type(rtlphy) == RF_1T1R) {
2036                                 if (curtxbw_40mhz)
2037                                         ratr_mask = 0x000ff015;
2038                                 else
2039                                         ratr_mask = 0x000ff005;
2040                         } else {
2041                                 if (curtxbw_40mhz)
2042                                         ratr_mask = 0x0f0ff015;
2043                                 else
2044                                         ratr_mask = 0x0f0ff005;
2045                         }
2046
2047                         ratr_value &= ratr_mask;
2048                 }
2049                 break;
2050         default:
2051                 if (rtlphy->rf_type == RF_1T2R)
2052                         ratr_value &= 0x000ff0ff;
2053                 else
2054                         ratr_value &= 0x0f0ff0ff;
2055
2056                 break;
2057         }
2058
2059         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2060                 ratr_value &= 0x0FFFFFFF;
2061         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2062                 ratr_value &= 0x0FFFFFF0;
2063
2064         if (nmode && ((curtxbw_40mhz &&
2065                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2066                                                  curshortgi_20mhz))) {
2067
2068                 ratr_value |= 0x10000000;
2069                 tmp_ratr_value = (ratr_value >> 12);
2070
2071                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2072                         if ((1 << shortgi_rate) & tmp_ratr_value)
2073                                 break;
2074                 }
2075
2076                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2077                     (shortgi_rate << 4) | (shortgi_rate);
2078
2079                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2080         }
2081
2082         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2083         if (ratr_value & 0xfffff000)
2084                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2085         else
2086                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2087
2088         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2089                  ("%x\n", rtl_read_dword(rtlpriv, ARFR0)));
2090 }
2091
2092 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2093                                          struct ieee80211_sta *sta,
2094                                          u8 rssi_level)
2095 {
2096         struct rtl_priv *rtlpriv = rtl_priv(hw);
2097         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2098         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2099         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2100         struct rtl_sta_info *sta_entry = NULL;
2101         u32 ratr_bitmap;
2102         u8 ratr_index = 0;
2103         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2104                                 ? 1 : 0;
2105         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2106                                 1 : 0;
2107         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2108                                 1 : 0;
2109         enum wireless_mode wirelessmode = 0;
2110         bool shortgi = false;
2111         u32 ratr_value = 0;
2112         u8 shortgi_rate = 0;
2113         u32 mask = 0;
2114         u32 band = 0;
2115         bool bmulticast = false;
2116         u8 macid = 0;
2117         u8 mimo_ps = IEEE80211_SMPS_OFF;
2118
2119         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2120         wirelessmode = sta_entry->wireless_mode;
2121         if (mac->opmode == NL80211_IFTYPE_STATION)
2122                 curtxbw_40mhz = mac->bw_40;
2123         else if (mac->opmode == NL80211_IFTYPE_AP ||
2124                 mac->opmode == NL80211_IFTYPE_ADHOC)
2125                 macid = sta->aid + 1;
2126
2127         if (rtlhal->current_bandtype == BAND_ON_5G)
2128                 ratr_bitmap = sta->supp_rates[1] << 4;
2129         else
2130                 ratr_bitmap = sta->supp_rates[0];
2131         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2132                         sta->ht_cap.mcs.rx_mask[0] << 12);
2133         switch (wirelessmode) {
2134         case WIRELESS_MODE_B:
2135                 band |= WIRELESS_11B;
2136                 ratr_index = RATR_INX_WIRELESS_B;
2137                 if (ratr_bitmap & 0x0000000c)
2138                         ratr_bitmap &= 0x0000000d;
2139                 else
2140                         ratr_bitmap &= 0x0000000f;
2141                 break;
2142         case WIRELESS_MODE_G:
2143                 band |= (WIRELESS_11G | WIRELESS_11B);
2144                 ratr_index = RATR_INX_WIRELESS_GB;
2145
2146                 if (rssi_level == 1)
2147                         ratr_bitmap &= 0x00000f00;
2148                 else if (rssi_level == 2)
2149                         ratr_bitmap &= 0x00000ff0;
2150                 else
2151                         ratr_bitmap &= 0x00000ff5;
2152                 break;
2153         case WIRELESS_MODE_A:
2154                 band |= WIRELESS_11A;
2155                 ratr_index = RATR_INX_WIRELESS_A;
2156                 ratr_bitmap &= 0x00000ff0;
2157                 break;
2158         case WIRELESS_MODE_N_24G:
2159         case WIRELESS_MODE_N_5G:
2160                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2161                 ratr_index = RATR_INX_WIRELESS_NGB;
2162
2163                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2164                         if (rssi_level == 1)
2165                                 ratr_bitmap &= 0x00070000;
2166                         else if (rssi_level == 2)
2167                                 ratr_bitmap &= 0x0007f000;
2168                         else
2169                                 ratr_bitmap &= 0x0007f005;
2170                 } else {
2171                         if (rtlphy->rf_type == RF_1T2R ||
2172                                 rtlphy->rf_type == RF_1T1R) {
2173                                 if (rssi_level == 1) {
2174                                                 ratr_bitmap &= 0x000f0000;
2175                                 } else if (rssi_level == 3) {
2176                                         ratr_bitmap &= 0x000fc000;
2177                                 } else if (rssi_level == 5) {
2178                                                 ratr_bitmap &= 0x000ff000;
2179                                 } else {
2180                                         if (curtxbw_40mhz)
2181                                                 ratr_bitmap &= 0x000ff015;
2182                                         else
2183                                                 ratr_bitmap &= 0x000ff005;
2184                                 }
2185                         } else {
2186                                 if (rssi_level == 1) {
2187                                         ratr_bitmap &= 0x0f8f0000;
2188                                 } else if (rssi_level == 3) {
2189                                         ratr_bitmap &= 0x0f8fc000;
2190                                 } else if (rssi_level == 5) {
2191                                         ratr_bitmap &= 0x0f8ff000;
2192                                 } else {
2193                                         if (curtxbw_40mhz)
2194                                                 ratr_bitmap &= 0x0f8ff015;
2195                                         else
2196                                                 ratr_bitmap &= 0x0f8ff005;
2197                                 }
2198                         }
2199                 }
2200
2201                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2202                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2203                         if (macid == 0)
2204                                 shortgi = true;
2205                         else if (macid == 1)
2206                                 shortgi = false;
2207                 }
2208                 break;
2209         default:
2210                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2211                 ratr_index = RATR_INX_WIRELESS_NGB;
2212
2213                 if (rtlphy->rf_type == RF_1T2R)
2214                         ratr_bitmap &= 0x000ff0ff;
2215                 else
2216                         ratr_bitmap &= 0x0f8ff0ff;
2217                 break;
2218         }
2219
2220         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2221                 ratr_bitmap &= 0x0FFFFFFF;
2222         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2223                 ratr_bitmap &= 0x0FFFFFF0;
2224
2225         if (shortgi) {
2226                 ratr_bitmap |= 0x10000000;
2227                 /* Get MAX MCS available. */
2228                 ratr_value = (ratr_bitmap >> 12);
2229                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2230                         if ((1 << shortgi_rate) & ratr_value)
2231                                 break;
2232                 }
2233
2234                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2235                         (shortgi_rate << 4) | (shortgi_rate);
2236                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2237         }
2238
2239         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2240
2241         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, ("mask = %x, bitmap = %x\n",
2242                         mask, ratr_bitmap));
2243         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2244         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2245
2246         if (macid != 0)
2247                 sta_entry->ratr_index = ratr_index;
2248 }
2249
2250 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2251                 struct ieee80211_sta *sta, u8 rssi_level)
2252 {
2253         struct rtl_priv *rtlpriv = rtl_priv(hw);
2254
2255         if (rtlpriv->dm.useramask)
2256                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2257         else
2258                 rtl92se_update_hal_rate_table(hw, sta);
2259 }
2260
2261 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2262 {
2263         struct rtl_priv *rtlpriv = rtl_priv(hw);
2264         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2265         u16 sifs_timer;
2266
2267         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2268                                       (u8 *)&mac->slot_time);
2269         sifs_timer = 0x0e0e;
2270         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2271
2272 }
2273
2274 /* this ifunction is for RFKILL, it's different with windows,
2275  * because UI will disable wireless when GPIO Radio Off.
2276  * And here we not check or Disable/Enable ASPM like windows*/
2277 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2278 {
2279         struct rtl_priv *rtlpriv = rtl_priv(hw);
2280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2281         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2282         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2283         unsigned long flag = 0;
2284         bool actuallyset = false;
2285         bool turnonbypowerdomain = false;
2286
2287         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2288         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2289                 return false;
2290
2291         if (ppsc->swrf_processing)
2292                 return false;
2293
2294         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2295         if (ppsc->rfchange_inprogress) {
2296                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2297                 return false;
2298         } else {
2299                 ppsc->rfchange_inprogress = true;
2300                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2301         }
2302
2303         /* cur_rfstate = ppsc->rfpwr_state;*/
2304
2305         /* because after _rtl92s_phy_set_rfhalt, all power
2306          * closed, so we must open some power for GPIO check,
2307          * or we will always check GPIO RFOFF here,
2308          * And we should close power after GPIO check */
2309         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2310                 _rtl92se_power_domain_init(hw);
2311                 turnonbypowerdomain = true;
2312         }
2313
2314         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2315
2316         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2317                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2318                          ("RFKILL-HW Radio ON, RF ON\n"));
2319
2320                 rfpwr_toset = ERFON;
2321                 ppsc->hwradiooff = false;
2322                 actuallyset = true;
2323         } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2324                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2325                          ("RFKILL-HW Radio OFF, RF OFF\n"));
2326
2327                 rfpwr_toset = ERFOFF;
2328                 ppsc->hwradiooff = true;
2329                 actuallyset = true;
2330         }
2331
2332         if (actuallyset) {
2333                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2334                 ppsc->rfchange_inprogress = false;
2335                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2336
2337         /* this not include ifconfig wlan0 down case */
2338         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2339         } else {
2340                 /* because power_domain_init may be happen when
2341                  * _rtl92s_phy_set_rfhalt, this will open some powers
2342                  * and cause current increasing about 40 mA for ips,
2343                  * rfoff and ifconfig down, so we set
2344                  * _rtl92s_phy_set_rfhalt again here */
2345                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2346                         turnonbypowerdomain) {
2347                         _rtl92s_phy_set_rfhalt(hw);
2348                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2349                 }
2350
2351                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2352                 ppsc->rfchange_inprogress = false;
2353                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2354         }
2355
2356         *valid = 1;
2357         return !ppsc->hwradiooff;
2358
2359 }
2360
2361 /* Is_wepkey just used for WEP used as group & pairwise key
2362  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2363 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2364         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2365 {
2366         struct rtl_priv *rtlpriv = rtl_priv(hw);
2367         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2368         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2369         u8 *macaddr = p_macaddr;
2370
2371         u32 entry_id = 0;
2372         bool is_pairwise = false;
2373
2374         static u8 cam_const_addr[4][6] = {
2375                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2376                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2377                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2378                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2379         };
2380         static u8 cam_const_broad[] = {
2381                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2382         };
2383
2384         if (clear_all) {
2385                 u8 idx = 0;
2386                 u8 cam_offset = 0;
2387                 u8 clear_number = 5;
2388
2389                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2390
2391                 for (idx = 0; idx < clear_number; idx++) {
2392                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2393                         rtl_cam_empty_entry(hw, cam_offset + idx);
2394
2395                         if (idx < 5) {
2396                                 memset(rtlpriv->sec.key_buf[idx], 0,
2397                                        MAX_KEY_LEN);
2398                                 rtlpriv->sec.key_len[idx] = 0;
2399                         }
2400                 }
2401
2402         } else {
2403                 switch (enc_algo) {
2404                 case WEP40_ENCRYPTION:
2405                         enc_algo = CAM_WEP40;
2406                         break;
2407                 case WEP104_ENCRYPTION:
2408                         enc_algo = CAM_WEP104;
2409                         break;
2410                 case TKIP_ENCRYPTION:
2411                         enc_algo = CAM_TKIP;
2412                         break;
2413                 case AESCCMP_ENCRYPTION:
2414                         enc_algo = CAM_AES;
2415                         break;
2416                 default:
2417                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2418                                         ("switch case not process\n"));
2419                         enc_algo = CAM_TKIP;
2420                         break;
2421                 }
2422
2423                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2424                         macaddr = cam_const_addr[key_index];
2425                         entry_id = key_index;
2426                 } else {
2427                         if (is_group) {
2428                                 macaddr = cam_const_broad;
2429                                 entry_id = key_index;
2430                         } else {
2431                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2432                                         entry_id = rtl_cam_get_free_entry(hw,
2433                                                                  p_macaddr);
2434                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2435                                                 RT_TRACE(rtlpriv,
2436                                                    COMP_SEC, DBG_EMERG,
2437                                                    ("Can not find free hw"
2438                                                    " security cam entry\n"));
2439                                                 return;
2440                                         }
2441                                 } else {
2442                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2443                                 }
2444
2445                                 key_index = PAIRWISE_KEYIDX;
2446                                 is_pairwise = true;
2447                         }
2448                 }
2449
2450                 if (rtlpriv->sec.key_len[key_index] == 0) {
2451                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2452                                  ("delete one entry, entry_id is %d\n",
2453                                  entry_id));
2454                         if (mac->opmode == NL80211_IFTYPE_AP)
2455                                 rtl_cam_del_entry(hw, p_macaddr);
2456                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2457                 } else {
2458                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2459                                  ("The insert KEY length is %d\n",
2460                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2461                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2462                                  ("The insert KEY  is %x %x\n",
2463                                   rtlpriv->sec.key_buf[0][0],
2464                                   rtlpriv->sec.key_buf[0][1]));
2465
2466                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2467                                  ("add one entry\n"));
2468                         if (is_pairwise) {
2469                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2470                                       "Pairwiase Key content :",
2471                                        rtlpriv->sec.pairwise_key,
2472                                        rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2473
2474                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2475                                          ("set Pairwiase key\n"));
2476
2477                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2478                                         entry_id, enc_algo,
2479                                         CAM_CONFIG_NO_USEDK,
2480                                         rtlpriv->sec.key_buf[key_index]);
2481                         } else {
2482                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2483                                          ("set group key\n"));
2484
2485                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2486                                         rtl_cam_add_one_entry(hw,
2487                                                 rtlefuse->dev_addr,
2488                                                 PAIRWISE_KEYIDX,
2489                                                 CAM_PAIRWISE_KEY_POSITION,
2490                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2491                                                 rtlpriv->sec.key_buf[entry_id]);
2492                                 }
2493
2494                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2495                                               entry_id, enc_algo,
2496                                               CAM_CONFIG_NO_USEDK,
2497                                               rtlpriv->sec.key_buf[entry_id]);
2498                         }
2499
2500                 }
2501         }
2502 }
2503
2504 void rtl92se_suspend(struct ieee80211_hw *hw)
2505 {
2506         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2507
2508         rtlpci->up_first_time = true;
2509 }
2510
2511 void rtl92se_resume(struct ieee80211_hw *hw)
2512 {
2513         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2514         u32 val;
2515
2516         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2517         if ((val & 0x0000ff00) != 0)
2518                 pci_write_config_dword(rtlpci->pdev, 0x40,
2519                         val & 0xffff00ff);
2520 }