drivers/net/wireless/rtlwifi/rtl8192ce/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "hw.h"
  36 #include "phy.h"
  37 #include "rf.h"
  38 #include "dm.h"
  39 #include "table.h"
  40
  41 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  42
  43 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
  44                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
  45 {
  46         struct rtl_priv *rtlpriv = rtl_priv(hw);
  47         u32 original_value, readback_value, bitshift;
  48         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  49         unsigned long flags;
  50
  51         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  52                                                "rfpath(%#x), bitmask(%#x)\n",
  53                                                regaddr, rfpath, bitmask));
  54
  55         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  56
  57         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  58                 original_value = _rtl92c_phy_rf_serial_read(hw,
  59                                                             rfpath, regaddr);
  60         } else {
  61                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  62                                                                rfpath, regaddr);
  63         }
  64
  65         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  66         readback_value = (original_value & bitmask) >> bitshift;
  67
  68         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
  69
  70         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  71                  ("regaddr(%#x), rfpath(%#x), "
  72                   "bitmask(%#x), original_value(%#x)\n",
  73                   regaddr, rfpath, bitmask, original_value));
  74
  75         return readback_value;
  76 }
  77
  78 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
  79 {
  80         struct rtl_priv *rtlpriv = rtl_priv(hw);
  81         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  82         bool is92c = IS_92C_SERIAL(rtlhal->version);
  83         bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
  84
  85         if (is92c)
  86                 rtl_write_byte(rtlpriv, 0x14, 0x71);
  87         return rtstatus;
  88 }
  89
  90 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
  91 {
  92         bool rtstatus = true;
  93         struct rtl_priv *rtlpriv = rtl_priv(hw);
  94         u16 regval;
  95         u32 regvaldw;
  96         u8 reg_hwparafile = 1;
  97
  98         _rtl92c_phy_init_bb_rf_register_definition(hw);
  99         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 100         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 101                        regval | BIT(13) | BIT(0) | BIT(1));
 102         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 103         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 104         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 105         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 106                        FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 107                        FEN_BB_GLB_RSTn | FEN_BBRSTB);
 108         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 109         regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 110         rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 111         if (reg_hwparafile == 1)
 112                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 113         return rtstatus;
 114 }
 115
 116 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
 117                             enum radio_path rfpath,
 118                             u32 regaddr, u32 bitmask, u32 data)
 119 {
 120         struct rtl_priv *rtlpriv = rtl_priv(hw);
 121         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 122         u32 original_value, bitshift;
 123         unsigned long flags;
 124
 125         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 126                  ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 127                   regaddr, bitmask, data, rfpath));
 128
 129         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 130
 131         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 132                 if (bitmask != RFREG_OFFSET_MASK) {
 133                         original_value = _rtl92c_phy_rf_serial_read(hw,
 134                                                                     rfpath,
 135                                                                     regaddr);
 136                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 137                         data =
 138                             ((original_value & (~bitmask)) |
 139                              (data << bitshift));
 140                 }
 141
 142                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 143         } else {
 144                 if (bitmask != RFREG_OFFSET_MASK) {
 145                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 146                                                                        rfpath,
 147                                                                        regaddr);
 148                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 149                         data =
 150                             ((original_value & (~bitmask)) |
 151                              (data << bitshift));
 152                 }
 153                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 154         }
 155
 156         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 157
 158         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 159                                                "bitmask(%#x), data(%#x), "
 160                                                "rfpath(%#x)\n", regaddr,
 161                                                bitmask, data, rfpath));
 162 }
 163
 164 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 165 {
 166         struct rtl_priv *rtlpriv = rtl_priv(hw);
 167         u32 i;
 168         u32 arraylength;
 169         u32 *ptrarray;
 170
 171         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
 172         arraylength = MAC_2T_ARRAYLENGTH;
 173         ptrarray = RTL8192CEMAC_2T_ARRAY;
 174         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 175                  ("Img:RTL8192CEMAC_2T_ARRAY\n"));
 176         for (i = 0; i < arraylength; i = i + 2)
 177                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 178         return true;
 179 }
 180
 181 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 182                                             u8 configtype)
 183 {
 184         int i;
 185         u32 *phy_regarray_table;
 186         u32 *agctab_array_table;
 187         u16 phy_reg_arraylen, agctab_arraylen;
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190
 191         if (IS_92C_SERIAL(rtlhal->version)) {
 192                 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 193                 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 194                 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 195                 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 196         } else {
 197                 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 198                 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 199                 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 200                 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 201         }
 202         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 203                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 204                         if (phy_regarray_table[i] == 0xfe)
 205                                 mdelay(50);
 206                         else if (phy_regarray_table[i] == 0xfd)
 207                                 mdelay(5);
 208                         else if (phy_regarray_table[i] == 0xfc)
 209                                 mdelay(1);
 210                         else if (phy_regarray_table[i] == 0xfb)
 211                                 udelay(50);
 212                         else if (phy_regarray_table[i] == 0xfa)
 213                                 udelay(5);
 214                         else if (phy_regarray_table[i] == 0xf9)
 215                                 udelay(1);
 216                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 217                                       phy_regarray_table[i + 1]);
 218                         udelay(1);
 219                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 220                                  ("The phy_regarray_table[0] is %x"
 221                                   " Rtl819XPHY_REGArray[1] is %x\n",
 222                                   phy_regarray_table[i],
 223                                   phy_regarray_table[i + 1]));
 224                 }
 225         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 226                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 227                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 228                                       agctab_array_table[i + 1]);
 229                         udelay(1);
 230                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 231                                  ("The agctab_array_table[0] is "
 232                                   "%x Rtl819XPHY_REGArray[1] is %x\n",
 233                                   agctab_array_table[i],
 234                                   agctab_array_table[i + 1]));
 235                 }
 236         }
 237         return true;
 238 }
 239
 240 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 241                                               u8 configtype)
 242 {
 243         struct rtl_priv *rtlpriv = rtl_priv(hw);
 244         int i;
 245         u32 *phy_regarray_table_pg;
 246         u16 phy_regarray_pg_len;
 247
 248         phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 249         phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 250
 251         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 252                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 253                         if (phy_regarray_table_pg[i] == 0xfe)
 254                                 mdelay(50);
 255                         else if (phy_regarray_table_pg[i] == 0xfd)
 256                                 mdelay(5);
 257                         else if (phy_regarray_table_pg[i] == 0xfc)
 258                                 mdelay(1);
 259                         else if (phy_regarray_table_pg[i] == 0xfb)
 260                                 udelay(50);
 261                         else if (phy_regarray_table_pg[i] == 0xfa)
 262                                 udelay(5);
 263                         else if (phy_regarray_table_pg[i] == 0xf9)
 264                                 udelay(1);
 265
 266                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 267                                                phy_regarray_table_pg[i],
 268                                                phy_regarray_table_pg[i + 1],
 269                                                phy_regarray_table_pg[i + 2]);
 270                 }
 271         } else {
 272
 273                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 274                          ("configtype != BaseBand_Config_PHY_REG\n"));
 275         }
 276         return true;
 277 }
 278
 279 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 280                                           enum radio_path rfpath)
 281 {
 282
 283         int i;
 284         u32 *radioa_array_table;
 285         u32 *radiob_array_table;
 286         u16 radioa_arraylen, radiob_arraylen;
 287         struct rtl_priv *rtlpriv = rtl_priv(hw);
 288         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 289
 290         if (IS_92C_SERIAL(rtlhal->version)) {
 291                 radioa_arraylen = RADIOA_2TARRAYLENGTH;
 292                 radioa_array_table = RTL8192CERADIOA_2TARRAY;
 293                 radiob_arraylen = RADIOB_2TARRAYLENGTH;
 294                 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 295                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 296                          ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
 297                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 298                          ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
 299         } else {
 300                 radioa_arraylen = RADIOA_1TARRAYLENGTH;
 301                 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 302                 radiob_arraylen = RADIOB_1TARRAYLENGTH;
 303                 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 304                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 305                          ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
 306                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 307                          ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
 308         }
 309         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
 310         switch (rfpath) {
 311         case RF90_PATH_A:
 312                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 313                         if (radioa_array_table[i] == 0xfe)
 314                                 mdelay(50);
 315                         else if (radioa_array_table[i] == 0xfd)
 316                                 mdelay(5);
 317                         else if (radioa_array_table[i] == 0xfc)
 318                                 mdelay(1);
 319                         else if (radioa_array_table[i] == 0xfb)
 320                                 udelay(50);
 321                         else if (radioa_array_table[i] == 0xfa)
 322                                 udelay(5);
 323                         else if (radioa_array_table[i] == 0xf9)
 324                                 udelay(1);
 325                         else {
 326                                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 327                                               RFREG_OFFSET_MASK,
 328                                               radioa_array_table[i + 1]);
 329                                 udelay(1);
 330                         }
 331                 }
 332                 break;
 333         case RF90_PATH_B:
 334                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 335                         if (radiob_array_table[i] == 0xfe) {
 336                                 mdelay(50);
 337                         } else if (radiob_array_table[i] == 0xfd)
 338                                 mdelay(5);
 339                         else if (radiob_array_table[i] == 0xfc)
 340                                 mdelay(1);
 341                         else if (radiob_array_table[i] == 0xfb)
 342                                 udelay(50);
 343                         else if (radiob_array_table[i] == 0xfa)
 344                                 udelay(5);
 345                         else if (radiob_array_table[i] == 0xf9)
 346                                 udelay(1);
 347                         else {
 348                                 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
 349                                               RFREG_OFFSET_MASK,
 350                                               radiob_array_table[i + 1]);
 351                                 udelay(1);
 352                         }
 353                 }
 354                 break;
 355         case RF90_PATH_C:
 356                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 357                          ("switch case not process\n"));
 358                 break;
 359         case RF90_PATH_D:
 360                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 361                          ("switch case not process\n"));
 362                 break;
 363         }
 364         return true;
 365 }
 366
 367 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 371         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 372         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 373         u8 reg_bw_opmode;
 374         u8 reg_prsr_rsc;
 375
 376         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 377                  ("Switch to %s bandwidth\n",
 378                   rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 379                   "20MHz" : "40MHz"))
 380
 381         if (is_hal_stop(rtlhal)) {
 382                 rtlphy->set_bwmode_inprogress = false;
 383                 return;
 384         }
 385
 386         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 387         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 388
 389         switch (rtlphy->current_chan_bw) {
 390         case HT_CHANNEL_WIDTH_20:
 391                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 392                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 393                 break;
 394         case HT_CHANNEL_WIDTH_20_40:
 395                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 396                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 397                 reg_prsr_rsc =
 398                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 399                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 400                 break;
 401         default:
 402                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 403                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 404                 break;
 405         }
 406
 407         switch (rtlphy->current_chan_bw) {
 408         case HT_CHANNEL_WIDTH_20:
 409                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 410                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 411                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 412                 break;
 413         case HT_CHANNEL_WIDTH_20_40:
 414                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 415                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 416
 417                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 418                               (mac->cur_40_prime_sc >> 1));
 419                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 420                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 421
 422                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 423                               (mac->cur_40_prime_sc ==
 424                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 425                 break;
 426         default:
 427                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 428                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 429                 break;
 430         }
 431         rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 432         rtlphy->set_bwmode_inprogress = false;
 433         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
 434 }
 435
 436 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 437 {
 438         u8 tmpreg;
 439         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 440         struct rtl_priv *rtlpriv = rtl_priv(hw);
 441
 442         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 443
 444         if ((tmpreg & 0x70) != 0)
 445                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 446         else
 447                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 448
 449         if ((tmpreg & 0x70) != 0) {
 450                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 451
 452                 if (is2t)
 453                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 454                                                   MASK12BITS);
 455
 456                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 457                               (rf_a_mode & 0x8FFFF) | 0x10000);
 458
 459                 if (is2t)
 460                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 461                                       (rf_b_mode & 0x8FFFF) | 0x10000);
 462         }
 463         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 464
 465         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 466
 467         mdelay(100);
 468
 469         if ((tmpreg & 0x70) != 0) {
 470                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 471                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 472
 473                 if (is2t)
 474                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 475                                       rf_b_mode);
 476         } else {
 477                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 478         }
 479 }
 480
 481 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
 482 {
 483         u32 u4b_tmp;
 484         u8 delay = 5;
 485         struct rtl_priv *rtlpriv = rtl_priv(hw);
 486
 487         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 488         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 489         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 490         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 491         while (u4b_tmp != 0 && delay > 0) {
 492                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
 493                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 494                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 495                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 496                 delay--;
 497         }
 498         if (delay == 0) {
 499                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
 500                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 501                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
 502                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 503                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 504                          ("Switch RF timeout !!!.\n"));
 505                 return;
 506         }
 507         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 508         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
 509 }
 510
 511 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 512                                             enum rf_pwrstate rfpwr_state)
 513 {
 514         struct rtl_priv *rtlpriv = rtl_priv(hw);
 515         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 516         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 517         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 518         bool bresult = true;
 519         u8 i, queue_id;
 520         struct rtl8192_tx_ring *ring = NULL;
 521
 522         ppsc->set_rfpowerstate_inprogress = true;
 523         switch (rfpwr_state) {
 524         case ERFON:{
 525                         if ((ppsc->rfpwr_state == ERFOFF) &&
 526                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 527                                 bool rtstatus;
 528                                 u32 InitializeCount = 0;
 529                                 do {
 530                                         InitializeCount++;
 531                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 532                                                  ("IPS Set eRf nic enable\n"));
 533                                         rtstatus = rtl_ps_enable_nic(hw);
 534                                 } while ((rtstatus != true)
 535                                          && (InitializeCount < 10));
 536                                 RT_CLEAR_PS_LEVEL(ppsc,
 537                                                   RT_RF_OFF_LEVL_HALT_NIC);
 538                         } else {
 539                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 540                                          ("Set ERFON sleeped:%d ms\n",
 541                                           jiffies_to_msecs(jiffies -
 542                                                    ppsc->
 543                                                    last_sleep_jiffies)));
 544                                 ppsc->last_awake_jiffies = jiffies;
 545                                 rtl92ce_phy_set_rf_on(hw);
 546                         }
 547                         if (mac->link_state == MAC80211_LINKED) {
 548                                 rtlpriv->cfg->ops->led_control(hw,
 549                                                                LED_CTL_LINK);
 550                         } else {
 551                                 rtlpriv->cfg->ops->led_control(hw,
 552                                                                LED_CTL_NO_LINK);
 553                         }
 554                         break;
 555                 }
 556         case ERFOFF:{
 557                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 558                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 559                                          ("IPS Set eRf nic disable\n"));
 560                                 rtl_ps_disable_nic(hw);
 561                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 562                         } else {
 563                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 564                                         rtlpriv->cfg->ops->led_control(hw,
 565                                                                LED_CTL_NO_LINK);
 566                                 } else {
 567                                         rtlpriv->cfg->ops->led_control(hw,
 568                                                              LED_CTL_POWER_OFF);
 569                                 }
 570                         }
 571                         break;
 572                 }
 573         case ERFSLEEP:{
 574                         if (ppsc->rfpwr_state == ERFOFF)
 575                                 break;
 576                         for (queue_id = 0, i = 0;
 577                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 578                                 ring = &pcipriv->dev.tx_ring[queue_id];
 579                                 if (skb_queue_len(&ring->queue) == 0) {
 580                                         queue_id++;
 581                                         continue;
 582                                 } else {
 583                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 584                                                  ("eRf Off/Sleep: %d times "
 585                                                   "TcbBusyQueue[%d] =%d before "
 586                                                   "doze!\n", (i + 1), queue_id,
 587                                                   skb_queue_len(&ring->queue)));
 588
 589                                         udelay(10);
 590                                         i++;
 591                                 }
 592                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 593                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 594                                                  ("\n ERFSLEEP: %d times "
 595                                                   "TcbBusyQueue[%d] = %d !\n",
 596                                                   MAX_DOZE_WAITING_TIMES_9x,
 597                                                   queue_id,
 598                                                   skb_queue_len(&ring->queue)));
 599                                         break;
 600                                 }
 601                         }
 602                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 603                                  ("Set ERFSLEEP awaked:%d ms\n",
 604                                   jiffies_to_msecs(jiffies -
 605                                                    ppsc->last_awake_jiffies)));
 606                         ppsc->last_sleep_jiffies = jiffies;
 607                         _rtl92ce_phy_set_rf_sleep(hw);
 608                         break;
 609                 }
 610         default:
 611                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 612                          ("switch case not process\n"));
 613                 bresult = false;
 614                 break;
 615         }
 616         if (bresult)
 617                 ppsc->rfpwr_state = rfpwr_state;
 618         ppsc->set_rfpowerstate_inprogress = false;
 619         return bresult;
 620 }
 621
 622 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 623                                    enum rf_pwrstate rfpwr_state)
 624 {
 625         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 626
 627         bool bresult = false;
 628
 629         if (rfpwr_state == ppsc->rfpwr_state)
 630                 return bresult;
 631         bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 632         return bresult;
 633 }