drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          ("switch case not process\n"));
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               (u8 *) (&e_aci));
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool) (*(u8 *) val);
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *((u8 *) val);
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                           mac->min_space_cfg));
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *((u8 *) val);
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                   mac->min_space_cfg));
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *((u8 *) val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                           factor_toset));
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *) val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (u8 *) (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *((u8 *) val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  ("HW_VAR_ACM_CTRL acm set "
 352                                                   "failed: eACI is %d\n", acm));
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  ("switch case not process\n"));
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 375                                   "Write 0x%X\n", acm_ctrl));
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = ((u8 *) (val))[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 415                                                (*(u8 *) val));
 416                         } else {
 417                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 418                                                ((*(u8 *) val) | BIT(7)));
 419                         }
 420
 421                         break;
 422                 }
 423         case HW_VAR_H2C_FW_PWRMODE:{
 424                         u8 psmode = (*(u8 *) val);
 425
 426                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 427                             (!IS_92C_SERIAL(rtlhal->version))) {
 428                                 rtl92c_dm_rf_saving(hw, true);
 429                         }
 430
 431                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 432                         break;
 433                 }
 434         case HW_VAR_FW_PSMODE_STATUS:
 435                 ppsc->fw_current_inpsmode = *((bool *) val);
 436                 break;
 437         case HW_VAR_H2C_FW_JOINBSSRPT:{
 438                         u8 mstatus = (*(u8 *) val);
 439                         u8 tmp_regcr, tmp_reg422;
 440                         bool recover = false;
 441
 442                         if (mstatus == RT_MEDIA_CONNECT) {
 443                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 444                                                               NULL);
 445
 446                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 447                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 448                                                (tmp_regcr | BIT(0)));
 449
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 451                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 452
 453                                 tmp_reg422 =
 454                                     rtl_read_byte(rtlpriv,
 455                                                   REG_FWHW_TXQ_CTRL + 2);
 456                                 if (tmp_reg422 & BIT(6))
 457                                         recover = true;
 458                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 459                                                tmp_reg422 & (~BIT(6)));
 460
 461                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 462
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 464                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 465
 466                                 if (recover) {
 467                                         rtl_write_byte(rtlpriv,
 468                                                        REG_FWHW_TXQ_CTRL + 2,
 469                                                        tmp_reg422);
 470                                 }
 471
 472                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 473                                                (tmp_regcr & ~(BIT(0))));
 474                         }
 475                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 476
 477                         break;
 478                 }
 479         case HW_VAR_AID:{
 480                         u16 u2btmp;
 481                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 482                         u2btmp &= 0xC000;
 483                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 484                                                 mac->assoc_id));
 485
 486                         break;
 487                 }
 488         case HW_VAR_CORRECT_TSF:{
 489                         u8 btype_ibss = ((u8 *) (val))[0];
 490
 491                         if (btype_ibss)
 492                                 _rtl92ce_stop_tx_beacon(hw);
 493
 494                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 495
 496                         rtl_write_dword(rtlpriv, REG_TSFTR,
 497                                         (u32) (mac->tsf & 0xffffffff));
 498                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 499                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 500
 501                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 502
 503                         if (btype_ibss)
 504                                 _rtl92ce_resume_tx_beacon(hw);
 505
 506                         break;
 507
 508                 }
 509         default:
 510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
 511                                                         "not process\n"));
 512                 break;
 513         }
 514 }
 515
 516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         bool status = true;
 520         long count = 0;
 521         u32 value = _LLT_INIT_ADDR(address) |
 522             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 523
 524         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 525
 526         do {
 527                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 528                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 529                         break;
 530
 531                 if (count > POLLING_LLT_THRESHOLD) {
 532                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 533                                  ("Failed to polling write LLT done at "
 534                                   "address %d!\n", address));
 535                         status = false;
 536                         break;
 537                 }
 538         } while (++count);
 539
 540         return status;
 541 }
 542
 543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 544 {
 545         struct rtl_priv *rtlpriv = rtl_priv(hw);
 546         unsigned short i;
 547         u8 txpktbuf_bndy;
 548         u8 maxPage;
 549         bool status;
 550
 551 #if LLT_CONFIG == 1
 552         maxPage = 255;
 553         txpktbuf_bndy = 252;
 554 #elif LLT_CONFIG == 2
 555         maxPage = 127;
 556         txpktbuf_bndy = 124;
 557 #elif LLT_CONFIG == 3
 558         maxPage = 255;
 559         txpktbuf_bndy = 174;
 560 #elif LLT_CONFIG == 4
 561         maxPage = 255;
 562         txpktbuf_bndy = 246;
 563 #elif LLT_CONFIG == 5
 564         maxPage = 255;
 565         txpktbuf_bndy = 246;
 566 #endif
 567
 568 #if LLT_CONFIG == 1
 569         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 570         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 571 #elif LLT_CONFIG == 2
 572         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 573 #elif LLT_CONFIG == 3
 574         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 575 #elif LLT_CONFIG == 4
 576         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 577 #elif LLT_CONFIG == 5
 578         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 579
 580         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 581 #endif
 582
 583         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 584         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 585
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 587         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 588
 589         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 590         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 591         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 592
 593         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 594                 status = _rtl92ce_llt_write(hw, i, i + 1);
 595                 if (true != status)
 596                         return status;
 597         }
 598
 599         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 600         if (true != status)
 601                 return status;
 602
 603         for (i = txpktbuf_bndy; i < maxPage; i++) {
 604                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 605                 if (true != status)
 606                         return status;
 607         }
 608
 609         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 610         if (true != status)
 611                 return status;
 612
 613         return true;
 614 }
 615
 616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 617 {
 618         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 619         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 621         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 622
 623         if (rtlpci->up_first_time)
 624                 return;
 625
 626         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 627                 rtl92ce_sw_led_on(hw, pLed0);
 628         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 629                 rtl92ce_sw_led_on(hw, pLed0);
 630         else
 631                 rtl92ce_sw_led_off(hw, pLed0);
 632 }
 633
 634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 635 {
 636         struct rtl_priv *rtlpriv = rtl_priv(hw);
 637         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 638         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 639         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 640
 641         unsigned char bytetmp;
 642         unsigned short wordtmp;
 643         u16 retry;
 644
 645         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 646         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 647                 u32 value32;
 648                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 649                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 650                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 651         }
 652         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 653         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 654
 655         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 656                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 657
 658                 u4b_tmp &= (~0x00024800);
 659                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 660         }
 661
 662         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 663         udelay(2);
 664
 665         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 666         udelay(2);
 667
 668         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 669         udelay(2);
 670
 671         retry = 0;
 672         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 673                                                 rtl_read_dword(rtlpriv, 0xEC),
 674                                                 bytetmp));
 675
 676         while ((bytetmp & BIT(0)) && retry < 1000) {
 677                 retry++;
 678                 udelay(50);
 679                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 680                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 681                                                         rtl_read_dword(rtlpriv,
 682                                                                        0xEC),
 683                                                         bytetmp));
 684                 udelay(50);
 685         }
 686
 687         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 688
 689         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 690         udelay(2);
 691
 692         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 693                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 694                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 695         }
 696
 697         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 698
 699         if (_rtl92ce_llt_table_init(hw) == false)
 700                 return false;
 701
 702         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 703         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 704
 705         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 706
 707         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 708         wordtmp &= 0xf;
 709         wordtmp |= 0xF771;
 710         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 711
 712         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 713         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 714         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 715
 716         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 717
 718         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 719                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 720                         DMA_BIT_MASK(32));
 721         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 722                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 723                         DMA_BIT_MASK(32));
 724         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 725                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 726         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 727                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 728         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 729                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 730         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 731                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 732         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 733                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 734                         DMA_BIT_MASK(32));
 735         rtl_write_dword(rtlpriv, REG_RX_DESA,
 736                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 737                         DMA_BIT_MASK(32));
 738
 739         if (IS_92C_SERIAL(rtlhal->version))
 740                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 741         else
 742                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 743
 744         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 745
 746         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 747         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 748         do {
 749                 retry++;
 750                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 751         } while ((retry < 200) && (bytetmp & BIT(7)));
 752
 753         _rtl92ce_gen_refresh_led_state(hw);
 754
 755         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 756
 757         return true;
 758 }
 759
 760 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 761 {
 762         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 763         struct rtl_priv *rtlpriv = rtl_priv(hw);
 764         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 765         u8 reg_bw_opmode;
 766         u32 reg_prsr;
 767
 768         reg_bw_opmode = BW_OPMODE_20MHZ;
 769         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 770
 771         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 772
 773         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 774
 775         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 776
 777         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 778
 779         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 780
 781         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 782
 783         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 784
 785         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 786
 787         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 788
 789         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 790         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 791         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 792         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 793
 794         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 795             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 796                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 797         else
 798                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 799
 800         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 801
 802         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 803
 804         rtlpci->reg_bcn_ctrl_val = 0x1f;
 805         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 806
 807         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 808
 809         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 810
 811         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 812         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 813
 814         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 815             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 816                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 817                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 818         } else {
 819                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 820                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 821         }
 822
 823         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 824              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 825                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 826         else
 827                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 828
 829         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 830
 831         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 832         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 833
 834         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 835
 836         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 837
 838         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 839         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 840
 841 }
 842
 843 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 844 {
 845         struct rtl_priv *rtlpriv = rtl_priv(hw);
 846         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 847
 848         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 849         rtl_write_word(rtlpriv, 0x350, 0x870c);
 850         rtl_write_byte(rtlpriv, 0x352, 0x1);
 851
 852         if (ppsc->support_backdoor)
 853                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 854         else
 855                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 856
 857         rtl_write_word(rtlpriv, 0x350, 0x2718);
 858         rtl_write_byte(rtlpriv, 0x352, 0x1);
 859 }
 860
 861 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 862 {
 863         struct rtl_priv *rtlpriv = rtl_priv(hw);
 864         u8 sec_reg_value;
 865
 866         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 867                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 868                   rtlpriv->sec.pairwise_enc_algorithm,
 869                   rtlpriv->sec.group_enc_algorithm));
 870
 871         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 872                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
 873                                                         "hw encryption\n"));
 874                 return;
 875         }
 876
 877         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 878
 879         if (rtlpriv->sec.use_defaultkey) {
 880                 sec_reg_value |= SCR_TxUseDK;
 881                 sec_reg_value |= SCR_RxUseDK;
 882         }
 883
 884         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 885
 886         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 887
 888         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 889                  ("The SECR-value %x\n", sec_reg_value));
 890
 891         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 892
 893 }
 894
 895 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 896 {
 897         struct rtl_priv *rtlpriv = rtl_priv(hw);
 898         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 899         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 900         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 901         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 902         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 903         static bool iqk_initialized; /* initialized to false */
 904         bool rtstatus = true;
 905         bool is92c;
 906         int err;
 907         u8 tmp_u1b;
 908         unsigned long flags;
 909
 910         rtlpci->being_init_adapter = true;
 911
 912         /* Since this function can take a very long time (up to 350 ms)
 913          * and can be called with irqs disabled, reenable the irqs
 914          * to let the other devices continue being serviced.
 915          *
 916          * It is safe doing so since our own interrupts will only be enabled
 917          * in a subsequent step.
 918          */
 919         local_save_flags(flags);
 920         local_irq_enable();
 921
 922         rtlpriv->intf_ops->disable_aspm(hw);
 923         rtstatus = _rtl92ce_init_mac(hw);
 924         if (rtstatus != true) {
 925                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
 926                 err = 1;
 927                 goto exit;
 928         }
 929
 930         err = rtl92c_download_fw(hw);
 931         if (err) {
 932                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 933                          ("Failed to download FW. Init HW "
 934                           "without FW now..\n"));
 935                 err = 1;
 936                 rtlhal->fw_ready = false;
 937                 goto exit;
 938         } else {
 939                 rtlhal->fw_ready = true;
 940         }
 941
 942         rtlhal->last_hmeboxnum = 0;
 943         rtl92c_phy_mac_config(hw);
 944         rtl92c_phy_bb_config(hw);
 945         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 946         rtl92c_phy_rf_config(hw);
 947         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 948                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 949         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 950                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 951         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 952         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 953         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 954         _rtl92ce_hw_configure(hw);
 955         rtl_cam_reset_all_entry(hw);
 956         rtl92ce_enable_hw_security_config(hw);
 957
 958         ppsc->rfpwr_state = ERFON;
 959
 960         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 961         _rtl92ce_enable_aspm_back_door(hw);
 962         rtlpriv->intf_ops->enable_aspm(hw);
 963
 964         rtl8192ce_bt_hw_init(hw);
 965
 966         if (ppsc->rfpwr_state == ERFON) {
 967                 rtl92c_phy_set_rfpath_switch(hw, 1);
 968                 if (iqk_initialized) {
 969                         rtl92c_phy_iq_calibrate(hw, true);
 970                 } else {
 971                         rtl92c_phy_iq_calibrate(hw, false);
 972                         iqk_initialized = true;
 973                 }
 974
 975                 rtl92c_dm_check_txpower_tracking(hw);
 976                 rtl92c_phy_lc_calibrate(hw);
 977         }
 978
 979         is92c = IS_92C_SERIAL(rtlhal->version);
 980         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 981         if (!(tmp_u1b & BIT(0))) {
 982                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 983                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
 984         }
 985
 986         if (!(tmp_u1b & BIT(1)) && is92c) {
 987                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 988                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
 989         }
 990
 991         if (!(tmp_u1b & BIT(4))) {
 992                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 993                 tmp_u1b &= 0x0F;
 994                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 995                 udelay(10);
 996                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 997                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
 998         }
 999         rtl92c_dm_init(hw);
1000 exit:
1001         local_irq_restore(flags);
1002         rtlpci->being_init_adapter = false;
1003         return err;
1004 }
1005
1006 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1007 {
1008         struct rtl_priv *rtlpriv = rtl_priv(hw);
1009         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1010         enum version_8192c version = VERSION_UNKNOWN;
1011         u32 value32;
1012
1013         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1014         if (value32 & TRP_VAUX_EN) {
1015                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1016                            VERSION_A_CHIP_88C;
1017         } else {
1018                 version = (enum version_8192c) (CHIP_VER_B |
1019                                 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1020                                 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1021                 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1022                      CHIP_VER_RTL_MASK)) {
1023                         version = (enum version_8192c)(version |
1024                                    ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1025                                    ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1026                                    CHIP_VENDOR_UMC));
1027                 }
1028         }
1029
1030         switch (version) {
1031         case VERSION_B_CHIP_92C:
1032                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1033                          ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1034                 break;
1035         case VERSION_B_CHIP_88C:
1036                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1037                          ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1038                 break;
1039         case VERSION_A_CHIP_92C:
1040                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1041                          ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1042                 break;
1043         case VERSION_A_CHIP_88C:
1044                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1045                          ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1046                 break;
1047         default:
1048                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1049                          ("Chip Version ID: Unknown. Bug?\n"));
1050                 break;
1051         }
1052
1053         switch (version & 0x3) {
1054         case CHIP_88C:
1055                 rtlphy->rf_type = RF_1T1R;
1056                 break;
1057         case CHIP_92C:
1058                 rtlphy->rf_type = RF_2T2R;
1059                 break;
1060         case CHIP_92C_1T2R:
1061                 rtlphy->rf_type = RF_1T2R;
1062                 break;
1063         default:
1064                 rtlphy->rf_type = RF_1T1R;
1065                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1066                          ("ERROR RF_Type is set!!"));
1067                 break;
1068         }
1069
1070         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1071                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1072                   "RF_2T2R" : "RF_1T1R"));
1073
1074         return version;
1075 }
1076
1077 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1078                                      enum nl80211_iftype type)
1079 {
1080         struct rtl_priv *rtlpriv = rtl_priv(hw);
1081         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1082         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1083         bt_msr &= 0xfc;
1084
1085         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1086             type == NL80211_IFTYPE_STATION) {
1087                 _rtl92ce_stop_tx_beacon(hw);
1088                 _rtl92ce_enable_bcn_sub_func(hw);
1089         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1090                 _rtl92ce_resume_tx_beacon(hw);
1091                 _rtl92ce_disable_bcn_sub_func(hw);
1092         } else {
1093                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1094                          ("Set HW_VAR_MEDIA_STATUS: "
1095                           "No such media status(%x).\n", type));
1096         }
1097
1098         switch (type) {
1099         case NL80211_IFTYPE_UNSPECIFIED:
1100                 bt_msr |= MSR_NOLINK;
1101                 ledaction = LED_CTL_LINK;
1102                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1103                          ("Set Network type to NO LINK!\n"));
1104                 break;
1105         case NL80211_IFTYPE_ADHOC:
1106                 bt_msr |= MSR_ADHOC;
1107                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1108                          ("Set Network type to Ad Hoc!\n"));
1109                 break;
1110         case NL80211_IFTYPE_STATION:
1111                 bt_msr |= MSR_INFRA;
1112                 ledaction = LED_CTL_LINK;
1113                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1114                          ("Set Network type to STA!\n"));
1115                 break;
1116         case NL80211_IFTYPE_AP:
1117                 bt_msr |= MSR_AP;
1118                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1119                          ("Set Network type to AP!\n"));
1120                 break;
1121         default:
1122                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1123                          ("Network type %d not support!\n", type));
1124                 return 1;
1125                 break;
1126
1127         }
1128
1129         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1130         rtlpriv->cfg->ops->led_control(hw, ledaction);
1131         if ((bt_msr & 0xfc) == MSR_AP)
1132                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1133         else
1134                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1135         return 0;
1136 }
1137
1138 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1139 {
1140         struct rtl_priv *rtlpriv = rtl_priv(hw);
1141         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1142
1143         if (rtlpriv->psc.rfpwr_state != ERFON)
1144                 return;
1145
1146         if (check_bssid) {
1147                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1148                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1149                                               (u8 *) (&reg_rcr));
1150                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1151         } else if (check_bssid == false) {
1152                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1153                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1154                 rtlpriv->cfg->ops->set_hw_reg(hw,
1155                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1156         }
1157
1158 }
1159
1160 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1161 {
1162         struct rtl_priv *rtlpriv = rtl_priv(hw);
1163
1164         if (_rtl92ce_set_media_status(hw, type))
1165                 return -EOPNOTSUPP;
1166
1167         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1168                 if (type != NL80211_IFTYPE_AP)
1169                         rtl92ce_set_check_bssid(hw, true);
1170         } else {
1171                 rtl92ce_set_check_bssid(hw, false);
1172         }
1173
1174         return 0;
1175 }
1176
1177 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1178 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1179 {
1180         struct rtl_priv *rtlpriv = rtl_priv(hw);
1181         rtl92c_dm_init_edca_turbo(hw);
1182         switch (aci) {
1183         case AC1_BK:
1184                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1185                 break;
1186         case AC0_BE:
1187                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1188                 break;
1189         case AC2_VI:
1190                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1191                 break;
1192         case AC3_VO:
1193                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1194                 break;
1195         default:
1196                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1197                 break;
1198         }
1199 }
1200
1201 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1202 {
1203         struct rtl_priv *rtlpriv = rtl_priv(hw);
1204         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1205
1206         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1207         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1208 }
1209
1210 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1211 {
1212         struct rtl_priv *rtlpriv = rtl_priv(hw);
1213         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1214
1215         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1216         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1217         synchronize_irq(rtlpci->pdev->irq);
1218 }
1219
1220 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1221 {
1222         struct rtl_priv *rtlpriv = rtl_priv(hw);
1223         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1224         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1225         u8 u1b_tmp;
1226         u32 u4b_tmp;
1227
1228         rtlpriv->intf_ops->enable_aspm(hw);
1229         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1230         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1231         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1232         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1233         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1234         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1235         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1236                 rtl92c_firmware_selfreset(hw);
1237         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1238         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1239         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1240         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1241         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1242              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1243              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1244                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1245                                 (u1b_tmp << 8));
1246         } else {
1247                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1248                                 (u1b_tmp << 8));
1249         }
1250         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1251         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1252         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1253         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1254         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1255                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1256                 u4b_tmp |= 0x03824800;
1257                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1258         } else {
1259                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1260         }
1261
1262         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1263         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1264 }
1265
1266 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1267 {
1268         struct rtl_priv *rtlpriv = rtl_priv(hw);
1269         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1270         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1272         enum nl80211_iftype opmode;
1273
1274         mac->link_state = MAC80211_NOLINK;
1275         opmode = NL80211_IFTYPE_UNSPECIFIED;
1276         _rtl92ce_set_media_status(hw, opmode);
1277         if (rtlpci->driver_is_goingto_unload ||
1278             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1279                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1280         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1281         _rtl92ce_poweroff_adapter(hw);
1282 }
1283
1284 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1285                                   u32 *p_inta, u32 *p_intb)
1286 {
1287         struct rtl_priv *rtlpriv = rtl_priv(hw);
1288         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1289
1290         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1291         rtl_write_dword(rtlpriv, ISR, *p_inta);
1292
1293         /*
1294          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1295          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1296          */
1297 }
1298
1299 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1300 {
1301
1302         struct rtl_priv *rtlpriv = rtl_priv(hw);
1303         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1304         u16 bcn_interval, atim_window;
1305
1306         bcn_interval = mac->beacon_interval;
1307         atim_window = 2;        /*FIX MERGE */
1308         rtl92ce_disable_interrupt(hw);
1309         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1310         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1311         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1312         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1313         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1314         rtl_write_byte(rtlpriv, 0x606, 0x30);
1315         rtl92ce_enable_interrupt(hw);
1316 }
1317
1318 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1319 {
1320         struct rtl_priv *rtlpriv = rtl_priv(hw);
1321         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1322         u16 bcn_interval = mac->beacon_interval;
1323
1324         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1325                  ("beacon_interval:%d\n", bcn_interval));
1326         rtl92ce_disable_interrupt(hw);
1327         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1328         rtl92ce_enable_interrupt(hw);
1329 }
1330
1331 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1332                                    u32 add_msr, u32 rm_msr)
1333 {
1334         struct rtl_priv *rtlpriv = rtl_priv(hw);
1335         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1336
1337         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1338                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1339
1340         if (add_msr)
1341                 rtlpci->irq_mask[0] |= add_msr;
1342         if (rm_msr)
1343                 rtlpci->irq_mask[0] &= (~rm_msr);
1344         rtl92ce_disable_interrupt(hw);
1345         rtl92ce_enable_interrupt(hw);
1346 }
1347
1348 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1349                                                  bool autoload_fail,
1350                                                  u8 *hwinfo)
1351 {
1352         struct rtl_priv *rtlpriv = rtl_priv(hw);
1353         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1354         u8 rf_path, index, tempval;
1355         u16 i;
1356
1357         for (rf_path = 0; rf_path < 2; rf_path++) {
1358                 for (i = 0; i < 3; i++) {
1359                         if (!autoload_fail) {
1360                                 rtlefuse->
1361                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1362                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1363                                 rtlefuse->
1364                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1365                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1366                                            i];
1367                         } else {
1368                                 rtlefuse->
1369                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1370                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1371                                 rtlefuse->
1372                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1373                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1374                         }
1375                 }
1376         }
1377
1378         for (i = 0; i < 3; i++) {
1379                 if (!autoload_fail)
1380                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1381                 else
1382                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1383                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1384                     (tempval & 0xf);
1385                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1386                     ((tempval & 0xf0) >> 4);
1387         }
1388
1389         for (rf_path = 0; rf_path < 2; rf_path++)
1390                 for (i = 0; i < 3; i++)
1391                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1392                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1393                                  i,
1394                                  rtlefuse->
1395                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
1396         for (rf_path = 0; rf_path < 2; rf_path++)
1397                 for (i = 0; i < 3; i++)
1398                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1399                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1400                                  rf_path, i,
1401                                  rtlefuse->
1402                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1403         for (rf_path = 0; rf_path < 2; rf_path++)
1404                 for (i = 0; i < 3; i++)
1405                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1406                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1407                                  rf_path, i,
1408                                  rtlefuse->
1409                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1410                                  [i]));
1411
1412         for (rf_path = 0; rf_path < 2; rf_path++) {
1413                 for (i = 0; i < 14; i++) {
1414                         index = _rtl92c_get_chnl_group((u8) i);
1415
1416                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1417                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1418                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1419                             rtlefuse->
1420                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1421
1422                         if ((rtlefuse->
1423                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1424                              rtlefuse->
1425                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1426                             > 0) {
1427                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1428                                     rtlefuse->
1429                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1430                                     [index] -
1431                                     rtlefuse->
1432                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1433                                     [index];
1434                         } else {
1435                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1436                         }
1437                 }
1438
1439                 for (i = 0; i < 14; i++) {
1440                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1441                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1442                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1443                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1444                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1445                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1446                 }
1447         }
1448
1449         for (i = 0; i < 3; i++) {
1450                 if (!autoload_fail) {
1451                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1452                             hwinfo[EEPROM_TXPWR_GROUP + i];
1453                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1454                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1455                 } else {
1456                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1457                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1458                 }
1459         }
1460
1461         for (rf_path = 0; rf_path < 2; rf_path++) {
1462                 for (i = 0; i < 14; i++) {
1463                         index = _rtl92c_get_chnl_group((u8) i);
1464
1465                         if (rf_path == RF90_PATH_A) {
1466                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1467                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1468                                      & 0xf);
1469                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1470                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1471                                      & 0xf);
1472                         } else if (rf_path == RF90_PATH_B) {
1473                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1474                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1475                                       & 0xf0) >> 4);
1476                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1477                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1478                                       & 0xf0) >> 4);
1479                         }
1480
1481                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1482                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1483                                  rf_path, i,
1484                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1485                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1486                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1487                                  rf_path, i,
1488                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1489                 }
1490         }
1491
1492         for (i = 0; i < 14; i++) {
1493                 index = _rtl92c_get_chnl_group((u8) i);
1494
1495                 if (!autoload_fail)
1496                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1497                 else
1498                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1499
1500                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1501                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1502                     ((tempval >> 4) & 0xF);
1503
1504                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1505                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1506
1507                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1508                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1509
1510                 index = _rtl92c_get_chnl_group((u8) i);
1511
1512                 if (!autoload_fail)
1513                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1514                 else
1515                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1516
1517                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1518                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1519                     ((tempval >> 4) & 0xF);
1520         }
1521
1522         rtlefuse->legacy_ht_txpowerdiff =
1523             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1524
1525         for (i = 0; i < 14; i++)
1526                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1527                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1528                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1529         for (i = 0; i < 14; i++)
1530                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1531                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1532                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1533         for (i = 0; i < 14; i++)
1534                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1535                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1536                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1537         for (i = 0; i < 14; i++)
1538                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1539                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1540                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1541
1542         if (!autoload_fail)
1543                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1544         else
1545                 rtlefuse->eeprom_regulatory = 0;
1546         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1547                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1548
1549         if (!autoload_fail) {
1550                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1551                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1552         } else {
1553                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1554                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1555         }
1556         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1557                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1558                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1559                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1560
1561         if (!autoload_fail)
1562                 tempval = hwinfo[EEPROM_THERMAL_METER];
1563         else
1564                 tempval = EEPROM_DEFAULT_THERMALMETER;
1565         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1566
1567         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1568                 rtlefuse->apk_thermalmeterignore = true;
1569
1570         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1571         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1572                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1573 }
1574
1575 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1576 {
1577         struct rtl_priv *rtlpriv = rtl_priv(hw);
1578         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1579         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1580         u16 i, usvalue;
1581         u8 hwinfo[HWSET_MAX_SIZE];
1582         u16 eeprom_id;
1583
1584         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1585                 rtl_efuse_shadow_map_update(hw);
1586
1587                 memcpy((void *)hwinfo,
1588                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1589                        HWSET_MAX_SIZE);
1590         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1591                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1592                          ("RTL819X Not boot from eeprom, check it !!"));
1593         }
1594
1595         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1596                       hwinfo, HWSET_MAX_SIZE);
1597
1598         eeprom_id = *((u16 *)&hwinfo[0]);
1599         if (eeprom_id != RTL8190_EEPROM_ID) {
1600                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1601                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1602                 rtlefuse->autoload_failflag = true;
1603         } else {
1604                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1605                 rtlefuse->autoload_failflag = false;
1606         }
1607
1608         if (rtlefuse->autoload_failflag)
1609                 return;
1610
1611         for (i = 0; i < 6; i += 2) {
1612                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1613                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1614         }
1615
1616         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1617                  ("%pM\n", rtlefuse->dev_addr));
1618
1619         _rtl92ce_read_txpower_info_from_hwpg(hw,
1620                                              rtlefuse->autoload_failflag,
1621                                              hwinfo);
1622
1623         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1624                                                  rtlefuse->autoload_failflag,
1625                                                  hwinfo);
1626
1627         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1628         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1629         rtlefuse->txpwr_fromeprom = true;
1630         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1631
1632         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1633                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1634
1635         /* set channel paln to world wide 13 */
1636         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1637
1638         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1639                 switch (rtlefuse->eeprom_oemid) {
1640                 case EEPROM_CID_DEFAULT:
1641                         if (rtlefuse->eeprom_did == 0x8176) {
1642                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1643                                      rtlefuse->eeprom_smid == 0x1629))
1644                                         rtlhal->oem_id = RT_CID_819x_HP;
1645                                 else
1646                                         rtlhal->oem_id = RT_CID_DEFAULT;
1647                         } else {
1648                                 rtlhal->oem_id = RT_CID_DEFAULT;
1649                         }
1650                         break;
1651                 case EEPROM_CID_TOSHIBA:
1652                         rtlhal->oem_id = RT_CID_TOSHIBA;
1653                         break;
1654                 case EEPROM_CID_QMI:
1655                         rtlhal->oem_id = RT_CID_819x_QMI;
1656                         break;
1657                 case EEPROM_CID_WHQL:
1658                 default:
1659                         rtlhal->oem_id = RT_CID_DEFAULT;
1660                         break;
1661
1662                 }
1663         }
1664
1665 }
1666
1667 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1668 {
1669         struct rtl_priv *rtlpriv = rtl_priv(hw);
1670         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1671         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1672
1673         switch (rtlhal->oem_id) {
1674         case RT_CID_819x_HP:
1675                 pcipriv->ledctl.led_opendrain = true;
1676                 break;
1677         case RT_CID_819x_Lenovo:
1678         case RT_CID_DEFAULT:
1679         case RT_CID_TOSHIBA:
1680         case RT_CID_CCX:
1681         case RT_CID_819x_Acer:
1682         case RT_CID_WHQL:
1683         default:
1684                 break;
1685         }
1686         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1687                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1688 }
1689
1690 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1691 {
1692         struct rtl_priv *rtlpriv = rtl_priv(hw);
1693         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1694         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1695         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1696         u8 tmp_u1b;
1697
1698         rtlhal->version = _rtl92ce_read_chip_version(hw);
1699         if (get_rf_type(rtlphy) == RF_1T1R)
1700                 rtlpriv->dm.rfpath_rxenable[0] = true;
1701         else
1702                 rtlpriv->dm.rfpath_rxenable[0] =
1703                     rtlpriv->dm.rfpath_rxenable[1] = true;
1704         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1705                                                 rtlhal->version));
1706         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1707         if (tmp_u1b & BIT(4)) {
1708                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1709                 rtlefuse->epromtype = EEPROM_93C46;
1710         } else {
1711                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1712                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1713         }
1714         if (tmp_u1b & BIT(5)) {
1715                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1716                 rtlefuse->autoload_failflag = false;
1717                 _rtl92ce_read_adapter_info(hw);
1718         } else {
1719                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1720         }
1721         _rtl92ce_hal_customized_behavior(hw);
1722 }
1723
1724 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1725                 struct ieee80211_sta *sta)
1726 {
1727         struct rtl_priv *rtlpriv = rtl_priv(hw);
1728         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1729         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1730         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1731         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1732         u32 ratr_value;
1733         u8 ratr_index = 0;
1734         u8 nmode = mac->ht_enable;
1735         u8 mimo_ps = IEEE80211_SMPS_OFF;
1736         u16 shortgi_rate;
1737         u32 tmp_ratr_value;
1738         u8 curtxbw_40mhz = mac->bw_40;
1739         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1740                                1 : 0;
1741         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1742                                1 : 0;
1743         enum wireless_mode wirelessmode = mac->mode;
1744
1745         if (rtlhal->current_bandtype == BAND_ON_5G)
1746                 ratr_value = sta->supp_rates[1] << 4;
1747         else
1748                 ratr_value = sta->supp_rates[0];
1749         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1750                         sta->ht_cap.mcs.rx_mask[0] << 12);
1751         switch (wirelessmode) {
1752         case WIRELESS_MODE_B:
1753                 if (ratr_value & 0x0000000c)
1754                         ratr_value &= 0x0000000d;
1755                 else
1756                         ratr_value &= 0x0000000f;
1757                 break;
1758         case WIRELESS_MODE_G:
1759                 ratr_value &= 0x00000FF5;
1760                 break;
1761         case WIRELESS_MODE_N_24G:
1762         case WIRELESS_MODE_N_5G:
1763                 nmode = 1;
1764                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1765                         ratr_value &= 0x0007F005;
1766                 } else {
1767                         u32 ratr_mask;
1768
1769                         if (get_rf_type(rtlphy) == RF_1T2R ||
1770                             get_rf_type(rtlphy) == RF_1T1R)
1771                                 ratr_mask = 0x000ff005;
1772                         else
1773                                 ratr_mask = 0x0f0ff005;
1774
1775                         ratr_value &= ratr_mask;
1776                 }
1777                 break;
1778         default:
1779                 if (rtlphy->rf_type == RF_1T2R)
1780                         ratr_value &= 0x000ff0ff;
1781                 else
1782                         ratr_value &= 0x0f0ff0ff;
1783
1784                 break;
1785         }
1786
1787         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1788             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1789             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1790             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1791             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1792             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1793                 ratr_value &= 0x0fffcfc0;
1794         else
1795                 ratr_value &= 0x0FFFFFFF;
1796
1797         if (nmode && ((curtxbw_40mhz &&
1798                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1799                                                curshortgi_20mhz))) {
1800
1801                 ratr_value |= 0x10000000;
1802                 tmp_ratr_value = (ratr_value >> 12);
1803
1804                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1805                         if ((1 << shortgi_rate) & tmp_ratr_value)
1806                                 break;
1807                 }
1808
1809                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1810                     (shortgi_rate << 4) | (shortgi_rate);
1811         }
1812
1813         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1814
1815         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1816                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1817 }
1818
1819 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1820                 struct ieee80211_sta *sta, u8 rssi_level)
1821 {
1822         struct rtl_priv *rtlpriv = rtl_priv(hw);
1823         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1824         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1825         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1826         struct rtl_sta_info *sta_entry = NULL;
1827         u32 ratr_bitmap;
1828         u8 ratr_index;
1829         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1830                                 ? 1 : 0;
1831         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1832                                 1 : 0;
1833         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1834                                 1 : 0;
1835         enum wireless_mode wirelessmode = 0;
1836         bool shortgi = false;
1837         u8 rate_mask[5];
1838         u8 macid = 0;
1839         u8 mimo_ps = IEEE80211_SMPS_OFF;
1840
1841         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1842         wirelessmode = sta_entry->wireless_mode;
1843         if (mac->opmode == NL80211_IFTYPE_STATION)
1844                 curtxbw_40mhz = mac->bw_40;
1845         else if (mac->opmode == NL80211_IFTYPE_AP ||
1846                 mac->opmode == NL80211_IFTYPE_ADHOC)
1847                 macid = sta->aid + 1;
1848
1849         if (rtlhal->current_bandtype == BAND_ON_5G)
1850                 ratr_bitmap = sta->supp_rates[1] << 4;
1851         else
1852                 ratr_bitmap = sta->supp_rates[0];
1853         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1854                         sta->ht_cap.mcs.rx_mask[0] << 12);
1855         switch (wirelessmode) {
1856         case WIRELESS_MODE_B:
1857                 ratr_index = RATR_INX_WIRELESS_B;
1858                 if (ratr_bitmap & 0x0000000c)
1859                         ratr_bitmap &= 0x0000000d;
1860                 else
1861                         ratr_bitmap &= 0x0000000f;
1862                 break;
1863         case WIRELESS_MODE_G:
1864                 ratr_index = RATR_INX_WIRELESS_GB;
1865
1866                 if (rssi_level == 1)
1867                         ratr_bitmap &= 0x00000f00;
1868                 else if (rssi_level == 2)
1869                         ratr_bitmap &= 0x00000ff0;
1870                 else
1871                         ratr_bitmap &= 0x00000ff5;
1872                 break;
1873         case WIRELESS_MODE_A:
1874                 ratr_index = RATR_INX_WIRELESS_A;
1875                 ratr_bitmap &= 0x00000ff0;
1876                 break;
1877         case WIRELESS_MODE_N_24G:
1878         case WIRELESS_MODE_N_5G:
1879                 ratr_index = RATR_INX_WIRELESS_NGB;
1880
1881                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1882                         if (rssi_level == 1)
1883                                 ratr_bitmap &= 0x00070000;
1884                         else if (rssi_level == 2)
1885                                 ratr_bitmap &= 0x0007f000;
1886                         else
1887                                 ratr_bitmap &= 0x0007f005;
1888                 } else {
1889                         if (rtlphy->rf_type == RF_1T2R ||
1890                             rtlphy->rf_type == RF_1T1R) {
1891                                 if (curtxbw_40mhz) {
1892                                         if (rssi_level == 1)
1893                                                 ratr_bitmap &= 0x000f0000;
1894                                         else if (rssi_level == 2)
1895                                                 ratr_bitmap &= 0x000ff000;
1896                                         else
1897                                                 ratr_bitmap &= 0x000ff015;
1898                                 } else {
1899                                         if (rssi_level == 1)
1900                                                 ratr_bitmap &= 0x000f0000;
1901                                         else if (rssi_level == 2)
1902                                                 ratr_bitmap &= 0x000ff000;
1903                                         else
1904                                                 ratr_bitmap &= 0x000ff005;
1905                                 }
1906                         } else {
1907                                 if (curtxbw_40mhz) {
1908                                         if (rssi_level == 1)
1909                                                 ratr_bitmap &= 0x0f0f0000;
1910                                         else if (rssi_level == 2)
1911                                                 ratr_bitmap &= 0x0f0ff000;
1912                                         else
1913                                                 ratr_bitmap &= 0x0f0ff015;
1914                                 } else {
1915                                         if (rssi_level == 1)
1916                                                 ratr_bitmap &= 0x0f0f0000;
1917                                         else if (rssi_level == 2)
1918                                                 ratr_bitmap &= 0x0f0ff000;
1919                                         else
1920                                                 ratr_bitmap &= 0x0f0ff005;
1921                                 }
1922                         }
1923                 }
1924
1925                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1926                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1927
1928                         if (macid == 0)
1929                                 shortgi = true;
1930                         else if (macid == 1)
1931                                 shortgi = false;
1932                 }
1933                 break;
1934         default:
1935                 ratr_index = RATR_INX_WIRELESS_NGB;
1936
1937                 if (rtlphy->rf_type == RF_1T2R)
1938                         ratr_bitmap &= 0x000ff0ff;
1939                 else
1940                         ratr_bitmap &= 0x0f0ff0ff;
1941                 break;
1942         }
1943         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1944                  ("ratr_bitmap :%x\n", ratr_bitmap));
1945         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1946                                      (ratr_index << 28));
1947         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1948         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1949                                                  "ratr_val:%x, %x:%x:%x:%x:%x\n",
1950                                                  ratr_index, ratr_bitmap,
1951                                                  rate_mask[0], rate_mask[1],
1952                                                  rate_mask[2], rate_mask[3],
1953                                                  rate_mask[4]));
1954         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1955
1956         if (macid != 0)
1957                 sta_entry->ratr_index = ratr_index;
1958 }
1959
1960 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1961                 struct ieee80211_sta *sta, u8 rssi_level)
1962 {
1963         struct rtl_priv *rtlpriv = rtl_priv(hw);
1964
1965         if (rtlpriv->dm.useramask)
1966                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1967         else
1968                 rtl92ce_update_hal_rate_table(hw, sta);
1969 }
1970
1971 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1972 {
1973         struct rtl_priv *rtlpriv = rtl_priv(hw);
1974         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1975         u16 sifs_timer;
1976
1977         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1978                                       (u8 *)&mac->slot_time);
1979         if (!mac->ht_enable)
1980                 sifs_timer = 0x0a0a;
1981         else
1982                 sifs_timer = 0x1010;
1983         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1984 }
1985
1986 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1987 {
1988         struct rtl_priv *rtlpriv = rtl_priv(hw);
1989         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1990         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1991         enum rf_pwrstate e_rfpowerstate_toset;
1992         u8 u1tmp;
1993         bool actuallyset = false;
1994         unsigned long flag;
1995
1996         if (rtlpci->being_init_adapter)
1997                 return false;
1998
1999         if (ppsc->swrf_processing)
2000                 return false;
2001
2002         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2003         if (ppsc->rfchange_inprogress) {
2004                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2005                 return false;
2006         } else {
2007                 ppsc->rfchange_inprogress = true;
2008                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2009         }
2010
2011         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2012                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
2013
2014         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2015         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2016
2017         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2018                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2019                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
2020
2021                 e_rfpowerstate_toset = ERFON;
2022                 ppsc->hwradiooff = false;
2023                 actuallyset = true;
2024         } else if ((ppsc->hwradiooff == false)
2025                    && (e_rfpowerstate_toset == ERFOFF)) {
2026                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2027                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
2028
2029                 e_rfpowerstate_toset = ERFOFF;
2030                 ppsc->hwradiooff = true;
2031                 actuallyset = true;
2032         }
2033
2034         if (actuallyset) {
2035                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2036                 ppsc->rfchange_inprogress = false;
2037                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2038         } else {
2039                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2040                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2041
2042                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2043                 ppsc->rfchange_inprogress = false;
2044                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2045         }
2046
2047         *valid = 1;
2048         return !ppsc->hwradiooff;
2049
2050 }
2051
2052 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2053                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2054                      bool is_wepkey, bool clear_all)
2055 {
2056         struct rtl_priv *rtlpriv = rtl_priv(hw);
2057         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2058         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2059         u8 *macaddr = p_macaddr;
2060         u32 entry_id = 0;
2061         bool is_pairwise = false;
2062
2063         static u8 cam_const_addr[4][6] = {
2064                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2065                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2066                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2067                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2068         };
2069         static u8 cam_const_broad[] = {
2070                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2071         };
2072
2073         if (clear_all) {
2074                 u8 idx = 0;
2075                 u8 cam_offset = 0;
2076                 u8 clear_number = 5;
2077
2078                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2079
2080                 for (idx = 0; idx < clear_number; idx++) {
2081                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2082                         rtl_cam_empty_entry(hw, cam_offset + idx);
2083
2084                         if (idx < 5) {
2085                                 memset(rtlpriv->sec.key_buf[idx], 0,
2086                                        MAX_KEY_LEN);
2087                                 rtlpriv->sec.key_len[idx] = 0;
2088                         }
2089                 }
2090
2091         } else {
2092                 switch (enc_algo) {
2093                 case WEP40_ENCRYPTION:
2094                         enc_algo = CAM_WEP40;
2095                         break;
2096                 case WEP104_ENCRYPTION:
2097                         enc_algo = CAM_WEP104;
2098                         break;
2099                 case TKIP_ENCRYPTION:
2100                         enc_algo = CAM_TKIP;
2101                         break;
2102                 case AESCCMP_ENCRYPTION:
2103                         enc_algo = CAM_AES;
2104                         break;
2105                 default:
2106                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2107                                         "not process\n"));
2108                         enc_algo = CAM_TKIP;
2109                         break;
2110                 }
2111
2112                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2113                         macaddr = cam_const_addr[key_index];
2114                         entry_id = key_index;
2115                 } else {
2116                         if (is_group) {
2117                                 macaddr = cam_const_broad;
2118                                 entry_id = key_index;
2119                         } else {
2120                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2121                                         entry_id = rtl_cam_get_free_entry(hw,
2122                                                                  p_macaddr);
2123                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2124                                                 RT_TRACE(rtlpriv, COMP_SEC,
2125                                                      DBG_EMERG,
2126                                                      ("Can not find free hw"
2127                                                      " security cam entry\n"));
2128                                                 return;
2129                                         }
2130                                 } else {
2131                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2132                                 }
2133
2134                                 key_index = PAIRWISE_KEYIDX;
2135                                 is_pairwise = true;
2136                         }
2137                 }
2138
2139                 if (rtlpriv->sec.key_len[key_index] == 0) {
2140                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2141                                  ("delete one entry, entry_id is %d\n",
2142                                  entry_id));
2143                         if (mac->opmode == NL80211_IFTYPE_AP)
2144                                 rtl_cam_del_entry(hw, p_macaddr);
2145                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2146                 } else {
2147                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2148                                  ("The insert KEY length is %d\n",
2149                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2150                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2151                                  ("The insert KEY  is %x %x\n",
2152                                   rtlpriv->sec.key_buf[0][0],
2153                                   rtlpriv->sec.key_buf[0][1]));
2154
2155                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2156                                  ("add one entry\n"));
2157                         if (is_pairwise) {
2158                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2159                                               "Pairwiase Key content :",
2160                                               rtlpriv->sec.pairwise_key,
2161                                               rtlpriv->sec.
2162                                               key_len[PAIRWISE_KEYIDX]);
2163
2164                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2165                                          ("set Pairwiase key\n"));
2166
2167                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2168                                                       entry_id, enc_algo,
2169                                                       CAM_CONFIG_NO_USEDK,
2170                                                       rtlpriv->sec.
2171                                                       key_buf[key_index]);
2172                         } else {
2173                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2174                                          ("set group key\n"));
2175
2176                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2177                                         rtl_cam_add_one_entry(hw,
2178                                                 rtlefuse->dev_addr,
2179                                                 PAIRWISE_KEYIDX,
2180                                                 CAM_PAIRWISE_KEY_POSITION,
2181                                                 enc_algo,
2182                                                 CAM_CONFIG_NO_USEDK,
2183                                                 rtlpriv->sec.key_buf
2184                                                 [entry_id]);
2185                                 }
2186
2187                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2188                                                 entry_id, enc_algo,
2189                                                 CAM_CONFIG_NO_USEDK,
2190                                                 rtlpriv->sec.key_buf[entry_id]);
2191                         }
2192
2193                 }
2194         }
2195 }
2196
2197 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2198 {
2199         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2200
2201         rtlpcipriv->bt_coexist.bt_coexistence =
2202                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2203         rtlpcipriv->bt_coexist.bt_ant_num =
2204                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2205         rtlpcipriv->bt_coexist.bt_coexist_type =
2206                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2207
2208         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2209                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2210                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2211         else
2212                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2213                         rtlpcipriv->bt_coexist.reg_bt_iso;
2214
2215         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2216                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2217
2218         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2219
2220                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2221                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2222                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2223                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2224                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2225                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2226                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2227                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2228                 else
2229                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2230
2231                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2232                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2233                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2234         }
2235 }
2236
2237 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2238                                               bool auto_load_fail, u8 *hwinfo)
2239 {
2240         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2241         u8 value;
2242
2243         if (!auto_load_fail) {
2244                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2245                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2246                 value = hwinfo[RF_OPTION4];
2247                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2248                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2249                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2250                                                          ((value & 0x10) >> 4);
2251                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2252                                                          ((value & 0x20) >> 5);
2253         } else {
2254                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2255                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2256                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2257                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2258                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2259         }
2260
2261         rtl8192ce_bt_var_init(hw);
2262 }
2263
2264 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2265 {
2266         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2267
2268         /* 0:Low, 1:High, 2:From Efuse. */
2269         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2270         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2271         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2272         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2273         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2274 }
2275
2276
2277 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2278 {
2279         struct rtl_priv *rtlpriv = rtl_priv(hw);
2280         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2281         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2282
2283         u8 u1_tmp;
2284
2285         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2286             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2287               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2288
2289                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2290                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2291
2292                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2293                          BIT_OFFSET_LEN_MASK_32(0, 1);
2294                 u1_tmp = u1_tmp |
2295                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2296                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2297                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2298                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2299                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2300
2301                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2302                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2303                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2304
2305                 /* Config to 1T1R. */
2306                 if (rtlphy->rf_type == RF_1T1R) {
2307                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2308                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2309                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2310
2311                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2312                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2313                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2314                 }
2315         }
2316 }
2317
2318 void rtl92ce_suspend(struct ieee80211_hw *hw)
2319 {
2320 }
2321
2322 void rtl92ce_resume(struct ieee80211_hw *hw)
2323 {
2324 }