drivers/net/wireless/rtlwifi/rtl8192c/phy_common.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL92C_PHY_H__
  31 #define __RTL92C_PHY_H__
  32
  33 #define MAX_PRECMD_CNT                  16
  34 #define MAX_RFDEPENDCMD_CNT             16
  35 #define MAX_POSTCMD_CNT                 16
  36
  37 #define MAX_DOZE_WAITING_TIMES_9x       64
  38
  39 #define RT_CANNOT_IO(hw)                false
  40 #define HIGHPOWER_RADIOA_ARRAYLEN       22
  41
  42 #define MAX_TOLERANCE                   5
  43 #define IQK_DELAY_TIME                  1
  44
  45 #define APK_BB_REG_NUM                  5
  46 #define APK_AFE_REG_NUM                 16
  47 #define APK_CURVE_REG_NUM               4
  48 #define PATH_NUM                        2
  49
  50 #define LOOP_LIMIT                      5
  51 #define MAX_STALL_TIME                  50
  52 #define AntennaDiversityValue           0x80
  53 #define MAX_TXPWR_IDX_NMODE_92S         63
  54 #define Reset_Cnt_Limit                 3
  55
  56 #define IQK_ADDA_REG_NUM                16
  57 #define IQK_MAC_REG_NUM                 4
  58
  59 #define RF90_PATH_MAX                   2
  60
  61 #define CT_OFFSET_MAC_ADDR              0X16
  62
  63 #define CT_OFFSET_CCK_TX_PWR_IDX        0x5A
  64 #define CT_OFFSET_HT401S_TX_PWR_IDX     0x60
  65 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
  66 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF  0x69
  67 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF  0x6C
  68
  69 #define CT_OFFSET_HT40_MAX_PWR_OFFSET   0x6F
  70 #define CT_OFFSET_HT20_MAX_PWR_OFFSET   0x72
  71
  72 #define CT_OFFSET_CHANNEL_PLAH          0x75
  73 #define CT_OFFSET_THERMAL_METER         0x78
  74 #define CT_OFFSET_RF_OPTION             0x79
  75 #define CT_OFFSET_VERSION               0x7E
  76 #define CT_OFFSET_CUSTOMER_ID           0x7F
  77
  78 #define RTL92C_MAX_PATH_NUM             2
  79 #define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
  80 enum swchnlcmd_id {
  81         CMDID_END,
  82         CMDID_SET_TXPOWEROWER_LEVEL,
  83         CMDID_BBREGWRITE10,
  84         CMDID_WRITEPORT_ULONG,
  85         CMDID_WRITEPORT_USHORT,
  86         CMDID_WRITEPORT_UCHAR,
  87         CMDID_RF_WRITEREG,
  88 };
  89
  90 struct swchnlcmd {
  91         enum swchnlcmd_id cmdid;
  92         u32 para1;
  93         u32 para2;
  94         u32 msdelay;
  95 };
  96
  97 enum hw90_block_e {
  98         HW90_BLOCK_MAC = 0,
  99         HW90_BLOCK_PHY0 = 1,
 100         HW90_BLOCK_PHY1 = 2,
 101         HW90_BLOCK_RF = 3,
 102         HW90_BLOCK_MAXIMUM = 4,
 103 };
 104
 105 enum baseband_config_type {
 106         BASEBAND_CONFIG_PHY_REG = 0,
 107         BASEBAND_CONFIG_AGC_TAB = 1,
 108 };
 109
 110 enum ra_offset_area {
 111         RA_OFFSET_LEGACY_OFDM1,
 112         RA_OFFSET_LEGACY_OFDM2,
 113         RA_OFFSET_HT_OFDM1,
 114         RA_OFFSET_HT_OFDM2,
 115         RA_OFFSET_HT_OFDM3,
 116         RA_OFFSET_HT_OFDM4,
 117         RA_OFFSET_HT_CCK,
 118 };
 119
 120 enum antenna_path {
 121         ANTENNA_NONE,
 122         ANTENNA_D,
 123         ANTENNA_C,
 124         ANTENNA_CD,
 125         ANTENNA_B,
 126         ANTENNA_BD,
 127         ANTENNA_BC,
 128         ANTENNA_BCD,
 129         ANTENNA_A,
 130         ANTENNA_AD,
 131         ANTENNA_AC,
 132         ANTENNA_ACD,
 133         ANTENNA_AB,
 134         ANTENNA_ABD,
 135         ANTENNA_ABC,
 136         ANTENNA_ABCD
 137 };
 138
 139 struct r_antenna_select_ofdm {
 140         u32 r_tx_antenna:4;
 141         u32 r_ant_l:4;
 142         u32 r_ant_non_ht:4;
 143         u32 r_ant_ht1:4;
 144         u32 r_ant_ht2:4;
 145         u32 r_ant_ht_s1:4;
 146         u32 r_ant_non_ht_s1:4;
 147         u32 ofdm_txsc:2;
 148         u32 reserved:2;
 149 };
 150
 151 struct r_antenna_select_cck {
 152         u8 r_cckrx_enable_2:2;
 153         u8 r_cckrx_enable:2;
 154         u8 r_ccktx_enable:4;
 155 };
 156
 157 struct efuse_contents {
 158         u8 mac_addr[ETH_ALEN];
 159         u8 cck_tx_power_idx[6];
 160         u8 ht40_1s_tx_power_idx[6];
 161         u8 ht40_2s_tx_power_idx_diff[3];
 162         u8 ht20_tx_power_idx_diff[3];
 163         u8 ofdm_tx_power_idx_diff[3];
 164         u8 ht40_max_power_offset[3];
 165         u8 ht20_max_power_offset[3];
 166         u8 channel_plan;
 167         u8 thermal_meter;
 168         u8 rf_option[5];
 169         u8 version;
 170         u8 oem_id;
 171         u8 regulatory;
 172 };
 173
 174 struct tx_power_struct {
 175         u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 176         u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 177         u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 178         u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 179         u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 180         u8 legacy_ht_txpowerdiff;
 181         u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 182         u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 183         u8 pwrgroup_cnt;
 184         u32 mcs_original_offset[4][16];
 185 };
 186
 187 extern u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
 188                                    u32 regaddr, u32 bitmask);
 189 extern void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
 190                                   u32 regaddr, u32 bitmask, u32 data);
 191 extern u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
 192                                    enum radio_path rfpath, u32 regaddr,
 193                                    u32 bitmask);
 194 extern void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
 195                                   enum radio_path rfpath, u32 regaddr,
 196                                   u32 bitmask, u32 data);
 197 extern bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
 198 extern bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
 199 extern bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
 200 extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
 201                                                  enum radio_path rfpath);
 202 extern void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
 203 extern void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
 204                                          long *powerlevel);
 205 extern void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
 206 extern bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
 207                                           long power_indbm);
 208 extern void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
 209                                              u8 operation);
 210 extern void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
 211 extern void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
 212                                    enum nl80211_channel_type ch_type);
 213 extern void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
 214 extern u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
 215 extern void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
 216 extern void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
 217                                          u16 beaconinterval);
 218 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
 219 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
 220 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
 221 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 222                                           enum radio_path rfpath);
 223 extern bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
 224                                               u32 rfpath);
 225 extern bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 226                                           enum rf_pwrstate rfpwr_state);
 227 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
 228 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
 229 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
 230 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
 231 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 232                                   enum wireless_mode wirelessmode,
 233                                   u8 txpwridx);
 234 u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
 235                                 enum wireless_mode wirelessmode,
 236                                 long power_indbm);
 237 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
 238 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 239                                              u32 cmdtableidx, u32 cmdtablesz,
 240                                              enum swchnlcmd_id cmdid, u32 para1,
 241                                              u32 para2, u32 msdelay);
 242 static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 243                                              u8 channel, u8 *stage, u8 *step,
 244                                              u32 *delay);
 245
 246 #endif