drivers/net/wireless/rtlwifi/pci.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "core.h"
  31 #include "wifi.h"
  32 #include "pci.h"
  33 #include "base.h"
  34 #include "ps.h"
  35
  36 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
  37         INTEL_VENDOR_ID,
  38         ATI_VENDOR_ID,
  39         AMD_VENDOR_ID,
  40         SIS_VENDOR_ID
  41 };
  42
  43 /* Update PCI dependent default settings*/
  44 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
  45 {
  46         struct rtl_priv *rtlpriv = rtl_priv(hw);
  47         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  51
  52         ppsc->reg_rfps_level = 0;
  53         ppsc->support_aspm = 0;
  54
  55         /*Update PCI ASPM setting */
  56         ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
  57         switch (rtlpci->const_pci_aspm) {
  58         case 0:
  59                 /*No ASPM */
  60                 break;
  61
  62         case 1:
  63                 /*ASPM dynamically enabled/disable. */
  64                 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
  65                 break;
  66
  67         case 2:
  68                 /*ASPM with Clock Req dynamically enabled/disable. */
  69                 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
  70                                          RT_RF_OFF_LEVL_CLK_REQ);
  71                 break;
  72
  73         case 3:
  74                 /*
  75                  * Always enable ASPM and Clock Req
  76                  * from initialization to halt.
  77                  * */
  78                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
  79                 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
  80                                          RT_RF_OFF_LEVL_CLK_REQ);
  81                 break;
  82
  83         case 4:
  84                 /*
  85                  * Always enable ASPM without Clock Req
  86                  * from initialization to halt.
  87                  * */
  88                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
  89                                           RT_RF_OFF_LEVL_CLK_REQ);
  90                 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
  91                 break;
  92         }
  93
  94         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
  95
  96         /*Update Radio OFF setting */
  97         switch (rtlpci->const_hwsw_rfoff_d3) {
  98         case 1:
  99                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 100                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 101                 break;
 102
 103         case 2:
 104                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 105                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 106                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 107                 break;
 108
 109         case 3:
 110                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
 111                 break;
 112         }
 113
 114         /*Set HW definition to determine if it supports ASPM. */
 115         switch (rtlpci->const_support_pciaspm) {
 116         case 0:{
 117                         /*Not support ASPM. */
 118                         bool support_aspm = false;
 119                         ppsc->support_aspm = support_aspm;
 120                         break;
 121                 }
 122         case 1:{
 123                         /*Support ASPM. */
 124                         bool support_aspm = true;
 125                         bool support_backdoor = true;
 126                         ppsc->support_aspm = support_aspm;
 127
 128                         /*if(priv->oem_id == RT_CID_TOSHIBA &&
 129                            !priv->ndis_adapter.amd_l1_patch)
 130                            support_backdoor = false; */
 131
 132                         ppsc->support_backdoor = support_backdoor;
 133
 134                         break;
 135                 }
 136         case 2:
 137                 /*ASPM value set by chipset. */
 138                 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
 139                         bool support_aspm = true;
 140                         ppsc->support_aspm = support_aspm;
 141                 }
 142                 break;
 143         default:
 144                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 145                          ("switch case not process\n"));
 146                 break;
 147         }
 148 }
 149
 150 static bool _rtl_pci_platform_switch_device_pci_aspm(
 151                         struct ieee80211_hw *hw,
 152                         u8 value)
 153 {
 154         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 155         bool bresult = false;
 156
 157         value |= 0x40;
 158
 159         pci_write_config_byte(rtlpci->pdev, 0x80, value);
 160
 161         return bresult;
 162 }
 163
 164 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
 165 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
 166 {
 167         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 168         u8 buffer;
 169         bool bresult = false;
 170
 171         buffer = value;
 172
 173         pci_write_config_byte(rtlpci->pdev, 0x81, value);
 174         bresult = true;
 175
 176         return bresult;
 177 }
 178
 179 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
 180 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
 181 {
 182         struct rtl_priv *rtlpriv = rtl_priv(hw);
 183         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 184         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 185         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 186         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 187         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 188         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 189         /*Retrieve original configuration settings. */
 190         u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
 191         u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
 192                                 pcibridge_linkctrlreg;
 193         u16 aspmlevel = 0;
 194
 195         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 196                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 197                          ("PCI(Bridge) UNKNOWN.\n"));
 198
 199                 return;
 200         }
 201
 202         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 203                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 204                 _rtl_pci_switch_clk_req(hw, 0x0);
 205         }
 206
 207         if (1) {
 208                 /*for promising device will in L0 state after an I/O. */
 209                 u8 tmp_u1b;
 210                 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
 211         }
 212
 213         /*Set corresponding value. */
 214         aspmlevel |= BIT(0) | BIT(1);
 215         linkctrl_reg &= ~aspmlevel;
 216         pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
 217
 218         _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
 219         udelay(50);
 220
 221         /*4 Disable Pci Bridge ASPM */
 222         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 223                                      pcicfg_addrport + (num4bytes << 2));
 224         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
 225
 226         udelay(50);
 227
 228 }
 229
 230 /*
 231  *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 232  *power saving We should follow the sequence to enable
 233  *RTL8192SE first then enable Pci Bridge ASPM
 234  *or the system will show bluescreen.
 235  */
 236 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
 237 {
 238         struct rtl_priv *rtlpriv = rtl_priv(hw);
 239         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 240         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 241         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 242         u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
 243         u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
 244         u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
 245         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 246         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 247         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 248         u16 aspmlevel;
 249         u8 u_pcibridge_aspmsetting;
 250         u8 u_device_aspmsetting;
 251
 252         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 253                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 254                          ("PCI(Bridge) UNKNOWN.\n"));
 255                 return;
 256         }
 257
 258         /*4 Enable Pci Bridge ASPM */
 259         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 260                                      pcicfg_addrport + (num4bytes << 2));
 261
 262         u_pcibridge_aspmsetting =
 263             pcipriv->ndis_adapter.pcibridge_linkctrlreg |
 264             rtlpci->const_hostpci_aspm_setting;
 265
 266         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
 267                 u_pcibridge_aspmsetting &= ~BIT(0);
 268
 269         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
 270
 271         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 272                  ("PlatformEnableASPM():PciBridge busnumber[%x], "
 273                   "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 274                   pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
 275                   (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
 276                   u_pcibridge_aspmsetting));
 277
 278         udelay(50);
 279
 280         /*Get ASPM level (with/without Clock Req) */
 281         aspmlevel = rtlpci->const_devicepci_aspm_setting;
 282         u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
 283
 284         /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
 285         /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
 286
 287         u_device_aspmsetting |= aspmlevel;
 288
 289         _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
 290
 291         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 292                 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
 293                                              RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 294                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 295         }
 296         udelay(200);
 297 }
 298
 299 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
 300 {
 301         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 302         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 303
 304         bool status = false;
 305         u8 offset_e0;
 306         unsigned offset_e4;
 307
 308         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 309                         pcicfg_addrport + 0xE0);
 310         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
 311
 312         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 313                         pcicfg_addrport + 0xE0);
 314         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
 315
 316         if (offset_e0 == 0xA0) {
 317                 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 318                                              pcicfg_addrport + 0xE4);
 319                 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
 320                 if (offset_e4 & BIT(23))
 321                         status = true;
 322         }
 323
 324         return status;
 325 }
 326
 327 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
 328 {
 329         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 330         u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
 331         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 332         u8 linkctrl_reg;
 333         u8 num4bBytes;
 334
 335         num4bBytes = (capabilityoffset + 0x10) / 4;
 336
 337         /*Read  Link Control Register */
 338         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 339                                      pcicfg_addrport + (num4bBytes << 2));
 340         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
 341
 342         pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
 343 }
 344
 345 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
 346                 struct ieee80211_hw *hw)
 347 {
 348         struct rtl_priv *rtlpriv = rtl_priv(hw);
 349         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 350
 351         u8 tmp;
 352         int pos;
 353         u8 linkctrl_reg;
 354
 355         /*Link Control Register */
 356         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 357         pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
 358         pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
 359
 360         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 361                  ("Link Control Register =%x\n",
 362                   pcipriv->ndis_adapter.linkctrl_reg));
 363
 364         pci_read_config_byte(pdev, 0x98, &tmp);
 365         tmp |= BIT(4);
 366         pci_write_config_byte(pdev, 0x98, tmp);
 367
 368         tmp = 0x17;
 369         pci_write_config_byte(pdev, 0x70f, tmp);
 370 }
 371
 372 static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
 373 {
 374         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 375
 376         _rtl_pci_update_default_setting(hw);
 377
 378         if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
 379                 /*Always enable ASPM & Clock Req. */
 380                 rtl_pci_enable_aspm(hw);
 381                 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
 382         }
 383
 384 }
 385
 386 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
 387 {
 388         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 389
 390         /*close ASPM for AMD defaultly */
 391         rtlpci->const_amdpci_aspm = 0;
 392
 393         /*
 394          * ASPM PS mode.
 395          * 0 - Disable ASPM,
 396          * 1 - Enable ASPM without Clock Req,
 397          * 2 - Enable ASPM with Clock Req,
 398          * 3 - Always Enable ASPM with Clock Req,
 399          * 4 - Always Enable ASPM without Clock Req.
 400          * set defult to RTL8192CE:3 RTL8192E:2
 401          * */
 402         rtlpci->const_pci_aspm = 3;
 403
 404         /*Setting for PCI-E device */
 405         rtlpci->const_devicepci_aspm_setting = 0x03;
 406
 407         /*Setting for PCI-E bridge */
 408         rtlpci->const_hostpci_aspm_setting = 0x02;
 409
 410         /*
 411          * In Hw/Sw Radio Off situation.
 412          * 0 - Default,
 413          * 1 - From ASPM setting without low Mac Pwr,
 414          * 2 - From ASPM setting with low Mac Pwr,
 415          * 3 - Bus D3
 416          * set default to RTL8192CE:0 RTL8192SE:2
 417          */
 418         rtlpci->const_hwsw_rfoff_d3 = 0;
 419
 420         /*
 421          * This setting works for those device with
 422          * backdoor ASPM setting such as EPHY setting.
 423          * 0 - Not support ASPM,
 424          * 1 - Support ASPM,
 425          * 2 - According to chipset.
 426          */
 427         rtlpci->const_support_pciaspm = 1;
 428
 429         _rtl_pci_initialize_adapter_common(hw);
 430 }
 431
 432 static void _rtl_pci_io_handler_init(struct device *dev,
 433                                      struct ieee80211_hw *hw)
 434 {
 435         struct rtl_priv *rtlpriv = rtl_priv(hw);
 436
 437         rtlpriv->io.dev = dev;
 438
 439         rtlpriv->io.write8_async = pci_write8_async;
 440         rtlpriv->io.write16_async = pci_write16_async;
 441         rtlpriv->io.write32_async = pci_write32_async;
 442
 443         rtlpriv->io.read8_sync = pci_read8_sync;
 444         rtlpriv->io.read16_sync = pci_read16_sync;
 445         rtlpriv->io.read32_sync = pci_read32_sync;
 446
 447 }
 448
 449 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
 450 {
 451 }
 452
 453 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
 454 {
 455         struct rtl_priv *rtlpriv = rtl_priv(hw);
 456         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 457
 458         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
 459
 460         while (skb_queue_len(&ring->queue)) {
 461                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 462                 struct sk_buff *skb;
 463                 struct ieee80211_tx_info *info;
 464
 465                 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
 466                                                           HW_DESC_OWN);
 467
 468                 /*
 469                  *beacon packet will only use the first
 470                  *descriptor defautly,and the own may not
 471                  *be cleared by the hardware
 472                  */
 473                 if (own)
 474                         return;
 475                 ring->idx = (ring->idx + 1) % ring->entries;
 476
 477                 skb = __skb_dequeue(&ring->queue);
 478                 pci_unmap_single(rtlpci->pdev,
 479                                  rtlpriv->cfg->ops->
 480                                              get_desc((u8 *) entry, true,
 481                                                       HW_DESC_TXBUFF_ADDR),
 482                                  skb->len, PCI_DMA_TODEVICE);
 483
 484                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
 485                          ("new ring->idx:%d, "
 486                           "free: skb_queue_len:%d, free: seq:%x\n",
 487                           ring->idx,
 488                           skb_queue_len(&ring->queue),
 489                           *(u16 *) (skb->data + 22)));
 490
 491                 info = IEEE80211_SKB_CB(skb);
 492                 ieee80211_tx_info_clear_status(info);
 493
 494                 info->flags |= IEEE80211_TX_STAT_ACK;
 495                 /*info->status.rates[0].count = 1; */
 496
 497                 ieee80211_tx_status_irqsafe(hw, skb);
 498
 499                 if ((ring->entries - skb_queue_len(&ring->queue))
 500                                 == 2) {
 501
 502                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 503                                         ("more desc left, wake"
 504                                          "skb_queue@%d,ring->idx = %d,"
 505                                          "skb_queue_len = 0x%d\n",
 506                                          prio, ring->idx,
 507                                          skb_queue_len(&ring->queue)));
 508
 509                         ieee80211_wake_queue(hw,
 510                                         skb_get_queue_mapping
 511                                         (skb));
 512                 }
 513
 514                 skb = NULL;
 515         }
 516
 517         if (((rtlpriv->link_info.num_rx_inperiod +
 518                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 519                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 520                 rtl_lps_leave(hw);
 521         }
 522 }
 523
 524 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
 525 {
 526         struct rtl_priv *rtlpriv = rtl_priv(hw);
 527         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 528         int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
 529
 530         struct ieee80211_rx_status rx_status = { 0 };
 531         unsigned int count = rtlpci->rxringcount;
 532         u8 own;
 533         u8 tmp_one;
 534         u32 bufferaddress;
 535         bool unicast = false;
 536
 537         struct rtl_stats stats = {
 538                 .signal = 0,
 539                 .noise = -98,
 540                 .rate = 0,
 541         };
 542
 543         /*RX NORMAL PKT */
 544         while (count--) {
 545                 /*rx descriptor */
 546                 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
 547                                 rtlpci->rx_ring[rx_queue_idx].idx];
 548                 /*rx pkt */
 549                 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
 550                                 rtlpci->rx_ring[rx_queue_idx].idx];
 551
 552                 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 553                                                        false, HW_DESC_OWN);
 554
 555                 if (own) {
 556                         /*wait data to be filled by hardware */
 557                         return;
 558                 } else {
 559                         struct ieee80211_hdr *hdr;
 560                         __le16 fc;
 561                         struct sk_buff *new_skb = NULL;
 562
 563                         rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
 564                                                          &rx_status,
 565                                                          (u8 *) pdesc, skb);
 566
 567                         pci_unmap_single(rtlpci->pdev,
 568                                          *((dma_addr_t *) skb->cb),
 569                                          rtlpci->rxbuffersize,
 570                                          PCI_DMA_FROMDEVICE);
 571
 572                         skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 573                                                          false,
 574                                                          HW_DESC_RXPKT_LEN));
 575                         skb_reserve(skb,
 576                                     stats.rx_drvinfo_size + stats.rx_bufshift);
 577
 578                         /*
 579                          *NOTICE This can not be use for mac80211,
 580                          *this is done in mac80211 code,
 581                          *if you done here sec DHCP will fail
 582                          *skb_trim(skb, skb->len - 4);
 583                          */
 584
 585                         hdr = (struct ieee80211_hdr *)(skb->data);
 586                         fc = hdr->frame_control;
 587
 588                         if (!stats.crc) {
 589                                 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
 590                                        sizeof(rx_status));
 591
 592                                 if (is_broadcast_ether_addr(hdr->addr1))
 593                                         ;/*TODO*/
 594                                 else {
 595                                         if (is_multicast_ether_addr(hdr->addr1))
 596                                                 ;/*TODO*/
 597                                         else {
 598                                                 unicast = true;
 599                                                 rtlpriv->stats.rxbytesunicast +=
 600                                                     skb->len;
 601                                         }
 602                                 }
 603
 604                                 rtl_is_special_data(hw, skb, false);
 605
 606                                 if (ieee80211_is_data(fc)) {
 607                                         rtlpriv->cfg->ops->led_control(hw,
 608                                                                LED_CTL_RX);
 609
 610                                         if (unicast)
 611                                                 rtlpriv->link_info.
 612                                                     num_rx_inperiod++;
 613                                 }
 614
 615                                 if (unlikely(!rtl_action_proc(hw, skb,
 616                                     false))) {
 617                                         dev_kfree_skb_any(skb);
 618                                 } else {
 619                                         struct sk_buff *uskb = NULL;
 620                                         u8 *pdata;
 621                                         uskb = dev_alloc_skb(skb->len + 128);
 622                                         if (!uskb) {
 623                                                 RT_TRACE(rtlpriv,
 624                                                         (COMP_INTR | COMP_RECV),
 625                                                         DBG_EMERG,
 626                                                         ("can't alloc rx skb\n"));
 627                                                 goto done;
 628                                         }
 629                                         memcpy(IEEE80211_SKB_RXCB(uskb),
 630                                                         &rx_status,
 631                                                         sizeof(rx_status));
 632                                         pdata = (u8 *)skb_put(uskb, skb->len);
 633                                         memcpy(pdata, skb->data, skb->len);
 634                                         dev_kfree_skb_any(skb);
 635
 636                                         ieee80211_rx_irqsafe(hw, uskb);
 637                                 }
 638                         } else {
 639                                 dev_kfree_skb_any(skb);
 640                         }
 641
 642                         if (((rtlpriv->link_info.num_rx_inperiod +
 643                                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 644                                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 645                                 rtl_lps_leave(hw);
 646                         }
 647
 648                         new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
 649                         if (unlikely(!new_skb)) {
 650                                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
 651                                          DBG_EMERG,
 652                                          ("can't alloc skb for rx\n"));
 653                                 goto done;
 654                         }
 655                         skb = new_skb;
 656                         /*skb->dev = dev; */
 657
 658                         rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
 659                                                              rx_ring
 660                                                              [rx_queue_idx].
 661                                                              idx] = skb;
 662                         *((dma_addr_t *) skb->cb) =
 663                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
 664                                            rtlpci->rxbuffersize,
 665                                            PCI_DMA_FROMDEVICE);
 666
 667                 }
 668 done:
 669                 bufferaddress = (u32)(*((dma_addr_t *) skb->cb));
 670                 tmp_one = 1;
 671                 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
 672                                             HW_DESC_RXBUFF_ADDR,
 673                                             (u8 *)&bufferaddress);
 674                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
 675                                             (u8 *)&tmp_one);
 676                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 677                                             HW_DESC_RXPKT_LEN,
 678                                             (u8 *)&rtlpci->rxbuffersize);
 679
 680                 if (rtlpci->rx_ring[rx_queue_idx].idx ==
 681                     rtlpci->rxringcount - 1)
 682                         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 683                                                     HW_DESC_RXERO,
 684                                                     (u8 *)&tmp_one);
 685
 686                 rtlpci->rx_ring[rx_queue_idx].idx =
 687                     (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
 688                     rtlpci->rxringcount;
 689         }
 690
 691 }
 692
 693 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
 694 {
 695         struct ieee80211_hw *hw = dev_id;
 696         struct rtl_priv *rtlpriv = rtl_priv(hw);
 697         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 698         unsigned long flags;
 699         u32 inta = 0;
 700         u32 intb = 0;
 701
 702         if (rtlpci->irq_enabled == 0)
 703                 return IRQ_HANDLED;
 704
 705         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
 706
 707         /*read ISR: 4/8bytes */
 708         rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
 709
 710         /*Shared IRQ or HW disappared */
 711         if (!inta || inta == 0xffff)
 712                 goto done;
 713
 714         /*<1> beacon related */
 715         if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
 716                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 717                          ("beacon ok interrupt!\n"));
 718         }
 719
 720         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
 721                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 722                          ("beacon err interrupt!\n"));
 723         }
 724
 725         if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
 726                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 727                          ("beacon interrupt!\n"));
 728         }
 729
 730         if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
 731                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 732                          ("prepare beacon for interrupt!\n"));
 733                 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
 734         }
 735
 736         /*<3> Tx related */
 737         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
 738                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
 739
 740         if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
 741                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 742                          ("Manage ok interrupt!\n"));
 743                 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
 744         }
 745
 746         if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
 747                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 748                          ("HIGH_QUEUE ok interrupt!\n"));
 749                 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
 750         }
 751
 752         if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
 753                 rtlpriv->link_info.num_tx_inperiod++;
 754
 755                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 756                          ("BK Tx OK interrupt!\n"));
 757                 _rtl_pci_tx_isr(hw, BK_QUEUE);
 758         }
 759
 760         if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
 761                 rtlpriv->link_info.num_tx_inperiod++;
 762
 763                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 764                          ("BE TX OK interrupt!\n"));
 765                 _rtl_pci_tx_isr(hw, BE_QUEUE);
 766         }
 767
 768         if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
 769                 rtlpriv->link_info.num_tx_inperiod++;
 770
 771                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 772                          ("VI TX OK interrupt!\n"));
 773                 _rtl_pci_tx_isr(hw, VI_QUEUE);
 774         }
 775
 776         if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
 777                 rtlpriv->link_info.num_tx_inperiod++;
 778
 779                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 780                          ("Vo TX OK interrupt!\n"));
 781                 _rtl_pci_tx_isr(hw, VO_QUEUE);
 782         }
 783
 784         /*<2> Rx related */
 785         if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
 786                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
 787                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 788         }
 789
 790         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
 791                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 792                          ("rx descriptor unavailable!\n"));
 793                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 794         }
 795
 796         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
 797                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
 798                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 799         }
 800
 801         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 802         return IRQ_HANDLED;
 803
 804 done:
 805         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 806         return IRQ_HANDLED;
 807 }
 808
 809 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
 810 {
 811         _rtl_pci_rx_interrupt(hw);
 812 }
 813
 814 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
 815 {
 816         struct rtl_priv *rtlpriv = rtl_priv(hw);
 817         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 818         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 819         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
 820         struct ieee80211_hdr *hdr = NULL;
 821         struct ieee80211_tx_info *info = NULL;
 822         struct sk_buff *pskb = NULL;
 823         struct rtl_tx_desc *pdesc = NULL;
 824         unsigned int queue_index;
 825         u8 temp_one = 1;
 826
 827         ring = &rtlpci->tx_ring[BEACON_QUEUE];
 828         pskb = __skb_dequeue(&ring->queue);
 829         if (pskb)
 830                 kfree_skb(pskb);
 831
 832         /*NB: the beacon data buffer must be 32-bit aligned. */
 833         pskb = ieee80211_beacon_get(hw, mac->vif);
 834         if (pskb == NULL)
 835                 return;
 836         hdr = (struct ieee80211_hdr *)(pskb->data);
 837         info = IEEE80211_SKB_CB(pskb);
 838
 839         queue_index = BEACON_QUEUE;
 840
 841         pdesc = &ring->desc[0];
 842         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
 843                                         info, pskb, queue_index);
 844
 845         __skb_queue_tail(&ring->queue, pskb);
 846
 847         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
 848                                     (u8 *)&temp_one);
 849
 850         return;
 851 }
 852
 853 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
 854 {
 855         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 856         u8 i;
 857
 858         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
 859                 rtlpci->txringcount[i] = RT_TXDESC_NUM;
 860
 861         /*
 862          *we just alloc 2 desc for beacon queue,
 863          *because we just need first desc in hw beacon.
 864          */
 865         rtlpci->txringcount[BEACON_QUEUE] = 2;
 866
 867         /*
 868          *BE queue need more descriptor for performance
 869          *consideration or, No more tx desc will happen,
 870          *and may cause mac80211 mem leakage.
 871          */
 872         rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
 873
 874         rtlpci->rxbuffersize = 9100;    /*2048/1024; */
 875         rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;     /*64; */
 876 }
 877
 878 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
 879                 struct pci_dev *pdev)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 883         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 884         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 885         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 886
 887         rtlpci->up_first_time = true;
 888         rtlpci->being_init_adapter = false;
 889
 890         rtlhal->hw = hw;
 891         rtlpci->pdev = pdev;
 892
 893         ppsc->inactiveps = false;
 894         ppsc->leisure_ps = true;
 895         ppsc->fwctrl_lps = true;
 896         ppsc->reg_fwctrl_lps = 3;
 897         ppsc->reg_max_lps_awakeintvl = 5;
 898
 899         if (ppsc->reg_fwctrl_lps == 1)
 900                 ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
 901         else if (ppsc->reg_fwctrl_lps == 2)
 902                 ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
 903         else if (ppsc->reg_fwctrl_lps == 3)
 904                 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
 905
 906         /*Tx/Rx related var */
 907         _rtl_pci_init_trx_var(hw);
 908
 909          /*IBSS*/ mac->beacon_interval = 100;
 910
 911          /*AMPDU*/ mac->min_space_cfg = 0;
 912         mac->max_mss_density = 0;
 913         /*set sane AMPDU defaults */
 914         mac->current_ampdu_density = 7;
 915         mac->current_ampdu_factor = 3;
 916
 917          /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
 918
 919         /*task */
 920         tasklet_init(&rtlpriv->works.irq_tasklet,
 921                      (void (*)(unsigned long))_rtl_pci_irq_tasklet,
 922                      (unsigned long)hw);
 923         tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
 924                      (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
 925                      (unsigned long)hw);
 926 }
 927
 928 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
 929                                  unsigned int prio, unsigned int entries)
 930 {
 931         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 932         struct rtl_priv *rtlpriv = rtl_priv(hw);
 933         struct rtl_tx_desc *ring;
 934         dma_addr_t dma;
 935         u32 nextdescaddress;
 936         int i;
 937
 938         ring = pci_alloc_consistent(rtlpci->pdev,
 939                                     sizeof(*ring) * entries, &dma);
 940
 941         if (!ring || (unsigned long)ring & 0xFF) {
 942                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 943                          ("Cannot allocate TX ring (prio = %d)\n", prio));
 944                 return -ENOMEM;
 945         }
 946
 947         memset(ring, 0, sizeof(*ring) * entries);
 948         rtlpci->tx_ring[prio].desc = ring;
 949         rtlpci->tx_ring[prio].dma = dma;
 950         rtlpci->tx_ring[prio].idx = 0;
 951         rtlpci->tx_ring[prio].entries = entries;
 952         skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
 953
 954         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 955                  ("queue:%d, ring_addr:%p\n", prio, ring));
 956
 957         for (i = 0; i < entries; i++) {
 958                 nextdescaddress = (u32) dma + ((i + 1) % entries) *
 959                                               sizeof(*ring);
 960
 961                 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
 962                                             true, HW_DESC_TX_NEXTDESC_ADDR,
 963                                             (u8 *)&nextdescaddress);
 964         }
 965
 966         return 0;
 967 }
 968
 969 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
 970 {
 971         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 972         struct rtl_priv *rtlpriv = rtl_priv(hw);
 973         struct rtl_rx_desc *entry = NULL;
 974         int i, rx_queue_idx;
 975         u8 tmp_one = 1;
 976
 977         /*
 978          *rx_queue_idx 0:RX_MPDU_QUEUE
 979          *rx_queue_idx 1:RX_CMD_QUEUE
 980          */
 981         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
 982              rx_queue_idx++) {
 983                 rtlpci->rx_ring[rx_queue_idx].desc =
 984                     pci_alloc_consistent(rtlpci->pdev,
 985                                          sizeof(*rtlpci->rx_ring[rx_queue_idx].
 986                                                 desc) * rtlpci->rxringcount,
 987                                          &rtlpci->rx_ring[rx_queue_idx].dma);
 988
 989                 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
 990                     (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
 991                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 992                                  ("Cannot allocate RX ring\n"));
 993                         return -ENOMEM;
 994                 }
 995
 996                 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
 997                        sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
 998                        rtlpci->rxringcount);
 999
1000                 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1001
1002                 for (i = 0; i < rtlpci->rxringcount; i++) {
1003                         struct sk_buff *skb =
1004                             dev_alloc_skb(rtlpci->rxbuffersize);
1005                         u32 bufferaddress;
1006                         if (!skb)
1007                                 return 0;
1008                         entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1009
1010                         /*skb->dev = dev; */
1011
1012                         rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1013
1014                         /*
1015                          *just set skb->cb to mapping addr
1016                          *for pci_unmap_single use
1017                          */
1018                         *((dma_addr_t *) skb->cb) =
1019                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1020                                            rtlpci->rxbuffersize,
1021                                            PCI_DMA_FROMDEVICE);
1022
1023                         bufferaddress = (u32)(*((dma_addr_t *)skb->cb));
1024                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1025                                                     HW_DESC_RXBUFF_ADDR,
1026                                                     (u8 *)&bufferaddress);
1027                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1028                                                     HW_DESC_RXPKT_LEN,
1029                                                     (u8 *)&rtlpci->
1030                                                     rxbuffersize);
1031                         rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1032                                                     HW_DESC_RXOWN,
1033                                                     (u8 *)&tmp_one);
1034                 }
1035
1036                 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1037                                             HW_DESC_RXERO, (u8 *)&tmp_one);
1038         }
1039         return 0;
1040 }
1041
1042 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1043                 unsigned int prio)
1044 {
1045         struct rtl_priv *rtlpriv = rtl_priv(hw);
1046         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1047         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1048
1049         while (skb_queue_len(&ring->queue)) {
1050                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1051                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1052
1053                 pci_unmap_single(rtlpci->pdev,
1054                                  rtlpriv->cfg->
1055                                              ops->get_desc((u8 *) entry, true,
1056                                                    HW_DESC_TXBUFF_ADDR),
1057                                  skb->len, PCI_DMA_TODEVICE);
1058                 kfree_skb(skb);
1059                 ring->idx = (ring->idx + 1) % ring->entries;
1060         }
1061
1062         pci_free_consistent(rtlpci->pdev,
1063                             sizeof(*ring->desc) * ring->entries,
1064                             ring->desc, ring->dma);
1065         ring->desc = NULL;
1066 }
1067
1068 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1069 {
1070         int i, rx_queue_idx;
1071
1072         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1073         /*rx_queue_idx 1:RX_CMD_QUEUE */
1074         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1075              rx_queue_idx++) {
1076                 for (i = 0; i < rtlpci->rxringcount; i++) {
1077                         struct sk_buff *skb =
1078                             rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1079                         if (!skb)
1080                                 continue;
1081
1082                         pci_unmap_single(rtlpci->pdev,
1083                                          *((dma_addr_t *) skb->cb),
1084                                          rtlpci->rxbuffersize,
1085                                          PCI_DMA_FROMDEVICE);
1086                         kfree_skb(skb);
1087                 }
1088
1089                 pci_free_consistent(rtlpci->pdev,
1090                                     sizeof(*rtlpci->rx_ring[rx_queue_idx].
1091                                            desc) * rtlpci->rxringcount,
1092                                     rtlpci->rx_ring[rx_queue_idx].desc,
1093                                     rtlpci->rx_ring[rx_queue_idx].dma);
1094                 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1095         }
1096 }
1097
1098 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1099 {
1100         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1101         int ret;
1102         int i;
1103
1104         ret = _rtl_pci_init_rx_ring(hw);
1105         if (ret)
1106                 return ret;
1107
1108         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1109                 ret = _rtl_pci_init_tx_ring(hw, i,
1110                                  rtlpci->txringcount[i]);
1111                 if (ret)
1112                         goto err_free_rings;
1113         }
1114
1115         return 0;
1116
1117 err_free_rings:
1118         _rtl_pci_free_rx_ring(rtlpci);
1119
1120         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1121                 if (rtlpci->tx_ring[i].desc)
1122                         _rtl_pci_free_tx_ring(hw, i);
1123
1124         return 1;
1125 }
1126
1127 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1128 {
1129         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1130         u32 i;
1131
1132         /*free rx rings */
1133         _rtl_pci_free_rx_ring(rtlpci);
1134
1135         /*free tx rings */
1136         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1137                 _rtl_pci_free_tx_ring(hw, i);
1138
1139         return 0;
1140 }
1141
1142 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1143 {
1144         struct rtl_priv *rtlpriv = rtl_priv(hw);
1145         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1146         int i, rx_queue_idx;
1147         unsigned long flags;
1148         u8 tmp_one = 1;
1149
1150         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1151         /*rx_queue_idx 1:RX_CMD_QUEUE */
1152         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1153              rx_queue_idx++) {
1154                 /*
1155                  *force the rx_ring[RX_MPDU_QUEUE/
1156                  *RX_CMD_QUEUE].idx to the first one
1157                  */
1158                 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1159                         struct rtl_rx_desc *entry = NULL;
1160
1161                         for (i = 0; i < rtlpci->rxringcount; i++) {
1162                                 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1163                                 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1164                                                             false,
1165                                                             HW_DESC_RXOWN,
1166                                                             (u8 *)&tmp_one);
1167                         }
1168                         rtlpci->rx_ring[rx_queue_idx].idx = 0;
1169                 }
1170         }
1171
1172         /*
1173          *after reset, release previous pending packet,
1174          *and force the  tx idx to the first one
1175          */
1176         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1177         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1178                 if (rtlpci->tx_ring[i].desc) {
1179                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1180
1181                         while (skb_queue_len(&ring->queue)) {
1182                                 struct rtl_tx_desc *entry =
1183                                     &ring->desc[ring->idx];
1184                                 struct sk_buff *skb =
1185                                     __skb_dequeue(&ring->queue);
1186
1187                                 pci_unmap_single(rtlpci->pdev,
1188                                                  rtlpriv->cfg->ops->
1189                                                          get_desc((u8 *)
1190                                                          entry,
1191                                                          true,
1192                                                          HW_DESC_TXBUFF_ADDR),
1193                                                  skb->len, PCI_DMA_TODEVICE);
1194                                 kfree_skb(skb);
1195                                 ring->idx = (ring->idx + 1) % ring->entries;
1196                         }
1197                         ring->idx = 0;
1198                 }
1199         }
1200
1201         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1202
1203         return 0;
1204 }
1205
1206 static unsigned int _rtl_mac_to_hwqueue(__le16 fc,
1207                 unsigned int mac80211_queue_index)
1208 {
1209         unsigned int hw_queue_index;
1210
1211         if (unlikely(ieee80211_is_beacon(fc))) {
1212                 hw_queue_index = BEACON_QUEUE;
1213                 goto out;
1214         }
1215
1216         if (ieee80211_is_mgmt(fc)) {
1217                 hw_queue_index = MGNT_QUEUE;
1218                 goto out;
1219         }
1220
1221         switch (mac80211_queue_index) {
1222         case 0:
1223                 hw_queue_index = VO_QUEUE;
1224                 break;
1225         case 1:
1226                 hw_queue_index = VI_QUEUE;
1227                 break;
1228         case 2:
1229                 hw_queue_index = BE_QUEUE;
1230                 break;
1231         case 3:
1232                 hw_queue_index = BK_QUEUE;
1233                 break;
1234         default:
1235                 hw_queue_index = BE_QUEUE;
1236                 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
1237                                   mac80211_queue_index));
1238                 break;
1239         }
1240
1241 out:
1242         return hw_queue_index;
1243 }
1244
1245 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1246 {
1247         struct rtl_priv *rtlpriv = rtl_priv(hw);
1248         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1249         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1250         struct rtl8192_tx_ring *ring;
1251         struct rtl_tx_desc *pdesc;
1252         u8 idx;
1253         unsigned int queue_index, hw_queue;
1254         unsigned long flags;
1255         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
1256         __le16 fc = hdr->frame_control;
1257         u8 *pda_addr = hdr->addr1;
1258         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1259         /*ssn */
1260         u8 *qc = NULL;
1261         u8 tid = 0;
1262         u16 seq_number = 0;
1263         u8 own;
1264         u8 temp_one = 1;
1265
1266         if (ieee80211_is_mgmt(fc))
1267                 rtl_tx_mgmt_proc(hw, skb);
1268         rtl_action_proc(hw, skb, true);
1269
1270         queue_index = skb_get_queue_mapping(skb);
1271         hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
1272
1273         if (is_multicast_ether_addr(pda_addr))
1274                 rtlpriv->stats.txbytesmulticast += skb->len;
1275         else if (is_broadcast_ether_addr(pda_addr))
1276                 rtlpriv->stats.txbytesbroadcast += skb->len;
1277         else
1278                 rtlpriv->stats.txbytesunicast += skb->len;
1279
1280         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1281
1282         ring = &rtlpci->tx_ring[hw_queue];
1283         if (hw_queue != BEACON_QUEUE)
1284                 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1285                                 ring->entries;
1286         else
1287                 idx = 0;
1288
1289         pdesc = &ring->desc[idx];
1290         own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1291                         true, HW_DESC_OWN);
1292
1293         if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1294                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1295                          ("No more TX desc@%d, ring->idx = %d,"
1296                           "idx = %d, skb_queue_len = 0x%d\n",
1297                           hw_queue, ring->idx, idx,
1298                           skb_queue_len(&ring->queue)));
1299
1300                 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1301                 return skb->len;
1302         }
1303
1304         /*
1305          *if(ieee80211_is_nullfunc(fc)) {
1306          *      spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1307          *      return 1;
1308          *}
1309          */
1310
1311         if (ieee80211_is_data_qos(fc)) {
1312                 qc = ieee80211_get_qos_ctl(hdr);
1313                 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1314
1315                 seq_number = mac->tids[tid].seq_number;
1316                 seq_number &= IEEE80211_SCTL_SEQ;
1317                 /*
1318                  *hdr->seq_ctrl = hdr->seq_ctrl &
1319                  *cpu_to_le16(IEEE80211_SCTL_FRAG);
1320                  *hdr->seq_ctrl |= cpu_to_le16(seq_number);
1321                  */
1322
1323                 seq_number += 1;
1324         }
1325
1326         if (ieee80211_is_data(fc))
1327                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1328
1329         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1330                                         info, skb, hw_queue);
1331
1332         __skb_queue_tail(&ring->queue, skb);
1333
1334         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
1335                                     HW_DESC_OWN, (u8 *)&temp_one);
1336
1337         if (!ieee80211_has_morefrags(hdr->frame_control)) {
1338                 if (qc)
1339                         mac->tids[tid].seq_number = seq_number;
1340         }
1341
1342         if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1343             hw_queue != BEACON_QUEUE) {
1344
1345                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1346                          ("less desc left, stop skb_queue@%d, "
1347                           "ring->idx = %d,"
1348                           "idx = %d, skb_queue_len = 0x%d\n",
1349                           hw_queue, ring->idx, idx,
1350                           skb_queue_len(&ring->queue)));
1351
1352                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1353         }
1354
1355         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1356
1357         rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1358
1359         return 0;
1360 }
1361
1362 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1363 {
1364         struct rtl_priv *rtlpriv = rtl_priv(hw);
1365         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366
1367         _rtl_pci_deinit_trx_ring(hw);
1368
1369         synchronize_irq(rtlpci->pdev->irq);
1370         tasklet_kill(&rtlpriv->works.irq_tasklet);
1371
1372         flush_workqueue(rtlpriv->works.rtl_wq);
1373         destroy_workqueue(rtlpriv->works.rtl_wq);
1374
1375 }
1376
1377 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1378 {
1379         struct rtl_priv *rtlpriv = rtl_priv(hw);
1380         int err;
1381
1382         _rtl_pci_init_struct(hw, pdev);
1383
1384         err = _rtl_pci_init_trx_ring(hw);
1385         if (err) {
1386                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1387                          ("tx ring initialization failed"));
1388                 return err;
1389         }
1390
1391         return 1;
1392 }
1393
1394 static int rtl_pci_start(struct ieee80211_hw *hw)
1395 {
1396         struct rtl_priv *rtlpriv = rtl_priv(hw);
1397         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1398         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1399         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1400
1401         int err;
1402
1403         rtl_pci_reset_trx_ring(hw);
1404
1405         rtlpci->driver_is_goingto_unload = false;
1406         err = rtlpriv->cfg->ops->hw_init(hw);
1407         if (err) {
1408                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1409                          ("Failed to config hardware!\n"));
1410                 return err;
1411         }
1412
1413         rtlpriv->cfg->ops->enable_interrupt(hw);
1414         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1415
1416         rtl_init_rx_config(hw);
1417
1418         /*should after adapter start and interrupt enable. */
1419         set_hal_start(rtlhal);
1420
1421         RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1422
1423         rtlpci->up_first_time = false;
1424
1425         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1426         return 0;
1427 }
1428
1429 static void rtl_pci_stop(struct ieee80211_hw *hw)
1430 {
1431         struct rtl_priv *rtlpriv = rtl_priv(hw);
1432         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1433         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1434         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1435         unsigned long flags;
1436         u8 RFInProgressTimeOut = 0;
1437
1438         /*
1439          *should before disable interrrupt&adapter
1440          *and will do it immediately.
1441          */
1442         set_hal_stop(rtlhal);
1443
1444         rtlpriv->cfg->ops->disable_interrupt(hw);
1445
1446         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1447         while (ppsc->rfchange_inprogress) {
1448                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1449                 if (RFInProgressTimeOut > 100) {
1450                         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1451                         break;
1452                 }
1453                 mdelay(1);
1454                 RFInProgressTimeOut++;
1455                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1456         }
1457         ppsc->rfchange_inprogress = true;
1458         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1459
1460         rtlpci->driver_is_goingto_unload = true;
1461         rtlpriv->cfg->ops->hw_disable(hw);
1462         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1463
1464         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1465         ppsc->rfchange_inprogress = false;
1466         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1467
1468         rtl_pci_enable_aspm(hw);
1469 }
1470
1471 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1472                 struct ieee80211_hw *hw)
1473 {
1474         struct rtl_priv *rtlpriv = rtl_priv(hw);
1475         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1476         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1477         struct pci_dev *bridge_pdev = pdev->bus->self;
1478         u16 venderid;
1479         u16 deviceid;
1480         u16 irqline;
1481         u8 tmp;
1482
1483         venderid = pdev->vendor;
1484         deviceid = pdev->device;
1485         pci_read_config_word(pdev, 0x3C, &irqline);
1486
1487         if (deviceid == RTL_PCI_8192_DID ||
1488             deviceid == RTL_PCI_0044_DID ||
1489             deviceid == RTL_PCI_0047_DID ||
1490             deviceid == RTL_PCI_8192SE_DID ||
1491             deviceid == RTL_PCI_8174_DID ||
1492             deviceid == RTL_PCI_8173_DID ||
1493             deviceid == RTL_PCI_8172_DID ||
1494             deviceid == RTL_PCI_8171_DID) {
1495                 switch (pdev->revision) {
1496                 case RTL_PCI_REVISION_ID_8192PCIE:
1497                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1498                                  ("8192 PCI-E is found - "
1499                                   "vid/did=%x/%x\n", venderid, deviceid));
1500                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1501                         break;
1502                 case RTL_PCI_REVISION_ID_8192SE:
1503                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1504                                  ("8192SE is found - "
1505                                   "vid/did=%x/%x\n", venderid, deviceid));
1506                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1507                         break;
1508                 default:
1509                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1510                                  ("Err: Unknown device - "
1511                                   "vid/did=%x/%x\n", venderid, deviceid));
1512                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1513                         break;
1514
1515                 }
1516         } else if (deviceid == RTL_PCI_8192CET_DID ||
1517                    deviceid == RTL_PCI_8192CE_DID ||
1518                    deviceid == RTL_PCI_8191CE_DID ||
1519                    deviceid == RTL_PCI_8188CE_DID) {
1520                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1521                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1522                          ("8192C PCI-E is found - "
1523                           "vid/did=%x/%x\n", venderid, deviceid));
1524         } else {
1525                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1526                          ("Err: Unknown device -"
1527                           " vid/did=%x/%x\n", venderid, deviceid));
1528
1529                 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1530         }
1531
1532         /*find bus info */
1533         pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1534         pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1535         pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1536
1537         /*find bridge info */
1538         pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1539         for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1540                 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1541                         pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1542                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1543                                  ("Pci Bridge Vendor is found index: %d\n",
1544                                   tmp));
1545                         break;
1546                 }
1547         }
1548
1549         if (pcipriv->ndis_adapter.pcibridge_vendor !=
1550                 PCI_BRIDGE_VENDOR_UNKNOWN) {
1551                 pcipriv->ndis_adapter.pcibridge_busnum =
1552                     bridge_pdev->bus->number;
1553                 pcipriv->ndis_adapter.pcibridge_devnum =
1554                     PCI_SLOT(bridge_pdev->devfn);
1555                 pcipriv->ndis_adapter.pcibridge_funcnum =
1556                     PCI_FUNC(bridge_pdev->devfn);
1557                 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1558                     pci_pcie_cap(bridge_pdev);
1559                 pcipriv->ndis_adapter.pcicfg_addrport =
1560                     (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1561                     (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1562                     (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1563                 pcipriv->ndis_adapter.num4bytes =
1564                     (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1565
1566                 rtl_pci_get_linkcontrol_field(hw);
1567
1568                 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1569                     PCI_BRIDGE_VENDOR_AMD) {
1570                         pcipriv->ndis_adapter.amd_l1_patch =
1571                             rtl_pci_get_amd_l1_patch(hw);
1572                 }
1573         }
1574
1575         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1576                  ("pcidev busnumber:devnumber:funcnumber:"
1577                   "vendor:link_ctl %d:%d:%d:%x:%x\n",
1578                   pcipriv->ndis_adapter.busnumber,
1579                   pcipriv->ndis_adapter.devnumber,
1580                   pcipriv->ndis_adapter.funcnumber,
1581                   pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1582
1583         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1584                  ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1585                   "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1586                   pcipriv->ndis_adapter.pcibridge_busnum,
1587                   pcipriv->ndis_adapter.pcibridge_devnum,
1588                   pcipriv->ndis_adapter.pcibridge_funcnum,
1589                   pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1590                   pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1591                   pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1592                   pcipriv->ndis_adapter.amd_l1_patch));
1593
1594         rtl_pci_parse_configuration(pdev, hw);
1595
1596         return true;
1597 }
1598
1599 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1600                             const struct pci_device_id *id)
1601 {
1602         struct ieee80211_hw *hw = NULL;
1603
1604         struct rtl_priv *rtlpriv = NULL;
1605         struct rtl_pci_priv *pcipriv = NULL;
1606         struct rtl_pci *rtlpci;
1607         unsigned long pmem_start, pmem_len, pmem_flags;
1608         int err;
1609
1610         err = pci_enable_device(pdev);
1611         if (err) {
1612                 RT_ASSERT(false,
1613                           ("%s : Cannot enable new PCI device\n",
1614                            pci_name(pdev)));
1615                 return err;
1616         }
1617
1618         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1619                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1620                         RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1621                                           "for consistent allocations\n"));
1622                         pci_disable_device(pdev);
1623                         return -ENOMEM;
1624                 }
1625         }
1626
1627         pci_set_master(pdev);
1628
1629         hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1630                                 sizeof(struct rtl_priv), &rtl_ops);
1631         if (!hw) {
1632                 RT_ASSERT(false,
1633                           ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1634                 err = -ENOMEM;
1635                 goto fail1;
1636         }
1637
1638         SET_IEEE80211_DEV(hw, &pdev->dev);
1639         pci_set_drvdata(pdev, hw);
1640
1641         rtlpriv = hw->priv;
1642         pcipriv = (void *)rtlpriv->priv;
1643         pcipriv->dev.pdev = pdev;
1644
1645         /*
1646          *init dbgp flags before all
1647          *other functions, because we will
1648          *use it in other funtions like
1649          *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1650          *you can not use these macro
1651          *before this
1652          */
1653         rtl_dbgp_flag_init(hw);
1654
1655         /* MEM map */
1656         err = pci_request_regions(pdev, KBUILD_MODNAME);
1657         if (err) {
1658                 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1659                 return err;
1660         }
1661
1662         pmem_start = pci_resource_start(pdev, 2);
1663         pmem_len = pci_resource_len(pdev, 2);
1664         pmem_flags = pci_resource_flags(pdev, 2);
1665
1666         /*shared mem start */
1667         rtlpriv->io.pci_mem_start =
1668                         (unsigned long)pci_iomap(pdev, 2, pmem_len);
1669         if (rtlpriv->io.pci_mem_start == 0) {
1670                 RT_ASSERT(false, ("Can't map PCI mem\n"));
1671                 goto fail2;
1672         }
1673
1674         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1675                  ("mem mapped space: start: 0x%08lx len:%08lx "
1676                   "flags:%08lx, after map:0x%08lx\n",
1677                   pmem_start, pmem_len, pmem_flags,
1678                   rtlpriv->io.pci_mem_start));
1679
1680         /* Disable Clk Request */
1681         pci_write_config_byte(pdev, 0x81, 0);
1682         /* leave D3 mode */
1683         pci_write_config_byte(pdev, 0x44, 0);
1684         pci_write_config_byte(pdev, 0x04, 0x06);
1685         pci_write_config_byte(pdev, 0x04, 0x07);
1686
1687         /* init cfg & intf_ops */
1688         rtlpriv->rtlhal.interface = INTF_PCI;
1689         rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1690         rtlpriv->intf_ops = &rtl_pci_ops;
1691
1692         /* find adapter */
1693         _rtl_pci_find_adapter(pdev, hw);
1694
1695         /* Init IO handler */
1696         _rtl_pci_io_handler_init(&pdev->dev, hw);
1697
1698         /*like read eeprom and so on */
1699         rtlpriv->cfg->ops->read_eeprom_info(hw);
1700
1701         if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1703                          ("Can't init_sw_vars.\n"));
1704                 goto fail3;
1705         }
1706
1707         rtlpriv->cfg->ops->init_sw_leds(hw);
1708
1709         /*aspm */
1710         rtl_pci_init_aspm(hw);
1711
1712         /* Init mac80211 sw */
1713         err = rtl_init_core(hw);
1714         if (err) {
1715                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1716                          ("Can't allocate sw for mac80211.\n"));
1717                 goto fail3;
1718         }
1719
1720         /* Init PCI sw */
1721         err = !rtl_pci_init(hw, pdev);
1722         if (err) {
1723                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1724                          ("Failed to init PCI.\n"));
1725                 goto fail3;
1726         }
1727
1728         err = ieee80211_register_hw(hw);
1729         if (err) {
1730                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1731                          ("Can't register mac80211 hw.\n"));
1732                 goto fail3;
1733         } else {
1734                 rtlpriv->mac80211.mac80211_registered = 1;
1735         }
1736
1737         err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1738         if (err) {
1739                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1740                          ("failed to create sysfs device attributes\n"));
1741                 goto fail3;
1742         }
1743
1744         /*init rfkill */
1745         rtl_init_rfkill(hw);
1746
1747         rtlpci = rtl_pcidev(pcipriv);
1748         err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1749                           IRQF_SHARED, KBUILD_MODNAME, hw);
1750         if (err) {
1751                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1752                          ("%s: failed to register IRQ handler\n",
1753                           wiphy_name(hw->wiphy)));
1754                 goto fail3;
1755         } else {
1756                 rtlpci->irq_alloc = 1;
1757         }
1758
1759         set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1760         return 0;
1761
1762 fail3:
1763         pci_set_drvdata(pdev, NULL);
1764         rtl_deinit_core(hw);
1765         _rtl_pci_io_handler_release(hw);
1766         ieee80211_free_hw(hw);
1767
1768         if (rtlpriv->io.pci_mem_start != 0)
1769                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1770
1771 fail2:
1772         pci_release_regions(pdev);
1773
1774 fail1:
1775
1776         pci_disable_device(pdev);
1777
1778         return -ENODEV;
1779
1780 }
1781 EXPORT_SYMBOL(rtl_pci_probe);
1782
1783 void rtl_pci_disconnect(struct pci_dev *pdev)
1784 {
1785         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1786         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1787         struct rtl_priv *rtlpriv = rtl_priv(hw);
1788         struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1789         struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1790
1791         clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1792
1793         sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1794
1795         /*ieee80211_unregister_hw will call ops_stop */
1796         if (rtlmac->mac80211_registered == 1) {
1797                 ieee80211_unregister_hw(hw);
1798                 rtlmac->mac80211_registered = 0;
1799         } else {
1800                 rtl_deinit_deferred_work(hw);
1801                 rtlpriv->intf_ops->adapter_stop(hw);
1802         }
1803
1804         /*deinit rfkill */
1805         rtl_deinit_rfkill(hw);
1806
1807         rtl_pci_deinit(hw);
1808         rtl_deinit_core(hw);
1809         rtlpriv->cfg->ops->deinit_sw_leds(hw);
1810         _rtl_pci_io_handler_release(hw);
1811         rtlpriv->cfg->ops->deinit_sw_vars(hw);
1812
1813         if (rtlpci->irq_alloc) {
1814                 free_irq(rtlpci->pdev->irq, hw);
1815                 rtlpci->irq_alloc = 0;
1816         }
1817
1818         if (rtlpriv->io.pci_mem_start != 0) {
1819                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1820                 pci_release_regions(pdev);
1821         }
1822
1823         pci_disable_device(pdev);
1824         pci_set_drvdata(pdev, NULL);
1825
1826         ieee80211_free_hw(hw);
1827 }
1828 EXPORT_SYMBOL(rtl_pci_disconnect);
1829
1830 /***************************************
1831 kernel pci power state define:
1832 PCI_D0         ((pci_power_t __force) 0)
1833 PCI_D1         ((pci_power_t __force) 1)
1834 PCI_D2         ((pci_power_t __force) 2)
1835 PCI_D3hot      ((pci_power_t __force) 3)
1836 PCI_D3cold     ((pci_power_t __force) 4)
1837 PCI_UNKNOWN    ((pci_power_t __force) 5)
1838
1839 This function is called when system
1840 goes into suspend state mac80211 will
1841 call rtl_mac_stop() from the mac80211
1842 suspend function first, So there is
1843 no need to call hw_disable here.
1844 ****************************************/
1845 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1846 {
1847         pci_save_state(pdev);
1848         pci_disable_device(pdev);
1849         pci_set_power_state(pdev, PCI_D3hot);
1850
1851         return 0;
1852 }
1853 EXPORT_SYMBOL(rtl_pci_suspend);
1854
1855 int rtl_pci_resume(struct pci_dev *pdev)
1856 {
1857         int ret;
1858
1859         pci_set_power_state(pdev, PCI_D0);
1860         ret = pci_enable_device(pdev);
1861         if (ret) {
1862                 RT_ASSERT(false, ("ERR: <======\n"));
1863                 return ret;
1864         }
1865
1866         pci_restore_state(pdev);
1867
1868         return 0;
1869 }
1870 EXPORT_SYMBOL(rtl_pci_resume);
1871
1872 struct rtl_intf_ops rtl_pci_ops = {
1873         .adapter_start = rtl_pci_start,
1874         .adapter_stop = rtl_pci_stop,
1875         .adapter_tx = rtl_pci_tx,
1876         .reset_trx_ring = rtl_pci_reset_trx_ring,
1877
1878         .disable_aspm = rtl_pci_disable_aspm,
1879         .enable_aspm = rtl_pci_enable_aspm,
1880 };