drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt73usb.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt73usb_register_read and rt73usb_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  * The _lock versions must be used if you already hold the usb_cache_mutex
  52  */
  53 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
  54                                          const unsigned int offset, u32 *value)
  55 {
  56         __le32 reg;
  57         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  58                                       USB_VENDOR_REQUEST_IN, offset,
  59                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  60         *value = le32_to_cpu(reg);
  61 }
  62
  63 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
  64                                               const unsigned int offset, u32 *value)
  65 {
  66         __le32 reg;
  67         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
  68                                        USB_VENDOR_REQUEST_IN, offset,
  69                                        &reg, sizeof(u32), REGISTER_TIMEOUT);
  70         *value = le32_to_cpu(reg);
  71 }
  72
  73 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
  74                                               const unsigned int offset,
  75                                               void *value, const u32 length)
  76 {
  77         int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
  78         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
  79                                       USB_VENDOR_REQUEST_IN, offset,
  80                                       value, length, timeout);
  81 }
  82
  83 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
  84                                           const unsigned int offset, u32 value)
  85 {
  86         __le32 reg = cpu_to_le32(value);
  87         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
  88                                       USB_VENDOR_REQUEST_OUT, offset,
  89                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  90 }
  91
  92 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
  93                                                const unsigned int offset, u32 value)
  94 {
  95         __le32 reg = cpu_to_le32(value);
  96         rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
  97                                        USB_VENDOR_REQUEST_OUT, offset,
  98                                       &reg, sizeof(u32), REGISTER_TIMEOUT);
  99 }
 100
 101 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
 102                                                const unsigned int offset,
 103                                                void *value, const u32 length)
 104 {
 105         int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
 106         rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
 107                                       USB_VENDOR_REQUEST_OUT, offset,
 108                                       value, length, timeout);
 109 }
 110
 111 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
 112 {
 113         u32 reg;
 114         unsigned int i;
 115
 116         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 117                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
 118                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 119                         break;
 120                 udelay(REGISTER_BUSY_DELAY);
 121         }
 122
 123         return reg;
 124 }
 125
 126 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 127                               const unsigned int word, const u8 value)
 128 {
 129         u32 reg;
 130
 131         mutex_lock(&rt2x00dev->usb_cache_mutex);
 132
 133         /*
 134          * Wait until the BBP becomes ready.
 135          */
 136         reg = rt73usb_bbp_check(rt2x00dev);
 137         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 138                 goto exit_fail;
 139
 140         /*
 141          * Write the data into the BBP.
 142          */
 143         reg = 0;
 144         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
 145         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 146         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 147         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
 148
 149         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 150         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 151
 152         return;
 153
 154 exit_fail:
 155         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 156
 157         ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
 158 }
 159
 160 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 161                              const unsigned int word, u8 *value)
 162 {
 163         u32 reg;
 164
 165         mutex_lock(&rt2x00dev->usb_cache_mutex);
 166
 167         /*
 168          * Wait until the BBP becomes ready.
 169          */
 170         reg = rt73usb_bbp_check(rt2x00dev);
 171         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 172                 goto exit_fail;
 173
 174         /*
 175          * Write the request into the BBP.
 176          */
 177         reg = 0;
 178         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 179         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 180         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 181
 182         rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 183
 184         /*
 185          * Wait until the BBP becomes ready.
 186          */
 187         reg = rt73usb_bbp_check(rt2x00dev);
 188         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
 189                 goto exit_fail;
 190
 191         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 192         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 193
 194         return;
 195
 196 exit_fail:
 197         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 198
 199         ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 200         *value = 0xff;
 201 }
 202
 203 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 204                              const unsigned int word, const u32 value)
 205 {
 206         u32 reg;
 207         unsigned int i;
 208
 209         if (!word)
 210                 return;
 211
 212         mutex_lock(&rt2x00dev->usb_cache_mutex);
 213
 214         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 215                 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
 216                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 217                         goto rf_write;
 218                 udelay(REGISTER_BUSY_DELAY);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 222         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 223         return;
 224
 225 rf_write:
 226         reg = 0;
 227         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 228
 229         /*
 230          * RF5225 and RF2527 contain 21 bits per RF register value,
 231          * all others contain 20 bits.
 232          */
 233         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 234                            20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 235                                  rt2x00_rf(&rt2x00dev->chip, RF2527)));
 236         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 237         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 238
 239         rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 240         rt2x00_rf_write(rt2x00dev, word, value);
 241         mutex_unlock(&rt2x00dev->usb_cache_mutex);
 242 }
 243
 244 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 245 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 246
 247 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
 248                              const unsigned int word, u32 *data)
 249 {
 250         rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
 251 }
 252
 253 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
 254                               const unsigned int word, u32 data)
 255 {
 256         rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
 257 }
 258
 259 static const struct rt2x00debug rt73usb_rt2x00debug = {
 260         .owner  = THIS_MODULE,
 261         .csr    = {
 262                 .read           = rt73usb_read_csr,
 263                 .write          = rt73usb_write_csr,
 264                 .word_size      = sizeof(u32),
 265                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 266         },
 267         .eeprom = {
 268                 .read           = rt2x00_eeprom_read,
 269                 .write          = rt2x00_eeprom_write,
 270                 .word_size      = sizeof(u16),
 271                 .word_count     = EEPROM_SIZE / sizeof(u16),
 272         },
 273         .bbp    = {
 274                 .read           = rt73usb_bbp_read,
 275                 .write          = rt73usb_bbp_write,
 276                 .word_size      = sizeof(u8),
 277                 .word_count     = BBP_SIZE / sizeof(u8),
 278         },
 279         .rf     = {
 280                 .read           = rt2x00_rf_read,
 281                 .write          = rt73usb_rf_write,
 282                 .word_size      = sizeof(u32),
 283                 .word_count     = RF_SIZE / sizeof(u32),
 284         },
 285 };
 286 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 287
 288 #ifdef CONFIG_RT73USB_LEDS
 289 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 290                                    enum led_brightness brightness)
 291 {
 292         struct rt2x00_led *led =
 293            container_of(led_cdev, struct rt2x00_led, led_dev);
 294         unsigned int enabled = brightness != LED_OFF;
 295         unsigned int a_mode =
 296             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 297         unsigned int bg_mode =
 298             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 299
 300         if (led->type == LED_TYPE_RADIO) {
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_RADIO_STATUS, enabled);
 303
 304                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 305                                             0, led->rt2x00dev->led_mcu_reg,
 306                                             REGISTER_TIMEOUT);
 307         } else if (led->type == LED_TYPE_ASSOC) {
 308                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 309                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 310                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 311                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 312
 313                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 314                                             0, led->rt2x00dev->led_mcu_reg,
 315                                             REGISTER_TIMEOUT);
 316         } else if (led->type == LED_TYPE_QUALITY) {
 317                 /*
 318                  * The brightness is divided into 6 levels (0 - 5),
 319                  * this means we need to convert the brightness
 320                  * argument into the matching level within that range.
 321                  */
 322                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 323                                             brightness / (LED_FULL / 6),
 324                                             led->rt2x00dev->led_mcu_reg,
 325                                             REGISTER_TIMEOUT);
 326         }
 327 }
 328
 329 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 330                              unsigned long *delay_on,
 331                              unsigned long *delay_off)
 332 {
 333         struct rt2x00_led *led =
 334             container_of(led_cdev, struct rt2x00_led, led_dev);
 335         u32 reg;
 336
 337         rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 338         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 339         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 340         rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 341
 342         return 0;
 343 }
 344 #endif /* CONFIG_RT73USB_LEDS */
 345
 346 /*
 347  * Configuration handlers.
 348  */
 349 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 350                                   const unsigned int filter_flags)
 351 {
 352         u32 reg;
 353
 354         /*
 355          * Start configuration steps.
 356          * Note that the version error will always be dropped
 357          * and broadcast frames will always be accepted since
 358          * there is no filter for it at this time.
 359          */
 360         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 361         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 362                            !(filter_flags & FIF_FCSFAIL));
 363         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 364                            !(filter_flags & FIF_PLCPFAIL));
 365         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 366                            !(filter_flags & FIF_CONTROL));
 367         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 368                            !(filter_flags & FIF_PROMISC_IN_BSS));
 369         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 370                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 371                            !rt2x00dev->intf_ap_count);
 372         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 373         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 374                            !(filter_flags & FIF_ALLMULTI));
 375         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 376         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 377                            !(filter_flags & FIF_CONTROL));
 378         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 379 }
 380
 381 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 382                                 struct rt2x00_intf *intf,
 383                                 struct rt2x00intf_conf *conf,
 384                                 const unsigned int flags)
 385 {
 386         unsigned int beacon_base;
 387         u32 reg;
 388
 389         if (flags & CONFIG_UPDATE_TYPE) {
 390                 /*
 391                  * Clear current synchronisation setup.
 392                  * For the Beacon base registers we only need to clear
 393                  * the first byte since that byte contains the VALID and OWNER
 394                  * bits which (when set to 0) will invalidate the entire beacon.
 395                  */
 396                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 397                 rt73usb_register_write(rt2x00dev, beacon_base, 0);
 398
 399                 /*
 400                  * Enable synchronisation.
 401                  */
 402                 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 403                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 404                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 405                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 406                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 407         }
 408
 409         if (flags & CONFIG_UPDATE_MAC) {
 410                 reg = le32_to_cpu(conf->mac[1]);
 411                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 412                 conf->mac[1] = cpu_to_le32(reg);
 413
 414                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 415                                             conf->mac, sizeof(conf->mac));
 416         }
 417
 418         if (flags & CONFIG_UPDATE_BSSID) {
 419                 reg = le32_to_cpu(conf->bssid[1]);
 420                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 421                 conf->bssid[1] = cpu_to_le32(reg);
 422
 423                 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 424                                             conf->bssid, sizeof(conf->bssid));
 425         }
 426 }
 427
 428 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 429                                struct rt2x00lib_erp *erp)
 430 {
 431         u32 reg;
 432
 433         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 434         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 435         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 436
 437         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 438         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 439                            !!erp->short_preamble);
 440         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 441 }
 442
 443 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
 444                                    const int basic_rate_mask)
 445 {
 446         rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 447 }
 448
 449 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 450                                    struct rf_channel *rf, const int txpower)
 451 {
 452         u8 r3;
 453         u8 r94;
 454         u8 smart;
 455
 456         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 457         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 458
 459         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 460                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 461
 462         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 463         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 464         rt73usb_bbp_write(rt2x00dev, 3, r3);
 465
 466         r94 = 6;
 467         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 468                 r94 += txpower - MAX_TXPOWER;
 469         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 470                 r94 += txpower;
 471         rt73usb_bbp_write(rt2x00dev, 94, r94);
 472
 473         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 474         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 475         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 476         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 477
 478         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 479         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 480         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 481         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 482
 483         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 484         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 485         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 486         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 487
 488         udelay(10);
 489 }
 490
 491 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 492                                    const int txpower)
 493 {
 494         struct rf_channel rf;
 495
 496         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 497         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 498         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 499         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 500
 501         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 502 }
 503
 504 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 505                                       struct antenna_setup *ant)
 506 {
 507         u8 r3;
 508         u8 r4;
 509         u8 r77;
 510         u8 temp;
 511
 512         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 513         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 514         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 515
 516         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 517
 518         /*
 519          * Configure the RX antenna.
 520          */
 521         switch (ant->rx) {
 522         case ANTENNA_HW_DIVERSITY:
 523                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 524                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 525                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 526                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 527                 break;
 528         case ANTENNA_A:
 529                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 530                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 531                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 532                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 533                 else
 534                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 535                 break;
 536         case ANTENNA_B:
 537         default:
 538                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 539                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 540                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 541                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 542                 else
 543                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 544                 break;
 545         }
 546
 547         rt73usb_bbp_write(rt2x00dev, 77, r77);
 548         rt73usb_bbp_write(rt2x00dev, 3, r3);
 549         rt73usb_bbp_write(rt2x00dev, 4, r4);
 550 }
 551
 552 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 553                                       struct antenna_setup *ant)
 554 {
 555         u8 r3;
 556         u8 r4;
 557         u8 r77;
 558
 559         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 560         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 561         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 562
 563         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 564         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 565                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 566
 567         /*
 568          * Configure the RX antenna.
 569          */
 570         switch (ant->rx) {
 571         case ANTENNA_HW_DIVERSITY:
 572                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 573                 break;
 574         case ANTENNA_A:
 575                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 576                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 577                 break;
 578         case ANTENNA_B:
 579         default:
 580                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 581                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 582                 break;
 583         }
 584
 585         rt73usb_bbp_write(rt2x00dev, 77, r77);
 586         rt73usb_bbp_write(rt2x00dev, 3, r3);
 587         rt73usb_bbp_write(rt2x00dev, 4, r4);
 588 }
 589
 590 struct antenna_sel {
 591         u8 word;
 592         /*
 593          * value[0] -> non-LNA
 594          * value[1] -> LNA
 595          */
 596         u8 value[2];
 597 };
 598
 599 static const struct antenna_sel antenna_sel_a[] = {
 600         { 96,  { 0x58, 0x78 } },
 601         { 104, { 0x38, 0x48 } },
 602         { 75,  { 0xfe, 0x80 } },
 603         { 86,  { 0xfe, 0x80 } },
 604         { 88,  { 0xfe, 0x80 } },
 605         { 35,  { 0x60, 0x60 } },
 606         { 97,  { 0x58, 0x58 } },
 607         { 98,  { 0x58, 0x58 } },
 608 };
 609
 610 static const struct antenna_sel antenna_sel_bg[] = {
 611         { 96,  { 0x48, 0x68 } },
 612         { 104, { 0x2c, 0x3c } },
 613         { 75,  { 0xfe, 0x80 } },
 614         { 86,  { 0xfe, 0x80 } },
 615         { 88,  { 0xfe, 0x80 } },
 616         { 35,  { 0x50, 0x50 } },
 617         { 97,  { 0x48, 0x48 } },
 618         { 98,  { 0x48, 0x48 } },
 619 };
 620
 621 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
 622                                    struct antenna_setup *ant)
 623 {
 624         const struct antenna_sel *sel;
 625         unsigned int lna;
 626         unsigned int i;
 627         u32 reg;
 628
 629         /*
 630          * We should never come here because rt2x00lib is supposed
 631          * to catch this and send us the correct antenna explicitely.
 632          */
 633         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 634                ant->tx == ANTENNA_SW_DIVERSITY);
 635
 636         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 637                 sel = antenna_sel_a;
 638                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 639         } else {
 640                 sel = antenna_sel_bg;
 641                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 642         }
 643
 644         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 645                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 646
 647         rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 648
 649         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 650                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 651         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 652                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 653
 654         rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
 655
 656         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
 657             rt2x00_rf(&rt2x00dev->chip, RF5225))
 658                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 659         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
 660                  rt2x00_rf(&rt2x00dev->chip, RF2527))
 661                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 662 }
 663
 664 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
 665                                     struct rt2x00lib_conf *libconf)
 666 {
 667         u32 reg;
 668
 669         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 670         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 671         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
 672
 673         rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 674         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 675         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 676         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 677         rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
 678
 679         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 680         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 681         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 682
 683         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 684         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 685         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 686
 687         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 688         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 689                            libconf->conf->beacon_int * 16);
 690         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 691 }
 692
 693 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 694                            struct rt2x00lib_conf *libconf,
 695                            const unsigned int flags)
 696 {
 697         if (flags & CONFIG_UPDATE_PHYMODE)
 698                 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
 699         if (flags & CONFIG_UPDATE_CHANNEL)
 700                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 701                                        libconf->conf->power_level);
 702         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 703                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 704         if (flags & CONFIG_UPDATE_ANTENNA)
 705                 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
 706         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 707                 rt73usb_config_duration(rt2x00dev, libconf);
 708 }
 709
 710 /*
 711  * Link tuning
 712  */
 713 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 714                                struct link_qual *qual)
 715 {
 716         u32 reg;
 717
 718         /*
 719          * Update FCS error count from register.
 720          */
 721         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
 722         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 723
 724         /*
 725          * Update False CCA count from register.
 726          */
 727         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
 728         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 729 }
 730
 731 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
 732 {
 733         rt73usb_bbp_write(rt2x00dev, 17, 0x20);
 734         rt2x00dev->link.vgc_level = 0x20;
 735 }
 736
 737 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
 738 {
 739         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 740         u8 r17;
 741         u8 up_bound;
 742         u8 low_bound;
 743
 744         rt73usb_bbp_read(rt2x00dev, 17, &r17);
 745
 746         /*
 747          * Determine r17 bounds.
 748          */
 749         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 750                 low_bound = 0x28;
 751                 up_bound = 0x48;
 752
 753                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 754                         low_bound += 0x10;
 755                         up_bound += 0x10;
 756                 }
 757         } else {
 758                 if (rssi > -82) {
 759                         low_bound = 0x1c;
 760                         up_bound = 0x40;
 761                 } else if (rssi > -84) {
 762                         low_bound = 0x1c;
 763                         up_bound = 0x20;
 764                 } else {
 765                         low_bound = 0x1c;
 766                         up_bound = 0x1c;
 767                 }
 768
 769                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 770                         low_bound += 0x14;
 771                         up_bound += 0x10;
 772                 }
 773         }
 774
 775         /*
 776          * If we are not associated, we should go straight to the
 777          * dynamic CCA tuning.
 778          */
 779         if (!rt2x00dev->intf_associated)
 780                 goto dynamic_cca_tune;
 781
 782         /*
 783          * Special big-R17 for very short distance
 784          */
 785         if (rssi > -35) {
 786                 if (r17 != 0x60)
 787                         rt73usb_bbp_write(rt2x00dev, 17, 0x60);
 788                 return;
 789         }
 790
 791         /*
 792          * Special big-R17 for short distance
 793          */
 794         if (rssi >= -58) {
 795                 if (r17 != up_bound)
 796                         rt73usb_bbp_write(rt2x00dev, 17, up_bound);
 797                 return;
 798         }
 799
 800         /*
 801          * Special big-R17 for middle-short distance
 802          */
 803         if (rssi >= -66) {
 804                 low_bound += 0x10;
 805                 if (r17 != low_bound)
 806                         rt73usb_bbp_write(rt2x00dev, 17, low_bound);
 807                 return;
 808         }
 809
 810         /*
 811          * Special mid-R17 for middle distance
 812          */
 813         if (rssi >= -74) {
 814                 if (r17 != (low_bound + 0x10))
 815                         rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
 816                 return;
 817         }
 818
 819         /*
 820          * Special case: Change up_bound based on the rssi.
 821          * Lower up_bound when rssi is weaker then -74 dBm.
 822          */
 823         up_bound -= 2 * (-74 - rssi);
 824         if (low_bound > up_bound)
 825                 up_bound = low_bound;
 826
 827         if (r17 > up_bound) {
 828                 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
 829                 return;
 830         }
 831
 832 dynamic_cca_tune:
 833
 834         /*
 835          * r17 does not yet exceed upper limit, continue and base
 836          * the r17 tuning on the false CCA count.
 837          */
 838         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 839                 r17 += 4;
 840                 if (r17 > up_bound)
 841                         r17 = up_bound;
 842                 rt73usb_bbp_write(rt2x00dev, 17, r17);
 843         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 844                 r17 -= 4;
 845                 if (r17 < low_bound)
 846                         r17 = low_bound;
 847                 rt73usb_bbp_write(rt2x00dev, 17, r17);
 848         }
 849 }
 850
 851 /*
 852  * Firmware functions
 853  */
 854 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 855 {
 856         return FIRMWARE_RT2571;
 857 }
 858
 859 static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
 860 {
 861         u16 crc;
 862
 863         /*
 864          * Use the crc itu-t algorithm.
 865          * The last 2 bytes in the firmware array are the crc checksum itself,
 866          * this means that we should never pass those 2 bytes to the crc
 867          * algorithm.
 868          */
 869         crc = crc_itu_t(0, data, len - 2);
 870         crc = crc_itu_t_byte(crc, 0);
 871         crc = crc_itu_t_byte(crc, 0);
 872
 873         return crc;
 874 }
 875
 876 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 877                                  const size_t len)
 878 {
 879         unsigned int i;
 880         int status;
 881         u32 reg;
 882         char *ptr = data;
 883         char *cache;
 884         int buflen;
 885         int timeout;
 886
 887         /*
 888          * Wait for stable hardware.
 889          */
 890         for (i = 0; i < 100; i++) {
 891                 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
 892                 if (reg)
 893                         break;
 894                 msleep(1);
 895         }
 896
 897         if (!reg) {
 898                 ERROR(rt2x00dev, "Unstable hardware.\n");
 899                 return -EBUSY;
 900         }
 901
 902         /*
 903          * Write firmware to device.
 904          * We setup a seperate cache for this action,
 905          * since we are going to write larger chunks of data
 906          * then normally used cache size.
 907          */
 908         cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
 909         if (!cache) {
 910                 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
 911                 return -ENOMEM;
 912         }
 913
 914         for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
 915                 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
 916                 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
 917
 918                 memcpy(cache, ptr, buflen);
 919
 920                 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
 921                                          USB_VENDOR_REQUEST_OUT,
 922                                          FIRMWARE_IMAGE_BASE + i, 0,
 923                                          cache, buflen, timeout);
 924
 925                 ptr += buflen;
 926         }
 927
 928         kfree(cache);
 929
 930         /*
 931          * Send firmware request to device to load firmware,
 932          * we need to specify a long timeout time.
 933          */
 934         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
 935                                              0, USB_MODE_FIRMWARE,
 936                                              REGISTER_TIMEOUT_FIRMWARE);
 937         if (status < 0) {
 938                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
 939                 return status;
 940         }
 941
 942         return 0;
 943 }
 944
 945 /*
 946  * Initialization functions.
 947  */
 948 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
 949 {
 950         u32 reg;
 951
 952         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 953         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
 954         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
 955         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
 956         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 957
 958         rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
 959         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
 960         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
 961         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
 962         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
 963         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
 964         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
 965         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
 966         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
 967         rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
 968
 969         /*
 970          * CCK TXD BBP registers
 971          */
 972         rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
 973         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
 974         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
 975         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
 976         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
 977         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
 978         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
 979         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
 980         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
 981         rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
 982
 983         /*
 984          * OFDM TXD BBP registers
 985          */
 986         rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
 987         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
 988         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
 989         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
 990         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
 991         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
 992         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
 993         rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
 994
 995         rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
 996         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
 997         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
 998         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
 999         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1000         rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1001
1002         rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1003         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1004         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1005         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1006         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1007         rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1008
1009         rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1010
1011         rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1012         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1013         rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1014
1015         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1016
1017         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1018                 return -EBUSY;
1019
1020         rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1021
1022         /*
1023          * Invalidate all Shared Keys (SEC_CSR0),
1024          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1025          */
1026         rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1027         rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1028         rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1029
1030         reg = 0x000023b0;
1031         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1032             rt2x00_rf(&rt2x00dev->chip, RF2527))
1033                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1034         rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1035
1036         rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1037         rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1038         rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1039
1040         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1041         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1042         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1043         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1044
1045         rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1046         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1047         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1048         rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1049
1050         rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1051         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1052         rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1053
1054         /*
1055          * Clear all beacons
1056          * For the Beacon base registers we only need to clear
1057          * the first byte since that byte contains the VALID and OWNER
1058          * bits which (when set to 0) will invalidate the entire beacon.
1059          */
1060         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1061         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1062         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1063         rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1064
1065         /*
1066          * We must clear the error counters.
1067          * These registers are cleared on read,
1068          * so we may pass a useless variable to store the value.
1069          */
1070         rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1071         rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1072         rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1073
1074         /*
1075          * Reset MAC and BBP registers.
1076          */
1077         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1078         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1079         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1080         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1081
1082         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1083         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1084         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1085         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1086
1087         rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1088         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1089         rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1090
1091         return 0;
1092 }
1093
1094 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1095 {
1096         unsigned int i;
1097         u16 eeprom;
1098         u8 reg_id;
1099         u8 value;
1100
1101         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1102                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1103                 if ((value != 0xff) && (value != 0x00))
1104                         goto continue_csr_init;
1105                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1106                 udelay(REGISTER_BUSY_DELAY);
1107         }
1108
1109         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1110         return -EACCES;
1111
1112 continue_csr_init:
1113         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1114         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1115         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1116         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1117         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1118         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1119         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1120         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1121         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1122         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1123         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1124         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1125         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1126         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1127         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1128         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1129         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1130         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1131         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1132         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1133         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1134         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1135         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1136         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1137         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1138
1139         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1140                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1141
1142                 if (eeprom != 0xffff && eeprom != 0x0000) {
1143                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1144                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1145                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1146                 }
1147         }
1148
1149         return 0;
1150 }
1151
1152 /*
1153  * Device state switch handlers.
1154  */
1155 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1156                               enum dev_state state)
1157 {
1158         u32 reg;
1159
1160         rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1161         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1162                            state == STATE_RADIO_RX_OFF);
1163         rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1164 }
1165
1166 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1167 {
1168         /*
1169          * Initialize all registers.
1170          */
1171         if (rt73usb_init_registers(rt2x00dev) ||
1172             rt73usb_init_bbp(rt2x00dev)) {
1173                 ERROR(rt2x00dev, "Register initialization failed.\n");
1174                 return -EIO;
1175         }
1176
1177         return 0;
1178 }
1179
1180 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1181 {
1182         rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1183
1184         /*
1185          * Disable synchronisation.
1186          */
1187         rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1188
1189         rt2x00usb_disable_radio(rt2x00dev);
1190 }
1191
1192 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1193 {
1194         u32 reg;
1195         unsigned int i;
1196         char put_to_sleep;
1197         char current_state;
1198
1199         put_to_sleep = (state != STATE_AWAKE);
1200
1201         rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1202         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1203         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1204         rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1205
1206         /*
1207          * Device is not guaranteed to be in the requested state yet.
1208          * We must wait until the register indicates that the
1209          * device has entered the correct state.
1210          */
1211         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1212                 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1213                 current_state =
1214                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1215                 if (current_state == !put_to_sleep)
1216                         return 0;
1217                 msleep(10);
1218         }
1219
1220         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1221                "current device state %d.\n", !put_to_sleep, current_state);
1222
1223         return -EBUSY;
1224 }
1225
1226 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1227                                     enum dev_state state)
1228 {
1229         int retval = 0;
1230
1231         switch (state) {
1232         case STATE_RADIO_ON:
1233                 retval = rt73usb_enable_radio(rt2x00dev);
1234                 break;
1235         case STATE_RADIO_OFF:
1236                 rt73usb_disable_radio(rt2x00dev);
1237                 break;
1238         case STATE_RADIO_RX_ON:
1239         case STATE_RADIO_RX_ON_LINK:
1240                 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1241                 break;
1242         case STATE_RADIO_RX_OFF:
1243         case STATE_RADIO_RX_OFF_LINK:
1244                 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1245                 break;
1246         case STATE_DEEP_SLEEP:
1247         case STATE_SLEEP:
1248         case STATE_STANDBY:
1249         case STATE_AWAKE:
1250                 retval = rt73usb_set_state(rt2x00dev, state);
1251                 break;
1252         default:
1253                 retval = -ENOTSUPP;
1254                 break;
1255         }
1256
1257         return retval;
1258 }
1259
1260 /*
1261  * TX descriptor initialization
1262  */
1263 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1264                                     struct sk_buff *skb,
1265                                     struct txentry_desc *txdesc,
1266                                     struct ieee80211_tx_control *control)
1267 {
1268         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1269         __le32 *txd = skbdesc->desc;
1270         u32 word;
1271
1272         /*
1273          * Start writing the descriptor words.
1274          */
1275         rt2x00_desc_read(txd, 1, &word);
1276         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1277         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1278         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1279         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1280         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1281         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1282         rt2x00_desc_write(txd, 1, word);
1283
1284         rt2x00_desc_read(txd, 2, &word);
1285         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1286         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1287         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1288         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1289         rt2x00_desc_write(txd, 2, word);
1290
1291         rt2x00_desc_read(txd, 5, &word);
1292         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1293                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1294         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1295         rt2x00_desc_write(txd, 5, word);
1296
1297         rt2x00_desc_read(txd, 0, &word);
1298         rt2x00_set_field32(&word, TXD_W0_BURST,
1299                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1300         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1301         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1302                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1303         rt2x00_set_field32(&word, TXD_W0_ACK,
1304                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1305         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1306                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1307         rt2x00_set_field32(&word, TXD_W0_OFDM,
1308                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1309         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1310         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1311                            !!(control->flags &
1312                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1313         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1314         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1315         rt2x00_set_field32(&word, TXD_W0_BURST2,
1316                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1317         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1318         rt2x00_desc_write(txd, 0, word);
1319 }
1320
1321 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1322                                    struct sk_buff *skb)
1323 {
1324         int length;
1325
1326         /*
1327          * The length _must_ be a multiple of 4,
1328          * but it must _not_ be a multiple of the USB packet size.
1329          */
1330         length = roundup(skb->len, 4);
1331         length += (4 * !(length % rt2x00dev->usb_maxpacket));
1332
1333         return length;
1334 }
1335
1336 /*
1337  * TX data initialization
1338  */
1339 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1340                                   const unsigned int queue)
1341 {
1342         u32 reg;
1343
1344         if (queue != RT2X00_BCN_QUEUE_BEACON)
1345                 return;
1346
1347         /*
1348          * For Wi-Fi faily generated beacons between participating stations.
1349          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1350          */
1351         rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1352
1353         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1354         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1355                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1356                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1357                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1358                 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1359         }
1360 }
1361
1362 /*
1363  * RX control handlers
1364  */
1365 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1366 {
1367         u16 eeprom;
1368         u8 offset;
1369         u8 lna;
1370
1371         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1372         switch (lna) {
1373         case 3:
1374                 offset = 90;
1375                 break;
1376         case 2:
1377                 offset = 74;
1378                 break;
1379         case 1:
1380                 offset = 64;
1381                 break;
1382         default:
1383                 return 0;
1384         }
1385
1386         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1387                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1388                         if (lna == 3 || lna == 2)
1389                                 offset += 10;
1390                 } else {
1391                         if (lna == 3)
1392                                 offset += 6;
1393                         else if (lna == 2)
1394                                 offset += 8;
1395                 }
1396
1397                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1398                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1399         } else {
1400                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1401                         offset += 14;
1402
1403                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1404                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1405         }
1406
1407         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1408 }
1409
1410 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1411                                 struct rxdone_entry_desc *rxdesc)
1412 {
1413         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1414         __le32 *rxd = (__le32 *)entry->skb->data;
1415         unsigned int offset = entry->queue->desc_size + 2;
1416         u32 word0;
1417         u32 word1;
1418
1419         /*
1420          * Copy descriptor to the available headroom inside the skbuffer.
1421          */
1422         skb_push(entry->skb, offset);
1423         memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1424         rxd = (__le32 *)entry->skb->data;
1425
1426         /*
1427          * The descriptor is now aligned to 4 bytes and thus it is
1428          * now safe to read it on all architectures.
1429          */
1430         rt2x00_desc_read(rxd, 0, &word0);
1431         rt2x00_desc_read(rxd, 1, &word1);
1432
1433         rxdesc->flags = 0;
1434         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1435                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1436
1437         /*
1438          * Obtain the status about this packet.
1439          * When frame was received with an OFDM bitrate,
1440          * the signal is the PLCP value. If it was received with
1441          * a CCK bitrate the signal is the rate in 100kbit/s.
1442          */
1443         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1444         rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1445         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1446
1447         rxdesc->dev_flags = 0;
1448         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1449                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1450         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1451                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1452
1453         /*
1454          * Adjust the skb memory window to the frame boundaries.
1455          */
1456         skb_pull(entry->skb, offset + entry->queue->desc_size);
1457         skb_trim(entry->skb, rxdesc->size);
1458
1459         /*
1460          * Set descriptor and data pointer.
1461          */
1462         skbdesc->data = entry->skb->data;
1463         skbdesc->data_len = rxdesc->size;
1464         skbdesc->desc = rxd;
1465         skbdesc->desc_len = entry->queue->desc_size;
1466 }
1467
1468 /*
1469  * Device probe functions.
1470  */
1471 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1472 {
1473         u16 word;
1474         u8 *mac;
1475         s8 value;
1476
1477         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1478
1479         /*
1480          * Start validation of the data that has been read.
1481          */
1482         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1483         if (!is_valid_ether_addr(mac)) {
1484                 DECLARE_MAC_BUF(macbuf);
1485
1486                 random_ether_addr(mac);
1487                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1488         }
1489
1490         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1491         if (word == 0xffff) {
1492                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1493                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1494                                    ANTENNA_B);
1495                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1496                                    ANTENNA_B);
1497                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1498                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1499                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1500                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1501                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1502                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1503         }
1504
1505         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1506         if (word == 0xffff) {
1507                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1508                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1509                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1510         }
1511
1512         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1513         if (word == 0xffff) {
1514                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1515                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1516                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1517                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1518                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1519                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1520                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1521                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1522                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1523                                    LED_MODE_DEFAULT);
1524                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1525                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1526         }
1527
1528         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1529         if (word == 0xffff) {
1530                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1531                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1532                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1533                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1534         }
1535
1536         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1537         if (word == 0xffff) {
1538                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1539                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1540                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1541                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1542         } else {
1543                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1544                 if (value < -10 || value > 10)
1545                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1546                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1547                 if (value < -10 || value > 10)
1548                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1549                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1550         }
1551
1552         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1553         if (word == 0xffff) {
1554                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1555                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1556                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1557                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1558         } else {
1559                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1560                 if (value < -10 || value > 10)
1561                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1562                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1563                 if (value < -10 || value > 10)
1564                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1565                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1566         }
1567
1568         return 0;
1569 }
1570
1571 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1572 {
1573         u32 reg;
1574         u16 value;
1575         u16 eeprom;
1576
1577         /*
1578          * Read EEPROM word for configuration.
1579          */
1580         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1581
1582         /*
1583          * Identify RF chipset.
1584          */
1585         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1586         rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1587         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1588
1589         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1590                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1591                 return -ENODEV;
1592         }
1593
1594         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1595             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1596             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1597             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1598                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1599                 return -ENODEV;
1600         }
1601
1602         /*
1603          * Identify default antenna configuration.
1604          */
1605         rt2x00dev->default_ant.tx =
1606             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1607         rt2x00dev->default_ant.rx =
1608             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1609
1610         /*
1611          * Read the Frame type.
1612          */
1613         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1614                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1615
1616         /*
1617          * Read frequency offset.
1618          */
1619         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1620         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1621
1622         /*
1623          * Read external LNA informations.
1624          */
1625         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1626
1627         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1628                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1629                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1630         }
1631
1632         /*
1633          * Store led settings, for correct led behaviour.
1634          */
1635 #ifdef CONFIG_RT73USB_LEDS
1636         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1637
1638         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1639         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1640         rt2x00dev->led_radio.led_dev.brightness_set =
1641             rt73usb_brightness_set;
1642         rt2x00dev->led_radio.led_dev.blink_set =
1643             rt73usb_blink_set;
1644         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1645
1646         rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
1647         rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
1648         rt2x00dev->led_assoc.led_dev.brightness_set =
1649             rt73usb_brightness_set;
1650         rt2x00dev->led_assoc.led_dev.blink_set =
1651             rt73usb_blink_set;
1652         rt2x00dev->led_assoc.flags = LED_INITIALIZED;
1653
1654         if (value == LED_MODE_SIGNAL_STRENGTH) {
1655                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1656                 rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
1657                 rt2x00dev->led_qual.led_dev.brightness_set =
1658                     rt73usb_brightness_set;
1659                 rt2x00dev->led_qual.led_dev.blink_set =
1660                     rt73usb_blink_set;
1661                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1662         }
1663
1664         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1665         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1666                            rt2x00_get_field16(eeprom,
1667                                               EEPROM_LED_POLARITY_GPIO_0));
1668         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1669                            rt2x00_get_field16(eeprom,
1670                                               EEPROM_LED_POLARITY_GPIO_1));
1671         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1672                            rt2x00_get_field16(eeprom,
1673                                               EEPROM_LED_POLARITY_GPIO_2));
1674         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1675                            rt2x00_get_field16(eeprom,
1676                                               EEPROM_LED_POLARITY_GPIO_3));
1677         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1678                            rt2x00_get_field16(eeprom,
1679                                               EEPROM_LED_POLARITY_GPIO_4));
1680         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1681                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1682         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1683                            rt2x00_get_field16(eeprom,
1684                                               EEPROM_LED_POLARITY_RDY_G));
1685         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1686                            rt2x00_get_field16(eeprom,
1687                                               EEPROM_LED_POLARITY_RDY_A));
1688 #endif /* CONFIG_RT73USB_LEDS */
1689
1690         return 0;
1691 }
1692
1693 /*
1694  * RF value list for RF2528
1695  * Supports: 2.4 GHz
1696  */
1697 static const struct rf_channel rf_vals_bg_2528[] = {
1698         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1699         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1700         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1701         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1702         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1703         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1704         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1705         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1706         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1707         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1708         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1709         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1710         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1711         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1712 };
1713
1714 /*
1715  * RF value list for RF5226
1716  * Supports: 2.4 GHz & 5.2 GHz
1717  */
1718 static const struct rf_channel rf_vals_5226[] = {
1719         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1720         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1721         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1722         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1723         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1724         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1725         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1726         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1727         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1728         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1729         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1730         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1731         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1732         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1733
1734         /* 802.11 UNI / HyperLan 2 */
1735         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1736         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1737         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1738         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1739         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1740         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1741         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1742         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1743
1744         /* 802.11 HyperLan 2 */
1745         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1746         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1747         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1748         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1749         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1750         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1751         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1752         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1753         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1754         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1755
1756         /* 802.11 UNII */
1757         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1758         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1759         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1760         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1761         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1762         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1763
1764         /* MMAC(Japan)J52 ch 34,38,42,46 */
1765         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1766         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1767         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1768         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1769 };
1770
1771 /*
1772  * RF value list for RF5225 & RF2527
1773  * Supports: 2.4 GHz & 5.2 GHz
1774  */
1775 static const struct rf_channel rf_vals_5225_2527[] = {
1776         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1777         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1778         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1779         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1780         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1781         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1782         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1783         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1784         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1785         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1786         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1787         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1788         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1789         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1790
1791         /* 802.11 UNI / HyperLan 2 */
1792         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1793         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1794         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1795         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1796         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1797         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1798         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1799         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1800
1801         /* 802.11 HyperLan 2 */
1802         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1803         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1804         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1805         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1806         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1807         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1808         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1809         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1810         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1811         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1812
1813         /* 802.11 UNII */
1814         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1815         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1816         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1817         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1818         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1819         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1820
1821         /* MMAC(Japan)J52 ch 34,38,42,46 */
1822         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1823         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1824         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1825         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1826 };
1827
1828
1829 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1830 {
1831         struct hw_mode_spec *spec = &rt2x00dev->spec;
1832         u8 *txpower;
1833         unsigned int i;
1834
1835         /*
1836          * Initialize all hw fields.
1837          */
1838         rt2x00dev->hw->flags =
1839             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1840             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1841         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1842         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1843         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1844         rt2x00dev->hw->queues = 4;
1845
1846         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1847         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1848                                 rt2x00_eeprom_addr(rt2x00dev,
1849                                                    EEPROM_MAC_ADDR_0));
1850
1851         /*
1852          * Convert tx_power array in eeprom.
1853          */
1854         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1855         for (i = 0; i < 14; i++)
1856                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1857
1858         /*
1859          * Initialize hw_mode information.
1860          */
1861         spec->supported_bands = SUPPORT_BAND_2GHZ;
1862         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1863         spec->tx_power_a = NULL;
1864         spec->tx_power_bg = txpower;
1865         spec->tx_power_default = DEFAULT_TXPOWER;
1866
1867         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1868                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1869                 spec->channels = rf_vals_bg_2528;
1870         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1871                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1872                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1873                 spec->channels = rf_vals_5226;
1874         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1875                 spec->num_channels = 14;
1876                 spec->channels = rf_vals_5225_2527;
1877         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1878                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1879                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1880                 spec->channels = rf_vals_5225_2527;
1881         }
1882
1883         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1884             rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1885                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1886                 for (i = 0; i < 14; i++)
1887                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1888
1889                 spec->tx_power_a = txpower;
1890         }
1891 }
1892
1893 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1894 {
1895         int retval;
1896
1897         /*
1898          * Allocate eeprom data.
1899          */
1900         retval = rt73usb_validate_eeprom(rt2x00dev);
1901         if (retval)
1902                 return retval;
1903
1904         retval = rt73usb_init_eeprom(rt2x00dev);
1905         if (retval)
1906                 return retval;
1907
1908         /*
1909          * Initialize hw specifications.
1910          */
1911         rt73usb_probe_hw_mode(rt2x00dev);
1912
1913         /*
1914          * This device requires firmware.
1915          */
1916         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1917         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
1918
1919         /*
1920          * Set the rssi offset.
1921          */
1922         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1923
1924         return 0;
1925 }
1926
1927 /*
1928  * IEEE80211 stack callback functions.
1929  */
1930 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1931                                    u32 short_retry, u32 long_retry)
1932 {
1933         struct rt2x00_dev *rt2x00dev = hw->priv;
1934         u32 reg;
1935
1936         rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1937         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1938         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1939         rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1940
1941         return 0;
1942 }
1943
1944 #if 0
1945 /*
1946  * Mac80211 demands get_tsf must be atomic.
1947  * This is not possible for rt73usb since all register access
1948  * functions require sleeping. Untill mac80211 no longer needs
1949  * get_tsf to be atomic, this function should be disabled.
1950  */
1951 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1952 {
1953         struct rt2x00_dev *rt2x00dev = hw->priv;
1954         u64 tsf;
1955         u32 reg;
1956
1957         rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1958         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1959         rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1960         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1961
1962         return tsf;
1963 }
1964 #else
1965 #define rt73usb_get_tsf NULL
1966 #endif
1967
1968 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1969                                  struct ieee80211_tx_control *control)
1970 {
1971         struct rt2x00_dev *rt2x00dev = hw->priv;
1972         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1973         struct skb_frame_desc *skbdesc;
1974         unsigned int beacon_base;
1975         unsigned int timeout;
1976         u32 reg;
1977
1978         if (unlikely(!intf->beacon))
1979                 return -ENOBUFS;
1980
1981         /*
1982          * Add the descriptor in front of the skb.
1983          */
1984         skb_push(skb, intf->beacon->queue->desc_size);
1985         memset(skb->data, 0, intf->beacon->queue->desc_size);
1986
1987         /*
1988          * Fill in skb descriptor
1989          */
1990         skbdesc = get_skb_frame_desc(skb);
1991         memset(skbdesc, 0, sizeof(*skbdesc));
1992         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1993         skbdesc->data = skb->data + intf->beacon->queue->desc_size;
1994         skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
1995         skbdesc->desc = skb->data;
1996         skbdesc->desc_len = intf->beacon->queue->desc_size;
1997         skbdesc->entry = intf->beacon;
1998
1999         /*
2000          * Disable beaconing while we are reloading the beacon data,
2001          * otherwise we might be sending out invalid data.
2002          */
2003         rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
2004         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2005         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2006         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2007         rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2008
2009         /*
2010          * mac80211 doesn't provide the control->queue variable
2011          * for beacons. Set our own queue identification so
2012          * it can be used during descriptor initialization.
2013          */
2014         control->queue = RT2X00_BCN_QUEUE_BEACON;
2015         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2016
2017         /*
2018          * Write entire beacon with descriptor to register,
2019          * and kick the beacon generator.
2020          */
2021         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2022         timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2023         rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2024                                  USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2025                                  skb->data, skb->len, timeout);
2026         rt73usb_kick_tx_queue(rt2x00dev, control->queue);
2027
2028         return 0;
2029 }
2030
2031 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2032         .tx                     = rt2x00mac_tx,
2033         .start                  = rt2x00mac_start,
2034         .stop                   = rt2x00mac_stop,
2035         .add_interface          = rt2x00mac_add_interface,
2036         .remove_interface       = rt2x00mac_remove_interface,
2037         .config                 = rt2x00mac_config,
2038         .config_interface       = rt2x00mac_config_interface,
2039         .configure_filter       = rt2x00mac_configure_filter,
2040         .get_stats              = rt2x00mac_get_stats,
2041         .set_retry_limit        = rt73usb_set_retry_limit,
2042         .bss_info_changed       = rt2x00mac_bss_info_changed,
2043         .conf_tx                = rt2x00mac_conf_tx,
2044         .get_tx_stats           = rt2x00mac_get_tx_stats,
2045         .get_tsf                = rt73usb_get_tsf,
2046         .beacon_update          = rt73usb_beacon_update,
2047 };
2048
2049 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2050         .probe_hw               = rt73usb_probe_hw,
2051         .get_firmware_name      = rt73usb_get_firmware_name,
2052         .get_firmware_crc       = rt73usb_get_firmware_crc,
2053         .load_firmware          = rt73usb_load_firmware,
2054         .initialize             = rt2x00usb_initialize,
2055         .uninitialize           = rt2x00usb_uninitialize,
2056         .init_rxentry           = rt2x00usb_init_rxentry,
2057         .init_txentry           = rt2x00usb_init_txentry,
2058         .set_device_state       = rt73usb_set_device_state,
2059         .link_stats             = rt73usb_link_stats,
2060         .reset_tuner            = rt73usb_reset_tuner,
2061         .link_tuner             = rt73usb_link_tuner,
2062         .write_tx_desc          = rt73usb_write_tx_desc,
2063         .write_tx_data          = rt2x00usb_write_tx_data,
2064         .get_tx_data_len        = rt73usb_get_tx_data_len,
2065         .kick_tx_queue          = rt73usb_kick_tx_queue,
2066         .fill_rxdone            = rt73usb_fill_rxdone,
2067         .config_filter          = rt73usb_config_filter,
2068         .config_intf            = rt73usb_config_intf,
2069         .config_erp             = rt73usb_config_erp,
2070         .config                 = rt73usb_config,
2071 };
2072
2073 static const struct data_queue_desc rt73usb_queue_rx = {
2074         .entry_num              = RX_ENTRIES,
2075         .data_size              = DATA_FRAME_SIZE,
2076         .desc_size              = RXD_DESC_SIZE,
2077         .priv_size              = sizeof(struct queue_entry_priv_usb_rx),
2078 };
2079
2080 static const struct data_queue_desc rt73usb_queue_tx = {
2081         .entry_num              = TX_ENTRIES,
2082         .data_size              = DATA_FRAME_SIZE,
2083         .desc_size              = TXD_DESC_SIZE,
2084         .priv_size              = sizeof(struct queue_entry_priv_usb_tx),
2085 };
2086
2087 static const struct data_queue_desc rt73usb_queue_bcn = {
2088         .entry_num              = 4 * BEACON_ENTRIES,
2089         .data_size              = MGMT_FRAME_SIZE,
2090         .desc_size              = TXINFO_SIZE,
2091         .priv_size              = sizeof(struct queue_entry_priv_usb_tx),
2092 };
2093
2094 static const struct rt2x00_ops rt73usb_ops = {
2095         .name           = KBUILD_MODNAME,
2096         .max_sta_intf   = 1,
2097         .max_ap_intf    = 4,
2098         .eeprom_size    = EEPROM_SIZE,
2099         .rf_size        = RF_SIZE,
2100         .rx             = &rt73usb_queue_rx,
2101         .tx             = &rt73usb_queue_tx,
2102         .bcn            = &rt73usb_queue_bcn,
2103         .lib            = &rt73usb_rt2x00_ops,
2104         .hw             = &rt73usb_mac80211_ops,
2105 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2106         .debugfs        = &rt73usb_rt2x00debug,
2107 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2108 };
2109
2110 /*
2111  * rt73usb module information.
2112  */
2113 static struct usb_device_id rt73usb_device_table[] = {
2114         /* AboCom */
2115         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2116         /* Askey */
2117         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2118         /* ASUS */
2119         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2120         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2121         /* Belkin */
2122         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2123         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2124         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2125         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2126         /* Billionton */
2127         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2128         /* Buffalo */
2129         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2130         /* CNet */
2131         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2132         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2133         /* Conceptronic */
2134         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2135         /* Corega */
2136         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2137         /* D-Link */
2138         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2139         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2140         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2141         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2142         /* Gemtek */
2143         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2144         /* Gigabyte */
2145         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2146         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2147         /* Huawei-3Com */
2148         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2149         /* Hercules */
2150         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2151         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2152         /* Linksys */
2153         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2154         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2155         /* MSI */
2156         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2157         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2158         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2159         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2160         /* Ralink */
2161         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2162         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2163         /* Qcom */
2164         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2165         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2166         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2167         /* Senao */
2168         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2169         /* Sitecom */
2170         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2171         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2172         /* Surecom */
2173         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2174         /* Planex */
2175         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2176         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2177         { 0, }
2178 };
2179
2180 MODULE_AUTHOR(DRV_PROJECT);
2181 MODULE_VERSION(DRV_VERSION);
2182 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2183 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2184 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2185 MODULE_FIRMWARE(FIRMWARE_RT2571);
2186 MODULE_LICENSE("GPL");
2187
2188 static struct usb_driver rt73usb_driver = {
2189         .name           = KBUILD_MODNAME,
2190         .id_table       = rt73usb_device_table,
2191         .probe          = rt2x00usb_probe,
2192         .disconnect     = rt2x00usb_disconnect,
2193         .suspend        = rt2x00usb_suspend,
2194         .resume         = rt2x00usb_resume,
2195 };
2196
2197 static int __init rt73usb_init(void)
2198 {
2199         return usb_register(&rt73usb_driver);
2200 }
2201
2202 static void __exit rt73usb_exit(void)
2203 {
2204         usb_deregister(&rt73usb_driver);
2205 }
2206
2207 module_init(rt73usb_init);
2208 module_exit(rt73usb_exit);