drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/pci.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt61pci.h"
  40
  41 /*
  42  * Allow hardware encryption to be disabled.
  43  */
  44 static int modparam_nohwcrypt = 0;
  45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  47
  48 /*
  49  * Register access.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attempt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  */
  59 #define WAIT_FOR_BBP(__dev, __reg) \
  60         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  61 #define WAIT_FOR_RF(__dev, __reg) \
  62         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  63 #define WAIT_FOR_MCU(__dev, __reg) \
  64         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  65                                H2M_MAILBOX_CSR_OWNER, (__reg))
  66
  67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                               const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         mutex_lock(&rt2x00dev->csr_mutex);
  73
  74         /*
  75          * Wait until the BBP becomes available, afterwards we
  76          * can safely write the new data into the register.
  77          */
  78         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  79                 reg = 0;
  80                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  83                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  84
  85                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  86         }
  87
  88         mutex_unlock(&rt2x00dev->csr_mutex);
  89 }
  90
  91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  92                              const unsigned int word, u8 *value)
  93 {
  94         u32 reg;
  95
  96         mutex_lock(&rt2x00dev->csr_mutex);
  97
  98         /*
  99          * Wait until the BBP becomes available, afterwards we
 100          * can safely write the read request into the register.
 101          * After the data has been written, we wait until hardware
 102          * returns the correct value, if at any time the register
 103          * doesn't become available in time, reg will be 0xffffffff
 104          * which means we return 0xff to the caller.
 105          */
 106         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 107                 reg = 0;
 108                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 110                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 111
 112                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 113
 114                 WAIT_FOR_BBP(rt2x00dev, &reg);
 115         }
 116
 117         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 118
 119         mutex_unlock(&rt2x00dev->csr_mutex);
 120 }
 121
 122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 123                              const unsigned int word, const u32 value)
 124 {
 125         u32 reg;
 126
 127         mutex_lock(&rt2x00dev->csr_mutex);
 128
 129         /*
 130          * Wait until the RF becomes available, afterwards we
 131          * can safely write the new data into the register.
 132          */
 133         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 134                 reg = 0;
 135                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 136                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 137                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 139
 140                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 141                 rt2x00_rf_write(rt2x00dev, word, value);
 142         }
 143
 144         mutex_unlock(&rt2x00dev->csr_mutex);
 145 }
 146
 147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 148                                 const u8 command, const u8 token,
 149                                 const u8 arg0, const u8 arg1)
 150 {
 151         u32 reg;
 152
 153         mutex_lock(&rt2x00dev->csr_mutex);
 154
 155         /*
 156          * Wait until the MCU becomes available, afterwards we
 157          * can safely write the new data into the register.
 158          */
 159         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 160                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 161                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 164                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 165
 166                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 167                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 168                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 169                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 170         }
 171
 172         mutex_unlock(&rt2x00dev->csr_mutex);
 173
 174 }
 175
 176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 177 {
 178         struct rt2x00_dev *rt2x00dev = eeprom->data;
 179         u32 reg;
 180
 181         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 182
 183         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 184         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 185         eeprom->reg_data_clock =
 186             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 187         eeprom->reg_chip_select =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 189 }
 190
 191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 192 {
 193         struct rt2x00_dev *rt2x00dev = eeprom->data;
 194         u32 reg = 0;
 195
 196         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 197         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 199                            !!eeprom->reg_data_clock);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 201                            !!eeprom->reg_chip_select);
 202
 203         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 204 }
 205
 206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 207 static const struct rt2x00debug rt61pci_rt2x00debug = {
 208         .owner  = THIS_MODULE,
 209         .csr    = {
 210                 .read           = rt2x00pci_register_read,
 211                 .write          = rt2x00pci_register_write,
 212                 .flags          = RT2X00DEBUGFS_OFFSET,
 213                 .word_base      = CSR_REG_BASE,
 214                 .word_size      = sizeof(u32),
 215                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 216         },
 217         .eeprom = {
 218                 .read           = rt2x00_eeprom_read,
 219                 .write          = rt2x00_eeprom_write,
 220                 .word_base      = EEPROM_BASE,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt61pci_bbp_read,
 226                 .write          = rt61pci_bbp_write,
 227                 .word_base      = BBP_BASE,
 228                 .word_size      = sizeof(u8),
 229                 .word_count     = BBP_SIZE / sizeof(u8),
 230         },
 231         .rf     = {
 232                 .read           = rt2x00_rf_read,
 233                 .write          = rt61pci_rf_write,
 234                 .word_base      = RF_BASE,
 235                 .word_size      = sizeof(u32),
 236                 .word_count     = RF_SIZE / sizeof(u32),
 237         },
 238 };
 239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 240
 241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 242 {
 243         u32 reg;
 244
 245         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 246         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 247 }
 248
 249 #ifdef CONFIG_RT2X00_LIB_LEDS
 250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 251                                    enum led_brightness brightness)
 252 {
 253         struct rt2x00_led *led =
 254             container_of(led_cdev, struct rt2x00_led, led_dev);
 255         unsigned int enabled = brightness != LED_OFF;
 256         unsigned int a_mode =
 257             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 258         unsigned int bg_mode =
 259             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 260
 261         if (led->type == LED_TYPE_RADIO) {
 262                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 263                                    MCU_LEDCS_RADIO_STATUS, enabled);
 264
 265                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 266                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 267                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 268         } else if (led->type == LED_TYPE_ASSOC) {
 269                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 270                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 271                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 272                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 273
 274                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 275                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 276                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 277         } else if (led->type == LED_TYPE_QUALITY) {
 278                 /*
 279                  * The brightness is divided into 6 levels (0 - 5),
 280                  * this means we need to convert the brightness
 281                  * argument into the matching level within that range.
 282                  */
 283                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 284                                     brightness / (LED_FULL / 6), 0);
 285         }
 286 }
 287
 288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 289                              unsigned long *delay_on,
 290                              unsigned long *delay_off)
 291 {
 292         struct rt2x00_led *led =
 293             container_of(led_cdev, struct rt2x00_led, led_dev);
 294         u32 reg;
 295
 296         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 297         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 298         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 299         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 300
 301         return 0;
 302 }
 303
 304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 305                              struct rt2x00_led *led,
 306                              enum led_type type)
 307 {
 308         led->rt2x00dev = rt2x00dev;
 309         led->type = type;
 310         led->led_dev.brightness_set = rt61pci_brightness_set;
 311         led->led_dev.blink_set = rt61pci_blink_set;
 312         led->flags = LED_INITIALIZED;
 313 }
 314 #endif /* CONFIG_RT2X00_LIB_LEDS */
 315
 316 /*
 317  * Configuration handlers.
 318  */
 319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 320                                      struct rt2x00lib_crypto *crypto,
 321                                      struct ieee80211_key_conf *key)
 322 {
 323         struct hw_key_entry key_entry;
 324         struct rt2x00_field32 field;
 325         u32 mask;
 326         u32 reg;
 327
 328         if (crypto->cmd == SET_KEY) {
 329                 /*
 330                  * rt2x00lib can't determine the correct free
 331                  * key_idx for shared keys. We have 1 register
 332                  * with key valid bits. The goal is simple, read
 333                  * the register, if that is full we have no slots
 334                  * left.
 335                  * Note that each BSS is allowed to have up to 4
 336                  * shared keys, so put a mask over the allowed
 337                  * entries.
 338                  */
 339                 mask = (0xf << crypto->bssidx);
 340
 341                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 342                 reg &= mask;
 343
 344                 if (reg && reg == mask)
 345                         return -ENOSPC;
 346
 347                 key->hw_key_idx += reg ? ffz(reg) : 0;
 348
 349                 /*
 350                  * Upload key to hardware
 351                  */
 352                 memcpy(key_entry.key, crypto->key,
 353                        sizeof(key_entry.key));
 354                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 355                        sizeof(key_entry.tx_mic));
 356                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 357                        sizeof(key_entry.rx_mic));
 358
 359                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 360                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 361                                               &key_entry, sizeof(key_entry));
 362
 363                 /*
 364                  * The cipher types are stored over 2 registers.
 365                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 366                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 367                  * Using the correct defines correctly will cause overhead,
 368                  * so just calculate the correct offset.
 369                  */
 370                 if (key->hw_key_idx < 8) {
 371                         field.bit_offset = (3 * key->hw_key_idx);
 372                         field.bit_mask = 0x7 << field.bit_offset;
 373
 374                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 375                         rt2x00_set_field32(&reg, field, crypto->cipher);
 376                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 377                 } else {
 378                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 379                         field.bit_mask = 0x7 << field.bit_offset;
 380
 381                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 382                         rt2x00_set_field32(&reg, field, crypto->cipher);
 383                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 384                 }
 385
 386                 /*
 387                  * The driver does not support the IV/EIV generation
 388                  * in hardware. However it doesn't support the IV/EIV
 389                  * inside the ieee80211 frame either, but requires it
 390                  * to be provided separately for the descriptor.
 391                  * rt2x00lib will cut the IV/EIV data out of all frames
 392                  * given to us by mac80211, but we must tell mac80211
 393                  * to generate the IV/EIV data.
 394                  */
 395                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 396         }
 397
 398         /*
 399          * SEC_CSR0 contains only single-bit fields to indicate
 400          * a particular key is valid. Because using the FIELD32()
 401          * defines directly will cause a lot of overhead, we use
 402          * a calculation to determine the correct bit directly.
 403          */
 404         mask = 1 << key->hw_key_idx;
 405
 406         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 407         if (crypto->cmd == SET_KEY)
 408                 reg |= mask;
 409         else if (crypto->cmd == DISABLE_KEY)
 410                 reg &= ~mask;
 411         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 412
 413         return 0;
 414 }
 415
 416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 417                                        struct rt2x00lib_crypto *crypto,
 418                                        struct ieee80211_key_conf *key)
 419 {
 420         struct hw_pairwise_ta_entry addr_entry;
 421         struct hw_key_entry key_entry;
 422         u32 mask;
 423         u32 reg;
 424
 425         if (crypto->cmd == SET_KEY) {
 426                 /*
 427                  * rt2x00lib can't determine the correct free
 428                  * key_idx for pairwise keys. We have 2 registers
 429                  * with key valid bits. The goal is simple: read
 430                  * the first register. If that is full, move to
 431                  * the next register.
 432                  * When both registers are full, we drop the key.
 433                  * Otherwise, we use the first invalid entry.
 434                  */
 435                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 436                 if (reg && reg == ~0) {
 437                         key->hw_key_idx = 32;
 438                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 439                         if (reg && reg == ~0)
 440                                 return -ENOSPC;
 441                 }
 442
 443                 key->hw_key_idx += reg ? ffz(reg) : 0;
 444
 445                 /*
 446                  * Upload key to hardware
 447                  */
 448                 memcpy(key_entry.key, crypto->key,
 449                        sizeof(key_entry.key));
 450                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 451                        sizeof(key_entry.tx_mic));
 452                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 453                        sizeof(key_entry.rx_mic));
 454
 455                 memset(&addr_entry, 0, sizeof(addr_entry));
 456                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 457                 addr_entry.cipher = crypto->cipher;
 458
 459                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 460                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 461                                               &key_entry, sizeof(key_entry));
 462
 463                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 464                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 465                                               &addr_entry, sizeof(addr_entry));
 466
 467                 /*
 468                  * Enable pairwise lookup table for given BSS idx.
 469                  * Without this, received frames will not be decrypted
 470                  * by the hardware.
 471                  */
 472                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 473                 reg |= (1 << crypto->bssidx);
 474                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 475
 476                 /*
 477                  * The driver does not support the IV/EIV generation
 478                  * in hardware. However it doesn't support the IV/EIV
 479                  * inside the ieee80211 frame either, but requires it
 480                  * to be provided separately for the descriptor.
 481                  * rt2x00lib will cut the IV/EIV data out of all frames
 482                  * given to us by mac80211, but we must tell mac80211
 483                  * to generate the IV/EIV data.
 484                  */
 485                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 486         }
 487
 488         /*
 489          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 490          * a particular key is valid. Because using the FIELD32()
 491          * defines directly will cause a lot of overhead, we use
 492          * a calculation to determine the correct bit directly.
 493          */
 494         if (key->hw_key_idx < 32) {
 495                 mask = 1 << key->hw_key_idx;
 496
 497                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 498                 if (crypto->cmd == SET_KEY)
 499                         reg |= mask;
 500                 else if (crypto->cmd == DISABLE_KEY)
 501                         reg &= ~mask;
 502                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 503         } else {
 504                 mask = 1 << (key->hw_key_idx - 32);
 505
 506                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 507                 if (crypto->cmd == SET_KEY)
 508                         reg |= mask;
 509                 else if (crypto->cmd == DISABLE_KEY)
 510                         reg &= ~mask;
 511                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 512         }
 513
 514         return 0;
 515 }
 516
 517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 518                                   const unsigned int filter_flags)
 519 {
 520         u32 reg;
 521
 522         /*
 523          * Start configuration steps.
 524          * Note that the version error will always be dropped
 525          * and broadcast frames will always be accepted since
 526          * there is no filter for it at this time.
 527          */
 528         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 529         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 530                            !(filter_flags & FIF_FCSFAIL));
 531         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 532                            !(filter_flags & FIF_PLCPFAIL));
 533         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 534                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 536                            !(filter_flags & FIF_PROMISC_IN_BSS));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 538                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 539                            !rt2x00dev->intf_ap_count);
 540         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 542                            !(filter_flags & FIF_ALLMULTI));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 544         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 547 }
 548
 549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 550                                 struct rt2x00_intf *intf,
 551                                 struct rt2x00intf_conf *conf,
 552                                 const unsigned int flags)
 553 {
 554         unsigned int beacon_base;
 555         u32 reg;
 556
 557         if (flags & CONFIG_UPDATE_TYPE) {
 558                 /*
 559                  * Clear current synchronisation setup.
 560                  * For the Beacon base registers, we only need to clear
 561                  * the first byte since that byte contains the VALID and OWNER
 562                  * bits which (when set to 0) will invalidate the entire beacon.
 563                  */
 564                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 565                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 566
 567                 /*
 568                  * Enable synchronisation.
 569                  */
 570                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 571                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 572                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 573                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 574                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 575         }
 576
 577         if (flags & CONFIG_UPDATE_MAC) {
 578                 reg = le32_to_cpu(conf->mac[1]);
 579                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 580                 conf->mac[1] = cpu_to_le32(reg);
 581
 582                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 583                                               conf->mac, sizeof(conf->mac));
 584         }
 585
 586         if (flags & CONFIG_UPDATE_BSSID) {
 587                 reg = le32_to_cpu(conf->bssid[1]);
 588                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 589                 conf->bssid[1] = cpu_to_le32(reg);
 590
 591                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 592                                               conf->bssid, sizeof(conf->bssid));
 593         }
 594 }
 595
 596 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 597                                struct rt2x00lib_erp *erp)
 598 {
 599         u32 reg;
 600
 601         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 602         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 603         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 604         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 605
 606         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 607         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 608         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 609                            !!erp->short_preamble);
 610         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 611
 612         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 613
 614         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 615         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 616                            erp->beacon_int * 16);
 617         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 618
 619         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 620         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 621         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 622
 623         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 624         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 625         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 626         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 627         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 628 }
 629
 630 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 631                                       struct antenna_setup *ant)
 632 {
 633         u8 r3;
 634         u8 r4;
 635         u8 r77;
 636
 637         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 638         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 639         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 640
 641         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
 642
 643         /*
 644          * Configure the RX antenna.
 645          */
 646         switch (ant->rx) {
 647         case ANTENNA_HW_DIVERSITY:
 648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 649                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 650                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 651                 break;
 652         case ANTENNA_A:
 653                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 654                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 655                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 656                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 657                 else
 658                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 659                 break;
 660         case ANTENNA_B:
 661         default:
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 666                 else
 667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 668                 break;
 669         }
 670
 671         rt61pci_bbp_write(rt2x00dev, 77, r77);
 672         rt61pci_bbp_write(rt2x00dev, 3, r3);
 673         rt61pci_bbp_write(rt2x00dev, 4, r4);
 674 }
 675
 676 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 677                                       struct antenna_setup *ant)
 678 {
 679         u8 r3;
 680         u8 r4;
 681         u8 r77;
 682
 683         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 684         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 685         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 686
 687         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
 688         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 689                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 690
 691         /*
 692          * Configure the RX antenna.
 693          */
 694         switch (ant->rx) {
 695         case ANTENNA_HW_DIVERSITY:
 696                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 697                 break;
 698         case ANTENNA_A:
 699                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 700                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 701                 break;
 702         case ANTENNA_B:
 703         default:
 704                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 705                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 706                 break;
 707         }
 708
 709         rt61pci_bbp_write(rt2x00dev, 77, r77);
 710         rt61pci_bbp_write(rt2x00dev, 3, r3);
 711         rt61pci_bbp_write(rt2x00dev, 4, r4);
 712 }
 713
 714 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 715                                            const int p1, const int p2)
 716 {
 717         u32 reg;
 718
 719         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 720
 721         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 722         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 723
 724         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 725         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 726
 727         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 728 }
 729
 730 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 731                                         struct antenna_setup *ant)
 732 {
 733         u8 r3;
 734         u8 r4;
 735         u8 r77;
 736
 737         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 738         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 739         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 740
 741         /*
 742          * Configure the RX antenna.
 743          */
 744         switch (ant->rx) {
 745         case ANTENNA_A:
 746                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 747                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 748                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 749                 break;
 750         case ANTENNA_HW_DIVERSITY:
 751                 /*
 752                  * FIXME: Antenna selection for the rf 2529 is very confusing
 753                  * in the legacy driver. Just default to antenna B until the
 754                  * legacy code can be properly translated into rt2x00 code.
 755                  */
 756         case ANTENNA_B:
 757         default:
 758                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 759                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 760                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 761                 break;
 762         }
 763
 764         rt61pci_bbp_write(rt2x00dev, 77, r77);
 765         rt61pci_bbp_write(rt2x00dev, 3, r3);
 766         rt61pci_bbp_write(rt2x00dev, 4, r4);
 767 }
 768
 769 struct antenna_sel {
 770         u8 word;
 771         /*
 772          * value[0] -> non-LNA
 773          * value[1] -> LNA
 774          */
 775         u8 value[2];
 776 };
 777
 778 static const struct antenna_sel antenna_sel_a[] = {
 779         { 96,  { 0x58, 0x78 } },
 780         { 104, { 0x38, 0x48 } },
 781         { 75,  { 0xfe, 0x80 } },
 782         { 86,  { 0xfe, 0x80 } },
 783         { 88,  { 0xfe, 0x80 } },
 784         { 35,  { 0x60, 0x60 } },
 785         { 97,  { 0x58, 0x58 } },
 786         { 98,  { 0x58, 0x58 } },
 787 };
 788
 789 static const struct antenna_sel antenna_sel_bg[] = {
 790         { 96,  { 0x48, 0x68 } },
 791         { 104, { 0x2c, 0x3c } },
 792         { 75,  { 0xfe, 0x80 } },
 793         { 86,  { 0xfe, 0x80 } },
 794         { 88,  { 0xfe, 0x80 } },
 795         { 35,  { 0x50, 0x50 } },
 796         { 97,  { 0x48, 0x48 } },
 797         { 98,  { 0x48, 0x48 } },
 798 };
 799
 800 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 801                                struct antenna_setup *ant)
 802 {
 803         const struct antenna_sel *sel;
 804         unsigned int lna;
 805         unsigned int i;
 806         u32 reg;
 807
 808         /*
 809          * We should never come here because rt2x00lib is supposed
 810          * to catch this and send us the correct antenna explicitely.
 811          */
 812         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 813                ant->tx == ANTENNA_SW_DIVERSITY);
 814
 815         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 816                 sel = antenna_sel_a;
 817                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 818         } else {
 819                 sel = antenna_sel_bg;
 820                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 821         }
 822
 823         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 824                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 825
 826         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 827
 828         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 829                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 830         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 831                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 832
 833         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 834
 835         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
 836                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 837         else if (rt2x00_rf(rt2x00dev, RF2527))
 838                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 839         else if (rt2x00_rf(rt2x00dev, RF2529)) {
 840                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 841                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 842                 else
 843                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 844         }
 845 }
 846
 847 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 848                                     struct rt2x00lib_conf *libconf)
 849 {
 850         u16 eeprom;
 851         short lna_gain = 0;
 852
 853         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 854                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 855                         lna_gain += 14;
 856
 857                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 858                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 859         } else {
 860                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 861                         lna_gain += 14;
 862
 863                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 864                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 865         }
 866
 867         rt2x00dev->lna_gain = lna_gain;
 868 }
 869
 870 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 871                                    struct rf_channel *rf, const int txpower)
 872 {
 873         u8 r3;
 874         u8 r94;
 875         u8 smart;
 876
 877         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 878         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 879
 880         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 881
 882         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 883         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 884         rt61pci_bbp_write(rt2x00dev, 3, r3);
 885
 886         r94 = 6;
 887         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 888                 r94 += txpower - MAX_TXPOWER;
 889         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 890                 r94 += txpower;
 891         rt61pci_bbp_write(rt2x00dev, 94, r94);
 892
 893         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 894         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 895         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 896         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 897
 898         udelay(200);
 899
 900         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 901         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 902         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 903         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 904
 905         udelay(200);
 906
 907         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 908         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 909         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 910         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 911
 912         msleep(1);
 913 }
 914
 915 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 916                                    const int txpower)
 917 {
 918         struct rf_channel rf;
 919
 920         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 921         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 922         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 923         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 924
 925         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 926 }
 927
 928 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 929                                     struct rt2x00lib_conf *libconf)
 930 {
 931         u32 reg;
 932
 933         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 934         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 935                            libconf->conf->long_frame_max_tx_count);
 936         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 937                            libconf->conf->short_frame_max_tx_count);
 938         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 939 }
 940
 941 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 942                                 struct rt2x00lib_conf *libconf)
 943 {
 944         enum dev_state state =
 945             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 946                 STATE_SLEEP : STATE_AWAKE;
 947         u32 reg;
 948
 949         if (state == STATE_SLEEP) {
 950                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 951                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 952                                    rt2x00dev->beacon_int - 10);
 953                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 954                                    libconf->conf->listen_interval - 1);
 955                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 956
 957                 /* We must first disable autowake before it can be enabled */
 958                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 959                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 960
 961                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 962                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 963
 964                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 965                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 966                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 967
 968                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 969         } else {
 970                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 971                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 972                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 974                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 975                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 976
 977                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
 978                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
 979                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
 980
 981                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
 982         }
 983 }
 984
 985 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 986                            struct rt2x00lib_conf *libconf,
 987                            const unsigned int flags)
 988 {
 989         /* Always recalculate LNA gain before changing configuration */
 990         rt61pci_config_lna_gain(rt2x00dev, libconf);
 991
 992         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 993                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 994                                        libconf->conf->power_level);
 995         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 996             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 997                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 998         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 999                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1000         if (flags & IEEE80211_CONF_CHANGE_PS)
1001                 rt61pci_config_ps(rt2x00dev, libconf);
1002 }
1003
1004 /*
1005  * Link tuning
1006  */
1007 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008                                struct link_qual *qual)
1009 {
1010         u32 reg;
1011
1012         /*
1013          * Update FCS error count from register.
1014          */
1015         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1016         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1017
1018         /*
1019          * Update False CCA count from register.
1020          */
1021         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1022         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1023 }
1024
1025 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1026                                    struct link_qual *qual, u8 vgc_level)
1027 {
1028         if (qual->vgc_level != vgc_level) {
1029                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1030                 qual->vgc_level = vgc_level;
1031                 qual->vgc_level_reg = vgc_level;
1032         }
1033 }
1034
1035 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036                                 struct link_qual *qual)
1037 {
1038         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1039 }
1040
1041 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1042                                struct link_qual *qual, const u32 count)
1043 {
1044         u8 up_bound;
1045         u8 low_bound;
1046
1047         /*
1048          * Determine r17 bounds.
1049          */
1050         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1051                 low_bound = 0x28;
1052                 up_bound = 0x48;
1053                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1054                         low_bound += 0x10;
1055                         up_bound += 0x10;
1056                 }
1057         } else {
1058                 low_bound = 0x20;
1059                 up_bound = 0x40;
1060                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1061                         low_bound += 0x10;
1062                         up_bound += 0x10;
1063                 }
1064         }
1065
1066         /*
1067          * If we are not associated, we should go straight to the
1068          * dynamic CCA tuning.
1069          */
1070         if (!rt2x00dev->intf_associated)
1071                 goto dynamic_cca_tune;
1072
1073         /*
1074          * Special big-R17 for very short distance
1075          */
1076         if (qual->rssi >= -35) {
1077                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1078                 return;
1079         }
1080
1081         /*
1082          * Special big-R17 for short distance
1083          */
1084         if (qual->rssi >= -58) {
1085                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1086                 return;
1087         }
1088
1089         /*
1090          * Special big-R17 for middle-short distance
1091          */
1092         if (qual->rssi >= -66) {
1093                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1094                 return;
1095         }
1096
1097         /*
1098          * Special mid-R17 for middle distance
1099          */
1100         if (qual->rssi >= -74) {
1101                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1102                 return;
1103         }
1104
1105         /*
1106          * Special case: Change up_bound based on the rssi.
1107          * Lower up_bound when rssi is weaker then -74 dBm.
1108          */
1109         up_bound -= 2 * (-74 - qual->rssi);
1110         if (low_bound > up_bound)
1111                 up_bound = low_bound;
1112
1113         if (qual->vgc_level > up_bound) {
1114                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1115                 return;
1116         }
1117
1118 dynamic_cca_tune:
1119
1120         /*
1121          * r17 does not yet exceed upper limit, continue and base
1122          * the r17 tuning on the false CCA count.
1123          */
1124         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1125                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1126         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1127                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1128 }
1129
1130 /*
1131  * Firmware functions
1132  */
1133 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1134 {
1135         u16 chip;
1136         char *fw_name;
1137
1138         pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1139         switch (chip) {
1140         case RT2561_PCI_ID:
1141                 fw_name = FIRMWARE_RT2561;
1142                 break;
1143         case RT2561s_PCI_ID:
1144                 fw_name = FIRMWARE_RT2561s;
1145                 break;
1146         case RT2661_PCI_ID:
1147                 fw_name = FIRMWARE_RT2661;
1148                 break;
1149         default:
1150                 fw_name = NULL;
1151                 break;
1152         }
1153
1154         return fw_name;
1155 }
1156
1157 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1158                                   const u8 *data, const size_t len)
1159 {
1160         u16 fw_crc;
1161         u16 crc;
1162
1163         /*
1164          * Only support 8kb firmware files.
1165          */
1166         if (len != 8192)
1167                 return FW_BAD_LENGTH;
1168
1169         /*
1170          * The last 2 bytes in the firmware array are the crc checksum itself.
1171          * This means that we should never pass those 2 bytes to the crc
1172          * algorithm.
1173          */
1174         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1175
1176         /*
1177          * Use the crc itu-t algorithm.
1178          */
1179         crc = crc_itu_t(0, data, len - 2);
1180         crc = crc_itu_t_byte(crc, 0);
1181         crc = crc_itu_t_byte(crc, 0);
1182
1183         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1184 }
1185
1186 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1187                                  const u8 *data, const size_t len)
1188 {
1189         int i;
1190         u32 reg;
1191
1192         /*
1193          * Wait for stable hardware.
1194          */
1195         for (i = 0; i < 100; i++) {
1196                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1197                 if (reg)
1198                         break;
1199                 msleep(1);
1200         }
1201
1202         if (!reg) {
1203                 ERROR(rt2x00dev, "Unstable hardware.\n");
1204                 return -EBUSY;
1205         }
1206
1207         /*
1208          * Prepare MCU and mailbox for firmware loading.
1209          */
1210         reg = 0;
1211         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1212         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1213         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1214         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1215         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1216
1217         /*
1218          * Write firmware to device.
1219          */
1220         reg = 0;
1221         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1222         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1223         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1224
1225         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1226                                       data, len);
1227
1228         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1229         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1230
1231         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1232         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233
1234         for (i = 0; i < 100; i++) {
1235                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1236                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1237                         break;
1238                 msleep(1);
1239         }
1240
1241         if (i == 100) {
1242                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1243                 return -EBUSY;
1244         }
1245
1246         /*
1247          * Hardware needs another millisecond before it is ready.
1248          */
1249         msleep(1);
1250
1251         /*
1252          * Reset MAC and BBP registers.
1253          */
1254         reg = 0;
1255         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1256         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1257         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1258
1259         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1260         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1261         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1262         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1263
1264         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1265         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1266         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1267
1268         return 0;
1269 }
1270
1271 /*
1272  * Initialization functions.
1273  */
1274 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1275 {
1276         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1277         u32 word;
1278
1279         if (entry->queue->qid == QID_RX) {
1280                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1281
1282                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1283         } else {
1284                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1285
1286                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1287                         rt2x00_get_field32(word, TXD_W0_VALID));
1288         }
1289 }
1290
1291 static void rt61pci_clear_entry(struct queue_entry *entry)
1292 {
1293         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1294         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1295         u32 word;
1296
1297         if (entry->queue->qid == QID_RX) {
1298                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1299                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1300                                    skbdesc->skb_dma);
1301                 rt2x00_desc_write(entry_priv->desc, 5, word);
1302
1303                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1304                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1305                 rt2x00_desc_write(entry_priv->desc, 0, word);
1306         } else {
1307                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1308                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1309                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1310                 rt2x00_desc_write(entry_priv->desc, 0, word);
1311         }
1312 }
1313
1314 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1315 {
1316         struct queue_entry_priv_pci *entry_priv;
1317         u32 reg;
1318
1319         /*
1320          * Initialize registers.
1321          */
1322         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1323         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1324                            rt2x00dev->tx[0].limit);
1325         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1326                            rt2x00dev->tx[1].limit);
1327         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1328                            rt2x00dev->tx[2].limit);
1329         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1330                            rt2x00dev->tx[3].limit);
1331         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1332
1333         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1334         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1335                            rt2x00dev->tx[0].desc_size / 4);
1336         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1337
1338         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1339         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1340         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1341                            entry_priv->desc_dma);
1342         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1343
1344         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1345         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1346         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1347                            entry_priv->desc_dma);
1348         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1349
1350         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1351         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1352         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1353                            entry_priv->desc_dma);
1354         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1355
1356         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1357         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1358         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1359                            entry_priv->desc_dma);
1360         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1361
1362         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1363         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1364         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1365                            rt2x00dev->rx->desc_size / 4);
1366         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1367         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1368
1369         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1370         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1371         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1372                            entry_priv->desc_dma);
1373         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1374
1375         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1376         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1377         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1378         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1379         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1380         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1381
1382         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1383         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1384         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1385         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1386         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1387         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1388
1389         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1390         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1391         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1392
1393         return 0;
1394 }
1395
1396 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1397 {
1398         u32 reg;
1399
1400         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1401         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1402         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1403         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1404         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1405
1406         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1407         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1408         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1409         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1410         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1411         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1412         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1413         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1414         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1415         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1416
1417         /*
1418          * CCK TXD BBP registers
1419          */
1420         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1421         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1422         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1423         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1424         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1425         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1426         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1427         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1428         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1430
1431         /*
1432          * OFDM TXD BBP registers
1433          */
1434         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1435         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1436         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1437         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1438         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1439         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1440         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1441         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1442
1443         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1444         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1445         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1446         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1447         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1448         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1449
1450         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1451         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1452         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1453         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1454         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1455         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1456
1457         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1458         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1459         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1460         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1461         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1462         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1463         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1464         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1465
1466         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1467
1468         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1469
1470         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1471         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1472         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1473
1474         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1475
1476         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1477                 return -EBUSY;
1478
1479         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1480
1481         /*
1482          * Invalidate all Shared Keys (SEC_CSR0),
1483          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1484          */
1485         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1486         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1487         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1488
1489         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1490         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1491         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1492         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1493
1494         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1495
1496         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1497
1498         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1499
1500         /*
1501          * Clear all beacons
1502          * For the Beacon base registers we only need to clear
1503          * the first byte since that byte contains the VALID and OWNER
1504          * bits which (when set to 0) will invalidate the entire beacon.
1505          */
1506         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1507         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1508         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1509         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1510
1511         /*
1512          * We must clear the error counters.
1513          * These registers are cleared on read,
1514          * so we may pass a useless variable to store the value.
1515          */
1516         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1517         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1518         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1519
1520         /*
1521          * Reset MAC and BBP registers.
1522          */
1523         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1524         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1525         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1526         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1527
1528         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1529         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1530         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1531         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1532
1533         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1534         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1535         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1536
1537         return 0;
1538 }
1539
1540 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1541 {
1542         unsigned int i;
1543         u8 value;
1544
1545         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1546                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1547                 if ((value != 0xff) && (value != 0x00))
1548                         return 0;
1549                 udelay(REGISTER_BUSY_DELAY);
1550         }
1551
1552         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1553         return -EACCES;
1554 }
1555
1556 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1557 {
1558         unsigned int i;
1559         u16 eeprom;
1560         u8 reg_id;
1561         u8 value;
1562
1563         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1564                 return -EACCES;
1565
1566         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1567         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1568         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1569         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1570         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1571         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1572         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1573         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1574         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1575         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1576         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1577         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1578         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1579         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1580         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1581         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1582         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1583         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1584         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1585         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1586         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1587         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1588         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1589         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1590
1591         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1592                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1593
1594                 if (eeprom != 0xffff && eeprom != 0x0000) {
1595                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1596                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1597                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1598                 }
1599         }
1600
1601         return 0;
1602 }
1603
1604 /*
1605  * Device state switch handlers.
1606  */
1607 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1608                               enum dev_state state)
1609 {
1610         u32 reg;
1611
1612         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1613         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1614                            (state == STATE_RADIO_RX_OFF) ||
1615                            (state == STATE_RADIO_RX_OFF_LINK));
1616         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1617 }
1618
1619 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1620                                enum dev_state state)
1621 {
1622         int mask = (state == STATE_RADIO_IRQ_OFF);
1623         u32 reg;
1624
1625         /*
1626          * When interrupts are being enabled, the interrupt registers
1627          * should clear the register to assure a clean state.
1628          */
1629         if (state == STATE_RADIO_IRQ_ON) {
1630                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1631                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1632
1633                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1634                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1635         }
1636
1637         /*
1638          * Only toggle the interrupts bits we are going to use.
1639          * Non-checked interrupt bits are disabled by default.
1640          */
1641         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1642         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1643         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1644         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1645         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1646         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1647
1648         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1649         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1650         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1651         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1652         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1653         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1654         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1655         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1656         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1657         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1658 }
1659
1660 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1661 {
1662         u32 reg;
1663
1664         /*
1665          * Initialize all registers.
1666          */
1667         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1668                      rt61pci_init_registers(rt2x00dev) ||
1669                      rt61pci_init_bbp(rt2x00dev)))
1670                 return -EIO;
1671
1672         /*
1673          * Enable RX.
1674          */
1675         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1676         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1677         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1678
1679         return 0;
1680 }
1681
1682 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1683 {
1684         /*
1685          * Disable power
1686          */
1687         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1688 }
1689
1690 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1691 {
1692         u32 reg, reg2;
1693         unsigned int i;
1694         char put_to_sleep;
1695
1696         put_to_sleep = (state != STATE_AWAKE);
1697
1698         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1699         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1700         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1701         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1702
1703         /*
1704          * Device is not guaranteed to be in the requested state yet.
1705          * We must wait until the register indicates that the
1706          * device has entered the correct state.
1707          */
1708         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1709                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1710                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1711                 if (state == !put_to_sleep)
1712                         return 0;
1713                 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1714                 msleep(10);
1715         }
1716
1717         return -EBUSY;
1718 }
1719
1720 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1721                                     enum dev_state state)
1722 {
1723         int retval = 0;
1724
1725         switch (state) {
1726         case STATE_RADIO_ON:
1727                 retval = rt61pci_enable_radio(rt2x00dev);
1728                 break;
1729         case STATE_RADIO_OFF:
1730                 rt61pci_disable_radio(rt2x00dev);
1731                 break;
1732         case STATE_RADIO_RX_ON:
1733         case STATE_RADIO_RX_ON_LINK:
1734         case STATE_RADIO_RX_OFF:
1735         case STATE_RADIO_RX_OFF_LINK:
1736                 rt61pci_toggle_rx(rt2x00dev, state);
1737                 break;
1738         case STATE_RADIO_IRQ_ON:
1739         case STATE_RADIO_IRQ_OFF:
1740                 rt61pci_toggle_irq(rt2x00dev, state);
1741                 break;
1742         case STATE_DEEP_SLEEP:
1743         case STATE_SLEEP:
1744         case STATE_STANDBY:
1745         case STATE_AWAKE:
1746                 retval = rt61pci_set_state(rt2x00dev, state);
1747                 break;
1748         default:
1749                 retval = -ENOTSUPP;
1750                 break;
1751         }
1752
1753         if (unlikely(retval))
1754                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1755                       state, retval);
1756
1757         return retval;
1758 }
1759
1760 /*
1761  * TX descriptor initialization
1762  */
1763 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1764                                   struct sk_buff *skb,
1765                                   struct txentry_desc *txdesc)
1766 {
1767         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1768         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1769         __le32 *txd = entry_priv->desc;
1770         u32 word;
1771
1772         /*
1773          * Start writing the descriptor words.
1774          */
1775         rt2x00_desc_read(txd, 1, &word);
1776         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1777         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1778         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1779         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1780         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1781         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1782                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1783         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1784         rt2x00_desc_write(txd, 1, word);
1785
1786         rt2x00_desc_read(txd, 2, &word);
1787         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1788         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1789         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1790         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1791         rt2x00_desc_write(txd, 2, word);
1792
1793         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1794                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1795                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1796         }
1797
1798         rt2x00_desc_read(txd, 5, &word);
1799         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1800         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1801                            skbdesc->entry->entry_idx);
1802         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1803                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1804         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1805         rt2x00_desc_write(txd, 5, word);
1806
1807         if (txdesc->queue != QID_BEACON) {
1808                 rt2x00_desc_read(txd, 6, &word);
1809                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1810                                    skbdesc->skb_dma);
1811                 rt2x00_desc_write(txd, 6, word);
1812
1813                 rt2x00_desc_read(txd, 11, &word);
1814                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1815                                    txdesc->length);
1816                 rt2x00_desc_write(txd, 11, word);
1817         }
1818
1819         /*
1820          * Writing TXD word 0 must the last to prevent a race condition with
1821          * the device, whereby the device may take hold of the TXD before we
1822          * finished updating it.
1823          */
1824         rt2x00_desc_read(txd, 0, &word);
1825         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1826         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1827         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1828                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1829         rt2x00_set_field32(&word, TXD_W0_ACK,
1830                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1831         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1832                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1833         rt2x00_set_field32(&word, TXD_W0_OFDM,
1834                            (txdesc->rate_mode == RATE_MODE_OFDM));
1835         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1836         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1837                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1838         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1839                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1840         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1841                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1842         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1843         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1844         rt2x00_set_field32(&word, TXD_W0_BURST,
1845                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1846         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1847         rt2x00_desc_write(txd, 0, word);
1848
1849         /*
1850          * Register descriptor details in skb frame descriptor.
1851          */
1852         skbdesc->desc = txd;
1853         skbdesc->desc_len =
1854                 (txdesc->queue == QID_BEACON) ?  TXINFO_SIZE : TXD_DESC_SIZE;
1855 }
1856
1857 /*
1858  * TX data initialization
1859  */
1860 static void rt61pci_write_beacon(struct queue_entry *entry,
1861                                  struct txentry_desc *txdesc)
1862 {
1863         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1864         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1865         unsigned int beacon_base;
1866         u32 reg;
1867
1868         /*
1869          * Disable beaconing while we are reloading the beacon data,
1870          * otherwise we might be sending out invalid data.
1871          */
1872         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1873         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1874         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1875
1876         /*
1877          * Write entire beacon with descriptor to register.
1878          */
1879         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1880         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1881                                       entry_priv->desc, TXINFO_SIZE);
1882         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1883                                       entry->skb->data, entry->skb->len);
1884
1885         /*
1886          * Enable beaconing again.
1887          *
1888          * For Wi-Fi faily generated beacons between participating
1889          * stations. Set TBTT phase adaptive adjustment step to 8us.
1890          */
1891         rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1892
1893         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1894         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1895         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1896         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1897
1898         /*
1899          * Clean up beacon skb.
1900          */
1901         dev_kfree_skb_any(entry->skb);
1902         entry->skb = NULL;
1903 }
1904
1905 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1906                                   const enum data_queue_qid queue)
1907 {
1908         u32 reg;
1909
1910         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1911         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1912         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1913         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1914         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1915         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1916 }
1917
1918 static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1919                                   const enum data_queue_qid qid)
1920 {
1921         u32 reg;
1922
1923         if (qid == QID_BEACON) {
1924                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1925                 return;
1926         }
1927
1928         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1929         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1930         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1931         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1932         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1933         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1934 }
1935
1936 /*
1937  * RX control handlers
1938  */
1939 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1940 {
1941         u8 offset = rt2x00dev->lna_gain;
1942         u8 lna;
1943
1944         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1945         switch (lna) {
1946         case 3:
1947                 offset += 90;
1948                 break;
1949         case 2:
1950                 offset += 74;
1951                 break;
1952         case 1:
1953                 offset += 64;
1954                 break;
1955         default:
1956                 return 0;
1957         }
1958
1959         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1960                 if (lna == 3 || lna == 2)
1961                         offset += 10;
1962         }
1963
1964         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1965 }
1966
1967 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1968                                 struct rxdone_entry_desc *rxdesc)
1969 {
1970         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1971         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1972         u32 word0;
1973         u32 word1;
1974
1975         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1976         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1977
1978         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1979                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1980
1981         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1982         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1983
1984         if (rxdesc->cipher != CIPHER_NONE) {
1985                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1986                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1987                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1988
1989                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1990                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1991
1992                 /*
1993                  * Hardware has stripped IV/EIV data from 802.11 frame during
1994                  * decryption. It has provided the data separately but rt2x00lib
1995                  * should decide if it should be reinserted.
1996                  */
1997                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1998
1999                 /*
2000                  * FIXME: Legacy driver indicates that the frame does
2001                  * contain the Michael Mic. Unfortunately, in rt2x00
2002                  * the MIC seems to be missing completely...
2003                  */
2004                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2005
2006                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2007                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2008                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2009                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2010         }
2011
2012         /*
2013          * Obtain the status about this packet.
2014          * When frame was received with an OFDM bitrate,
2015          * the signal is the PLCP value. If it was received with
2016          * a CCK bitrate the signal is the rate in 100kbit/s.
2017          */
2018         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2019         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2020         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2021
2022         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2023                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2024         else
2025                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2026         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2027                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2028 }
2029
2030 /*
2031  * Interrupt functions.
2032  */
2033 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2034 {
2035         struct data_queue *queue;
2036         struct queue_entry *entry;
2037         struct queue_entry *entry_done;
2038         struct queue_entry_priv_pci *entry_priv;
2039         struct txdone_entry_desc txdesc;
2040         u32 word;
2041         u32 reg;
2042         u32 old_reg;
2043         int type;
2044         int index;
2045
2046         /*
2047          * During each loop we will compare the freshly read
2048          * STA_CSR4 register value with the value read from
2049          * the previous loop. If the 2 values are equal then
2050          * we should stop processing because the chance is
2051          * quite big that the device has been unplugged and
2052          * we risk going into an endless loop.
2053          */
2054         old_reg = 0;
2055
2056         while (1) {
2057                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2058                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2059                         break;
2060
2061                 if (old_reg == reg)
2062                         break;
2063                 old_reg = reg;
2064
2065                 /*
2066                  * Skip this entry when it contains an invalid
2067                  * queue identication number.
2068                  */
2069                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2070                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2071                 if (unlikely(!queue))
2072                         continue;
2073
2074                 /*
2075                  * Skip this entry when it contains an invalid
2076                  * index number.
2077                  */
2078                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2079                 if (unlikely(index >= queue->limit))
2080                         continue;
2081
2082                 entry = &queue->entries[index];
2083                 entry_priv = entry->priv_data;
2084                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2085
2086                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2087                     !rt2x00_get_field32(word, TXD_W0_VALID))
2088                         return;
2089
2090                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2091                 while (entry != entry_done) {
2092                         /* Catch up.
2093                          * Just report any entries we missed as failed.
2094                          */
2095                         WARNING(rt2x00dev,
2096                                 "TX status report missed for entry %d\n",
2097                                 entry_done->entry_idx);
2098
2099                         txdesc.flags = 0;
2100                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2101                         txdesc.retry = 0;
2102
2103                         rt2x00lib_txdone(entry_done, &txdesc);
2104                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2105                 }
2106
2107                 /*
2108                  * Obtain the status about this packet.
2109                  */
2110                 txdesc.flags = 0;
2111                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2112                 case 0: /* Success, maybe with retry */
2113                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2114                         break;
2115                 case 6: /* Failure, excessive retries */
2116                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2117                         /* Don't break, this is a failed frame! */
2118                 default: /* Failure */
2119                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2120                 }
2121                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2122
2123                 rt2x00lib_txdone(entry, &txdesc);
2124         }
2125 }
2126
2127 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2128 {
2129         struct ieee80211_conf conf = { .flags = 0 };
2130         struct rt2x00lib_conf libconf = { .conf = &conf };
2131
2132         rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2133 }
2134
2135 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2136 {
2137         struct rt2x00_dev *rt2x00dev = dev_instance;
2138         u32 reg_mcu;
2139         u32 reg;
2140
2141         /*
2142          * Get the interrupt sources & saved to local variable.
2143          * Write register value back to clear pending interrupts.
2144          */
2145         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2146         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2147
2148         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2149         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2150
2151         if (!reg && !reg_mcu)
2152                 return IRQ_NONE;
2153
2154         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2155                 return IRQ_HANDLED;
2156
2157         /*
2158          * Handle interrupts, walk through all bits
2159          * and run the tasks, the bits are checked in order of
2160          * priority.
2161          */
2162
2163         /*
2164          * 1 - Rx ring done interrupt.
2165          */
2166         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2167                 rt2x00pci_rxdone(rt2x00dev);
2168
2169         /*
2170          * 2 - Tx ring done interrupt.
2171          */
2172         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2173                 rt61pci_txdone(rt2x00dev);
2174
2175         /*
2176          * 3 - Handle MCU command done.
2177          */
2178         if (reg_mcu)
2179                 rt2x00pci_register_write(rt2x00dev,
2180                                          M2H_CMD_DONE_CSR, 0xffffffff);
2181
2182         /*
2183          * 4 - MCU Autowakeup interrupt.
2184          */
2185         if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2186                 rt61pci_wakeup(rt2x00dev);
2187
2188         return IRQ_HANDLED;
2189 }
2190
2191 /*
2192  * Device probe functions.
2193  */
2194 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2195 {
2196         struct eeprom_93cx6 eeprom;
2197         u32 reg;
2198         u16 word;
2199         u8 *mac;
2200         s8 value;
2201
2202         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2203
2204         eeprom.data = rt2x00dev;
2205         eeprom.register_read = rt61pci_eepromregister_read;
2206         eeprom.register_write = rt61pci_eepromregister_write;
2207         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2208             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2209         eeprom.reg_data_in = 0;
2210         eeprom.reg_data_out = 0;
2211         eeprom.reg_data_clock = 0;
2212         eeprom.reg_chip_select = 0;
2213
2214         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2215                                EEPROM_SIZE / sizeof(u16));
2216
2217         /*
2218          * Start validation of the data that has been read.
2219          */
2220         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2221         if (!is_valid_ether_addr(mac)) {
2222                 random_ether_addr(mac);
2223                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2224         }
2225
2226         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2227         if (word == 0xffff) {
2228                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2229                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2230                                    ANTENNA_B);
2231                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2232                                    ANTENNA_B);
2233                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2234                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2235                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2236                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2237                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2238                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2239         }
2240
2241         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2242         if (word == 0xffff) {
2243                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2244                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2245                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2246                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2247                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2248                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2249                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2250                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2251                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2252         }
2253
2254         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2255         if (word == 0xffff) {
2256                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2257                                    LED_MODE_DEFAULT);
2258                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2259                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2260         }
2261
2262         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2263         if (word == 0xffff) {
2264                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2265                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2266                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2267                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2268         }
2269
2270         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2271         if (word == 0xffff) {
2272                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2273                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2274                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2275                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2276         } else {
2277                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2278                 if (value < -10 || value > 10)
2279                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2280                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2281                 if (value < -10 || value > 10)
2282                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2283                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2284         }
2285
2286         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2287         if (word == 0xffff) {
2288                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2289                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2290                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2291                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2292         } else {
2293                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2294                 if (value < -10 || value > 10)
2295                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2296                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2297                 if (value < -10 || value > 10)
2298                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2299                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2300         }
2301
2302         return 0;
2303 }
2304
2305 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2306 {
2307         u32 reg;
2308         u16 value;
2309         u16 eeprom;
2310
2311         /*
2312          * Read EEPROM word for configuration.
2313          */
2314         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2315
2316         /*
2317          * Identify RF chipset.
2318          */
2319         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2320         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2321         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2322                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2323
2324         if (!rt2x00_rf(rt2x00dev, RF5225) &&
2325             !rt2x00_rf(rt2x00dev, RF5325) &&
2326             !rt2x00_rf(rt2x00dev, RF2527) &&
2327             !rt2x00_rf(rt2x00dev, RF2529)) {
2328                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2329                 return -ENODEV;
2330         }
2331
2332         /*
2333          * Determine number of antennas.
2334          */
2335         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2336                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2337
2338         /*
2339          * Identify default antenna configuration.
2340          */
2341         rt2x00dev->default_ant.tx =
2342             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2343         rt2x00dev->default_ant.rx =
2344             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2345
2346         /*
2347          * Read the Frame type.
2348          */
2349         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2350                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2351
2352         /*
2353          * Detect if this device has a hardware controlled radio.
2354          */
2355         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2356                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2357
2358         /*
2359          * Read frequency offset and RF programming sequence.
2360          */
2361         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2362         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2363                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2364
2365         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2366
2367         /*
2368          * Read external LNA informations.
2369          */
2370         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2371
2372         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2373                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2374         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2375                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2376
2377         /*
2378          * When working with a RF2529 chip without double antenna,
2379          * the antenna settings should be gathered from the NIC
2380          * eeprom word.
2381          */
2382         if (rt2x00_rf(rt2x00dev, RF2529) &&
2383             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2384                 rt2x00dev->default_ant.rx =
2385                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2386                 rt2x00dev->default_ant.tx =
2387                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2388
2389                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2390                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2391                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2392                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2393         }
2394
2395         /*
2396          * Store led settings, for correct led behaviour.
2397          * If the eeprom value is invalid,
2398          * switch to default led mode.
2399          */
2400 #ifdef CONFIG_RT2X00_LIB_LEDS
2401         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2402         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2403
2404         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2405         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2406         if (value == LED_MODE_SIGNAL_STRENGTH)
2407                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2408                                  LED_TYPE_QUALITY);
2409
2410         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2411         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2412                            rt2x00_get_field16(eeprom,
2413                                               EEPROM_LED_POLARITY_GPIO_0));
2414         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2415                            rt2x00_get_field16(eeprom,
2416                                               EEPROM_LED_POLARITY_GPIO_1));
2417         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2418                            rt2x00_get_field16(eeprom,
2419                                               EEPROM_LED_POLARITY_GPIO_2));
2420         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2421                            rt2x00_get_field16(eeprom,
2422                                               EEPROM_LED_POLARITY_GPIO_3));
2423         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2424                            rt2x00_get_field16(eeprom,
2425                                               EEPROM_LED_POLARITY_GPIO_4));
2426         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2427                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2428         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2429                            rt2x00_get_field16(eeprom,
2430                                               EEPROM_LED_POLARITY_RDY_G));
2431         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2432                            rt2x00_get_field16(eeprom,
2433                                               EEPROM_LED_POLARITY_RDY_A));
2434 #endif /* CONFIG_RT2X00_LIB_LEDS */
2435
2436         return 0;
2437 }
2438
2439 /*
2440  * RF value list for RF5225 & RF5325
2441  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2442  */
2443 static const struct rf_channel rf_vals_noseq[] = {
2444         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2445         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2446         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2447         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2448         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2449         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2450         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2451         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2452         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2453         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2454         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2455         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2456         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2457         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2458
2459         /* 802.11 UNI / HyperLan 2 */
2460         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2461         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2462         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2463         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2464         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2465         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2466         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2467         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2468
2469         /* 802.11 HyperLan 2 */
2470         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2471         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2472         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2473         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2474         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2475         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2476         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2477         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2478         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2479         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2480
2481         /* 802.11 UNII */
2482         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2483         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2484         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2485         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2486         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2487         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2488
2489         /* MMAC(Japan)J52 ch 34,38,42,46 */
2490         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2491         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2492         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2493         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2494 };
2495
2496 /*
2497  * RF value list for RF5225 & RF5325
2498  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2499  */
2500 static const struct rf_channel rf_vals_seq[] = {
2501         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2502         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2503         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2504         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2505         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2506         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2507         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2508         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2509         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2510         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2511         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2512         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2513         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2514         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2515
2516         /* 802.11 UNI / HyperLan 2 */
2517         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2518         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2519         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2520         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2521         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2522         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2523         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2524         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2525
2526         /* 802.11 HyperLan 2 */
2527         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2528         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2529         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2530         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2531         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2532         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2533         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2534         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2535         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2536         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2537
2538         /* 802.11 UNII */
2539         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2540         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2541         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2542         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2543         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2544         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2545
2546         /* MMAC(Japan)J52 ch 34,38,42,46 */
2547         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2548         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2549         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2550         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2551 };
2552
2553 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2554 {
2555         struct hw_mode_spec *spec = &rt2x00dev->spec;
2556         struct channel_info *info;
2557         char *tx_power;
2558         unsigned int i;
2559
2560         /*
2561          * Disable powersaving as default.
2562          */
2563         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2564
2565         /*
2566          * Initialize all hw fields.
2567          */
2568         rt2x00dev->hw->flags =
2569             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2570             IEEE80211_HW_SIGNAL_DBM |
2571             IEEE80211_HW_SUPPORTS_PS |
2572             IEEE80211_HW_PS_NULLFUNC_STACK;
2573
2574         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2575         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2576                                 rt2x00_eeprom_addr(rt2x00dev,
2577                                                    EEPROM_MAC_ADDR_0));
2578
2579         /*
2580          * Initialize hw_mode information.
2581          */
2582         spec->supported_bands = SUPPORT_BAND_2GHZ;
2583         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2584
2585         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2586                 spec->num_channels = 14;
2587                 spec->channels = rf_vals_noseq;
2588         } else {
2589                 spec->num_channels = 14;
2590                 spec->channels = rf_vals_seq;
2591         }
2592
2593         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2594                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2595                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2596         }
2597
2598         /*
2599          * Create channel information array
2600          */
2601         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2602         if (!info)
2603                 return -ENOMEM;
2604
2605         spec->channels_info = info;
2606
2607         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2608         for (i = 0; i < 14; i++)
2609                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2610
2611         if (spec->num_channels > 14) {
2612                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2613                 for (i = 14; i < spec->num_channels; i++)
2614                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2621 {
2622         int retval;
2623
2624         /*
2625          * Disable power saving.
2626          */
2627         rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2628
2629         /*
2630          * Allocate eeprom data.
2631          */
2632         retval = rt61pci_validate_eeprom(rt2x00dev);
2633         if (retval)
2634                 return retval;
2635
2636         retval = rt61pci_init_eeprom(rt2x00dev);
2637         if (retval)
2638                 return retval;
2639
2640         /*
2641          * Initialize hw specifications.
2642          */
2643         retval = rt61pci_probe_hw_mode(rt2x00dev);
2644         if (retval)
2645                 return retval;
2646
2647         /*
2648          * This device has multiple filters for control frames,
2649          * but has no a separate filter for PS Poll frames.
2650          */
2651         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2652
2653         /*
2654          * This device requires firmware and DMA mapped skbs.
2655          */
2656         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2657         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2658         if (!modparam_nohwcrypt)
2659                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2660
2661         /*
2662          * Set the rssi offset.
2663          */
2664         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2665
2666         return 0;
2667 }
2668
2669 /*
2670  * IEEE80211 stack callback functions.
2671  */
2672 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2673                            const struct ieee80211_tx_queue_params *params)
2674 {
2675         struct rt2x00_dev *rt2x00dev = hw->priv;
2676         struct data_queue *queue;
2677         struct rt2x00_field32 field;
2678         int retval;
2679         u32 reg;
2680         u32 offset;
2681
2682         /*
2683          * First pass the configuration through rt2x00lib, that will
2684          * update the queue settings and validate the input. After that
2685          * we are free to update the registers based on the value
2686          * in the queue parameter.
2687          */
2688         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2689         if (retval)
2690                 return retval;
2691
2692         /*
2693          * We only need to perform additional register initialization
2694          * for WMM queues.
2695          */
2696         if (queue_idx >= 4)
2697                 return 0;
2698
2699         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2700
2701         /* Update WMM TXOP register */
2702         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2703         field.bit_offset = (queue_idx & 1) * 16;
2704         field.bit_mask = 0xffff << field.bit_offset;
2705
2706         rt2x00pci_register_read(rt2x00dev, offset, &reg);
2707         rt2x00_set_field32(&reg, field, queue->txop);
2708         rt2x00pci_register_write(rt2x00dev, offset, reg);
2709
2710         /* Update WMM registers */
2711         field.bit_offset = queue_idx * 4;
2712         field.bit_mask = 0xf << field.bit_offset;
2713
2714         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2715         rt2x00_set_field32(&reg, field, queue->aifs);
2716         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2717
2718         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2719         rt2x00_set_field32(&reg, field, queue->cw_min);
2720         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2721
2722         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2723         rt2x00_set_field32(&reg, field, queue->cw_max);
2724         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2725
2726         return 0;
2727 }
2728
2729 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2730 {
2731         struct rt2x00_dev *rt2x00dev = hw->priv;
2732         u64 tsf;
2733         u32 reg;
2734
2735         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2736         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2737         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2738         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2739
2740         return tsf;
2741 }
2742
2743 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2744         .tx                     = rt2x00mac_tx,
2745         .start                  = rt2x00mac_start,
2746         .stop                   = rt2x00mac_stop,
2747         .add_interface          = rt2x00mac_add_interface,
2748         .remove_interface       = rt2x00mac_remove_interface,
2749         .config                 = rt2x00mac_config,
2750         .configure_filter       = rt2x00mac_configure_filter,
2751         .set_tim                = rt2x00mac_set_tim,
2752         .set_key                = rt2x00mac_set_key,
2753         .get_stats              = rt2x00mac_get_stats,
2754         .bss_info_changed       = rt2x00mac_bss_info_changed,
2755         .conf_tx                = rt61pci_conf_tx,
2756         .get_tsf                = rt61pci_get_tsf,
2757         .rfkill_poll            = rt2x00mac_rfkill_poll,
2758 };
2759
2760 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2761         .irq_handler            = rt61pci_interrupt,
2762         .probe_hw               = rt61pci_probe_hw,
2763         .get_firmware_name      = rt61pci_get_firmware_name,
2764         .check_firmware         = rt61pci_check_firmware,
2765         .load_firmware          = rt61pci_load_firmware,
2766         .initialize             = rt2x00pci_initialize,
2767         .uninitialize           = rt2x00pci_uninitialize,
2768         .get_entry_state        = rt61pci_get_entry_state,
2769         .clear_entry            = rt61pci_clear_entry,
2770         .set_device_state       = rt61pci_set_device_state,
2771         .rfkill_poll            = rt61pci_rfkill_poll,
2772         .link_stats             = rt61pci_link_stats,
2773         .reset_tuner            = rt61pci_reset_tuner,
2774         .link_tuner             = rt61pci_link_tuner,
2775         .write_tx_desc          = rt61pci_write_tx_desc,
2776         .write_tx_data          = rt2x00pci_write_tx_data,
2777         .write_beacon           = rt61pci_write_beacon,
2778         .kick_tx_queue          = rt61pci_kick_tx_queue,
2779         .kill_tx_queue          = rt61pci_kill_tx_queue,
2780         .fill_rxdone            = rt61pci_fill_rxdone,
2781         .config_shared_key      = rt61pci_config_shared_key,
2782         .config_pairwise_key    = rt61pci_config_pairwise_key,
2783         .config_filter          = rt61pci_config_filter,
2784         .config_intf            = rt61pci_config_intf,
2785         .config_erp             = rt61pci_config_erp,
2786         .config_ant             = rt61pci_config_ant,
2787         .config                 = rt61pci_config,
2788 };
2789
2790 static const struct data_queue_desc rt61pci_queue_rx = {
2791         .entry_num              = RX_ENTRIES,
2792         .data_size              = DATA_FRAME_SIZE,
2793         .desc_size              = RXD_DESC_SIZE,
2794         .priv_size              = sizeof(struct queue_entry_priv_pci),
2795 };
2796
2797 static const struct data_queue_desc rt61pci_queue_tx = {
2798         .entry_num              = TX_ENTRIES,
2799         .data_size              = DATA_FRAME_SIZE,
2800         .desc_size              = TXD_DESC_SIZE,
2801         .priv_size              = sizeof(struct queue_entry_priv_pci),
2802 };
2803
2804 static const struct data_queue_desc rt61pci_queue_bcn = {
2805         .entry_num              = 4 * BEACON_ENTRIES,
2806         .data_size              = 0, /* No DMA required for beacons */
2807         .desc_size              = TXINFO_SIZE,
2808         .priv_size              = sizeof(struct queue_entry_priv_pci),
2809 };
2810
2811 static const struct rt2x00_ops rt61pci_ops = {
2812         .name                   = KBUILD_MODNAME,
2813         .max_sta_intf           = 1,
2814         .max_ap_intf            = 4,
2815         .eeprom_size            = EEPROM_SIZE,
2816         .rf_size                = RF_SIZE,
2817         .tx_queues              = NUM_TX_QUEUES,
2818         .extra_tx_headroom      = 0,
2819         .rx                     = &rt61pci_queue_rx,
2820         .tx                     = &rt61pci_queue_tx,
2821         .bcn                    = &rt61pci_queue_bcn,
2822         .lib                    = &rt61pci_rt2x00_ops,
2823         .hw                     = &rt61pci_mac80211_ops,
2824 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2825         .debugfs                = &rt61pci_rt2x00debug,
2826 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2827 };
2828
2829 /*
2830  * RT61pci module information.
2831  */
2832 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2833         /* RT2561s */
2834         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2835         /* RT2561 v2 */
2836         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2837         /* RT2661 */
2838         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2839         { 0, }
2840 };
2841
2842 MODULE_AUTHOR(DRV_PROJECT);
2843 MODULE_VERSION(DRV_VERSION);
2844 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2845 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2846                         "PCI & PCMCIA chipset based cards");
2847 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2848 MODULE_FIRMWARE(FIRMWARE_RT2561);
2849 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2850 MODULE_FIRMWARE(FIRMWARE_RT2661);
2851 MODULE_LICENSE("GPL");
2852
2853 static struct pci_driver rt61pci_driver = {
2854         .name           = KBUILD_MODNAME,
2855         .id_table       = rt61pci_device_table,
2856         .probe          = rt2x00pci_probe,
2857         .remove         = __devexit_p(rt2x00pci_remove),
2858         .suspend        = rt2x00pci_suspend,
2859         .resume         = rt2x00pci_resume,
2860 };
2861
2862 static int __init rt61pci_init(void)
2863 {
2864         return pci_register_driver(&rt61pci_driver);
2865 }
2866
2867 static void __exit rt61pci_exit(void)
2868 {
2869         pci_unregister_driver(&rt61pci_driver);
2870 }
2871
2872 module_init(rt61pci_init);
2873 module_exit(rt61pci_exit);