drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2x00usb_register_read and rt2x00usb_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                                H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 126                                   const unsigned int word, const u8 value)
 127 {
 128         u32 reg;
 129
 130         mutex_lock(&rt2x00dev->csr_mutex);
 131
 132         /*
 133          * Wait until the RFCSR becomes available, afterwards we
 134          * can safely write the new data into the register.
 135          */
 136         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 137                 reg = 0;
 138                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 139                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 140                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 141                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 142
 143                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 150                                  const unsigned int word, u8 *value)
 151 {
 152         u32 reg;
 153
 154         mutex_lock(&rt2x00dev->csr_mutex);
 155
 156         /*
 157          * Wait until the RFCSR becomes available, afterwards we
 158          * can safely write the read request into the register.
 159          * After the data has been written, we wait until hardware
 160          * returns the correct value, if at any time the register
 161          * doesn't become available in time, reg will be 0xffffffff
 162          * which means we return 0xff to the caller.
 163          */
 164         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 165                 reg = 0;
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 167                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 168                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 169
 170                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 171
 172                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 173         }
 174
 175         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 176
 177         mutex_unlock(&rt2x00dev->csr_mutex);
 178 }
 179
 180 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 181                                const unsigned int word, const u32 value)
 182 {
 183         u32 reg;
 184
 185         mutex_lock(&rt2x00dev->csr_mutex);
 186
 187         /*
 188          * Wait until the RF becomes available, afterwards we
 189          * can safely write the new data into the register.
 190          */
 191         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 192                 reg = 0;
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 194                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 195                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 196                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 197
 198                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 199                 rt2x00_rf_write(rt2x00dev, word, value);
 200         }
 201
 202         mutex_unlock(&rt2x00dev->csr_mutex);
 203 }
 204
 205 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 206                                   const u8 command, const u8 token,
 207                                   const u8 arg0, const u8 arg1)
 208 {
 209         u32 reg;
 210
 211         mutex_lock(&rt2x00dev->csr_mutex);
 212
 213         /*
 214          * Wait until the MCU becomes available, afterwards we
 215          * can safely write the new data into the register.
 216          */
 217         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 218                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 219                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 220                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 221                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 222                 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 223
 224                 reg = 0;
 225                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 226                 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 227         }
 228
 229         mutex_unlock(&rt2x00dev->csr_mutex);
 230 }
 231
 232 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 233 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 234         .owner  = THIS_MODULE,
 235         .csr    = {
 236                 .read           = rt2x00usb_register_read,
 237                 .write          = rt2x00usb_register_write,
 238                 .flags          = RT2X00DEBUGFS_OFFSET,
 239                 .word_base      = CSR_REG_BASE,
 240                 .word_size      = sizeof(u32),
 241                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 242         },
 243         .eeprom = {
 244                 .read           = rt2x00_eeprom_read,
 245                 .write          = rt2x00_eeprom_write,
 246                 .word_base      = EEPROM_BASE,
 247                 .word_size      = sizeof(u16),
 248                 .word_count     = EEPROM_SIZE / sizeof(u16),
 249         },
 250         .bbp    = {
 251                 .read           = rt2800usb_bbp_read,
 252                 .write          = rt2800usb_bbp_write,
 253                 .word_base      = BBP_BASE,
 254                 .word_size      = sizeof(u8),
 255                 .word_count     = BBP_SIZE / sizeof(u8),
 256         },
 257         .rf     = {
 258                 .read           = rt2x00_rf_read,
 259                 .write          = rt2800usb_rf_write,
 260                 .word_base      = RF_BASE,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT2X00_LIB_RFKILL
 268 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 273         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 274 }
 275 #else
 276 #define rt2800usb_rfkill_poll   NULL
 277 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 278
 279 #ifdef CONFIG_RT2X00_LIB_LEDS
 280 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 281                                      enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int bg_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 288         unsigned int polarity =
 289                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 290                                    EEPROM_FREQ_LED_POLARITY);
 291         unsigned int ledmode =
 292                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 293                                    EEPROM_FREQ_LED_MODE);
 294
 295         if (led->type == LED_TYPE_RADIO) {
 296                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 297                                       enabled ? 0x20 : 0);
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 300                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 301         } else if (led->type == LED_TYPE_QUALITY) {
 302                 /*
 303                  * The brightness is divided into 6 levels (0 - 5),
 304                  * The specs tell us the following levels:
 305                  *      0, 1 ,3, 7, 15, 31
 306                  * to determine the level in a simple way we can simply
 307                  * work with bitshifting:
 308                  *      (1 << level) - 1
 309                  */
 310                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 311                                       (1 << brightness / (LED_FULL / 6)) - 1,
 312                                       polarity);
 313         }
 314 }
 315
 316 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 317                                unsigned long *delay_on,
 318                                unsigned long *delay_off)
 319 {
 320         struct rt2x00_led *led =
 321             container_of(led_cdev, struct rt2x00_led, led_dev);
 322         u32 reg;
 323
 324         rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
 325         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 326         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 327         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 328         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 329         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 330         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 331         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 332         rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
 333
 334         return 0;
 335 }
 336
 337 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 338                                struct rt2x00_led *led,
 339                                enum led_type type)
 340 {
 341         led->rt2x00dev = rt2x00dev;
 342         led->type = type;
 343         led->led_dev.brightness_set = rt2800usb_brightness_set;
 344         led->led_dev.blink_set = rt2800usb_blink_set;
 345         led->flags = LED_INITIALIZED;
 346 }
 347 #endif /* CONFIG_RT2X00_LIB_LEDS */
 348
 349 /*
 350  * Configuration handlers.
 351  */
 352 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 353                                        struct rt2x00lib_crypto *crypto,
 354                                        struct ieee80211_key_conf *key)
 355 {
 356         struct mac_wcid_entry wcid_entry;
 357         struct mac_iveiv_entry iveiv_entry;
 358         u32 offset;
 359         u32 reg;
 360
 361         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 362
 363         rt2x00usb_register_read(rt2x00dev, offset, &reg);
 364         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 365                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 366         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 367                            (crypto->cmd == SET_KEY) * crypto->cipher);
 368         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 369                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 370         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 371         rt2x00usb_register_write(rt2x00dev, offset, reg);
 372
 373         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 374
 375         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 376         if ((crypto->cipher == CIPHER_TKIP) ||
 377             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 378             (crypto->cipher == CIPHER_AES))
 379                 iveiv_entry.iv[3] |= 0x20;
 380         iveiv_entry.iv[3] |= key->keyidx << 6;
 381         rt2x00usb_register_multiwrite(rt2x00dev, offset,
 382                                       &iveiv_entry, sizeof(iveiv_entry));
 383
 384         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 385
 386         memset(&wcid_entry, 0, sizeof(wcid_entry));
 387         if (crypto->cmd == SET_KEY)
 388                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 389         rt2x00usb_register_multiwrite(rt2x00dev, offset,
 390                                       &wcid_entry, sizeof(wcid_entry));
 391 }
 392
 393 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 394                                        struct rt2x00lib_crypto *crypto,
 395                                        struct ieee80211_key_conf *key)
 396 {
 397         struct hw_key_entry key_entry;
 398         struct rt2x00_field32 field;
 399         int timeout;
 400         u32 offset;
 401         u32 reg;
 402
 403         if (crypto->cmd == SET_KEY) {
 404                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 405
 406                 memcpy(key_entry.key, crypto->key,
 407                        sizeof(key_entry.key));
 408                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 409                        sizeof(key_entry.tx_mic));
 410                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 411                        sizeof(key_entry.rx_mic));
 412
 413                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 414                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 415                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 416                                                     USB_VENDOR_REQUEST_OUT,
 417                                                     offset, &key_entry,
 418                                                     sizeof(key_entry),
 419                                                     timeout);
 420         }
 421
 422         /*
 423          * The cipher types are stored over multiple registers
 424          * starting with SHARED_KEY_MODE_BASE each word will have
 425          * 32 bits and contains the cipher types for 2 bssidx each.
 426          * Using the correct defines correctly will cause overhead,
 427          * so just calculate the correct offset.
 428          */
 429         field.bit_offset = 4 * (key->hw_key_idx % 8);
 430         field.bit_mask = 0x7 << field.bit_offset;
 431
 432         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 433
 434         rt2x00usb_register_read(rt2x00dev, offset, &reg);
 435         rt2x00_set_field32(&reg, field,
 436                            (crypto->cmd == SET_KEY) * crypto->cipher);
 437         rt2x00usb_register_write(rt2x00dev, offset, reg);
 438
 439         /*
 440          * Update WCID information
 441          */
 442         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 443
 444         return 0;
 445 }
 446
 447 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 448                                          struct rt2x00lib_crypto *crypto,
 449                                          struct ieee80211_key_conf *key)
 450 {
 451         struct hw_key_entry key_entry;
 452         int timeout;
 453         u32 offset;
 454
 455         if (crypto->cmd == SET_KEY) {
 456                 /*
 457                  * 1 pairwise key is possible per AID, this means that the AID
 458                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 459                  * last possible shared key entry.
 460                  */
 461                 if (crypto->aid > (256 - 32))
 462                         return -ENOSPC;
 463
 464                 key->hw_key_idx = 32 + crypto->aid;
 465
 466                 memcpy(key_entry.key, crypto->key,
 467                        sizeof(key_entry.key));
 468                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 469                        sizeof(key_entry.tx_mic));
 470                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 471                        sizeof(key_entry.rx_mic));
 472
 473                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 474                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 475                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 476                                                     USB_VENDOR_REQUEST_OUT,
 477                                                     offset, &key_entry,
 478                                                     sizeof(key_entry),
 479                                                     timeout);
 480         }
 481
 482         /*
 483          * Update WCID information
 484          */
 485         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 486
 487         return 0;
 488 }
 489
 490 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 491                                     const unsigned int filter_flags)
 492 {
 493         u32 reg;
 494
 495         /*
 496          * Start configuration steps.
 497          * Note that the version error will always be dropped
 498          * and broadcast frames will always be accepted since
 499          * there is no filter for it at this time.
 500          */
 501         rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 503                            !(filter_flags & FIF_FCSFAIL));
 504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 505                            !(filter_flags & FIF_PLCPFAIL));
 506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 507                            !(filter_flags & FIF_PROMISC_IN_BSS));
 508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 509         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 511                            !(filter_flags & FIF_ALLMULTI));
 512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 513         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 515                            !(filter_flags & FIF_CONTROL));
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 517                            !(filter_flags & FIF_CONTROL));
 518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 519                            !(filter_flags & FIF_CONTROL));
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 521                            !(filter_flags & FIF_CONTROL));
 522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 523                            !(filter_flags & FIF_CONTROL));
 524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 525                            !(filter_flags & FIF_CONTROL));
 526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 529                            !(filter_flags & FIF_CONTROL));
 530         rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 531 }
 532
 533 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 534                                   struct rt2x00_intf *intf,
 535                                   struct rt2x00intf_conf *conf,
 536                                   const unsigned int flags)
 537 {
 538         unsigned int beacon_base;
 539         u32 reg;
 540
 541         if (flags & CONFIG_UPDATE_TYPE) {
 542                 /*
 543                  * Clear current synchronisation setup.
 544                  * For the Beacon base registers we only need to clear
 545                  * the first byte since that byte contains the VALID and OWNER
 546                  * bits which (when set to 0) will invalidate the entire beacon.
 547                  */
 548                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 549                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 550
 551                 /*
 552                  * Enable synchronisation.
 553                  */
 554                 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 555                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 556                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 557                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 558                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 559         }
 560
 561         if (flags & CONFIG_UPDATE_MAC) {
 562                 reg = le32_to_cpu(conf->mac[1]);
 563                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 564                 conf->mac[1] = cpu_to_le32(reg);
 565
 566                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 567                                               conf->mac, sizeof(conf->mac));
 568         }
 569
 570         if (flags & CONFIG_UPDATE_BSSID) {
 571                 reg = le32_to_cpu(conf->bssid[1]);
 572                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 573                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 574                 conf->bssid[1] = cpu_to_le32(reg);
 575
 576                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 577                                               conf->bssid, sizeof(conf->bssid));
 578         }
 579 }
 580
 581 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 582                                  struct rt2x00lib_erp *erp)
 583 {
 584         u32 reg;
 585
 586         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 587         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 588                            DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
 589         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 590
 591         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 592         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 593                            !!erp->short_preamble);
 594         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 595                            !!erp->short_preamble);
 596         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 597
 598         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 599         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 600                            erp->cts_protection ? 2 : 0);
 601         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 602
 603         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 604                                  erp->basic_rates);
 605         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 606
 607         rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 608         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 609         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 610         rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 611
 612         rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 614         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 615         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 616         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 617         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 618         rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 619 }
 620
 621 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 622                                  struct antenna_setup *ant)
 623 {
 624         u8 r1;
 625         u8 r3;
 626
 627         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 628         rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 629
 630         /*
 631          * Configure the TX antenna.
 632          */
 633         switch ((int)ant->tx) {
 634         case 1:
 635                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 636                 break;
 637         case 2:
 638                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 639                 break;
 640         case 3:
 641                 /* Do nothing */
 642                 break;
 643         }
 644
 645         /*
 646          * Configure the RX antenna.
 647          */
 648         switch ((int)ant->rx) {
 649         case 1:
 650                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 651                 break;
 652         case 2:
 653                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 654                 break;
 655         case 3:
 656                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 657                 break;
 658         }
 659
 660         rt2800usb_bbp_write(rt2x00dev, 3, r3);
 661         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 662 }
 663
 664 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 665                                       struct rt2x00lib_conf *libconf)
 666 {
 667         u16 eeprom;
 668         short lna_gain;
 669
 670         if (libconf->rf.channel <= 14) {
 671                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 672                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 673         } else if (libconf->rf.channel <= 64) {
 674                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 675                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 676         } else if (libconf->rf.channel <= 128) {
 677                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 678                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 679         } else {
 680                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 681                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 682         }
 683
 684         rt2x00dev->lna_gain = lna_gain;
 685 }
 686
 687 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 688                                           struct ieee80211_conf *conf,
 689                                           struct rf_channel *rf,
 690                                           struct channel_info *info)
 691 {
 692         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 693
 694         if (rt2x00dev->default_ant.tx == 1)
 695                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 696
 697         if (rt2x00dev->default_ant.rx == 1) {
 698                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 699                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 700         } else if (rt2x00dev->default_ant.rx == 2)
 701                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 702
 703         if (rf->channel > 14) {
 704                 /*
 705                  * When TX power is below 0, we should increase it by 7 to
 706                  * make it a positive value (Minumum value is -7).
 707                  * However this means that values between 0 and 7 have
 708                  * double meaning, and we should set a 7DBm boost flag.
 709                  */
 710                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 711                                    (info->tx_power1 >= 0));
 712
 713                 if (info->tx_power1 < 0)
 714                         info->tx_power1 += 7;
 715
 716                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 717                                    TXPOWER_A_TO_DEV(info->tx_power1));
 718
 719                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 720                                    (info->tx_power2 >= 0));
 721
 722                 if (info->tx_power2 < 0)
 723                         info->tx_power2 += 7;
 724
 725                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 726                                    TXPOWER_A_TO_DEV(info->tx_power2));
 727         } else {
 728                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 729                                    TXPOWER_G_TO_DEV(info->tx_power1));
 730                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 731                                    TXPOWER_G_TO_DEV(info->tx_power2));
 732         }
 733
 734         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 735
 736         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 737         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 738         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 739         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 740
 741         udelay(200);
 742
 743         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 744         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 745         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 746         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 747
 748         udelay(200);
 749
 750         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 751         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 752         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 753         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 754 }
 755
 756 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 757                                           struct ieee80211_conf *conf,
 758                                           struct rf_channel *rf,
 759                                           struct channel_info *info)
 760 {
 761         u8 rfcsr;
 762
 763         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 764         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 765
 766         rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 767         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 768         rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 769
 770         rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 771         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 772                           TXPOWER_G_TO_DEV(info->tx_power1));
 773         rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 774
 775         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 776         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 777         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 778
 779         rt2800usb_rfcsr_write(rt2x00dev, 24,
 780                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 781
 782         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 783         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 784         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 785 }
 786
 787 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 788                                      struct ieee80211_conf *conf,
 789                                      struct rf_channel *rf,
 790                                      struct channel_info *info)
 791 {
 792         u32 reg;
 793         unsigned int tx_pin;
 794         u8 bbp;
 795
 796         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 797                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 798         else
 799                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 800
 801         /*
 802          * Change BBP settings
 803          */
 804         rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 805         rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 806         rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 807         rt2800usb_bbp_write(rt2x00dev, 86, 0);
 808
 809         if (rf->channel <= 14) {
 810                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 811                         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 812                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 813                 } else {
 814                         rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 815                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 816                 }
 817         } else {
 818                 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 819
 820                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 821                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 822                 else
 823                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 824         }
 825
 826         rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 827         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 828         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 829         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 830         rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 831
 832         tx_pin = 0;
 833
 834         /* Turn on unused PA or LNA when not using 1T or 1R */
 835         if (rt2x00dev->default_ant.tx != 1) {
 836                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 837                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 838         }
 839
 840         /* Turn on unused PA or LNA when not using 1T or 1R */
 841         if (rt2x00dev->default_ant.rx != 1) {
 842                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 843                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 844         }
 845
 846         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 847         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 848         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 849         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 850         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 851         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 852
 853         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 854
 855         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
 856         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 857         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
 858
 859         rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
 860         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 861         rt2800usb_bbp_write(rt2x00dev, 3, bbp);
 862
 863         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 864                 if (conf_is_ht40(conf)) {
 865                         rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
 866                         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
 867                         rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
 868                 } else {
 869                         rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
 870                         rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
 871                         rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
 872                 }
 873         }
 874
 875         msleep(1);
 876 }
 877
 878 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 879                                      const int txpower)
 880 {
 881         u32 reg;
 882         u32 value = TXPOWER_G_TO_DEV(txpower);
 883         u8 r1;
 884
 885         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 886         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 887         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 888
 889         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 890         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 891         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 892         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 893         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 894         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 895         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 896         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 897         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 898         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 899
 900         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 901         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 902         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 903         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 909         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 910
 911         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 912         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 913         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 920         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 921
 922         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 923         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 931         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 932
 933         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 938         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 939 }
 940
 941 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 942                                          struct rt2x00lib_conf *libconf)
 943 {
 944         u32 reg;
 945
 946         rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 947         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 948                            libconf->conf->short_frame_max_tx_count);
 949         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 950                            libconf->conf->long_frame_max_tx_count);
 951         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 952         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 953         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 954         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 955         rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
 956 }
 957
 958 static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
 959                                       struct rt2x00lib_conf *libconf)
 960 {
 961         u32 reg;
 962
 963         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 964         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 965                            libconf->conf->beacon_int * 16);
 966         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 967 }
 968
 969 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 970                                 struct rt2x00lib_conf *libconf)
 971 {
 972         enum dev_state state =
 973             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 974                 STATE_SLEEP : STATE_AWAKE;
 975         u32 reg;
 976
 977         if (state == STATE_SLEEP) {
 978                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 979
 980                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 981                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 982                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 983                                    libconf->conf->listen_interval - 1);
 984                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 985                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 986
 987                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 988         } else {
 989                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
 990
 991                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 992                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 993                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 994                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 995                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 996         }
 997 }
 998
 999 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1000                              struct rt2x00lib_conf *libconf,
1001                              const unsigned int flags)
1002 {
1003         /* Always recalculate LNA gain before changing configuration */
1004         rt2800usb_config_lna_gain(rt2x00dev, libconf);
1005
1006         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1007                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1008                                          &libconf->rf, &libconf->channel);
1009         if (flags & IEEE80211_CONF_CHANGE_POWER)
1010                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1011         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1012                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1013         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1014                 rt2800usb_config_duration(rt2x00dev, libconf);
1015         if (flags & IEEE80211_CONF_CHANGE_PS)
1016                 rt2800usb_config_ps(rt2x00dev, libconf);
1017 }
1018
1019 /*
1020  * Link tuning
1021  */
1022 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1023                                  struct link_qual *qual)
1024 {
1025         u32 reg;
1026
1027         /*
1028          * Update FCS error count from register.
1029          */
1030         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1031         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1032 }
1033
1034 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1035 {
1036         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1037                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1038                         return 0x1c + (2 * rt2x00dev->lna_gain);
1039                 else
1040                         return 0x2e + rt2x00dev->lna_gain;
1041         }
1042
1043         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1044                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1045         else
1046                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1047 }
1048
1049 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1050                                      struct link_qual *qual, u8 vgc_level)
1051 {
1052         if (qual->vgc_level != vgc_level) {
1053                 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1054                 qual->vgc_level = vgc_level;
1055                 qual->vgc_level_reg = vgc_level;
1056         }
1057 }
1058
1059 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1060                                   struct link_qual *qual)
1061 {
1062         rt2800usb_set_vgc(rt2x00dev, qual,
1063                           rt2800usb_get_default_vgc(rt2x00dev));
1064 }
1065
1066 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1067                                  struct link_qual *qual, const u32 count)
1068 {
1069         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1070                 return;
1071
1072         /*
1073          * When RSSI is better then -80 increase VGC level with 0x10
1074          */
1075         rt2800usb_set_vgc(rt2x00dev, qual,
1076                           rt2800usb_get_default_vgc(rt2x00dev) +
1077                           ((qual->rssi > -80) * 0x10));
1078 }
1079
1080 /*
1081  * Firmware functions
1082  */
1083 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1084 {
1085         return FIRMWARE_RT2870;
1086 }
1087
1088 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1089 {
1090         u16 fw_crc;
1091         u16 crc;
1092
1093         /*
1094          * The last 2 bytes in the firmware array are the crc checksum itself,
1095          * this means that we should never pass those 2 bytes to the crc
1096          * algorithm.
1097          */
1098         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1099
1100         /*
1101          * Use the crc ccitt algorithm.
1102          * This will return the same value as the legacy driver which
1103          * used bit ordering reversion on the both the firmware bytes
1104          * before input input as well as on the final output.
1105          * Obviously using crc ccitt directly is much more efficient.
1106          */
1107         crc = crc_ccitt(~0, data, len - 2);
1108
1109         /*
1110          * There is a small difference between the crc-itu-t + bitrev and
1111          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1112          * will be swapped, use swab16 to convert the crc to the correct
1113          * value.
1114          */
1115         crc = swab16(crc);
1116
1117         return fw_crc == crc;
1118 }
1119
1120 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1121                                     const u8 *data, const size_t len)
1122 {
1123         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1124         size_t offset = 0;
1125
1126         /*
1127          * Firmware files:
1128          * There are 2 variations of the rt2870 firmware.
1129          * a) size: 4kb
1130          * b) size: 8kb
1131          * Note that (b) contains 2 seperate firmware blobs of 4k
1132          * within the file. The first blob is the same firmware as (a),
1133          * but the second blob is for the additional chipsets.
1134          */
1135         if (len != 4096 && len != 8192)
1136                 return FW_BAD_LENGTH;
1137
1138         /*
1139          * Check if we need the upper 4kb firmware data or not.
1140          */
1141         if ((len == 4096) &&
1142             (chipset != 0x2860) &&
1143             (chipset != 0x2872) &&
1144             (chipset != 0x3070))
1145                 return FW_BAD_VERSION;
1146
1147         /*
1148          * 8kb firmware files must be checked as if it were
1149          * 2 seperate firmware files.
1150          */
1151         while (offset < len) {
1152                 if (!rt2800usb_check_crc(data + offset, 4096))
1153                         return FW_BAD_CRC;
1154
1155                 offset += 4096;
1156         }
1157
1158         return FW_OK;
1159 }
1160
1161 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1162                                    const u8 *data, const size_t len)
1163 {
1164         unsigned int i;
1165         int status;
1166         u32 reg;
1167         u32 offset;
1168         u32 length;
1169         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1170
1171         /*
1172          * Check which section of the firmware we need.
1173          */
1174         if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1175                 offset = 0;
1176                 length = 4096;
1177         } else {
1178                 offset = 4096;
1179                 length = 4096;
1180         }
1181
1182         /*
1183          * Wait for stable hardware.
1184          */
1185         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1186                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1187                 if (reg && reg != ~0)
1188                         break;
1189                 msleep(1);
1190         }
1191
1192         if (i == REGISTER_BUSY_COUNT) {
1193                 ERROR(rt2x00dev, "Unstable hardware.\n");
1194                 return -EBUSY;
1195         }
1196
1197         /*
1198          * Write firmware to device.
1199          */
1200         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1201                                             USB_VENDOR_REQUEST_OUT,
1202                                             FIRMWARE_IMAGE_BASE,
1203                                             data + offset, length,
1204                                             REGISTER_TIMEOUT32(length));
1205
1206         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1207         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1208
1209         /*
1210          * Send firmware request to device to load firmware,
1211          * we need to specify a long timeout time.
1212          */
1213         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1214                                              0, USB_MODE_FIRMWARE,
1215                                              REGISTER_TIMEOUT_FIRMWARE);
1216         if (status < 0) {
1217                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1218                 return status;
1219         }
1220
1221         /*
1222          * Wait for device to stabilize.
1223          */
1224         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1225                 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1226                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1227                         break;
1228                 msleep(1);
1229         }
1230
1231         if (i == REGISTER_BUSY_COUNT) {
1232                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1233                 return -EBUSY;
1234         }
1235
1236         /*
1237          * Initialize firmware.
1238          */
1239         rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1240         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1241         msleep(1);
1242
1243         return 0;
1244 }
1245
1246 /*
1247  * Initialization functions.
1248  */
1249 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1250 {
1251         u32 reg;
1252         unsigned int i;
1253
1254         /*
1255          * Wait untill BBP and RF are ready.
1256          */
1257         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1258                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1259                 if (reg && reg != ~0)
1260                         break;
1261                 msleep(1);
1262         }
1263
1264         if (i == REGISTER_BUSY_COUNT) {
1265                 ERROR(rt2x00dev, "Unstable hardware.\n");
1266                 return -EBUSY;
1267         }
1268
1269         rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1270         rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1271
1272         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1273         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1274         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1275         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1276
1277         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1278
1279         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1280                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1281
1282         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1283
1284         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1285         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1286         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1287         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1288         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1289         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1290
1291         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1292         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1293         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1294         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1295         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1296         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1297
1298         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1299         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1300
1301         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1302
1303         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1304         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1305         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1306         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1307         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1308         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1309         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1310         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1311
1312         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1313                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1314                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1315                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1316         } else {
1317                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1318                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1319         }
1320
1321         rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1322         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1323         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1324         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1325         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1326         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1327         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1328         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1329         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1330         rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1331
1332         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1333         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1334         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1335         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1336
1337         rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1338         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1339         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1340             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1341                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1342         else
1343                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1344         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1345         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1346         rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1347
1348         rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1349
1350         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1351         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1352         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1353         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1354         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1355         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1356         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1357
1358         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1359         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1360         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1361         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1362         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1363         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1364         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1365         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1366         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1367         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1368         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1369
1370         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1371         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1372         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1373         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1374         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1375         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1376         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1377         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1378         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1379         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1380         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1381
1382         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1383         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1384         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1385         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1386         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1387         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1388         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1389         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1390         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1391         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1392         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1393
1394         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1395         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1396         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1397         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1398         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1399         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1400         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1401         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1402         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1403         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1404         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1405
1406         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1407         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1408         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1409         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1410         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1411         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1412         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1413         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1414         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1415         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1416         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1417
1418         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1419         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1420         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1421         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1422         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1423         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1424         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1425         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1426         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1427         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1428         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1429
1430         rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1431
1432         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1433         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1434         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1435         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1436         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1437         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1438         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1439         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1442         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1443
1444         rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1445         rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1446
1447         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1448         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1449         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1450                            IEEE80211_MAX_RTS_THRESHOLD);
1451         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1452         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1453
1454         rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1455         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1456
1457         /*
1458          * ASIC will keep garbage value after boot, clear encryption keys.
1459          */
1460         for (i = 0; i < 256; i++) {
1461                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1462                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1463                                               wcid, sizeof(wcid));
1464
1465                 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1466                 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1467         }
1468
1469         for (i = 0; i < 16; i++)
1470                 rt2x00usb_register_write(rt2x00dev,
1471                                          SHARED_KEY_MODE_ENTRY(i), 0);
1472
1473         /*
1474          * Clear all beacons
1475          * For the Beacon base registers we only need to clear
1476          * the first byte since that byte contains the VALID and OWNER
1477          * bits which (when set to 0) will invalidate the entire beacon.
1478          */
1479         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1480         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1481         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1482         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1483         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1484         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1485         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1486         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1487
1488         rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1489         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1490         rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1491
1492         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1493         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1494         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1495         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1496         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1497         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1498         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1499         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1500         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1501         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1502
1503         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1504         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1505         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1506         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1507         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1508         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1509         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1510         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1511         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1512         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1513
1514         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1515         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1516         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1517         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1518         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1519         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1520         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1521         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1522         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1523         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1524
1525         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1526         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1527         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1528         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1529         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1530         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1531
1532         /*
1533          * We must clear the error counters.
1534          * These registers are cleared on read,
1535          * so we may pass a useless variable to store the value.
1536          */
1537         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1538         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1539         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1540         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1541         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1542         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1543
1544         return 0;
1545 }
1546
1547 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1548 {
1549         unsigned int i;
1550         u32 reg;
1551
1552         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1553                 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1554                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1555                         return 0;
1556
1557                 udelay(REGISTER_BUSY_DELAY);
1558         }
1559
1560         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1561         return -EACCES;
1562 }
1563
1564 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1565 {
1566         unsigned int i;
1567         u8 value;
1568
1569         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1570                 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1571                 if ((value != 0xff) && (value != 0x00))
1572                         return 0;
1573                 udelay(REGISTER_BUSY_DELAY);
1574         }
1575
1576         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1577         return -EACCES;
1578 }
1579
1580 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1581 {
1582         unsigned int i;
1583         u16 eeprom;
1584         u8 reg_id;
1585         u8 value;
1586
1587         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1588                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1589                 return -EACCES;
1590
1591         rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1592         rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1593         rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1594         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1595         rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1596         rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1597         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1598         rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1599         rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1600         rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1601         rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1602         rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1603         rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1604         rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1605
1606         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1607                 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1608                 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1609         }
1610
1611         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1612                 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1613         }
1614
1615         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1616                 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1617                 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1618                 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1619         }
1620
1621         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1622                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1623
1624                 if (eeprom != 0xffff && eeprom != 0x0000) {
1625                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1626                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1627                         rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1628                 }
1629         }
1630
1631         return 0;
1632 }
1633
1634 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1635                                    bool bw40, u8 rfcsr24, u8 filter_target)
1636 {
1637         unsigned int i;
1638         u8 bbp;
1639         u8 rfcsr;
1640         u8 passband;
1641         u8 stopband;
1642         u8 overtuned = 0;
1643
1644         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1645
1646         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1647         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1648         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1649
1650         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1651         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1652         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1653
1654         /*
1655          * Set power & frequency of passband test tone
1656          */
1657         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1658
1659         for (i = 0; i < 100; i++) {
1660                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1661                 msleep(1);
1662
1663                 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1664                 if (passband)
1665                         break;
1666         }
1667
1668         /*
1669          * Set power & frequency of stopband test tone
1670          */
1671         rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1672
1673         for (i = 0; i < 100; i++) {
1674                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1675                 msleep(1);
1676
1677                 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1678
1679                 if ((passband - stopband) <= filter_target) {
1680                         rfcsr24++;
1681                         overtuned += ((passband - stopband) == filter_target);
1682                 } else
1683                         break;
1684
1685                 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1686         }
1687
1688         rfcsr24 -= !!overtuned;
1689
1690         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1691         return rfcsr24;
1692 }
1693
1694 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1695 {
1696         u8 rfcsr;
1697         u8 bbp;
1698
1699         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1700                 return 0;
1701
1702         /*
1703          * Init RF calibration.
1704          */
1705         rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1706         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1707         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1708         msleep(1);
1709         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1710         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1711
1712         rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1713         rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1714         rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1715         rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1716         rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1717         rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1718         rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1719         rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1720         rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1721         rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1722         rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1723         rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1724         rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1725         rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1726         rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1727         rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1728         rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1729         rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1730         rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1731         rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1732
1733         /*
1734          * Set RX Filter calibration for 20MHz and 40MHz
1735          */
1736         rt2x00dev->calibration[0] =
1737             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1738         rt2x00dev->calibration[1] =
1739             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1740
1741         /*
1742          * Set back to initial state
1743          */
1744         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1745
1746         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1747         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1748         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1749
1750         /*
1751          * set BBP back to BW20
1752          */
1753         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1754         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1755         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Device state switch handlers.
1762  */
1763 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1764                                 enum dev_state state)
1765 {
1766         u32 reg;
1767
1768         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1769         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1770                            (state == STATE_RADIO_RX_ON) ||
1771                            (state == STATE_RADIO_RX_ON_LINK));
1772         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1773 }
1774
1775 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1776 {
1777         unsigned int i;
1778         u32 reg;
1779
1780         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1781                 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1782                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1783                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1784                         return 0;
1785
1786                 msleep(1);
1787         }
1788
1789         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1790         return -EACCES;
1791 }
1792
1793 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1794 {
1795         u32 reg;
1796         u16 word;
1797
1798         /*
1799          * Initialize all registers.
1800          */
1801         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1802                      rt2800usb_init_registers(rt2x00dev) ||
1803                      rt2800usb_init_bbp(rt2x00dev) ||
1804                      rt2800usb_init_rfcsr(rt2x00dev)))
1805                 return -EIO;
1806
1807         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1808         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1809         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1810
1811         udelay(50);
1812
1813         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1814         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1815         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1816         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1817         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1818
1819
1820         rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1821         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1822         /* Don't use bulk in aggregation when working with USB 1.1 */
1823         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1824                            (rt2x00dev->rx->usb_maxpacket == 512));
1825         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1826         /* FIXME: Calculate this value based on Aggregation defines */
1827         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1828         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1829         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1830         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1831
1832         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1833         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1834         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1835         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1836
1837         /*
1838          * Send signal to firmware during boot time.
1839          */
1840         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1841
1842         /*
1843          * Initialize LED control
1844          */
1845         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1846         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1847                               word & 0xff, (word >> 8) & 0xff);
1848
1849         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1850         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1851                               word & 0xff, (word >> 8) & 0xff);
1852
1853         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1854         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1855                               word & 0xff, (word >> 8) & 0xff);
1856
1857         return 0;
1858 }
1859
1860 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1861 {
1862         u32 reg;
1863
1864         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1865         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1866         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1867         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1868
1869         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1870         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1871         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1872
1873         /* Wait for DMA, ignore error */
1874         rt2800usb_wait_wpdma_ready(rt2x00dev);
1875
1876         rt2x00usb_disable_radio(rt2x00dev);
1877 }
1878
1879 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1880                                enum dev_state state)
1881 {
1882         rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1883
1884         if (state == STATE_AWAKE)
1885                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1886         else
1887                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1888
1889         return 0;
1890 }
1891
1892 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1893                                       enum dev_state state)
1894 {
1895         int retval = 0;
1896
1897         switch (state) {
1898         case STATE_RADIO_ON:
1899                 /*
1900                  * Before the radio can be enabled, the device first has
1901                  * to be woken up. After that it needs a bit of time
1902                  * to be fully awake and the radio can be enabled.
1903                  */
1904                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1905                 msleep(1);
1906                 retval = rt2800usb_enable_radio(rt2x00dev);
1907                 break;
1908         case STATE_RADIO_OFF:
1909                 /*
1910                  * After the radio has been disablee, the device should
1911                  * be put to sleep for powersaving.
1912                  */
1913                 rt2800usb_disable_radio(rt2x00dev);
1914                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1915                 break;
1916         case STATE_RADIO_RX_ON:
1917         case STATE_RADIO_RX_ON_LINK:
1918         case STATE_RADIO_RX_OFF:
1919         case STATE_RADIO_RX_OFF_LINK:
1920                 rt2800usb_toggle_rx(rt2x00dev, state);
1921                 break;
1922         case STATE_RADIO_IRQ_ON:
1923         case STATE_RADIO_IRQ_OFF:
1924                 /* No support, but no error either */
1925                 break;
1926         case STATE_DEEP_SLEEP:
1927         case STATE_SLEEP:
1928         case STATE_STANDBY:
1929         case STATE_AWAKE:
1930                 retval = rt2800usb_set_state(rt2x00dev, state);
1931                 break;
1932         default:
1933                 retval = -ENOTSUPP;
1934                 break;
1935         }
1936
1937         if (unlikely(retval))
1938                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1939                       state, retval);
1940
1941         return retval;
1942 }
1943
1944 /*
1945  * TX descriptor initialization
1946  */
1947 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1948                                     struct sk_buff *skb,
1949                                     struct txentry_desc *txdesc)
1950 {
1951         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1952         __le32 *txi = skbdesc->desc;
1953         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1954         u32 word;
1955
1956         /*
1957          * Initialize TX Info descriptor
1958          */
1959         rt2x00_desc_read(txwi, 0, &word);
1960         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1961                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1962         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1963         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1964         rt2x00_set_field32(&word, TXWI_W0_TS,
1965                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1966         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1967                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1968         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1969         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1970         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1971         rt2x00_set_field32(&word, TXWI_W0_BW,
1972                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1973         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1974                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1975         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1976         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1977         rt2x00_desc_write(txwi, 0, word);
1978
1979         rt2x00_desc_read(txwi, 1, &word);
1980         rt2x00_set_field32(&word, TXWI_W1_ACK,
1981                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1982         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1983                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1984         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1985         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1986                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1987                                txdesc->key_idx : 0xff);
1988         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
1989                            skb->len - txdesc->l2pad);
1990         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1991                            skbdesc->entry->entry_idx);
1992         rt2x00_desc_write(txwi, 1, word);
1993
1994         /*
1995          * Always write 0 to IV/EIV fields, hardware will insert the IV
1996          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
1997          * When TXINFO_W0_WIV is set to 1 it will use the IV data
1998          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1999          * crypto entry in the registers should be used to encrypt the frame.
2000          */
2001         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2002         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2003
2004         /*
2005          * Initialize TX descriptor
2006          */
2007         rt2x00_desc_read(txi, 0, &word);
2008         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2009                            skb->len + TXWI_DESC_SIZE);
2010         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2011                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2012         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2013         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2014         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2015         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2016                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2017         rt2x00_desc_write(txi, 0, word);
2018 }
2019
2020 /*
2021  * TX data initialization
2022  */
2023 static void rt2800usb_write_beacon(struct queue_entry *entry)
2024 {
2025         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2026         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2027         unsigned int beacon_base;
2028         u32 reg;
2029
2030         /*
2031          * Add the descriptor in front of the skb.
2032          */
2033         skb_push(entry->skb, entry->queue->desc_size);
2034         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2035         skbdesc->desc = entry->skb->data;
2036
2037         /*
2038          * Disable beaconing while we are reloading the beacon data,
2039          * otherwise we might be sending out invalid data.
2040          */
2041         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2042         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2043         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2044         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2045         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2046
2047         /*
2048          * Write entire beacon with descriptor to register.
2049          */
2050         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2051         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2052                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2053                                             entry->skb->data, entry->skb->len,
2054                                             REGISTER_TIMEOUT32(entry->skb->len));
2055
2056         /*
2057          * Clean up the beacon skb.
2058          */
2059         dev_kfree_skb(entry->skb);
2060         entry->skb = NULL;
2061 }
2062
2063 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2064 {
2065         int length;
2066
2067         /*
2068          * The length _must_ include 4 bytes padding,
2069          * it should always be multiple of 4,
2070          * but it must _not_ be a multiple of the USB packet size.
2071          */
2072         length = roundup(entry->skb->len + 4, 4);
2073         length += (4 * !(length % entry->queue->usb_maxpacket));
2074
2075         return length;
2076 }
2077
2078 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2079                                     const enum data_queue_qid queue)
2080 {
2081         u32 reg;
2082
2083         if (queue != QID_BEACON) {
2084                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2085                 return;
2086         }
2087
2088         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2089         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2090                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2091                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2092                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2093                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2094         }
2095 }
2096
2097 /*
2098  * RX control handlers
2099  */
2100 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2101                                   struct rxdone_entry_desc *rxdesc)
2102 {
2103         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2104         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2105         __le32 *rxd = (__le32 *)entry->skb->data;
2106         __le32 *rxwi;
2107         u32 rxd0;
2108         u32 rxwi0;
2109         u32 rxwi1;
2110         u32 rxwi2;
2111         u32 rxwi3;
2112
2113         /*
2114          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2115          * moving of frame data in rt2x00usb.
2116          */
2117         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2118         rxd = (__le32 *)skbdesc->desc;
2119         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2120
2121         /*
2122          * It is now safe to read the descriptor on all architectures.
2123          */
2124         rt2x00_desc_read(rxd, 0, &rxd0);
2125         rt2x00_desc_read(rxwi, 0, &rxwi0);
2126         rt2x00_desc_read(rxwi, 1, &rxwi1);
2127         rt2x00_desc_read(rxwi, 2, &rxwi2);
2128         rt2x00_desc_read(rxwi, 3, &rxwi3);
2129
2130         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2131                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2132
2133         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2134                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2135                 rxdesc->cipher_status =
2136                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2137         }
2138
2139         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2140                 /*
2141                  * Hardware has stripped IV/EIV data from 802.11 frame during
2142                  * decryption. Unfortunately the descriptor doesn't contain
2143                  * any fields with the EIV/IV data either, so they can't
2144                  * be restored by rt2x00lib.
2145                  */
2146                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2147
2148                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2149                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2150                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2151                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2152         }
2153
2154         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2155                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2156
2157         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD))
2158                 rxdesc->dev_flags |= RXDONE_L2PAD;
2159
2160         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2161                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2162
2163         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2164                 rxdesc->flags |= RX_FLAG_40MHZ;
2165
2166         /*
2167          * Detect RX rate, always use MCS as signal type.
2168          */
2169         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2170         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2171         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2172
2173         /*
2174          * Mask of 0x8 bit to remove the short preamble flag.
2175          */
2176         if (rxdesc->rate_mode == RATE_MODE_CCK)
2177                 rxdesc->signal &= ~0x8;
2178
2179         rxdesc->rssi =
2180             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2181              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2182
2183         rxdesc->noise =
2184             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2185              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2186
2187         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2188
2189         /*
2190          * Remove RXWI descriptor from start of buffer.
2191          */
2192         skb_pull(entry->skb, skbdesc->desc_len);
2193         skb_trim(entry->skb, rxdesc->size);
2194 }
2195
2196 /*
2197  * Device probe functions.
2198  */
2199 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2200 {
2201         u16 word;
2202         u8 *mac;
2203         u8 default_lna_gain;
2204
2205         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2206
2207         /*
2208          * Start validation of the data that has been read.
2209          */
2210         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2211         if (!is_valid_ether_addr(mac)) {
2212                 DECLARE_MAC_BUF(macbuf);
2213
2214                 random_ether_addr(mac);
2215                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2216         }
2217
2218         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2219         if (word == 0xffff) {
2220                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2221                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2222                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2223                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2224                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2225         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2226                 /*
2227                  * There is a max of 2 RX streams for RT2870 series
2228                  */
2229                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2230                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2231                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2232         }
2233
2234         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2235         if (word == 0xffff) {
2236                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2237                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2238                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2239                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2240                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2241                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2242                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2243                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2244                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2245                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2246                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2247                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2248         }
2249
2250         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2251         if ((word & 0x00ff) == 0x00ff) {
2252                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2253                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2254                                    LED_MODE_TXRX_ACTIVITY);
2255                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2256                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2257                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2258                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2259                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2260                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2261         }
2262
2263         /*
2264          * During the LNA validation we are going to use
2265          * lna0 as correct value. Note that EEPROM_LNA
2266          * is never validated.
2267          */
2268         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2269         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2270
2271         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2272         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2273                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2274         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2275                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2276         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2277
2278         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2279         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2280                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2281         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2282             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2283                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2284                                    default_lna_gain);
2285         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2286
2287         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2288         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2289                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2290         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2291                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2292         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2293
2294         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2295         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2296                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2297         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2298             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2299                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2300                                    default_lna_gain);
2301         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2302
2303         return 0;
2304 }
2305
2306 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2307 {
2308         u32 reg;
2309         u16 value;
2310         u16 eeprom;
2311
2312         /*
2313          * Read EEPROM word for configuration.
2314          */
2315         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2316
2317         /*
2318          * Identify RF chipset.
2319          */
2320         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2321         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2322         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2323
2324         /*
2325          * The check for rt2860 is not a typo, some rt2870 hardware
2326          * identifies itself as rt2860 in the CSR register.
2327          */
2328         if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2329             (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
2330             (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
2331                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2332                 return -ENODEV;
2333         }
2334
2335         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2336             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2337             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2338             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2339             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2340             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2341                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2342                 return -ENODEV;
2343         }
2344
2345         /*
2346          * Identify default antenna configuration.
2347          */
2348         rt2x00dev->default_ant.tx =
2349             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2350         rt2x00dev->default_ant.rx =
2351             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2352
2353         /*
2354          * Read frequency offset and RF programming sequence.
2355          */
2356         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2357         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2358
2359         /*
2360          * Read external LNA informations.
2361          */
2362         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2363
2364         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2365                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2366         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2367                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2368
2369         /*
2370          * Detect if this device has an hardware controlled radio.
2371          */
2372 #ifdef CONFIG_RT2X00_LIB_RFKILL
2373         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2374                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2375 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2376
2377         /*
2378          * Store led settings, for correct led behaviour.
2379          */
2380 #ifdef CONFIG_RT2X00_LIB_LEDS
2381         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2382         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2383         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2384
2385         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2386                            &rt2x00dev->led_mcu_reg);
2387 #endif /* CONFIG_RT2X00_LIB_LEDS */
2388
2389         return 0;
2390 }
2391
2392 /*
2393  * RF value list for rt2870
2394  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2395  */
2396 static const struct rf_channel rf_vals[] = {
2397         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2398         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2399         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2400         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2401         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2402         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2403         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2404         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2405         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2406         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2407         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2408         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2409         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2410         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2411
2412         /* 802.11 UNI / HyperLan 2 */
2413         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2414         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2415         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2416         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2417         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2418         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2419         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2420         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2421         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2422         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2423         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2424         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2425
2426         /* 802.11 HyperLan 2 */
2427         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2428         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2429         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2430         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2431         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2432         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2433         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2434         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2435         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2436         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2437         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2438         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2439         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2440         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2441         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2442         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2443
2444         /* 802.11 UNII */
2445         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2446         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2447         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2448         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2449         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2450         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2451         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2452         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2453         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2454         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2455         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2456
2457         /* 802.11 Japan */
2458         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2459         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2460         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2461         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2462         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2463         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2464         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2465 };
2466
2467 /*
2468  * RF value list for rt3070
2469  * Supports: 2.4 GHz
2470  */
2471 static const struct rf_channel rf_vals_3070[] = {
2472         {1,  241, 2, 2 },
2473         {2,  241, 2, 7 },
2474         {3,  242, 2, 2 },
2475         {4,  242, 2, 7 },
2476         {5,  243, 2, 2 },
2477         {6,  243, 2, 7 },
2478         {7,  244, 2, 2 },
2479         {8,  244, 2, 7 },
2480         {9,  245, 2, 2 },
2481         {10, 245, 2, 7 },
2482         {11, 246, 2, 2 },
2483         {12, 246, 2, 7 },
2484         {13, 247, 2, 2 },
2485         {14, 248, 2, 4 },
2486 };
2487
2488 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2489 {
2490         struct hw_mode_spec *spec = &rt2x00dev->spec;
2491         struct channel_info *info;
2492         char *tx_power1;
2493         char *tx_power2;
2494         unsigned int i;
2495         u16 eeprom;
2496
2497         /*
2498          * Initialize all hw fields.
2499          */
2500         rt2x00dev->hw->flags =
2501             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2502             IEEE80211_HW_SIGNAL_DBM |
2503             IEEE80211_HW_SUPPORTS_PS |
2504             IEEE80211_HW_PS_NULLFUNC_STACK;
2505         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2506
2507         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2508         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2509                                 rt2x00_eeprom_addr(rt2x00dev,
2510                                                    EEPROM_MAC_ADDR_0));
2511
2512         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2513
2514         /*
2515          * Initialize HT information.
2516          */
2517         spec->ht.ht_supported = true;
2518         spec->ht.cap =
2519             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2520             IEEE80211_HT_CAP_GRN_FLD |
2521             IEEE80211_HT_CAP_SGI_20 |
2522             IEEE80211_HT_CAP_SGI_40 |
2523             IEEE80211_HT_CAP_TX_STBC |
2524             IEEE80211_HT_CAP_RX_STBC |
2525             IEEE80211_HT_CAP_PSMP_SUPPORT;
2526         spec->ht.ampdu_factor = 3;
2527         spec->ht.ampdu_density = 4;
2528         spec->ht.mcs.tx_params =
2529             IEEE80211_HT_MCS_TX_DEFINED |
2530             IEEE80211_HT_MCS_TX_RX_DIFF |
2531             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2532                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2533
2534         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2535         case 3:
2536                 spec->ht.mcs.rx_mask[2] = 0xff;
2537         case 2:
2538                 spec->ht.mcs.rx_mask[1] = 0xff;
2539         case 1:
2540                 spec->ht.mcs.rx_mask[0] = 0xff;
2541                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2542                 break;
2543         }
2544
2545         /*
2546          * Initialize hw_mode information.
2547          */
2548         spec->supported_bands = SUPPORT_BAND_2GHZ;
2549         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2550
2551         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2552             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2553                 spec->num_channels = 14;
2554                 spec->channels = rf_vals;
2555         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2556                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2557                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2558                 spec->num_channels = ARRAY_SIZE(rf_vals);
2559                 spec->channels = rf_vals;
2560         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2561                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2562                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2563                 spec->channels = rf_vals_3070;
2564         }
2565
2566         /*
2567          * Create channel information array
2568          */
2569         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2570         if (!info)
2571                 return -ENOMEM;
2572
2573         spec->channels_info = info;
2574
2575         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2576         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2577
2578         for (i = 0; i < 14; i++) {
2579                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2580                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2581         }
2582
2583         if (spec->num_channels > 14) {
2584                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2585                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2586
2587                 for (i = 14; i < spec->num_channels; i++) {
2588                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2589                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2590                 }
2591         }
2592
2593         return 0;
2594 }
2595
2596 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2597 {
2598         int retval;
2599
2600         /*
2601          * Allocate eeprom data.
2602          */
2603         retval = rt2800usb_validate_eeprom(rt2x00dev);
2604         if (retval)
2605                 return retval;
2606
2607         retval = rt2800usb_init_eeprom(rt2x00dev);
2608         if (retval)
2609                 return retval;
2610
2611         /*
2612          * Initialize hw specifications.
2613          */
2614         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2615         if (retval)
2616                 return retval;
2617
2618         /*
2619          * This device requires firmware.
2620          */
2621         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2622         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2623         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2624         if (!modparam_nohwcrypt)
2625                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2626
2627         /*
2628          * Set the rssi offset.
2629          */
2630         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2631
2632         return 0;
2633 }
2634
2635 /*
2636  * IEEE80211 stack callback functions.
2637  */
2638 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2639                                    u32 *iv32, u16 *iv16)
2640 {
2641         struct rt2x00_dev *rt2x00dev = hw->priv;
2642         struct mac_iveiv_entry iveiv_entry;
2643         u32 offset;
2644
2645         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2646         rt2x00usb_register_multiread(rt2x00dev, offset,
2647                                       &iveiv_entry, sizeof(iveiv_entry));
2648
2649         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2650         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2651 }
2652
2653 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2654 {
2655         struct rt2x00_dev *rt2x00dev = hw->priv;
2656         u32 reg;
2657         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2658
2659         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2660         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2661         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2662
2663         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2664         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2665         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2666
2667         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2668         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2669         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2670
2671         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2672         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2673         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2674
2675         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2676         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2677         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2678
2679         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2680         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2681         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2682
2683         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2684         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2685         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2686
2687         return 0;
2688 }
2689
2690 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2691                              const struct ieee80211_tx_queue_params *params)
2692 {
2693         struct rt2x00_dev *rt2x00dev = hw->priv;
2694         struct data_queue *queue;
2695         struct rt2x00_field32 field;
2696         int retval;
2697         u32 reg;
2698         u32 offset;
2699
2700         /*
2701          * First pass the configuration through rt2x00lib, that will
2702          * update the queue settings and validate the input. After that
2703          * we are free to update the registers based on the value
2704          * in the queue parameter.
2705          */
2706         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2707         if (retval)
2708                 return retval;
2709
2710         /*
2711          * We only need to perform additional register initialization
2712          * for WMM queues/
2713          */
2714         if (queue_idx >= 4)
2715                 return 0;
2716
2717         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2718
2719         /* Update WMM TXOP register */
2720         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2721         field.bit_offset = (queue_idx & 1) * 16;
2722         field.bit_mask = 0xffff << field.bit_offset;
2723
2724         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2725         rt2x00_set_field32(&reg, field, queue->txop);
2726         rt2x00usb_register_write(rt2x00dev, offset, reg);
2727
2728         /* Update WMM registers */
2729         field.bit_offset = queue_idx * 4;
2730         field.bit_mask = 0xf << field.bit_offset;
2731
2732         rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2733         rt2x00_set_field32(&reg, field, queue->aifs);
2734         rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2735
2736         rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2737         rt2x00_set_field32(&reg, field, queue->cw_min);
2738         rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2739
2740         rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2741         rt2x00_set_field32(&reg, field, queue->cw_max);
2742         rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2743
2744         /* Update EDCA registers */
2745         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2746
2747         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2748         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2749         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2750         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2751         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2752         rt2x00usb_register_write(rt2x00dev, offset, reg);
2753
2754         return 0;
2755 }
2756
2757 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2758 {
2759         struct rt2x00_dev *rt2x00dev = hw->priv;
2760         u64 tsf;
2761         u32 reg;
2762
2763         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2764         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2765         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2766         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2767
2768         return tsf;
2769 }
2770
2771 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2772         .tx                     = rt2x00mac_tx,
2773         .start                  = rt2x00mac_start,
2774         .stop                   = rt2x00mac_stop,
2775         .add_interface          = rt2x00mac_add_interface,
2776         .remove_interface       = rt2x00mac_remove_interface,
2777         .config                 = rt2x00mac_config,
2778         .configure_filter       = rt2x00mac_configure_filter,
2779         .set_key                = rt2x00mac_set_key,
2780         .get_stats              = rt2x00mac_get_stats,
2781         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2782         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2783         .bss_info_changed       = rt2x00mac_bss_info_changed,
2784         .conf_tx                = rt2800usb_conf_tx,
2785         .get_tx_stats           = rt2x00mac_get_tx_stats,
2786         .get_tsf                = rt2800usb_get_tsf,
2787 };
2788
2789 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2790         .probe_hw               = rt2800usb_probe_hw,
2791         .get_firmware_name      = rt2800usb_get_firmware_name,
2792         .check_firmware         = rt2800usb_check_firmware,
2793         .load_firmware          = rt2800usb_load_firmware,
2794         .initialize             = rt2x00usb_initialize,
2795         .uninitialize           = rt2x00usb_uninitialize,
2796         .clear_entry            = rt2x00usb_clear_entry,
2797         .set_device_state       = rt2800usb_set_device_state,
2798         .rfkill_poll            = rt2800usb_rfkill_poll,
2799         .link_stats             = rt2800usb_link_stats,
2800         .reset_tuner            = rt2800usb_reset_tuner,
2801         .link_tuner             = rt2800usb_link_tuner,
2802         .write_tx_desc          = rt2800usb_write_tx_desc,
2803         .write_tx_data          = rt2x00usb_write_tx_data,
2804         .write_beacon           = rt2800usb_write_beacon,
2805         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2806         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2807         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2808         .fill_rxdone            = rt2800usb_fill_rxdone,
2809         .config_shared_key      = rt2800usb_config_shared_key,
2810         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2811         .config_filter          = rt2800usb_config_filter,
2812         .config_intf            = rt2800usb_config_intf,
2813         .config_erp             = rt2800usb_config_erp,
2814         .config_ant             = rt2800usb_config_ant,
2815         .config                 = rt2800usb_config,
2816 };
2817
2818 static const struct data_queue_desc rt2800usb_queue_rx = {
2819         .entry_num              = RX_ENTRIES,
2820         .data_size              = AGGREGATION_SIZE,
2821         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2822         .priv_size              = sizeof(struct queue_entry_priv_usb),
2823 };
2824
2825 static const struct data_queue_desc rt2800usb_queue_tx = {
2826         .entry_num              = TX_ENTRIES,
2827         .data_size              = AGGREGATION_SIZE,
2828         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2829         .priv_size              = sizeof(struct queue_entry_priv_usb),
2830 };
2831
2832 static const struct data_queue_desc rt2800usb_queue_bcn = {
2833         .entry_num              = 8 * BEACON_ENTRIES,
2834         .data_size              = MGMT_FRAME_SIZE,
2835         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2836         .priv_size              = sizeof(struct queue_entry_priv_usb),
2837 };
2838
2839 static const struct rt2x00_ops rt2800usb_ops = {
2840         .name           = KBUILD_MODNAME,
2841         .max_sta_intf   = 1,
2842         .max_ap_intf    = 8,
2843         .eeprom_size    = EEPROM_SIZE,
2844         .rf_size        = RF_SIZE,
2845         .tx_queues      = NUM_TX_QUEUES,
2846         .rx             = &rt2800usb_queue_rx,
2847         .tx             = &rt2800usb_queue_tx,
2848         .bcn            = &rt2800usb_queue_bcn,
2849         .lib            = &rt2800usb_rt2x00_ops,
2850         .hw             = &rt2800usb_mac80211_ops,
2851 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2852         .debugfs        = &rt2800usb_rt2x00debug,
2853 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2854 };
2855
2856 /*
2857  * rt2800usb module information.
2858  */
2859 static struct usb_device_id rt2800usb_device_table[] = {
2860         /* ??? */
2861         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
2862         /* Abocom */
2863         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2864         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2865         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2866         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2867         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2868         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2869         /* AirTies */
2870         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2871         /* Amigo */
2872         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2873         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2874         /* Amit */
2875         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2876         /* ASUS */
2877         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2878         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2879         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2880         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2881         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2882         /* AzureWave */
2883         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2884         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2885         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2886         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2887         /* Belkin */
2888         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2889         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2890         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2891         /* Buffalo */
2892         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         /* Conceptronic */
2895         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2896         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2897         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2898         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2899         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2901         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2902         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2903         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         /* Corega */
2906         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2908         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2910         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2911         /* D-Link */
2912         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2915         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         /* Edimax */
2918         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         /* EnGenius */
2922         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2928         /* Gemtek */
2929         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         /* Gigabyte */
2931         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         /* Hawking */
2935         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2937         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         /* LevelOne */
2940         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2941         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         /* Linksys */
2943         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         /* Logitec */
2947         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2950         /* Motorola */
2951         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         /* Ovislink */
2954         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         /* Pegatron */
2956         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         /* Philips */
2959         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         /* Planex */
2961         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2962         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         /* Qcom */
2965         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2966         /* Quanta */
2967         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2968         /* Ralink */
2969         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2975         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
2977         /* Samsung */
2978         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
2979         /* Siemens */
2980         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2981         /* Sitecom */
2982         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2983         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2986         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2989         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
2991         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
2993         /* SMC */
2994         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2995         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3001         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3002         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3003         /* Sparklan */
3004         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3005         /* U-Media*/
3006         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         /* ZCOM */
3008         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         /* Zinwell */
3011         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         /* Zyxel */
3014         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3016         { 0, }
3017 };
3018
3019 MODULE_AUTHOR(DRV_PROJECT);
3020 MODULE_VERSION(DRV_VERSION);
3021 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3022 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3023 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3024 MODULE_FIRMWARE(FIRMWARE_RT2870);
3025 MODULE_LICENSE("GPL");
3026
3027 static struct usb_driver rt2800usb_driver = {
3028         .name           = KBUILD_MODNAME,
3029         .id_table       = rt2800usb_device_table,
3030         .probe          = rt2x00usb_probe,
3031         .disconnect     = rt2x00usb_disconnect,
3032         .suspend        = rt2x00usb_suspend,
3033         .resume         = rt2x00usb_resume,
3034 };
3035
3036 static int __init rt2800usb_init(void)
3037 {
3038         return usb_register(&rt2800usb_driver);
3039 }
3040
3041 static void __exit rt2800usb_exit(void)
3042 {
3043         usb_deregister(&rt2800usb_driver);
3044 }
3045
3046 module_init(rt2800usb_init);
3047 module_exit(rt2800usb_exit);