drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 281                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 282                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 283                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 284                         return 0;
 285
 286                 msleep(1);
 287         }
 288
 289         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 290         return -EACCES;
 291 }
 292 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 293
 294 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 295 {
 296         u16 fw_crc;
 297         u16 crc;
 298
 299         /*
 300          * The last 2 bytes in the firmware array are the crc checksum itself,
 301          * this means that we should never pass those 2 bytes to the crc
 302          * algorithm.
 303          */
 304         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 305
 306         /*
 307          * Use the crc ccitt algorithm.
 308          * This will return the same value as the legacy driver which
 309          * used bit ordering reversion on the both the firmware bytes
 310          * before input input as well as on the final output.
 311          * Obviously using crc ccitt directly is much more efficient.
 312          */
 313         crc = crc_ccitt(~0, data, len - 2);
 314
 315         /*
 316          * There is a small difference between the crc-itu-t + bitrev and
 317          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 318          * will be swapped, use swab16 to convert the crc to the correct
 319          * value.
 320          */
 321         crc = swab16(crc);
 322
 323         return fw_crc == crc;
 324 }
 325
 326 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 327                           const u8 *data, const size_t len)
 328 {
 329         size_t offset = 0;
 330         size_t fw_len;
 331         bool multiple;
 332
 333         /*
 334          * PCI(e) & SOC devices require firmware with a length
 335          * of 8kb. USB devices require firmware files with a length
 336          * of 4kb. Certain USB chipsets however require different firmware,
 337          * which Ralink only provides attached to the original firmware
 338          * file. Thus for USB devices, firmware files have a length
 339          * which is a multiple of 4kb.
 340          */
 341         if (rt2x00_is_usb(rt2x00dev)) {
 342                 fw_len = 4096;
 343                 multiple = true;
 344         } else {
 345                 fw_len = 8192;
 346                 multiple = true;
 347         }
 348
 349         /*
 350          * Validate the firmware length
 351          */
 352         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 353                 return FW_BAD_LENGTH;
 354
 355         /*
 356          * Check if the chipset requires one of the upper parts
 357          * of the firmware.
 358          */
 359         if (rt2x00_is_usb(rt2x00dev) &&
 360             !rt2x00_rt(rt2x00dev, RT2860) &&
 361             !rt2x00_rt(rt2x00dev, RT2872) &&
 362             !rt2x00_rt(rt2x00dev, RT3070) &&
 363             ((len / fw_len) == 1))
 364                 return FW_BAD_VERSION;
 365
 366         /*
 367          * 8kb firmware files must be checked as if it were
 368          * 2 separate firmware files.
 369          */
 370         while (offset < len) {
 371                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 372                         return FW_BAD_CRC;
 373
 374                 offset += fw_len;
 375         }
 376
 377         return FW_OK;
 378 }
 379 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 380
 381 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 382                          const u8 *data, const size_t len)
 383 {
 384         unsigned int i;
 385         u32 reg;
 386
 387         /*
 388          * If driver doesn't wake up firmware here,
 389          * rt2800_load_firmware will hang forever when interface is up again.
 390          */
 391         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 392
 393         /*
 394          * Wait for stable hardware.
 395          */
 396         if (rt2800_wait_csr_ready(rt2x00dev))
 397                 return -EBUSY;
 398
 399         if (rt2x00_is_pci(rt2x00dev))
 400                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 401
 402         /*
 403          * Disable DMA, will be reenabled later when enabling
 404          * the radio.
 405          */
 406         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 407         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 408         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 409         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 410         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 411         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 412         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 413
 414         /*
 415          * Write firmware to the device.
 416          */
 417         rt2800_drv_write_firmware(rt2x00dev, data, len);
 418
 419         /*
 420          * Wait for device to stabilize.
 421          */
 422         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 423                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 424                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 425                         break;
 426                 msleep(1);
 427         }
 428
 429         if (i == REGISTER_BUSY_COUNT) {
 430                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 431                 return -EBUSY;
 432         }
 433
 434         /*
 435          * Initialize firmware.
 436          */
 437         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 438         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 439         msleep(1);
 440
 441         return 0;
 442 }
 443 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 444
 445 void rt2800_write_tx_data(struct queue_entry *entry,
 446                           struct txentry_desc *txdesc)
 447 {
 448         __le32 *txwi = rt2800_drv_get_txwi(entry);
 449         u32 word;
 450
 451         /*
 452          * Initialize TX Info descriptor
 453          */
 454         rt2x00_desc_read(txwi, 0, &word);
 455         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 456                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 457         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 458                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 459         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 460         rt2x00_set_field32(&word, TXWI_W0_TS,
 461                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 462         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 463                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 464         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 465         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
 466         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 467         rt2x00_set_field32(&word, TXWI_W0_BW,
 468                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 469         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 470                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 471         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 472         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 473         rt2x00_desc_write(txwi, 0, word);
 474
 475         rt2x00_desc_read(txwi, 1, &word);
 476         rt2x00_set_field32(&word, TXWI_W1_ACK,
 477                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 478         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 479                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 480         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 481         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 482                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 483                            txdesc->key_idx : 0xff);
 484         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 485                            txdesc->length);
 486         rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
 487         rt2x00_desc_write(txwi, 1, word);
 488
 489         /*
 490          * Always write 0 to IV/EIV fields, hardware will insert the IV
 491          * from the IVEIV register when TXD_W3_WIV is set to 0.
 492          * When TXD_W3_WIV is set to 1 it will use the IV data
 493          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 494          * crypto entry in the registers should be used to encrypt the frame.
 495          */
 496         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 497         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 498 }
 499 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 500
 501 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
 502 {
 503         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 504         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 505         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 506         u16 eeprom;
 507         u8 offset0;
 508         u8 offset1;
 509         u8 offset2;
 510
 511         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 512                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 513                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 514                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 515                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 516                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 517         } else {
 518                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 519                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 520                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 521                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 522                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 523         }
 524
 525         /*
 526          * Convert the value from the descriptor into the RSSI value
 527          * If the value in the descriptor is 0, it is considered invalid
 528          * and the default (extremely low) rssi value is assumed
 529          */
 530         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 531         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 532         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 533
 534         /*
 535          * mac80211 only accepts a single RSSI value. Calculating the
 536          * average doesn't deliver a fair answer either since -60:-60 would
 537          * be considered equally good as -50:-70 while the second is the one
 538          * which gives less energy...
 539          */
 540         rssi0 = max(rssi0, rssi1);
 541         return max(rssi0, rssi2);
 542 }
 543
 544 void rt2800_process_rxwi(struct queue_entry *entry,
 545                          struct rxdone_entry_desc *rxdesc)
 546 {
 547         __le32 *rxwi = (__le32 *) entry->skb->data;
 548         u32 word;
 549
 550         rt2x00_desc_read(rxwi, 0, &word);
 551
 552         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 553         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 554
 555         rt2x00_desc_read(rxwi, 1, &word);
 556
 557         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 558                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 559
 560         if (rt2x00_get_field32(word, RXWI_W1_BW))
 561                 rxdesc->flags |= RX_FLAG_40MHZ;
 562
 563         /*
 564          * Detect RX rate, always use MCS as signal type.
 565          */
 566         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 567         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 568         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 569
 570         /*
 571          * Mask of 0x8 bit to remove the short preamble flag.
 572          */
 573         if (rxdesc->rate_mode == RATE_MODE_CCK)
 574                 rxdesc->signal &= ~0x8;
 575
 576         rt2x00_desc_read(rxwi, 2, &word);
 577
 578         /*
 579          * Convert descriptor AGC value to RSSI value.
 580          */
 581         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 582
 583         /*
 584          * Remove RXWI descriptor from start of buffer.
 585          */
 586         skb_pull(entry->skb, RXWI_DESC_SIZE);
 587 }
 588 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 589
 590 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 591 {
 592         __le32 *txwi;
 593         u32 word;
 594         int wcid, ack, pid;
 595         int tx_wcid, tx_ack, tx_pid;
 596
 597         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 598         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 599         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 600
 601         /*
 602          * This frames has returned with an IO error,
 603          * so the status report is not intended for this
 604          * frame.
 605          */
 606         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 607                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 608                 return false;
 609         }
 610
 611         /*
 612          * Validate if this TX status report is intended for
 613          * this entry by comparing the WCID/ACK/PID fields.
 614          */
 615         txwi = rt2800_drv_get_txwi(entry);
 616
 617         rt2x00_desc_read(txwi, 1, &word);
 618         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 619         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 620         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 621
 622         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 623                 WARNING(entry->queue->rt2x00dev,
 624                         "TX status report missed for queue %d entry %d\n",
 625                 entry->queue->qid, entry->entry_idx);
 626                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 627                 return false;
 628         }
 629
 630         return true;
 631 }
 632
 633 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 634 {
 635         struct data_queue *queue;
 636         struct queue_entry *entry;
 637         __le32 *txwi;
 638         struct txdone_entry_desc txdesc;
 639         u32 word;
 640         u32 reg;
 641         u16 mcs, real_mcs;
 642         u8 pid;
 643         int i;
 644
 645         /*
 646          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 647          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 648          * flag is not set anymore.
 649          *
 650          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 651          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 652          * tx ring size for now.
 653          */
 654         for (i = 0; i < TX_ENTRIES; i++) {
 655                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 656                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 657                         break;
 658
 659                 /*
 660                  * Skip this entry when it contains an invalid
 661                  * queue identication number.
 662                  */
 663                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
 664                 if (pid >= QID_RX)
 665                         continue;
 666
 667                 queue = rt2x00queue_get_queue(rt2x00dev, pid);
 668                 if (unlikely(!queue))
 669                         continue;
 670
 671                 /*
 672                  * Inside each queue, we process each entry in a chronological
 673                  * order. We first check that the queue is not empty.
 674                  */
 675                 entry = NULL;
 676                 txwi = NULL;
 677                 while (!rt2x00queue_empty(queue)) {
 678                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 679                         if (rt2800_txdone_entry_check(entry, reg))
 680                                 break;
 681                 }
 682
 683                 if (!entry || rt2x00queue_empty(queue))
 684                         break;
 685
 686
 687                 /*
 688                  * Obtain the status about this packet.
 689                  */
 690                 txdesc.flags = 0;
 691                 txwi = rt2800_drv_get_txwi(entry);
 692                 rt2x00_desc_read(txwi, 0, &word);
 693                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 694                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 695
 696                 /*
 697                  * Ralink has a retry mechanism using a global fallback
 698                  * table. We setup this fallback table to try the immediate
 699                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 700                  * always contains the MCS used for the last transmission, be
 701                  * it successful or not.
 702                  */
 703                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 704                         /*
 705                          * Transmission succeeded. The number of retries is
 706                          * mcs - real_mcs
 707                          */
 708                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 709                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 710                 } else {
 711                         /*
 712                          * Transmission failed. The number of retries is
 713                          * always 7 in this case (for a total number of 8
 714                          * frames sent).
 715                          */
 716                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 717                         txdesc.retry = rt2x00dev->long_retry;
 718                 }
 719
 720                 /*
 721                  * the frame was retried at least once
 722                  * -> hw used fallback rates
 723                  */
 724                 if (txdesc.retry)
 725                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 726
 727                 rt2x00lib_txdone(entry, &txdesc);
 728         }
 729 }
 730 EXPORT_SYMBOL_GPL(rt2800_txdone);
 731
 732 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 733 {
 734         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 735         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 736         unsigned int beacon_base;
 737         u32 reg;
 738
 739         /*
 740          * Disable beaconing while we are reloading the beacon data,
 741          * otherwise we might be sending out invalid data.
 742          */
 743         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 744         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 745         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 746
 747         /*
 748          * Add space for the TXWI in front of the skb.
 749          */
 750         skb_push(entry->skb, TXWI_DESC_SIZE);
 751         memset(entry->skb, 0, TXWI_DESC_SIZE);
 752
 753         /*
 754          * Register descriptor details in skb frame descriptor.
 755          */
 756         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 757         skbdesc->desc = entry->skb->data;
 758         skbdesc->desc_len = TXWI_DESC_SIZE;
 759
 760         /*
 761          * Add the TXWI for the beacon to the skb.
 762          */
 763         rt2800_write_tx_data(entry, txdesc);
 764
 765         /*
 766          * Dump beacon to userspace through debugfs.
 767          */
 768         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 769
 770         /*
 771          * Write entire beacon with TXWI to register.
 772          */
 773         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 774         rt2800_register_multiwrite(rt2x00dev, beacon_base,
 775                                    entry->skb->data, entry->skb->len);
 776
 777         /*
 778          * Enable beaconing again.
 779          */
 780         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 781         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 782         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 783         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 784
 785         /*
 786          * Clean up beacon skb.
 787          */
 788         dev_kfree_skb_any(entry->skb);
 789         entry->skb = NULL;
 790 }
 791 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 792
 793 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
 794                                        unsigned int beacon_base)
 795 {
 796         int i;
 797
 798         /*
 799          * For the Beacon base registers we only need to clear
 800          * the whole TXWI which (when set to 0) will invalidate
 801          * the entire beacon.
 802          */
 803         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 804                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 805 }
 806
 807 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 808 const struct rt2x00debug rt2800_rt2x00debug = {
 809         .owner  = THIS_MODULE,
 810         .csr    = {
 811                 .read           = rt2800_register_read,
 812                 .write          = rt2800_register_write,
 813                 .flags          = RT2X00DEBUGFS_OFFSET,
 814                 .word_base      = CSR_REG_BASE,
 815                 .word_size      = sizeof(u32),
 816                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 817         },
 818         .eeprom = {
 819                 .read           = rt2x00_eeprom_read,
 820                 .write          = rt2x00_eeprom_write,
 821                 .word_base      = EEPROM_BASE,
 822                 .word_size      = sizeof(u16),
 823                 .word_count     = EEPROM_SIZE / sizeof(u16),
 824         },
 825         .bbp    = {
 826                 .read           = rt2800_bbp_read,
 827                 .write          = rt2800_bbp_write,
 828                 .word_base      = BBP_BASE,
 829                 .word_size      = sizeof(u8),
 830                 .word_count     = BBP_SIZE / sizeof(u8),
 831         },
 832         .rf     = {
 833                 .read           = rt2x00_rf_read,
 834                 .write          = rt2800_rf_write,
 835                 .word_base      = RF_BASE,
 836                 .word_size      = sizeof(u32),
 837                 .word_count     = RF_SIZE / sizeof(u32),
 838         },
 839 };
 840 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 841 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 842
 843 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 844 {
 845         u32 reg;
 846
 847         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 848         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 849 }
 850 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 851
 852 #ifdef CONFIG_RT2X00_LIB_LEDS
 853 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 854                                   enum led_brightness brightness)
 855 {
 856         struct rt2x00_led *led =
 857             container_of(led_cdev, struct rt2x00_led, led_dev);
 858         unsigned int enabled = brightness != LED_OFF;
 859         unsigned int bg_mode =
 860             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 861         unsigned int polarity =
 862                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 863                                    EEPROM_FREQ_LED_POLARITY);
 864         unsigned int ledmode =
 865                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 866                                    EEPROM_FREQ_LED_MODE);
 867
 868         if (led->type == LED_TYPE_RADIO) {
 869                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 870                                       enabled ? 0x20 : 0);
 871         } else if (led->type == LED_TYPE_ASSOC) {
 872                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 873                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 874         } else if (led->type == LED_TYPE_QUALITY) {
 875                 /*
 876                  * The brightness is divided into 6 levels (0 - 5),
 877                  * The specs tell us the following levels:
 878                  *      0, 1 ,3, 7, 15, 31
 879                  * to determine the level in a simple way we can simply
 880                  * work with bitshifting:
 881                  *      (1 << level) - 1
 882                  */
 883                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 884                                       (1 << brightness / (LED_FULL / 6)) - 1,
 885                                       polarity);
 886         }
 887 }
 888
 889 static int rt2800_blink_set(struct led_classdev *led_cdev,
 890                             unsigned long *delay_on, unsigned long *delay_off)
 891 {
 892         struct rt2x00_led *led =
 893             container_of(led_cdev, struct rt2x00_led, led_dev);
 894         u32 reg;
 895
 896         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 897         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 898         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 899         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 900
 901         return 0;
 902 }
 903
 904 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 905                      struct rt2x00_led *led, enum led_type type)
 906 {
 907         led->rt2x00dev = rt2x00dev;
 908         led->type = type;
 909         led->led_dev.brightness_set = rt2800_brightness_set;
 910         led->led_dev.blink_set = rt2800_blink_set;
 911         led->flags = LED_INITIALIZED;
 912 }
 913 #endif /* CONFIG_RT2X00_LIB_LEDS */
 914
 915 /*
 916  * Configuration handlers.
 917  */
 918 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 919                                     struct rt2x00lib_crypto *crypto,
 920                                     struct ieee80211_key_conf *key)
 921 {
 922         struct mac_wcid_entry wcid_entry;
 923         struct mac_iveiv_entry iveiv_entry;
 924         u32 offset;
 925         u32 reg;
 926
 927         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 928
 929         if (crypto->cmd == SET_KEY) {
 930                 rt2800_register_read(rt2x00dev, offset, &reg);
 931                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 932                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 933                 /*
 934                  * Both the cipher as the BSS Idx numbers are split in a main
 935                  * value of 3 bits, and a extended field for adding one additional
 936                  * bit to the value.
 937                  */
 938                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 939                                    (crypto->cipher & 0x7));
 940                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 941                                    (crypto->cipher & 0x8) >> 3);
 942                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 943                                    (crypto->bssidx & 0x7));
 944                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 945                                    (crypto->bssidx & 0x8) >> 3);
 946                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 947                 rt2800_register_write(rt2x00dev, offset, reg);
 948         } else {
 949                 rt2800_register_write(rt2x00dev, offset, 0);
 950         }
 951
 952         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 953
 954         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 955         if ((crypto->cipher == CIPHER_TKIP) ||
 956             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 957             (crypto->cipher == CIPHER_AES))
 958                 iveiv_entry.iv[3] |= 0x20;
 959         iveiv_entry.iv[3] |= key->keyidx << 6;
 960         rt2800_register_multiwrite(rt2x00dev, offset,
 961                                       &iveiv_entry, sizeof(iveiv_entry));
 962
 963         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 964
 965         memset(&wcid_entry, 0, sizeof(wcid_entry));
 966         if (crypto->cmd == SET_KEY)
 967                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 968         rt2800_register_multiwrite(rt2x00dev, offset,
 969                                       &wcid_entry, sizeof(wcid_entry));
 970 }
 971
 972 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 973                              struct rt2x00lib_crypto *crypto,
 974                              struct ieee80211_key_conf *key)
 975 {
 976         struct hw_key_entry key_entry;
 977         struct rt2x00_field32 field;
 978         u32 offset;
 979         u32 reg;
 980
 981         if (crypto->cmd == SET_KEY) {
 982                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 983
 984                 memcpy(key_entry.key, crypto->key,
 985                        sizeof(key_entry.key));
 986                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 987                        sizeof(key_entry.tx_mic));
 988                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 989                        sizeof(key_entry.rx_mic));
 990
 991                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 992                 rt2800_register_multiwrite(rt2x00dev, offset,
 993                                               &key_entry, sizeof(key_entry));
 994         }
 995
 996         /*
 997          * The cipher types are stored over multiple registers
 998          * starting with SHARED_KEY_MODE_BASE each word will have
 999          * 32 bits and contains the cipher types for 2 bssidx each.
1000          * Using the correct defines correctly will cause overhead,
1001          * so just calculate the correct offset.
1002          */
1003         field.bit_offset = 4 * (key->hw_key_idx % 8);
1004         field.bit_mask = 0x7 << field.bit_offset;
1005
1006         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1007
1008         rt2800_register_read(rt2x00dev, offset, &reg);
1009         rt2x00_set_field32(&reg, field,
1010                            (crypto->cmd == SET_KEY) * crypto->cipher);
1011         rt2800_register_write(rt2x00dev, offset, reg);
1012
1013         /*
1014          * Update WCID information
1015          */
1016         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1017
1018         return 0;
1019 }
1020 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1021
1022 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1023                                struct rt2x00lib_crypto *crypto,
1024                                struct ieee80211_key_conf *key)
1025 {
1026         struct hw_key_entry key_entry;
1027         u32 offset;
1028
1029         if (crypto->cmd == SET_KEY) {
1030                 /*
1031                  * 1 pairwise key is possible per AID, this means that the AID
1032                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1033                  * last possible shared key entry.
1034                  */
1035                 if (crypto->aid > (256 - 32))
1036                         return -ENOSPC;
1037
1038                 key->hw_key_idx = 32 + crypto->aid;
1039
1040                 memcpy(key_entry.key, crypto->key,
1041                        sizeof(key_entry.key));
1042                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1043                        sizeof(key_entry.tx_mic));
1044                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1045                        sizeof(key_entry.rx_mic));
1046
1047                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1048                 rt2800_register_multiwrite(rt2x00dev, offset,
1049                                               &key_entry, sizeof(key_entry));
1050         }
1051
1052         /*
1053          * Update WCID information
1054          */
1055         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1056
1057         return 0;
1058 }
1059 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1060
1061 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1062                           const unsigned int filter_flags)
1063 {
1064         u32 reg;
1065
1066         /*
1067          * Start configuration steps.
1068          * Note that the version error will always be dropped
1069          * and broadcast frames will always be accepted since
1070          * there is no filter for it at this time.
1071          */
1072         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1073         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1074                            !(filter_flags & FIF_FCSFAIL));
1075         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1076                            !(filter_flags & FIF_PLCPFAIL));
1077         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1078                            !(filter_flags & FIF_PROMISC_IN_BSS));
1079         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1080         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1081         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1082                            !(filter_flags & FIF_ALLMULTI));
1083         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1084         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1085         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1086                            !(filter_flags & FIF_CONTROL));
1087         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1088                            !(filter_flags & FIF_CONTROL));
1089         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1090                            !(filter_flags & FIF_CONTROL));
1091         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1092                            !(filter_flags & FIF_CONTROL));
1093         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1094                            !(filter_flags & FIF_CONTROL));
1095         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1096                            !(filter_flags & FIF_PSPOLL));
1097         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1098         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1099         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1100                            !(filter_flags & FIF_CONTROL));
1101         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1102 }
1103 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1104
1105 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1106                         struct rt2x00intf_conf *conf, const unsigned int flags)
1107 {
1108         u32 reg;
1109
1110         if (flags & CONFIG_UPDATE_TYPE) {
1111                 /*
1112                  * Clear current synchronisation setup.
1113                  */
1114                 rt2800_clear_beacon(rt2x00dev,
1115                                     HW_BEACON_OFFSET(intf->beacon->entry_idx));
1116                 /*
1117                  * Enable synchronisation.
1118                  */
1119                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1120                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1121                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1122                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1123                                    (conf->sync == TSF_SYNC_ADHOC ||
1124                                     conf->sync == TSF_SYNC_AP_NONE));
1125                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1126
1127                 /*
1128                  * Enable pre tbtt interrupt for beaconing modes
1129                  */
1130                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1131                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1132                                    (conf->sync == TSF_SYNC_AP_NONE));
1133                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1134
1135         }
1136
1137         if (flags & CONFIG_UPDATE_MAC) {
1138                 reg = le32_to_cpu(conf->mac[1]);
1139                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1140                 conf->mac[1] = cpu_to_le32(reg);
1141
1142                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1143                                               conf->mac, sizeof(conf->mac));
1144         }
1145
1146         if (flags & CONFIG_UPDATE_BSSID) {
1147                 reg = le32_to_cpu(conf->bssid[1]);
1148                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1149                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1150                 conf->bssid[1] = cpu_to_le32(reg);
1151
1152                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1153                                               conf->bssid, sizeof(conf->bssid));
1154         }
1155 }
1156 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1157
1158 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
1159 {
1160         u32 reg;
1161
1162         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1163         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1164                            !!erp->short_preamble);
1165         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1166                            !!erp->short_preamble);
1167         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1168
1169         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1170         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1171                            erp->cts_protection ? 2 : 0);
1172         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1173
1174         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1175                                  erp->basic_rates);
1176         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1177
1178         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1179         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
1180         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1181
1182         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1183         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1184         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1185
1186         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1187         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1188                            erp->beacon_int * 16);
1189         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1190 }
1191 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1192
1193 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1194 {
1195         u8 r1;
1196         u8 r3;
1197
1198         rt2800_bbp_read(rt2x00dev, 1, &r1);
1199         rt2800_bbp_read(rt2x00dev, 3, &r3);
1200
1201         /*
1202          * Configure the TX antenna.
1203          */
1204         switch ((int)ant->tx) {
1205         case 1:
1206                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1207                 break;
1208         case 2:
1209                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1210                 break;
1211         case 3:
1212                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1213                 break;
1214         }
1215
1216         /*
1217          * Configure the RX antenna.
1218          */
1219         switch ((int)ant->rx) {
1220         case 1:
1221                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1222                 break;
1223         case 2:
1224                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1225                 break;
1226         case 3:
1227                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1228                 break;
1229         }
1230
1231         rt2800_bbp_write(rt2x00dev, 3, r3);
1232         rt2800_bbp_write(rt2x00dev, 1, r1);
1233 }
1234 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1235
1236 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1237                                    struct rt2x00lib_conf *libconf)
1238 {
1239         u16 eeprom;
1240         short lna_gain;
1241
1242         if (libconf->rf.channel <= 14) {
1243                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1244                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1245         } else if (libconf->rf.channel <= 64) {
1246                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1247                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1248         } else if (libconf->rf.channel <= 128) {
1249                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1250                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1251         } else {
1252                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1253                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1254         }
1255
1256         rt2x00dev->lna_gain = lna_gain;
1257 }
1258
1259 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1260                                          struct ieee80211_conf *conf,
1261                                          struct rf_channel *rf,
1262                                          struct channel_info *info)
1263 {
1264         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1265
1266         if (rt2x00dev->default_ant.tx == 1)
1267                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1268
1269         if (rt2x00dev->default_ant.rx == 1) {
1270                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1271                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1272         } else if (rt2x00dev->default_ant.rx == 2)
1273                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1274
1275         if (rf->channel > 14) {
1276                 /*
1277                  * When TX power is below 0, we should increase it by 7 to
1278                  * make it a positive value (Minumum value is -7).
1279                  * However this means that values between 0 and 7 have
1280                  * double meaning, and we should set a 7DBm boost flag.
1281                  */
1282                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1283                                    (info->default_power1 >= 0));
1284
1285                 if (info->default_power1 < 0)
1286                         info->default_power1 += 7;
1287
1288                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1289
1290                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1291                                    (info->default_power2 >= 0));
1292
1293                 if (info->default_power2 < 0)
1294                         info->default_power2 += 7;
1295
1296                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1297         } else {
1298                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1299                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1300         }
1301
1302         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1303
1304         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1305         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1306         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1307         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1308
1309         udelay(200);
1310
1311         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1312         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1313         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1314         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1315
1316         udelay(200);
1317
1318         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1319         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1320         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1321         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1322 }
1323
1324 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1325                                          struct ieee80211_conf *conf,
1326                                          struct rf_channel *rf,
1327                                          struct channel_info *info)
1328 {
1329         u8 rfcsr;
1330
1331         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1332         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1333
1334         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1335         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1336         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1337
1338         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1339         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1340         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1341
1342         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1343         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1344         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1345
1346         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1347         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1348         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1349
1350         rt2800_rfcsr_write(rt2x00dev, 24,
1351                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1352
1353         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1354         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1355         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1356 }
1357
1358 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1359                                   struct ieee80211_conf *conf,
1360                                   struct rf_channel *rf,
1361                                   struct channel_info *info)
1362 {
1363         u32 reg;
1364         unsigned int tx_pin;
1365         u8 bbp;
1366
1367         if (rf->channel <= 14) {
1368                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1369                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1370         } else {
1371                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1372                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1373         }
1374
1375         if (rt2x00_rf(rt2x00dev, RF2020) ||
1376             rt2x00_rf(rt2x00dev, RF3020) ||
1377             rt2x00_rf(rt2x00dev, RF3021) ||
1378             rt2x00_rf(rt2x00dev, RF3022) ||
1379             rt2x00_rf(rt2x00dev, RF3052))
1380                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1381         else
1382                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1383
1384         /*
1385          * Change BBP settings
1386          */
1387         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1388         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1389         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1390         rt2800_bbp_write(rt2x00dev, 86, 0);
1391
1392         if (rf->channel <= 14) {
1393                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1394                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1395                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1396                 } else {
1397                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1398                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1399                 }
1400         } else {
1401                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1402
1403                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1404                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1405                 else
1406                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1407         }
1408
1409         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1410         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1411         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1412         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1413         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1414
1415         tx_pin = 0;
1416
1417         /* Turn on unused PA or LNA when not using 1T or 1R */
1418         if (rt2x00dev->default_ant.tx != 1) {
1419                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1420                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1421         }
1422
1423         /* Turn on unused PA or LNA when not using 1T or 1R */
1424         if (rt2x00dev->default_ant.rx != 1) {
1425                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1426                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1427         }
1428
1429         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1430         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1431         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1432         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1433         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1434         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1435
1436         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1437
1438         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1439         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1440         rt2800_bbp_write(rt2x00dev, 4, bbp);
1441
1442         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1443         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1444         rt2800_bbp_write(rt2x00dev, 3, bbp);
1445
1446         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1447                 if (conf_is_ht40(conf)) {
1448                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1449                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1450                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1451                 } else {
1452                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1453                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1454                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1455                 }
1456         }
1457
1458         msleep(1);
1459 }
1460
1461 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1462                                   const int max_txpower)
1463 {
1464         u8 txpower;
1465         u8 max_value = (u8)max_txpower;
1466         u16 eeprom;
1467         int i;
1468         u32 reg;
1469         u8 r1;
1470         u32 offset;
1471
1472         /*
1473          * set to normal tx power mode: +/- 0dBm
1474          */
1475         rt2800_bbp_read(rt2x00dev, 1, &r1);
1476         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1477         rt2800_bbp_write(rt2x00dev, 1, r1);
1478
1479         /*
1480          * The eeprom contains the tx power values for each rate. These
1481          * values map to 100% tx power. Each 16bit word contains four tx
1482          * power values and the order is the same as used in the TX_PWR_CFG
1483          * registers.
1484          */
1485         offset = TX_PWR_CFG_0;
1486
1487         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1488                 /* just to be safe */
1489                 if (offset > TX_PWR_CFG_4)
1490                         break;
1491
1492                 rt2800_register_read(rt2x00dev, offset, &reg);
1493
1494                 /* read the next four txpower values */
1495                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1496                                    &eeprom);
1497
1498                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1499                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1500                  * TX_PWR_CFG_4: unknown */
1501                 txpower = rt2x00_get_field16(eeprom,
1502                                              EEPROM_TXPOWER_BYRATE_RATE0);
1503                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1504                                    min(txpower, max_value));
1505
1506                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1507                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1508                  * TX_PWR_CFG_4: unknown */
1509                 txpower = rt2x00_get_field16(eeprom,
1510                                              EEPROM_TXPOWER_BYRATE_RATE1);
1511                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1512                                    min(txpower, max_value));
1513
1514                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1515                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1516                  * TX_PWR_CFG_4: unknown */
1517                 txpower = rt2x00_get_field16(eeprom,
1518                                              EEPROM_TXPOWER_BYRATE_RATE2);
1519                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1520                                    min(txpower, max_value));
1521
1522                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1523                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1524                  * TX_PWR_CFG_4: unknown */
1525                 txpower = rt2x00_get_field16(eeprom,
1526                                              EEPROM_TXPOWER_BYRATE_RATE3);
1527                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1528                                    min(txpower, max_value));
1529
1530                 /* read the next four txpower values */
1531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1532                                    &eeprom);
1533
1534                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1535                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1536                  * TX_PWR_CFG_4: unknown */
1537                 txpower = rt2x00_get_field16(eeprom,
1538                                              EEPROM_TXPOWER_BYRATE_RATE0);
1539                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1540                                    min(txpower, max_value));
1541
1542                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1543                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1544                  * TX_PWR_CFG_4: unknown */
1545                 txpower = rt2x00_get_field16(eeprom,
1546                                              EEPROM_TXPOWER_BYRATE_RATE1);
1547                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1548                                    min(txpower, max_value));
1549
1550                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1551                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1552                  * TX_PWR_CFG_4: unknown */
1553                 txpower = rt2x00_get_field16(eeprom,
1554                                              EEPROM_TXPOWER_BYRATE_RATE2);
1555                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1556                                    min(txpower, max_value));
1557
1558                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1559                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1560                  * TX_PWR_CFG_4: unknown */
1561                 txpower = rt2x00_get_field16(eeprom,
1562                                              EEPROM_TXPOWER_BYRATE_RATE3);
1563                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1564                                    min(txpower, max_value));
1565
1566                 rt2800_register_write(rt2x00dev, offset, reg);
1567
1568                 /* next TX_PWR_CFG register */
1569                 offset += 4;
1570         }
1571 }
1572
1573 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1574                                       struct rt2x00lib_conf *libconf)
1575 {
1576         u32 reg;
1577
1578         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1579         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1580                            libconf->conf->short_frame_max_tx_count);
1581         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1582                            libconf->conf->long_frame_max_tx_count);
1583         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1584 }
1585
1586 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1587                              struct rt2x00lib_conf *libconf)
1588 {
1589         enum dev_state state =
1590             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1591                 STATE_SLEEP : STATE_AWAKE;
1592         u32 reg;
1593
1594         if (state == STATE_SLEEP) {
1595                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1596
1597                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1598                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1599                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1600                                    libconf->conf->listen_interval - 1);
1601                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1602                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1603
1604                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1605         } else {
1606                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1607                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1608                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1609                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1610                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1611
1612                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1613         }
1614 }
1615
1616 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1617                    struct rt2x00lib_conf *libconf,
1618                    const unsigned int flags)
1619 {
1620         /* Always recalculate LNA gain before changing configuration */
1621         rt2800_config_lna_gain(rt2x00dev, libconf);
1622
1623         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1624                 rt2800_config_channel(rt2x00dev, libconf->conf,
1625                                       &libconf->rf, &libconf->channel);
1626         if (flags & IEEE80211_CONF_CHANGE_POWER)
1627                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1628         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1629                 rt2800_config_retry_limit(rt2x00dev, libconf);
1630         if (flags & IEEE80211_CONF_CHANGE_PS)
1631                 rt2800_config_ps(rt2x00dev, libconf);
1632 }
1633 EXPORT_SYMBOL_GPL(rt2800_config);
1634
1635 /*
1636  * Link tuning
1637  */
1638 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1639 {
1640         u32 reg;
1641
1642         /*
1643          * Update FCS error count from register.
1644          */
1645         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1646         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1647 }
1648 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1649
1650 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1651 {
1652         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1653                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1654                     rt2x00_rt(rt2x00dev, RT3071) ||
1655                     rt2x00_rt(rt2x00dev, RT3090) ||
1656                     rt2x00_rt(rt2x00dev, RT3390))
1657                         return 0x1c + (2 * rt2x00dev->lna_gain);
1658                 else
1659                         return 0x2e + rt2x00dev->lna_gain;
1660         }
1661
1662         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1663                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1664         else
1665                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1666 }
1667
1668 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1669                                   struct link_qual *qual, u8 vgc_level)
1670 {
1671         if (qual->vgc_level != vgc_level) {
1672                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1673                 qual->vgc_level = vgc_level;
1674                 qual->vgc_level_reg = vgc_level;
1675         }
1676 }
1677
1678 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1679 {
1680         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1681 }
1682 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1683
1684 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1685                        const u32 count)
1686 {
1687         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1688                 return;
1689
1690         /*
1691          * When RSSI is better then -80 increase VGC level with 0x10
1692          */
1693         rt2800_set_vgc(rt2x00dev, qual,
1694                        rt2800_get_default_vgc(rt2x00dev) +
1695                        ((qual->rssi > -80) * 0x10));
1696 }
1697 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1698
1699 /*
1700  * Initialization functions.
1701  */
1702 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1703 {
1704         u32 reg;
1705         u16 eeprom;
1706         unsigned int i;
1707         int ret;
1708
1709         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1710         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1711         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1712         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1713         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1714         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1715         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1716
1717         ret = rt2800_drv_init_registers(rt2x00dev);
1718         if (ret)
1719                 return ret;
1720
1721         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1722         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1723         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1724         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1725         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1726         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1727
1728         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1729         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1730         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1731         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1732         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1733         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1734
1735         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1736         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1737
1738         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1739
1740         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1741         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1742         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1743         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1744         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1745         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1746         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1747         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1748
1749         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1750
1751         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1752         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1753         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1754         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1755
1756         if (rt2x00_rt(rt2x00dev, RT3071) ||
1757             rt2x00_rt(rt2x00dev, RT3090) ||
1758             rt2x00_rt(rt2x00dev, RT3390)) {
1759                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1760                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1761                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1762                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1763                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1764                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1765                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1766                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1767                                                       0x0000002c);
1768                         else
1769                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1770                                                       0x0000000f);
1771                 } else {
1772                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1773                 }
1774         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1775                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1776
1777                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1778                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1779                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1780                 } else {
1781                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1782                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1783                 }
1784         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1785                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1786                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1787                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1788         } else {
1789                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1790                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1791         }
1792
1793         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1794         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1795         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1796         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1797         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1798         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1799         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1800         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1801         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1802         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1803
1804         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1805         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1806         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1807         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1808         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1809
1810         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1811         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1812         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1813             rt2x00_rt(rt2x00dev, RT2883) ||
1814             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1815                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1816         else
1817                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1818         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1819         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1820         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1821
1822         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1823         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1824         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1825         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1826         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1827         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1828         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1829         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1830         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1831
1832         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1833
1834         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1835         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1836         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1837         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1838         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1839         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1840         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1841         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1842
1843         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1844         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1845         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1846         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1847         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1848         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1849         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1850         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1851         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1852
1853         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1854         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1855         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1856         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1857         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1858         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1859         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1860         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1861         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1862         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1863         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1864         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1865
1866         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1867         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1868         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1869         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1870         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1871         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1872         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1873         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1874         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1875         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1876         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1877         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1878
1879         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1880         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1881         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1882         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1883         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1884         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1885         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1886         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1887         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1888         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1889         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1890         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1891
1892         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1893         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1894         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1895                            !rt2x00_is_usb(rt2x00dev));
1896         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1897         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1898         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1899         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1900         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1901         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1902         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1903         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1904         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1905
1906         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1907         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1908         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1909         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1910         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1911         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1912         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1913         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1914         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1915         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1916         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1917         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1918
1919         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1920         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1921         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1922         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1923         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1924         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1925         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1926         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1927         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1928         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1929         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1930         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1931
1932         if (rt2x00_is_usb(rt2x00dev)) {
1933                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1934
1935                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1936                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1937                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1938                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1939                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1940                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1941                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1942                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1943                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1944                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1945                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1946         }
1947
1948         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1949         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1950
1951         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1952         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1953         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1954                            IEEE80211_MAX_RTS_THRESHOLD);
1955         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1956         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1957
1958         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1959
1960         /*
1961          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1962          * time should be set to 16. However, the original Ralink driver uses
1963          * 16 for both and indeed using a value of 10 for CCK SIFS results in
1964          * connection problems with 11g + CTS protection. Hence, use the same
1965          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1966          */
1967         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1968         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1969         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1970         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1971         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1972         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1973         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1974
1975         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1976
1977         /*
1978          * ASIC will keep garbage value after boot, clear encryption keys.
1979          */
1980         for (i = 0; i < 4; i++)
1981                 rt2800_register_write(rt2x00dev,
1982                                          SHARED_KEY_MODE_ENTRY(i), 0);
1983
1984         for (i = 0; i < 256; i++) {
1985                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1986                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1987                                               wcid, sizeof(wcid));
1988
1989                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1990                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1991         }
1992
1993         /*
1994          * Clear all beacons
1995          */
1996         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1997         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1998         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1999         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2000         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2001         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2002         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2003         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
2004
2005         if (rt2x00_is_usb(rt2x00dev)) {
2006                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2007                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2008                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2009         }
2010
2011         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2012         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2013         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2014         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2015         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2016         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2017         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2018         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2019         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2020         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2021
2022         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2023         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2024         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2025         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2026         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2027         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2028         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2029         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2030         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2031         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2032
2033         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2034         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2035         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2036         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2037         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2038         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2039         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2040         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2041         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2042         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2043
2044         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2045         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2046         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2047         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2048         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2049         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2050
2051         /*
2052          * We must clear the error counters.
2053          * These registers are cleared on read,
2054          * so we may pass a useless variable to store the value.
2055          */
2056         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2057         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2058         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2059         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2060         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2061         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2062
2063         /*
2064          * Setup leadtime for pre tbtt interrupt to 6ms
2065          */
2066         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2067         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2068         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2069
2070         return 0;
2071 }
2072
2073 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2074 {
2075         unsigned int i;
2076         u32 reg;
2077
2078         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2079                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2080                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2081                         return 0;
2082
2083                 udelay(REGISTER_BUSY_DELAY);
2084         }
2085
2086         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2087         return -EACCES;
2088 }
2089
2090 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2091 {
2092         unsigned int i;
2093         u8 value;
2094
2095         /*
2096          * BBP was enabled after firmware was loaded,
2097          * but we need to reactivate it now.
2098          */
2099         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2100         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2101         msleep(1);
2102
2103         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2104                 rt2800_bbp_read(rt2x00dev, 0, &value);
2105                 if ((value != 0xff) && (value != 0x00))
2106                         return 0;
2107                 udelay(REGISTER_BUSY_DELAY);
2108         }
2109
2110         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2111         return -EACCES;
2112 }
2113
2114 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2115 {
2116         unsigned int i;
2117         u16 eeprom;
2118         u8 reg_id;
2119         u8 value;
2120
2121         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2122                      rt2800_wait_bbp_ready(rt2x00dev)))
2123                 return -EACCES;
2124
2125         if (rt2800_is_305x_soc(rt2x00dev))
2126                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2127
2128         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2129         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2130
2131         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2132                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2133                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2134         } else {
2135                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2136                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2137         }
2138
2139         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2140
2141         if (rt2x00_rt(rt2x00dev, RT3070) ||
2142             rt2x00_rt(rt2x00dev, RT3071) ||
2143             rt2x00_rt(rt2x00dev, RT3090) ||
2144             rt2x00_rt(rt2x00dev, RT3390)) {
2145                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2146                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2147                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2148         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2149                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2150                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2151         } else {
2152                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2153         }
2154
2155         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2156         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2157
2158         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2159                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2160         else
2161                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2162
2163         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2164         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2165         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2166
2167         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2168             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2169             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2170             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2171             rt2800_is_305x_soc(rt2x00dev))
2172                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2173         else
2174                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2175
2176         if (rt2800_is_305x_soc(rt2x00dev))
2177                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2178         else
2179                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2180         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2181
2182         if (rt2x00_rt(rt2x00dev, RT3071) ||
2183             rt2x00_rt(rt2x00dev, RT3090) ||
2184             rt2x00_rt(rt2x00dev, RT3390)) {
2185                 rt2800_bbp_read(rt2x00dev, 138, &value);
2186
2187                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2188                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2189                         value |= 0x20;
2190                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2191                         value &= ~0x02;
2192
2193                 rt2800_bbp_write(rt2x00dev, 138, value);
2194         }
2195
2196
2197         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2198                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2199
2200                 if (eeprom != 0xffff && eeprom != 0x0000) {
2201                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2202                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2203                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2204                 }
2205         }
2206
2207         return 0;
2208 }
2209
2210 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2211                                 bool bw40, u8 rfcsr24, u8 filter_target)
2212 {
2213         unsigned int i;
2214         u8 bbp;
2215         u8 rfcsr;
2216         u8 passband;
2217         u8 stopband;
2218         u8 overtuned = 0;
2219
2220         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2221
2222         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2223         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2224         rt2800_bbp_write(rt2x00dev, 4, bbp);
2225
2226         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2227         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2228         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2229
2230         /*
2231          * Set power & frequency of passband test tone
2232          */
2233         rt2800_bbp_write(rt2x00dev, 24, 0);
2234
2235         for (i = 0; i < 100; i++) {
2236                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2237                 msleep(1);
2238
2239                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2240                 if (passband)
2241                         break;
2242         }
2243
2244         /*
2245          * Set power & frequency of stopband test tone
2246          */
2247         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2248
2249         for (i = 0; i < 100; i++) {
2250                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2251                 msleep(1);
2252
2253                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2254
2255                 if ((passband - stopband) <= filter_target) {
2256                         rfcsr24++;
2257                         overtuned += ((passband - stopband) == filter_target);
2258                 } else
2259                         break;
2260
2261                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2262         }
2263
2264         rfcsr24 -= !!overtuned;
2265
2266         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2267         return rfcsr24;
2268 }
2269
2270 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2271 {
2272         u8 rfcsr;
2273         u8 bbp;
2274         u32 reg;
2275         u16 eeprom;
2276
2277         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2278             !rt2x00_rt(rt2x00dev, RT3071) &&
2279             !rt2x00_rt(rt2x00dev, RT3090) &&
2280             !rt2x00_rt(rt2x00dev, RT3390) &&
2281             !rt2800_is_305x_soc(rt2x00dev))
2282                 return 0;
2283
2284         /*
2285          * Init RF calibration.
2286          */
2287         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2288         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2289         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2290         msleep(1);
2291         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2292         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2293
2294         if (rt2x00_rt(rt2x00dev, RT3070) ||
2295             rt2x00_rt(rt2x00dev, RT3071) ||
2296             rt2x00_rt(rt2x00dev, RT3090)) {
2297                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2298                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2299                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2300                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2301                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2302                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2303                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2304                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2305                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2306                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2307                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2308                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2309                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2310                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2311                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2312                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2313                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2314                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2315                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2316         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2317                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2318                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2319                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2320                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2321                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2322                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2323                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2324                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2325                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2326                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2327                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2328                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2329                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2330                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2331                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2332                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2333                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2334                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2335                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2336                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2337                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2338                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2339                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2340                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2341                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2342                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2343                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2344                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2345                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2346                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2347                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2348                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2349         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2350                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2351                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2352                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2353                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2354                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2355                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2356                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2357                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2358                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2359                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2360                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2361                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2362                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2363                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2364                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2365                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2366                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2367                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2368                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2369                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2370                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2371                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2372                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2373                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2374                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2375                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2376                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2377                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2378                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2379                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2380                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2381                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2382                 return 0;
2383         }
2384
2385         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2386                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2387                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2388                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2389                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2390         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2391                    rt2x00_rt(rt2x00dev, RT3090)) {
2392                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2393                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2394                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2395
2396                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2397
2398                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2399                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2400                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2401                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2402                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2403                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2404                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2405                         else
2406                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2407                 }
2408                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2409         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2410                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2411                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2412                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2413         }
2414
2415         /*
2416          * Set RX Filter calibration for 20MHz and 40MHz
2417          */
2418         if (rt2x00_rt(rt2x00dev, RT3070)) {
2419                 rt2x00dev->calibration[0] =
2420                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2421                 rt2x00dev->calibration[1] =
2422                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2423         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2424                    rt2x00_rt(rt2x00dev, RT3090) ||
2425                    rt2x00_rt(rt2x00dev, RT3390)) {
2426                 rt2x00dev->calibration[0] =
2427                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2428                 rt2x00dev->calibration[1] =
2429                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2430         }
2431
2432         /*
2433          * Set back to initial state
2434          */
2435         rt2800_bbp_write(rt2x00dev, 24, 0);
2436
2437         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2438         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2439         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2440
2441         /*
2442          * set BBP back to BW20
2443          */
2444         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2445         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2446         rt2800_bbp_write(rt2x00dev, 4, bbp);
2447
2448         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2449             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2450             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2451             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2452                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2453
2454         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2455         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2456         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2457
2458         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2459         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2460         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2461             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2462             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2463                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2464                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2465         }
2466         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2467         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2468                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2469                                   rt2x00_get_field16(eeprom,
2470                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2471         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2472
2473         if (rt2x00_rt(rt2x00dev, RT3090)) {
2474                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2475
2476                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2477                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2478                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2479                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2480                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2481
2482                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2483         }
2484
2485         if (rt2x00_rt(rt2x00dev, RT3071) ||
2486             rt2x00_rt(rt2x00dev, RT3090) ||
2487             rt2x00_rt(rt2x00dev, RT3390)) {
2488                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2489                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2490                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2491                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2492                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2493                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2494                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2495
2496                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2497                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2498                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2499
2500                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2501                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2502                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2503
2504                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2505                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2506                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2507         }
2508
2509         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2510                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2511                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2512                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2513                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2514                 else
2515                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2516                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2517                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2518                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2519                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2520         }
2521
2522         return 0;
2523 }
2524
2525 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2526 {
2527         u32 reg;
2528         u16 word;
2529
2530         /*
2531          * Initialize all registers.
2532          */
2533         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2534                      rt2800_init_registers(rt2x00dev) ||
2535                      rt2800_init_bbp(rt2x00dev) ||
2536                      rt2800_init_rfcsr(rt2x00dev)))
2537                 return -EIO;
2538
2539         /*
2540          * Send signal to firmware during boot time.
2541          */
2542         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2543
2544         if (rt2x00_is_usb(rt2x00dev) &&
2545             (rt2x00_rt(rt2x00dev, RT3070) ||
2546              rt2x00_rt(rt2x00dev, RT3071) ||
2547              rt2x00_rt(rt2x00dev, RT3572))) {
2548                 udelay(200);
2549                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2550                 udelay(10);
2551         }
2552
2553         /*
2554          * Enable RX.
2555          */
2556         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2557         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2558         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2559         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2560
2561         udelay(50);
2562
2563         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2564         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2565         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2566         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2567         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2568         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2569
2570         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2571         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2572         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2573         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2574
2575         /*
2576          * Initialize LED control
2577          */
2578         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2579         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2580                            word & 0xff, (word >> 8) & 0xff);
2581
2582         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2583         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2584                            word & 0xff, (word >> 8) & 0xff);
2585
2586         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2587         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2588                            word & 0xff, (word >> 8) & 0xff);
2589
2590         return 0;
2591 }
2592 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2593
2594 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2595 {
2596         u32 reg;
2597
2598         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2599         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2600         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2601         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2602         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2603         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2604         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2605
2606         /* Wait for DMA, ignore error */
2607         rt2800_wait_wpdma_ready(rt2x00dev);
2608
2609         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2610         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2611         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2612         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2613
2614         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2615         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2616 }
2617 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2618
2619 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2620 {
2621         u32 reg;
2622
2623         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2624
2625         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2626 }
2627 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2628
2629 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2630 {
2631         u32 reg;
2632
2633         mutex_lock(&rt2x00dev->csr_mutex);
2634
2635         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2636         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2637         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2638         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2639         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2640
2641         /* Wait until the EEPROM has been loaded */
2642         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2643
2644         /* Apparently the data is read from end to start */
2645         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2646                                         (u32 *)&rt2x00dev->eeprom[i]);
2647         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2648                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2649         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2650                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2651         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2652                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2653
2654         mutex_unlock(&rt2x00dev->csr_mutex);
2655 }
2656
2657 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2658 {
2659         unsigned int i;
2660
2661         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2662                 rt2800_efuse_read(rt2x00dev, i);
2663 }
2664 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2665
2666 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2667 {
2668         u16 word;
2669         u8 *mac;
2670         u8 default_lna_gain;
2671
2672         /*
2673          * Start validation of the data that has been read.
2674          */
2675         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2676         if (!is_valid_ether_addr(mac)) {
2677                 random_ether_addr(mac);
2678                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2679         }
2680
2681         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2682         if (word == 0xffff) {
2683                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2684                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2685                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2686                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2687                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2688         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2689                    rt2x00_rt(rt2x00dev, RT2872)) {
2690                 /*
2691                  * There is a max of 2 RX streams for RT28x0 series
2692                  */
2693                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2694                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2695                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2696         }
2697
2698         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2699         if (word == 0xffff) {
2700                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2701                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2702                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2703                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2704                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2705                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2706                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2707                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2708                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2709                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2710                 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2711                 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2712                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2713                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2714         }
2715
2716         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2717         if ((word & 0x00ff) == 0x00ff) {
2718                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2719                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2720                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2721         }
2722         if ((word & 0xff00) == 0xff00) {
2723                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2724                                    LED_MODE_TXRX_ACTIVITY);
2725                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2726                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2727                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2728                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2729                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2730                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2731         }
2732
2733         /*
2734          * During the LNA validation we are going to use
2735          * lna0 as correct value. Note that EEPROM_LNA
2736          * is never validated.
2737          */
2738         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2739         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2740
2741         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2742         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2743                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2744         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2745                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2746         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2747
2748         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2749         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2750                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2751         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2752             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2753                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2754                                    default_lna_gain);
2755         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2756
2757         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2758         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2759                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2760         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2761                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2762         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2763
2764         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2765         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2766                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2767         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2768             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2769                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2770                                    default_lna_gain);
2771         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2772
2773         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2774         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2775                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2776         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2777                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2778         rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2779
2780         return 0;
2781 }
2782 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2783
2784 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2785 {
2786         u32 reg;
2787         u16 value;
2788         u16 eeprom;
2789
2790         /*
2791          * Read EEPROM word for configuration.
2792          */
2793         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2794
2795         /*
2796          * Identify RF chipset.
2797          */
2798         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2799         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2800
2801         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2802                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2803
2804         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2805             !rt2x00_rt(rt2x00dev, RT2872) &&
2806             !rt2x00_rt(rt2x00dev, RT2883) &&
2807             !rt2x00_rt(rt2x00dev, RT3070) &&
2808             !rt2x00_rt(rt2x00dev, RT3071) &&
2809             !rt2x00_rt(rt2x00dev, RT3090) &&
2810             !rt2x00_rt(rt2x00dev, RT3390) &&
2811             !rt2x00_rt(rt2x00dev, RT3572)) {
2812                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2813                 return -ENODEV;
2814         }
2815
2816         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2817             !rt2x00_rf(rt2x00dev, RF2850) &&
2818             !rt2x00_rf(rt2x00dev, RF2720) &&
2819             !rt2x00_rf(rt2x00dev, RF2750) &&
2820             !rt2x00_rf(rt2x00dev, RF3020) &&
2821             !rt2x00_rf(rt2x00dev, RF2020) &&
2822             !rt2x00_rf(rt2x00dev, RF3021) &&
2823             !rt2x00_rf(rt2x00dev, RF3022) &&
2824             !rt2x00_rf(rt2x00dev, RF3052)) {
2825                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2826                 return -ENODEV;
2827         }
2828
2829         /*
2830          * Identify default antenna configuration.
2831          */
2832         rt2x00dev->default_ant.tx =
2833             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2834         rt2x00dev->default_ant.rx =
2835             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2836
2837         /*
2838          * Read frequency offset and RF programming sequence.
2839          */
2840         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2841         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2842
2843         /*
2844          * Read external LNA informations.
2845          */
2846         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2847
2848         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2849                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2850         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2851                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2852
2853         /*
2854          * Detect if this device has an hardware controlled radio.
2855          */
2856         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2857                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2858
2859         /*
2860          * Store led settings, for correct led behaviour.
2861          */
2862 #ifdef CONFIG_RT2X00_LIB_LEDS
2863         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2864         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2865         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2866
2867         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2868 #endif /* CONFIG_RT2X00_LIB_LEDS */
2869
2870         return 0;
2871 }
2872 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2873
2874 /*
2875  * RF value list for rt28xx
2876  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2877  */
2878 static const struct rf_channel rf_vals[] = {
2879         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2880         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2881         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2882         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2883         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2884         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2885         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2886         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2887         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2888         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2889         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2890         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2891         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2892         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2893
2894         /* 802.11 UNI / HyperLan 2 */
2895         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2896         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2897         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2898         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2899         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2900         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2901         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2902         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2903         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2904         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2905         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2906         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2907
2908         /* 802.11 HyperLan 2 */
2909         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2910         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2911         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2912         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2913         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2914         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2915         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2916         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2917         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2918         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2919         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2920         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2921         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2922         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2923         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2924         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2925
2926         /* 802.11 UNII */
2927         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2928         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2929         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2930         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2931         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2932         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2933         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2934         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2935         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2936         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2937         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2938
2939         /* 802.11 Japan */
2940         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2941         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2942         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2943         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2944         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2945         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2946         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2947 };
2948
2949 /*
2950  * RF value list for rt3xxx
2951  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2952  */
2953 static const struct rf_channel rf_vals_3x[] = {
2954         {1,  241, 2, 2 },
2955         {2,  241, 2, 7 },
2956         {3,  242, 2, 2 },
2957         {4,  242, 2, 7 },
2958         {5,  243, 2, 2 },
2959         {6,  243, 2, 7 },
2960         {7,  244, 2, 2 },
2961         {8,  244, 2, 7 },
2962         {9,  245, 2, 2 },
2963         {10, 245, 2, 7 },
2964         {11, 246, 2, 2 },
2965         {12, 246, 2, 7 },
2966         {13, 247, 2, 2 },
2967         {14, 248, 2, 4 },
2968
2969         /* 802.11 UNI / HyperLan 2 */
2970         {36, 0x56, 0, 4},
2971         {38, 0x56, 0, 6},
2972         {40, 0x56, 0, 8},
2973         {44, 0x57, 0, 0},
2974         {46, 0x57, 0, 2},
2975         {48, 0x57, 0, 4},
2976         {52, 0x57, 0, 8},
2977         {54, 0x57, 0, 10},
2978         {56, 0x58, 0, 0},
2979         {60, 0x58, 0, 4},
2980         {62, 0x58, 0, 6},
2981         {64, 0x58, 0, 8},
2982
2983         /* 802.11 HyperLan 2 */
2984         {100, 0x5b, 0, 8},
2985         {102, 0x5b, 0, 10},
2986         {104, 0x5c, 0, 0},
2987         {108, 0x5c, 0, 4},
2988         {110, 0x5c, 0, 6},
2989         {112, 0x5c, 0, 8},
2990         {116, 0x5d, 0, 0},
2991         {118, 0x5d, 0, 2},
2992         {120, 0x5d, 0, 4},
2993         {124, 0x5d, 0, 8},
2994         {126, 0x5d, 0, 10},
2995         {128, 0x5e, 0, 0},
2996         {132, 0x5e, 0, 4},
2997         {134, 0x5e, 0, 6},
2998         {136, 0x5e, 0, 8},
2999         {140, 0x5f, 0, 0},
3000
3001         /* 802.11 UNII */
3002         {149, 0x5f, 0, 9},
3003         {151, 0x5f, 0, 11},
3004         {153, 0x60, 0, 1},
3005         {157, 0x60, 0, 5},
3006         {159, 0x60, 0, 7},
3007         {161, 0x60, 0, 9},
3008         {165, 0x61, 0, 1},
3009         {167, 0x61, 0, 3},
3010         {169, 0x61, 0, 5},
3011         {171, 0x61, 0, 7},
3012         {173, 0x61, 0, 9},
3013 };
3014
3015 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3016 {
3017         struct hw_mode_spec *spec = &rt2x00dev->spec;
3018         struct channel_info *info;
3019         char *default_power1;
3020         char *default_power2;
3021         unsigned int i;
3022         unsigned short max_power;
3023         u16 eeprom;
3024
3025         /*
3026          * Disable powersaving as default on PCI devices.
3027          */
3028         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3029                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3030
3031         /*
3032          * Initialize all hw fields.
3033          */
3034         rt2x00dev->hw->flags =
3035             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3036             IEEE80211_HW_SIGNAL_DBM |
3037             IEEE80211_HW_SUPPORTS_PS |
3038             IEEE80211_HW_PS_NULLFUNC_STACK |
3039             IEEE80211_HW_AMPDU_AGGREGATION;
3040
3041         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3042         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3043                                 rt2x00_eeprom_addr(rt2x00dev,
3044                                                    EEPROM_MAC_ADDR_0));
3045
3046         /*
3047          * As rt2800 has a global fallback table we cannot specify
3048          * more then one tx rate per frame but since the hw will
3049          * try several rates (based on the fallback table) we should
3050          * still initialize max_rates to the maximum number of rates
3051          * we are going to try. Otherwise mac80211 will truncate our
3052          * reported tx rates and the rc algortihm will end up with
3053          * incorrect data.
3054          */
3055         rt2x00dev->hw->max_rates = 7;
3056         rt2x00dev->hw->max_rate_tries = 1;
3057
3058         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3059
3060         /*
3061          * Initialize hw_mode information.
3062          */
3063         spec->supported_bands = SUPPORT_BAND_2GHZ;
3064         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3065
3066         if (rt2x00_rf(rt2x00dev, RF2820) ||
3067             rt2x00_rf(rt2x00dev, RF2720)) {
3068                 spec->num_channels = 14;
3069                 spec->channels = rf_vals;
3070         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3071                    rt2x00_rf(rt2x00dev, RF2750)) {
3072                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3073                 spec->num_channels = ARRAY_SIZE(rf_vals);
3074                 spec->channels = rf_vals;
3075         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3076                    rt2x00_rf(rt2x00dev, RF2020) ||
3077                    rt2x00_rf(rt2x00dev, RF3021) ||
3078                    rt2x00_rf(rt2x00dev, RF3022)) {
3079                 spec->num_channels = 14;
3080                 spec->channels = rf_vals_3x;
3081         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3082                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3083                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3084                 spec->channels = rf_vals_3x;
3085         }
3086
3087         /*
3088          * Initialize HT information.
3089          */
3090         if (!rt2x00_rf(rt2x00dev, RF2020))
3091                 spec->ht.ht_supported = true;
3092         else
3093                 spec->ht.ht_supported = false;
3094
3095         spec->ht.cap =
3096             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3097             IEEE80211_HT_CAP_GRN_FLD |
3098             IEEE80211_HT_CAP_SGI_20 |
3099             IEEE80211_HT_CAP_SGI_40;
3100
3101         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3102                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3103
3104         spec->ht.cap |=
3105             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3106                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3107
3108         spec->ht.ampdu_factor = 3;
3109         spec->ht.ampdu_density = 4;
3110         spec->ht.mcs.tx_params =
3111             IEEE80211_HT_MCS_TX_DEFINED |
3112             IEEE80211_HT_MCS_TX_RX_DIFF |
3113             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3114                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3115
3116         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3117         case 3:
3118                 spec->ht.mcs.rx_mask[2] = 0xff;
3119         case 2:
3120                 spec->ht.mcs.rx_mask[1] = 0xff;
3121         case 1:
3122                 spec->ht.mcs.rx_mask[0] = 0xff;
3123                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3124                 break;
3125         }
3126
3127         /*
3128          * Create channel information array
3129          */
3130         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3131         if (!info)
3132                 return -ENOMEM;
3133
3134         spec->channels_info = info;
3135
3136         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3137         max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3138         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3139         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3140
3141         for (i = 0; i < 14; i++) {
3142                 info[i].max_power = max_power;
3143                 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3144                 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3145         }
3146
3147         if (spec->num_channels > 14) {
3148                 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3149                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3150                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3151
3152                 for (i = 14; i < spec->num_channels; i++) {
3153                         info[i].max_power = max_power;
3154                         info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3155                         info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3156                 }
3157         }
3158
3159         return 0;
3160 }
3161 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3162
3163 /*
3164  * IEEE80211 stack callback functions.
3165  */
3166 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3167                          u16 *iv16)
3168 {
3169         struct rt2x00_dev *rt2x00dev = hw->priv;
3170         struct mac_iveiv_entry iveiv_entry;
3171         u32 offset;
3172
3173         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3174         rt2800_register_multiread(rt2x00dev, offset,
3175                                       &iveiv_entry, sizeof(iveiv_entry));
3176
3177         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3178         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3179 }
3180 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3181
3182 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3183 {
3184         struct rt2x00_dev *rt2x00dev = hw->priv;
3185         u32 reg;
3186         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3187
3188         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3189         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3190         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3191
3192         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3193         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3194         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3195
3196         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3197         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3198         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3199
3200         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3201         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3202         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3203
3204         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3205         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3206         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3207
3208         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3209         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3210         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3211
3212         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3213         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3214         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3215
3216         return 0;
3217 }
3218 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3219
3220 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3221                    const struct ieee80211_tx_queue_params *params)
3222 {
3223         struct rt2x00_dev *rt2x00dev = hw->priv;
3224         struct data_queue *queue;
3225         struct rt2x00_field32 field;
3226         int retval;
3227         u32 reg;
3228         u32 offset;
3229
3230         /*
3231          * First pass the configuration through rt2x00lib, that will
3232          * update the queue settings and validate the input. After that
3233          * we are free to update the registers based on the value
3234          * in the queue parameter.
3235          */
3236         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3237         if (retval)
3238                 return retval;
3239
3240         /*
3241          * We only need to perform additional register initialization
3242          * for WMM queues/
3243          */
3244         if (queue_idx >= 4)
3245                 return 0;
3246
3247         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3248
3249         /* Update WMM TXOP register */
3250         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3251         field.bit_offset = (queue_idx & 1) * 16;
3252         field.bit_mask = 0xffff << field.bit_offset;
3253
3254         rt2800_register_read(rt2x00dev, offset, &reg);
3255         rt2x00_set_field32(&reg, field, queue->txop);
3256         rt2800_register_write(rt2x00dev, offset, reg);
3257
3258         /* Update WMM registers */
3259         field.bit_offset = queue_idx * 4;
3260         field.bit_mask = 0xf << field.bit_offset;
3261
3262         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3263         rt2x00_set_field32(&reg, field, queue->aifs);
3264         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3265
3266         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3267         rt2x00_set_field32(&reg, field, queue->cw_min);
3268         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3269
3270         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3271         rt2x00_set_field32(&reg, field, queue->cw_max);
3272         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3273
3274         /* Update EDCA registers */
3275         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3276
3277         rt2800_register_read(rt2x00dev, offset, &reg);
3278         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3279         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3280         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3281         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3282         rt2800_register_write(rt2x00dev, offset, reg);
3283
3284         return 0;
3285 }
3286 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3287
3288 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3289 {
3290         struct rt2x00_dev *rt2x00dev = hw->priv;
3291         u64 tsf;
3292         u32 reg;
3293
3294         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3295         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3296         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3297         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3298
3299         return tsf;
3300 }
3301 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3302
3303 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3304                         enum ieee80211_ampdu_mlme_action action,
3305                         struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3306 {
3307         int ret = 0;
3308
3309         switch (action) {
3310         case IEEE80211_AMPDU_RX_START:
3311         case IEEE80211_AMPDU_RX_STOP:
3312                 /* we don't support RX aggregation yet */
3313                 ret = -ENOTSUPP;
3314                 break;
3315         case IEEE80211_AMPDU_TX_START:
3316                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3317                 break;
3318         case IEEE80211_AMPDU_TX_STOP:
3319                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3320                 break;
3321         case IEEE80211_AMPDU_TX_OPERATIONAL:
3322                 break;
3323         default:
3324                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3325         }
3326
3327         return ret;
3328 }
3329 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3330
3331 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3332 MODULE_VERSION(DRV_VERSION);
3333 MODULE_DESCRIPTION("Ralink RT2800 library");
3334 MODULE_LICENSE("GPL");