drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 281                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 282                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 283                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 284                         return 0;
 285
 286                 msleep(1);
 287         }
 288
 289         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 290         return -EACCES;
 291 }
 292 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 293
 294 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 295 {
 296         u16 fw_crc;
 297         u16 crc;
 298
 299         /*
 300          * The last 2 bytes in the firmware array are the crc checksum itself,
 301          * this means that we should never pass those 2 bytes to the crc
 302          * algorithm.
 303          */
 304         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 305
 306         /*
 307          * Use the crc ccitt algorithm.
 308          * This will return the same value as the legacy driver which
 309          * used bit ordering reversion on the both the firmware bytes
 310          * before input input as well as on the final output.
 311          * Obviously using crc ccitt directly is much more efficient.
 312          */
 313         crc = crc_ccitt(~0, data, len - 2);
 314
 315         /*
 316          * There is a small difference between the crc-itu-t + bitrev and
 317          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 318          * will be swapped, use swab16 to convert the crc to the correct
 319          * value.
 320          */
 321         crc = swab16(crc);
 322
 323         return fw_crc == crc;
 324 }
 325
 326 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 327                           const u8 *data, const size_t len)
 328 {
 329         size_t offset = 0;
 330         size_t fw_len;
 331         bool multiple;
 332
 333         /*
 334          * PCI(e) & SOC devices require firmware with a length
 335          * of 8kb. USB devices require firmware files with a length
 336          * of 4kb. Certain USB chipsets however require different firmware,
 337          * which Ralink only provides attached to the original firmware
 338          * file. Thus for USB devices, firmware files have a length
 339          * which is a multiple of 4kb.
 340          */
 341         if (rt2x00_is_usb(rt2x00dev)) {
 342                 fw_len = 4096;
 343                 multiple = true;
 344         } else {
 345                 fw_len = 8192;
 346                 multiple = true;
 347         }
 348
 349         /*
 350          * Validate the firmware length
 351          */
 352         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 353                 return FW_BAD_LENGTH;
 354
 355         /*
 356          * Check if the chipset requires one of the upper parts
 357          * of the firmware.
 358          */
 359         if (rt2x00_is_usb(rt2x00dev) &&
 360             !rt2x00_rt(rt2x00dev, RT2860) &&
 361             !rt2x00_rt(rt2x00dev, RT2872) &&
 362             !rt2x00_rt(rt2x00dev, RT3070) &&
 363             ((len / fw_len) == 1))
 364                 return FW_BAD_VERSION;
 365
 366         /*
 367          * 8kb firmware files must be checked as if it were
 368          * 2 separate firmware files.
 369          */
 370         while (offset < len) {
 371                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 372                         return FW_BAD_CRC;
 373
 374                 offset += fw_len;
 375         }
 376
 377         return FW_OK;
 378 }
 379 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 380
 381 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 382                          const u8 *data, const size_t len)
 383 {
 384         unsigned int i;
 385         u32 reg;
 386
 387         /*
 388          * Wait for stable hardware.
 389          */
 390         if (rt2800_wait_csr_ready(rt2x00dev))
 391                 return -EBUSY;
 392
 393         if (rt2x00_is_pci(rt2x00dev))
 394                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 395
 396         /*
 397          * Disable DMA, will be reenabled later when enabling
 398          * the radio.
 399          */
 400         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 401         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 402         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 403         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 404         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 405         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 406         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 407
 408         /*
 409          * Write firmware to the device.
 410          */
 411         rt2800_drv_write_firmware(rt2x00dev, data, len);
 412
 413         /*
 414          * Wait for device to stabilize.
 415          */
 416         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 417                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 418                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 419                         break;
 420                 msleep(1);
 421         }
 422
 423         if (i == REGISTER_BUSY_COUNT) {
 424                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 425                 return -EBUSY;
 426         }
 427
 428         /*
 429          * Initialize firmware.
 430          */
 431         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 432         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 433         msleep(1);
 434
 435         return 0;
 436 }
 437 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 438
 439 void rt2800_write_tx_data(struct queue_entry *entry,
 440                           struct txentry_desc *txdesc)
 441 {
 442         __le32 *txwi = rt2800_drv_get_txwi(entry);
 443         u32 word;
 444
 445         /*
 446          * Initialize TX Info descriptor
 447          */
 448         rt2x00_desc_read(txwi, 0, &word);
 449         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 450                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 451         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 452                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 453         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 454         rt2x00_set_field32(&word, TXWI_W0_TS,
 455                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 456         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 457                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 458         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 459         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
 460         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 461         rt2x00_set_field32(&word, TXWI_W0_BW,
 462                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 463         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 464                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 465         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 466         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 467         rt2x00_desc_write(txwi, 0, word);
 468
 469         rt2x00_desc_read(txwi, 1, &word);
 470         rt2x00_set_field32(&word, TXWI_W1_ACK,
 471                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 472         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 473                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 474         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 475         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 476                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 477                            txdesc->key_idx : 0xff);
 478         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 479                            txdesc->length);
 480         rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->qid + 1);
 481         rt2x00_desc_write(txwi, 1, word);
 482
 483         /*
 484          * Always write 0 to IV/EIV fields, hardware will insert the IV
 485          * from the IVEIV register when TXD_W3_WIV is set to 0.
 486          * When TXD_W3_WIV is set to 1 it will use the IV data
 487          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 488          * crypto entry in the registers should be used to encrypt the frame.
 489          */
 490         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 491         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 492 }
 493 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 494
 495 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
 496 {
 497         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 498         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 499         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 500         u16 eeprom;
 501         u8 offset0;
 502         u8 offset1;
 503         u8 offset2;
 504
 505         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 506                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 507                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 508                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 509                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 510                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 511         } else {
 512                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 513                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 514                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 515                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 516                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 517         }
 518
 519         /*
 520          * Convert the value from the descriptor into the RSSI value
 521          * If the value in the descriptor is 0, it is considered invalid
 522          * and the default (extremely low) rssi value is assumed
 523          */
 524         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 525         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 526         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 527
 528         /*
 529          * mac80211 only accepts a single RSSI value. Calculating the
 530          * average doesn't deliver a fair answer either since -60:-60 would
 531          * be considered equally good as -50:-70 while the second is the one
 532          * which gives less energy...
 533          */
 534         rssi0 = max(rssi0, rssi1);
 535         return max(rssi0, rssi2);
 536 }
 537
 538 void rt2800_process_rxwi(struct queue_entry *entry,
 539                          struct rxdone_entry_desc *rxdesc)
 540 {
 541         __le32 *rxwi = (__le32 *) entry->skb->data;
 542         u32 word;
 543
 544         rt2x00_desc_read(rxwi, 0, &word);
 545
 546         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 547         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 548
 549         rt2x00_desc_read(rxwi, 1, &word);
 550
 551         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 552                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 553
 554         if (rt2x00_get_field32(word, RXWI_W1_BW))
 555                 rxdesc->flags |= RX_FLAG_40MHZ;
 556
 557         /*
 558          * Detect RX rate, always use MCS as signal type.
 559          */
 560         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 561         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 562         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 563
 564         /*
 565          * Mask of 0x8 bit to remove the short preamble flag.
 566          */
 567         if (rxdesc->rate_mode == RATE_MODE_CCK)
 568                 rxdesc->signal &= ~0x8;
 569
 570         rt2x00_desc_read(rxwi, 2, &word);
 571
 572         /*
 573          * Convert descriptor AGC value to RSSI value.
 574          */
 575         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 576
 577         /*
 578          * Remove RXWI descriptor from start of buffer.
 579          */
 580         skb_pull(entry->skb, RXWI_DESC_SIZE);
 581 }
 582 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 583
 584 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 585 {
 586         __le32 *txwi;
 587         u32 word;
 588         int wcid, ack, pid;
 589         int tx_wcid, tx_ack, tx_pid;
 590
 591         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 592         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 593         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 594
 595         /*
 596          * This frames has returned with an IO error,
 597          * so the status report is not intended for this
 598          * frame.
 599          */
 600         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 601                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 602                 return false;
 603         }
 604
 605         /*
 606          * Validate if this TX status report is intended for
 607          * this entry by comparing the WCID/ACK/PID fields.
 608          */
 609         txwi = rt2800_drv_get_txwi(entry);
 610
 611         rt2x00_desc_read(txwi, 1, &word);
 612         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 613         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 614         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 615
 616         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 617                 WARNING(entry->queue->rt2x00dev,
 618                         "TX status report missed for queue %d entry %d\n",
 619                 entry->queue->qid, entry->entry_idx);
 620                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 621                 return false;
 622         }
 623
 624         return true;
 625 }
 626
 627 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 628 {
 629         struct data_queue *queue;
 630         struct queue_entry *entry;
 631         __le32 *txwi;
 632         struct txdone_entry_desc txdesc;
 633         u32 word;
 634         u32 reg;
 635         u16 mcs, real_mcs;
 636         u8 pid;
 637         int i;
 638
 639         /*
 640          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 641          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 642          * flag is not set anymore.
 643          *
 644          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 645          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 646          * tx ring size for now.
 647          */
 648         for (i = 0; i < TX_ENTRIES; i++) {
 649                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 650                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 651                         break;
 652
 653                 /*
 654                  * Skip this entry when it contains an invalid
 655                  * queue identication number.
 656                  */
 657                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
 658                 if (pid >= QID_RX)
 659                         continue;
 660
 661                 queue = rt2x00queue_get_queue(rt2x00dev, pid);
 662                 if (unlikely(!queue))
 663                         continue;
 664
 665                 /*
 666                  * Inside each queue, we process each entry in a chronological
 667                  * order. We first check that the queue is not empty.
 668                  */
 669                 entry = NULL;
 670                 txwi = NULL;
 671                 while (!rt2x00queue_empty(queue)) {
 672                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 673                         if (rt2800_txdone_entry_check(entry, reg))
 674                                 break;
 675                 }
 676
 677                 if (!entry || rt2x00queue_empty(queue))
 678                         break;
 679
 680
 681                 /*
 682                  * Obtain the status about this packet.
 683                  */
 684                 txdesc.flags = 0;
 685                 txwi = rt2800_drv_get_txwi(entry);
 686                 rt2x00_desc_read(txwi, 0, &word);
 687                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 688                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 689
 690                 /*
 691                  * Ralink has a retry mechanism using a global fallback
 692                  * table. We setup this fallback table to try the immediate
 693                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 694                  * always contains the MCS used for the last transmission, be
 695                  * it successful or not.
 696                  */
 697                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 698                         /*
 699                          * Transmission succeeded. The number of retries is
 700                          * mcs - real_mcs
 701                          */
 702                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 703                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 704                 } else {
 705                         /*
 706                          * Transmission failed. The number of retries is
 707                          * always 7 in this case (for a total number of 8
 708                          * frames sent).
 709                          */
 710                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 711                         txdesc.retry = rt2x00dev->long_retry;
 712                 }
 713
 714                 /*
 715                  * the frame was retried at least once
 716                  * -> hw used fallback rates
 717                  */
 718                 if (txdesc.retry)
 719                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 720
 721                 rt2x00lib_txdone(entry, &txdesc);
 722         }
 723 }
 724 EXPORT_SYMBOL_GPL(rt2800_txdone);
 725
 726 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 727 {
 728         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 729         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 730         unsigned int beacon_base;
 731         u32 reg;
 732
 733         /*
 734          * Disable beaconing while we are reloading the beacon data,
 735          * otherwise we might be sending out invalid data.
 736          */
 737         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 738         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 739         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 740
 741         /*
 742          * Add space for the TXWI in front of the skb.
 743          */
 744         skb_push(entry->skb, TXWI_DESC_SIZE);
 745         memset(entry->skb, 0, TXWI_DESC_SIZE);
 746
 747         /*
 748          * Register descriptor details in skb frame descriptor.
 749          */
 750         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 751         skbdesc->desc = entry->skb->data;
 752         skbdesc->desc_len = TXWI_DESC_SIZE;
 753
 754         /*
 755          * Add the TXWI for the beacon to the skb.
 756          */
 757         rt2800_write_tx_data(entry, txdesc);
 758
 759         /*
 760          * Dump beacon to userspace through debugfs.
 761          */
 762         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 763
 764         /*
 765          * Write entire beacon with TXWI to register.
 766          */
 767         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 768         rt2800_register_multiwrite(rt2x00dev, beacon_base,
 769                                    entry->skb->data, entry->skb->len);
 770
 771         /*
 772          * Enable beaconing again.
 773          */
 774         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 775         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 776         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 777         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 778
 779         /*
 780          * Clean up beacon skb.
 781          */
 782         dev_kfree_skb_any(entry->skb);
 783         entry->skb = NULL;
 784 }
 785 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 786
 787 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
 788                                        unsigned int beacon_base)
 789 {
 790         int i;
 791
 792         /*
 793          * For the Beacon base registers we only need to clear
 794          * the whole TXWI which (when set to 0) will invalidate
 795          * the entire beacon.
 796          */
 797         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 798                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 799 }
 800
 801 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 802 const struct rt2x00debug rt2800_rt2x00debug = {
 803         .owner  = THIS_MODULE,
 804         .csr    = {
 805                 .read           = rt2800_register_read,
 806                 .write          = rt2800_register_write,
 807                 .flags          = RT2X00DEBUGFS_OFFSET,
 808                 .word_base      = CSR_REG_BASE,
 809                 .word_size      = sizeof(u32),
 810                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 811         },
 812         .eeprom = {
 813                 .read           = rt2x00_eeprom_read,
 814                 .write          = rt2x00_eeprom_write,
 815                 .word_base      = EEPROM_BASE,
 816                 .word_size      = sizeof(u16),
 817                 .word_count     = EEPROM_SIZE / sizeof(u16),
 818         },
 819         .bbp    = {
 820                 .read           = rt2800_bbp_read,
 821                 .write          = rt2800_bbp_write,
 822                 .word_base      = BBP_BASE,
 823                 .word_size      = sizeof(u8),
 824                 .word_count     = BBP_SIZE / sizeof(u8),
 825         },
 826         .rf     = {
 827                 .read           = rt2x00_rf_read,
 828                 .write          = rt2800_rf_write,
 829                 .word_base      = RF_BASE,
 830                 .word_size      = sizeof(u32),
 831                 .word_count     = RF_SIZE / sizeof(u32),
 832         },
 833 };
 834 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 835 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 836
 837 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 838 {
 839         u32 reg;
 840
 841         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 842         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 843 }
 844 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 845
 846 #ifdef CONFIG_RT2X00_LIB_LEDS
 847 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 848                                   enum led_brightness brightness)
 849 {
 850         struct rt2x00_led *led =
 851             container_of(led_cdev, struct rt2x00_led, led_dev);
 852         unsigned int enabled = brightness != LED_OFF;
 853         unsigned int bg_mode =
 854             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 855         unsigned int polarity =
 856                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 857                                    EEPROM_FREQ_LED_POLARITY);
 858         unsigned int ledmode =
 859                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 860                                    EEPROM_FREQ_LED_MODE);
 861
 862         if (led->type == LED_TYPE_RADIO) {
 863                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 864                                       enabled ? 0x20 : 0);
 865         } else if (led->type == LED_TYPE_ASSOC) {
 866                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 867                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 868         } else if (led->type == LED_TYPE_QUALITY) {
 869                 /*
 870                  * The brightness is divided into 6 levels (0 - 5),
 871                  * The specs tell us the following levels:
 872                  *      0, 1 ,3, 7, 15, 31
 873                  * to determine the level in a simple way we can simply
 874                  * work with bitshifting:
 875                  *      (1 << level) - 1
 876                  */
 877                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 878                                       (1 << brightness / (LED_FULL / 6)) - 1,
 879                                       polarity);
 880         }
 881 }
 882
 883 static int rt2800_blink_set(struct led_classdev *led_cdev,
 884                             unsigned long *delay_on, unsigned long *delay_off)
 885 {
 886         struct rt2x00_led *led =
 887             container_of(led_cdev, struct rt2x00_led, led_dev);
 888         u32 reg;
 889
 890         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 891         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 892         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 893         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 894
 895         return 0;
 896 }
 897
 898 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 899                      struct rt2x00_led *led, enum led_type type)
 900 {
 901         led->rt2x00dev = rt2x00dev;
 902         led->type = type;
 903         led->led_dev.brightness_set = rt2800_brightness_set;
 904         led->led_dev.blink_set = rt2800_blink_set;
 905         led->flags = LED_INITIALIZED;
 906 }
 907 #endif /* CONFIG_RT2X00_LIB_LEDS */
 908
 909 /*
 910  * Configuration handlers.
 911  */
 912 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 913                                     struct rt2x00lib_crypto *crypto,
 914                                     struct ieee80211_key_conf *key)
 915 {
 916         struct mac_wcid_entry wcid_entry;
 917         struct mac_iveiv_entry iveiv_entry;
 918         u32 offset;
 919         u32 reg;
 920
 921         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 922
 923         if (crypto->cmd == SET_KEY) {
 924                 rt2800_register_read(rt2x00dev, offset, &reg);
 925                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 926                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 927                 /*
 928                  * Both the cipher as the BSS Idx numbers are split in a main
 929                  * value of 3 bits, and a extended field for adding one additional
 930                  * bit to the value.
 931                  */
 932                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 933                                    (crypto->cipher & 0x7));
 934                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 935                                    (crypto->cipher & 0x8) >> 3);
 936                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 937                                    (crypto->bssidx & 0x7));
 938                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 939                                    (crypto->bssidx & 0x8) >> 3);
 940                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 941                 rt2800_register_write(rt2x00dev, offset, reg);
 942         } else {
 943                 rt2800_register_write(rt2x00dev, offset, 0);
 944         }
 945
 946         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 947
 948         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 949         if ((crypto->cipher == CIPHER_TKIP) ||
 950             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 951             (crypto->cipher == CIPHER_AES))
 952                 iveiv_entry.iv[3] |= 0x20;
 953         iveiv_entry.iv[3] |= key->keyidx << 6;
 954         rt2800_register_multiwrite(rt2x00dev, offset,
 955                                       &iveiv_entry, sizeof(iveiv_entry));
 956
 957         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 958
 959         memset(&wcid_entry, 0, sizeof(wcid_entry));
 960         if (crypto->cmd == SET_KEY)
 961                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 962         rt2800_register_multiwrite(rt2x00dev, offset,
 963                                       &wcid_entry, sizeof(wcid_entry));
 964 }
 965
 966 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 967                              struct rt2x00lib_crypto *crypto,
 968                              struct ieee80211_key_conf *key)
 969 {
 970         struct hw_key_entry key_entry;
 971         struct rt2x00_field32 field;
 972         u32 offset;
 973         u32 reg;
 974
 975         if (crypto->cmd == SET_KEY) {
 976                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 977
 978                 memcpy(key_entry.key, crypto->key,
 979                        sizeof(key_entry.key));
 980                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 981                        sizeof(key_entry.tx_mic));
 982                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 983                        sizeof(key_entry.rx_mic));
 984
 985                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 986                 rt2800_register_multiwrite(rt2x00dev, offset,
 987                                               &key_entry, sizeof(key_entry));
 988         }
 989
 990         /*
 991          * The cipher types are stored over multiple registers
 992          * starting with SHARED_KEY_MODE_BASE each word will have
 993          * 32 bits and contains the cipher types for 2 bssidx each.
 994          * Using the correct defines correctly will cause overhead,
 995          * so just calculate the correct offset.
 996          */
 997         field.bit_offset = 4 * (key->hw_key_idx % 8);
 998         field.bit_mask = 0x7 << field.bit_offset;
 999
1000         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1001
1002         rt2800_register_read(rt2x00dev, offset, &reg);
1003         rt2x00_set_field32(&reg, field,
1004                            (crypto->cmd == SET_KEY) * crypto->cipher);
1005         rt2800_register_write(rt2x00dev, offset, reg);
1006
1007         /*
1008          * Update WCID information
1009          */
1010         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1011
1012         return 0;
1013 }
1014 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1015
1016 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1017                                struct rt2x00lib_crypto *crypto,
1018                                struct ieee80211_key_conf *key)
1019 {
1020         struct hw_key_entry key_entry;
1021         u32 offset;
1022
1023         if (crypto->cmd == SET_KEY) {
1024                 /*
1025                  * 1 pairwise key is possible per AID, this means that the AID
1026                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1027                  * last possible shared key entry.
1028                  */
1029                 if (crypto->aid > (256 - 32))
1030                         return -ENOSPC;
1031
1032                 key->hw_key_idx = 32 + crypto->aid;
1033
1034                 memcpy(key_entry.key, crypto->key,
1035                        sizeof(key_entry.key));
1036                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1037                        sizeof(key_entry.tx_mic));
1038                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1039                        sizeof(key_entry.rx_mic));
1040
1041                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1042                 rt2800_register_multiwrite(rt2x00dev, offset,
1043                                               &key_entry, sizeof(key_entry));
1044         }
1045
1046         /*
1047          * Update WCID information
1048          */
1049         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1050
1051         return 0;
1052 }
1053 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1054
1055 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1056                           const unsigned int filter_flags)
1057 {
1058         u32 reg;
1059
1060         /*
1061          * Start configuration steps.
1062          * Note that the version error will always be dropped
1063          * and broadcast frames will always be accepted since
1064          * there is no filter for it at this time.
1065          */
1066         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1067         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1068                            !(filter_flags & FIF_FCSFAIL));
1069         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1070                            !(filter_flags & FIF_PLCPFAIL));
1071         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1072                            !(filter_flags & FIF_PROMISC_IN_BSS));
1073         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1074         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1075         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1076                            !(filter_flags & FIF_ALLMULTI));
1077         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1078         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1079         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1080                            !(filter_flags & FIF_CONTROL));
1081         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1082                            !(filter_flags & FIF_CONTROL));
1083         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1084                            !(filter_flags & FIF_CONTROL));
1085         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1086                            !(filter_flags & FIF_CONTROL));
1087         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1088                            !(filter_flags & FIF_CONTROL));
1089         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1090                            !(filter_flags & FIF_PSPOLL));
1091         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1092         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1093         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1094                            !(filter_flags & FIF_CONTROL));
1095         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1096 }
1097 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1098
1099 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1100                         struct rt2x00intf_conf *conf, const unsigned int flags)
1101 {
1102         u32 reg;
1103
1104         if (flags & CONFIG_UPDATE_TYPE) {
1105                 /*
1106                  * Clear current synchronisation setup.
1107                  */
1108                 rt2800_clear_beacon(rt2x00dev,
1109                                     HW_BEACON_OFFSET(intf->beacon->entry_idx));
1110                 /*
1111                  * Enable synchronisation.
1112                  */
1113                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1114                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1115                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1116                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1117                                    (conf->sync == TSF_SYNC_ADHOC ||
1118                                     conf->sync == TSF_SYNC_AP_NONE));
1119                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1120
1121                 /*
1122                  * Enable pre tbtt interrupt for beaconing modes
1123                  */
1124                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1125                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1126                                    (conf->sync == TSF_SYNC_AP_NONE));
1127                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1128
1129         }
1130
1131         if (flags & CONFIG_UPDATE_MAC) {
1132                 reg = le32_to_cpu(conf->mac[1]);
1133                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1134                 conf->mac[1] = cpu_to_le32(reg);
1135
1136                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1137                                               conf->mac, sizeof(conf->mac));
1138         }
1139
1140         if (flags & CONFIG_UPDATE_BSSID) {
1141                 reg = le32_to_cpu(conf->bssid[1]);
1142                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1143                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1144                 conf->bssid[1] = cpu_to_le32(reg);
1145
1146                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1147                                               conf->bssid, sizeof(conf->bssid));
1148         }
1149 }
1150 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1151
1152 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
1153 {
1154         u32 reg;
1155
1156         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1157         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1158                            !!erp->short_preamble);
1159         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1160                            !!erp->short_preamble);
1161         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1162
1163         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1164         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1165                            erp->cts_protection ? 2 : 0);
1166         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1167
1168         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1169                                  erp->basic_rates);
1170         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1171
1172         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1173         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
1174         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1175
1176         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1177         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1178         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1179
1180         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1181         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1182                            erp->beacon_int * 16);
1183         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1184 }
1185 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1186
1187 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1188 {
1189         u8 r1;
1190         u8 r3;
1191
1192         rt2800_bbp_read(rt2x00dev, 1, &r1);
1193         rt2800_bbp_read(rt2x00dev, 3, &r3);
1194
1195         /*
1196          * Configure the TX antenna.
1197          */
1198         switch ((int)ant->tx) {
1199         case 1:
1200                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1201                 break;
1202         case 2:
1203                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1204                 break;
1205         case 3:
1206                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1207                 break;
1208         }
1209
1210         /*
1211          * Configure the RX antenna.
1212          */
1213         switch ((int)ant->rx) {
1214         case 1:
1215                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1216                 break;
1217         case 2:
1218                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1219                 break;
1220         case 3:
1221                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1222                 break;
1223         }
1224
1225         rt2800_bbp_write(rt2x00dev, 3, r3);
1226         rt2800_bbp_write(rt2x00dev, 1, r1);
1227 }
1228 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1229
1230 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1231                                    struct rt2x00lib_conf *libconf)
1232 {
1233         u16 eeprom;
1234         short lna_gain;
1235
1236         if (libconf->rf.channel <= 14) {
1237                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1238                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1239         } else if (libconf->rf.channel <= 64) {
1240                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1241                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1242         } else if (libconf->rf.channel <= 128) {
1243                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1244                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1245         } else {
1246                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1247                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1248         }
1249
1250         rt2x00dev->lna_gain = lna_gain;
1251 }
1252
1253 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1254                                          struct ieee80211_conf *conf,
1255                                          struct rf_channel *rf,
1256                                          struct channel_info *info)
1257 {
1258         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1259
1260         if (rt2x00dev->default_ant.tx == 1)
1261                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1262
1263         if (rt2x00dev->default_ant.rx == 1) {
1264                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1265                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1266         } else if (rt2x00dev->default_ant.rx == 2)
1267                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1268
1269         if (rf->channel > 14) {
1270                 /*
1271                  * When TX power is below 0, we should increase it by 7 to
1272                  * make it a positive value (Minumum value is -7).
1273                  * However this means that values between 0 and 7 have
1274                  * double meaning, and we should set a 7DBm boost flag.
1275                  */
1276                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1277                                    (info->default_power1 >= 0));
1278
1279                 if (info->default_power1 < 0)
1280                         info->default_power1 += 7;
1281
1282                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1283
1284                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1285                                    (info->default_power2 >= 0));
1286
1287                 if (info->default_power2 < 0)
1288                         info->default_power2 += 7;
1289
1290                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1291         } else {
1292                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1293                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1294         }
1295
1296         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1297
1298         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1299         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1300         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1301         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1302
1303         udelay(200);
1304
1305         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1306         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1307         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1308         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1309
1310         udelay(200);
1311
1312         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1313         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1314         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1315         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1316 }
1317
1318 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1319                                          struct ieee80211_conf *conf,
1320                                          struct rf_channel *rf,
1321                                          struct channel_info *info)
1322 {
1323         u8 rfcsr;
1324
1325         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1326         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1327
1328         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1329         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1330         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1331
1332         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1333         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1334         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1335
1336         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1337         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1338         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1339
1340         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1341         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1342         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1343
1344         rt2800_rfcsr_write(rt2x00dev, 24,
1345                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1346
1347         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1348         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1349         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1350 }
1351
1352 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1353                                   struct ieee80211_conf *conf,
1354                                   struct rf_channel *rf,
1355                                   struct channel_info *info)
1356 {
1357         u32 reg;
1358         unsigned int tx_pin;
1359         u8 bbp;
1360
1361         if (rf->channel <= 14) {
1362                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1363                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1364         } else {
1365                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1366                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1367         }
1368
1369         if (rt2x00_rf(rt2x00dev, RF2020) ||
1370             rt2x00_rf(rt2x00dev, RF3020) ||
1371             rt2x00_rf(rt2x00dev, RF3021) ||
1372             rt2x00_rf(rt2x00dev, RF3022) ||
1373             rt2x00_rf(rt2x00dev, RF3052))
1374                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1375         else
1376                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1377
1378         /*
1379          * Change BBP settings
1380          */
1381         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1382         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1383         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1384         rt2800_bbp_write(rt2x00dev, 86, 0);
1385
1386         if (rf->channel <= 14) {
1387                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1388                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1389                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1390                 } else {
1391                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1392                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1393                 }
1394         } else {
1395                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1396
1397                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1398                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1399                 else
1400                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1401         }
1402
1403         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1404         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1405         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1406         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1407         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1408
1409         tx_pin = 0;
1410
1411         /* Turn on unused PA or LNA when not using 1T or 1R */
1412         if (rt2x00dev->default_ant.tx != 1) {
1413                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1414                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1415         }
1416
1417         /* Turn on unused PA or LNA when not using 1T or 1R */
1418         if (rt2x00dev->default_ant.rx != 1) {
1419                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1420                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1421         }
1422
1423         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1424         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1425         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1426         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1427         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1428         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1429
1430         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1431
1432         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1433         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1434         rt2800_bbp_write(rt2x00dev, 4, bbp);
1435
1436         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1437         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1438         rt2800_bbp_write(rt2x00dev, 3, bbp);
1439
1440         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1441                 if (conf_is_ht40(conf)) {
1442                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1443                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1444                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1445                 } else {
1446                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1447                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1448                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1449                 }
1450         }
1451
1452         msleep(1);
1453 }
1454
1455 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1456                                   const int max_txpower)
1457 {
1458         u8 txpower;
1459         u8 max_value = (u8)max_txpower;
1460         u16 eeprom;
1461         int i;
1462         u32 reg;
1463         u8 r1;
1464         u32 offset;
1465
1466         /*
1467          * set to normal tx power mode: +/- 0dBm
1468          */
1469         rt2800_bbp_read(rt2x00dev, 1, &r1);
1470         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1471         rt2800_bbp_write(rt2x00dev, 1, r1);
1472
1473         /*
1474          * The eeprom contains the tx power values for each rate. These
1475          * values map to 100% tx power. Each 16bit word contains four tx
1476          * power values and the order is the same as used in the TX_PWR_CFG
1477          * registers.
1478          */
1479         offset = TX_PWR_CFG_0;
1480
1481         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1482                 /* just to be safe */
1483                 if (offset > TX_PWR_CFG_4)
1484                         break;
1485
1486                 rt2800_register_read(rt2x00dev, offset, &reg);
1487
1488                 /* read the next four txpower values */
1489                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1490                                    &eeprom);
1491
1492                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1493                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1494                  * TX_PWR_CFG_4: unknown */
1495                 txpower = rt2x00_get_field16(eeprom,
1496                                              EEPROM_TXPOWER_BYRATE_RATE0);
1497                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1498                                    min(txpower, max_value));
1499
1500                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1501                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1502                  * TX_PWR_CFG_4: unknown */
1503                 txpower = rt2x00_get_field16(eeprom,
1504                                              EEPROM_TXPOWER_BYRATE_RATE1);
1505                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1506                                    min(txpower, max_value));
1507
1508                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1509                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1510                  * TX_PWR_CFG_4: unknown */
1511                 txpower = rt2x00_get_field16(eeprom,
1512                                              EEPROM_TXPOWER_BYRATE_RATE2);
1513                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1514                                    min(txpower, max_value));
1515
1516                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1517                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1518                  * TX_PWR_CFG_4: unknown */
1519                 txpower = rt2x00_get_field16(eeprom,
1520                                              EEPROM_TXPOWER_BYRATE_RATE3);
1521                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1522                                    min(txpower, max_value));
1523
1524                 /* read the next four txpower values */
1525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1526                                    &eeprom);
1527
1528                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1529                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1530                  * TX_PWR_CFG_4: unknown */
1531                 txpower = rt2x00_get_field16(eeprom,
1532                                              EEPROM_TXPOWER_BYRATE_RATE0);
1533                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1534                                    min(txpower, max_value));
1535
1536                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1537                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1538                  * TX_PWR_CFG_4: unknown */
1539                 txpower = rt2x00_get_field16(eeprom,
1540                                              EEPROM_TXPOWER_BYRATE_RATE1);
1541                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1542                                    min(txpower, max_value));
1543
1544                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1545                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1546                  * TX_PWR_CFG_4: unknown */
1547                 txpower = rt2x00_get_field16(eeprom,
1548                                              EEPROM_TXPOWER_BYRATE_RATE2);
1549                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1550                                    min(txpower, max_value));
1551
1552                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1553                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1554                  * TX_PWR_CFG_4: unknown */
1555                 txpower = rt2x00_get_field16(eeprom,
1556                                              EEPROM_TXPOWER_BYRATE_RATE3);
1557                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1558                                    min(txpower, max_value));
1559
1560                 rt2800_register_write(rt2x00dev, offset, reg);
1561
1562                 /* next TX_PWR_CFG register */
1563                 offset += 4;
1564         }
1565 }
1566
1567 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1568                                       struct rt2x00lib_conf *libconf)
1569 {
1570         u32 reg;
1571
1572         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1573         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1574                            libconf->conf->short_frame_max_tx_count);
1575         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1576                            libconf->conf->long_frame_max_tx_count);
1577         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1578 }
1579
1580 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1581                              struct rt2x00lib_conf *libconf)
1582 {
1583         enum dev_state state =
1584             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1585                 STATE_SLEEP : STATE_AWAKE;
1586         u32 reg;
1587
1588         if (state == STATE_SLEEP) {
1589                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1590
1591                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1592                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1593                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1594                                    libconf->conf->listen_interval - 1);
1595                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1596                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1597
1598                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1599         } else {
1600                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1601                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1602                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1603                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1604                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1605
1606                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1607         }
1608 }
1609
1610 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1611                    struct rt2x00lib_conf *libconf,
1612                    const unsigned int flags)
1613 {
1614         /* Always recalculate LNA gain before changing configuration */
1615         rt2800_config_lna_gain(rt2x00dev, libconf);
1616
1617         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1618                 rt2800_config_channel(rt2x00dev, libconf->conf,
1619                                       &libconf->rf, &libconf->channel);
1620         if (flags & IEEE80211_CONF_CHANGE_POWER)
1621                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1622         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1623                 rt2800_config_retry_limit(rt2x00dev, libconf);
1624         if (flags & IEEE80211_CONF_CHANGE_PS)
1625                 rt2800_config_ps(rt2x00dev, libconf);
1626 }
1627 EXPORT_SYMBOL_GPL(rt2800_config);
1628
1629 /*
1630  * Link tuning
1631  */
1632 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1633 {
1634         u32 reg;
1635
1636         /*
1637          * Update FCS error count from register.
1638          */
1639         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1640         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1641 }
1642 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1643
1644 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1645 {
1646         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1647                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1648                     rt2x00_rt(rt2x00dev, RT3071) ||
1649                     rt2x00_rt(rt2x00dev, RT3090) ||
1650                     rt2x00_rt(rt2x00dev, RT3390))
1651                         return 0x1c + (2 * rt2x00dev->lna_gain);
1652                 else
1653                         return 0x2e + rt2x00dev->lna_gain;
1654         }
1655
1656         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1657                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1658         else
1659                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1660 }
1661
1662 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1663                                   struct link_qual *qual, u8 vgc_level)
1664 {
1665         if (qual->vgc_level != vgc_level) {
1666                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1667                 qual->vgc_level = vgc_level;
1668                 qual->vgc_level_reg = vgc_level;
1669         }
1670 }
1671
1672 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1673 {
1674         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1675 }
1676 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1677
1678 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1679                        const u32 count)
1680 {
1681         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1682                 return;
1683
1684         /*
1685          * When RSSI is better then -80 increase VGC level with 0x10
1686          */
1687         rt2800_set_vgc(rt2x00dev, qual,
1688                        rt2800_get_default_vgc(rt2x00dev) +
1689                        ((qual->rssi > -80) * 0x10));
1690 }
1691 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1692
1693 /*
1694  * Initialization functions.
1695  */
1696 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1697 {
1698         u32 reg;
1699         u16 eeprom;
1700         unsigned int i;
1701         int ret;
1702
1703         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1704         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1705         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1706         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1707         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1708         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1709         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1710
1711         ret = rt2800_drv_init_registers(rt2x00dev);
1712         if (ret)
1713                 return ret;
1714
1715         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1716         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1717         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1718         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1719         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1720         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1721
1722         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1723         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1724         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1725         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1726         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1727         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1728
1729         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1730         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1731
1732         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1733
1734         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1735         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1736         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1737         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1738         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1739         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1740         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1741         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1742
1743         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1744
1745         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1746         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1747         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1748         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1749
1750         if (rt2x00_rt(rt2x00dev, RT3071) ||
1751             rt2x00_rt(rt2x00dev, RT3090) ||
1752             rt2x00_rt(rt2x00dev, RT3390)) {
1753                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1754                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1755                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1756                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1757                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1758                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1759                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1760                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1761                                                       0x0000002c);
1762                         else
1763                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1764                                                       0x0000000f);
1765                 } else {
1766                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1767                 }
1768         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1769                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1770
1771                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1772                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1773                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1774                 } else {
1775                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1776                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1777                 }
1778         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1779                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1780                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1781                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1782         } else {
1783                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1784                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1785         }
1786
1787         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1788         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1789         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1790         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1791         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1792         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1793         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1794         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1795         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1796         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1797
1798         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1799         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1800         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1801         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1802         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1803
1804         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1805         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1806         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1807             rt2x00_rt(rt2x00dev, RT2883) ||
1808             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1809                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1810         else
1811                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1812         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1813         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1814         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1815
1816         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1817         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1818         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1819         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1820         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1821         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1822         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1823         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1824         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1825
1826         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1827
1828         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1829         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1830         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1831         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1832         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1833         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1834         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1835         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1836
1837         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1838         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1839         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1840         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1841         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1842         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1843         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1844         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1845         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1846
1847         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1848         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1849         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1850         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1851         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1852         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1853         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1854         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1855         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1856         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1857         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1858         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1859
1860         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1861         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1862         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1863         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1864         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1865         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1866         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1867         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1868         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1869         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1870         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1871         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1872
1873         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1874         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1875         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1876         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1877         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1878         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1879         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1880         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1881         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1882         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1883         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1884         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1885
1886         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1887         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1888         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1889                            !rt2x00_is_usb(rt2x00dev));
1890         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1891         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1892         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1893         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1894         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1895         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1896         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1897         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1898         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1899
1900         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1901         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1902         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1903         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1904         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1905         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1906         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1907         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1908         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1909         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1910         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1911         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1912
1913         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1914         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1915         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1916         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1917         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1918         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1919         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1920         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1921         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1922         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1923         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1924         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1925
1926         if (rt2x00_is_usb(rt2x00dev)) {
1927                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1928
1929                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1930                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1931                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1932                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1933                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1934                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1935                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1936                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1937                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1938                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1939                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1940         }
1941
1942         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1943         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1944
1945         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1946         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1947         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1948                            IEEE80211_MAX_RTS_THRESHOLD);
1949         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1950         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1951
1952         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1953
1954         /*
1955          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1956          * time should be set to 16. However, the original Ralink driver uses
1957          * 16 for both and indeed using a value of 10 for CCK SIFS results in
1958          * connection problems with 11g + CTS protection. Hence, use the same
1959          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1960          */
1961         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1962         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1963         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1964         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1965         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1966         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1967         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1968
1969         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1970
1971         /*
1972          * ASIC will keep garbage value after boot, clear encryption keys.
1973          */
1974         for (i = 0; i < 4; i++)
1975                 rt2800_register_write(rt2x00dev,
1976                                          SHARED_KEY_MODE_ENTRY(i), 0);
1977
1978         for (i = 0; i < 256; i++) {
1979                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1980                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1981                                               wcid, sizeof(wcid));
1982
1983                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1984                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1985         }
1986
1987         /*
1988          * Clear all beacons
1989          */
1990         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1991         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1992         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1993         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1994         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1995         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1996         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1997         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
1998
1999         if (rt2x00_is_usb(rt2x00dev)) {
2000                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2001                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2002                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2003         }
2004
2005         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2006         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2007         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2008         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2009         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2010         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2011         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2012         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2013         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2014         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2015
2016         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2017         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2018         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2019         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2020         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2021         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2022         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2023         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2024         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2025         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2026
2027         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2028         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2029         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2030         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2031         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2032         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2033         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2034         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2035         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2036         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2037
2038         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2039         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2040         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2041         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2042         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2043         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2044
2045         /*
2046          * We must clear the error counters.
2047          * These registers are cleared on read,
2048          * so we may pass a useless variable to store the value.
2049          */
2050         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2051         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2052         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2053         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2054         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2055         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2056
2057         /*
2058          * Setup leadtime for pre tbtt interrupt to 6ms
2059          */
2060         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2061         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2062         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2063
2064         return 0;
2065 }
2066
2067 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2068 {
2069         unsigned int i;
2070         u32 reg;
2071
2072         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2073                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2074                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2075                         return 0;
2076
2077                 udelay(REGISTER_BUSY_DELAY);
2078         }
2079
2080         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2081         return -EACCES;
2082 }
2083
2084 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2085 {
2086         unsigned int i;
2087         u8 value;
2088
2089         /*
2090          * BBP was enabled after firmware was loaded,
2091          * but we need to reactivate it now.
2092          */
2093         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2094         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2095         msleep(1);
2096
2097         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2098                 rt2800_bbp_read(rt2x00dev, 0, &value);
2099                 if ((value != 0xff) && (value != 0x00))
2100                         return 0;
2101                 udelay(REGISTER_BUSY_DELAY);
2102         }
2103
2104         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2105         return -EACCES;
2106 }
2107
2108 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2109 {
2110         unsigned int i;
2111         u16 eeprom;
2112         u8 reg_id;
2113         u8 value;
2114
2115         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2116                      rt2800_wait_bbp_ready(rt2x00dev)))
2117                 return -EACCES;
2118
2119         if (rt2800_is_305x_soc(rt2x00dev))
2120                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2121
2122         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2123         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2124
2125         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2126                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2127                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2128         } else {
2129                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2130                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2131         }
2132
2133         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2134
2135         if (rt2x00_rt(rt2x00dev, RT3070) ||
2136             rt2x00_rt(rt2x00dev, RT3071) ||
2137             rt2x00_rt(rt2x00dev, RT3090) ||
2138             rt2x00_rt(rt2x00dev, RT3390)) {
2139                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2140                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2141                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2142         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2143                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2144                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2145         } else {
2146                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2147         }
2148
2149         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2150         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2151
2152         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2153                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2154         else
2155                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2156
2157         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2158         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2159         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2160
2161         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2162             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2163             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2164             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2165             rt2800_is_305x_soc(rt2x00dev))
2166                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2167         else
2168                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2169
2170         if (rt2800_is_305x_soc(rt2x00dev))
2171                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2172         else
2173                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2174         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2175
2176         if (rt2x00_rt(rt2x00dev, RT3071) ||
2177             rt2x00_rt(rt2x00dev, RT3090) ||
2178             rt2x00_rt(rt2x00dev, RT3390)) {
2179                 rt2800_bbp_read(rt2x00dev, 138, &value);
2180
2181                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2182                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2183                         value |= 0x20;
2184                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2185                         value &= ~0x02;
2186
2187                 rt2800_bbp_write(rt2x00dev, 138, value);
2188         }
2189
2190
2191         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2192                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2193
2194                 if (eeprom != 0xffff && eeprom != 0x0000) {
2195                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2196                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2197                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2198                 }
2199         }
2200
2201         return 0;
2202 }
2203
2204 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2205                                 bool bw40, u8 rfcsr24, u8 filter_target)
2206 {
2207         unsigned int i;
2208         u8 bbp;
2209         u8 rfcsr;
2210         u8 passband;
2211         u8 stopband;
2212         u8 overtuned = 0;
2213
2214         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2215
2216         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2217         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2218         rt2800_bbp_write(rt2x00dev, 4, bbp);
2219
2220         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2221         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2222         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2223
2224         /*
2225          * Set power & frequency of passband test tone
2226          */
2227         rt2800_bbp_write(rt2x00dev, 24, 0);
2228
2229         for (i = 0; i < 100; i++) {
2230                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2231                 msleep(1);
2232
2233                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2234                 if (passband)
2235                         break;
2236         }
2237
2238         /*
2239          * Set power & frequency of stopband test tone
2240          */
2241         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2242
2243         for (i = 0; i < 100; i++) {
2244                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2245                 msleep(1);
2246
2247                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2248
2249                 if ((passband - stopband) <= filter_target) {
2250                         rfcsr24++;
2251                         overtuned += ((passband - stopband) == filter_target);
2252                 } else
2253                         break;
2254
2255                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2256         }
2257
2258         rfcsr24 -= !!overtuned;
2259
2260         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2261         return rfcsr24;
2262 }
2263
2264 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2265 {
2266         u8 rfcsr;
2267         u8 bbp;
2268         u32 reg;
2269         u16 eeprom;
2270
2271         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2272             !rt2x00_rt(rt2x00dev, RT3071) &&
2273             !rt2x00_rt(rt2x00dev, RT3090) &&
2274             !rt2x00_rt(rt2x00dev, RT3390) &&
2275             !rt2800_is_305x_soc(rt2x00dev))
2276                 return 0;
2277
2278         /*
2279          * Init RF calibration.
2280          */
2281         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2282         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2283         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2284         msleep(1);
2285         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2286         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2287
2288         if (rt2x00_rt(rt2x00dev, RT3070) ||
2289             rt2x00_rt(rt2x00dev, RT3071) ||
2290             rt2x00_rt(rt2x00dev, RT3090)) {
2291                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2292                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2293                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2294                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2295                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2296                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2297                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2298                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2299                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2300                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2301                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2302                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2303                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2304                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2305                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2306                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2307                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2308                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2309                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2310         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2311                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2312                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2313                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2314                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2315                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2316                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2317                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2318                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2319                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2320                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2321                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2322                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2323                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2324                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2325                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2326                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2327                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2328                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2329                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2330                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2331                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2332                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2333                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2334                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2335                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2336                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2337                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2338                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2339                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2340                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2341                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2342                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2343         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2344                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2345                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2346                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2347                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2348                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2349                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2350                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2351                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2352                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2353                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2354                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2355                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2356                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2357                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2358                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2359                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2360                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2361                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2362                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2363                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2364                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2365                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2366                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2367                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2368                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2369                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2370                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2371                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2372                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2373                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2374                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2375                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2376                 return 0;
2377         }
2378
2379         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2380                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2381                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2382                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2383                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2384         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2385                    rt2x00_rt(rt2x00dev, RT3090)) {
2386                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2387                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2388                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2389
2390                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2391
2392                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2393                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2394                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2395                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2396                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2397                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2398                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2399                         else
2400                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2401                 }
2402                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2403         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2404                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2405                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2406                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2407         }
2408
2409         /*
2410          * Set RX Filter calibration for 20MHz and 40MHz
2411          */
2412         if (rt2x00_rt(rt2x00dev, RT3070)) {
2413                 rt2x00dev->calibration[0] =
2414                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2415                 rt2x00dev->calibration[1] =
2416                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2417         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2418                    rt2x00_rt(rt2x00dev, RT3090) ||
2419                    rt2x00_rt(rt2x00dev, RT3390)) {
2420                 rt2x00dev->calibration[0] =
2421                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2422                 rt2x00dev->calibration[1] =
2423                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2424         }
2425
2426         /*
2427          * Set back to initial state
2428          */
2429         rt2800_bbp_write(rt2x00dev, 24, 0);
2430
2431         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2432         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2433         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2434
2435         /*
2436          * set BBP back to BW20
2437          */
2438         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2439         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2440         rt2800_bbp_write(rt2x00dev, 4, bbp);
2441
2442         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2443             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2444             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2445             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2446                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2447
2448         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2449         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2450         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2451
2452         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2453         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2454         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2455             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2456             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2457                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2458                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2459         }
2460         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2461         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2462                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2463                                   rt2x00_get_field16(eeprom,
2464                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2465         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2466
2467         if (rt2x00_rt(rt2x00dev, RT3090)) {
2468                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2469
2470                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2471                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2472                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2473                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2474                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2475
2476                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2477         }
2478
2479         if (rt2x00_rt(rt2x00dev, RT3071) ||
2480             rt2x00_rt(rt2x00dev, RT3090) ||
2481             rt2x00_rt(rt2x00dev, RT3390)) {
2482                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2483                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2484                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2485                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2486                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2487                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2488                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2489
2490                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2491                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2492                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2493
2494                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2495                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2496                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2497
2498                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2499                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2500                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2501         }
2502
2503         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2504                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2505                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2506                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2507                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2508                 else
2509                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2510                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2511                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2512                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2513                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2514         }
2515
2516         return 0;
2517 }
2518
2519 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2520 {
2521         u32 reg;
2522         u16 word;
2523
2524         /*
2525          * Initialize all registers.
2526          */
2527         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2528                      rt2800_init_registers(rt2x00dev) ||
2529                      rt2800_init_bbp(rt2x00dev) ||
2530                      rt2800_init_rfcsr(rt2x00dev)))
2531                 return -EIO;
2532
2533         /*
2534          * Send signal to firmware during boot time.
2535          */
2536         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2537
2538         if (rt2x00_is_usb(rt2x00dev) &&
2539             (rt2x00_rt(rt2x00dev, RT3070) ||
2540              rt2x00_rt(rt2x00dev, RT3071) ||
2541              rt2x00_rt(rt2x00dev, RT3572))) {
2542                 udelay(200);
2543                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2544                 udelay(10);
2545         }
2546
2547         /*
2548          * Enable RX.
2549          */
2550         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2551         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2552         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2553         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2554
2555         udelay(50);
2556
2557         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2558         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2559         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2560         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2561         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2562         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2563
2564         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2565         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2566         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2567         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2568
2569         /*
2570          * Initialize LED control
2571          */
2572         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2573         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2574                            word & 0xff, (word >> 8) & 0xff);
2575
2576         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2577         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2578                            word & 0xff, (word >> 8) & 0xff);
2579
2580         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2581         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2582                            word & 0xff, (word >> 8) & 0xff);
2583
2584         return 0;
2585 }
2586 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2587
2588 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2589 {
2590         u32 reg;
2591
2592         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2593         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2594         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2595         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2596         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2597         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2598         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2599
2600         /* Wait for DMA, ignore error */
2601         rt2800_wait_wpdma_ready(rt2x00dev);
2602
2603         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2604         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2605         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2606         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2607
2608         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2609         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2610 }
2611 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2612
2613 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2614 {
2615         u32 reg;
2616
2617         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2618
2619         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2620 }
2621 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2622
2623 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2624 {
2625         u32 reg;
2626
2627         mutex_lock(&rt2x00dev->csr_mutex);
2628
2629         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2630         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2631         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2632         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2633         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2634
2635         /* Wait until the EEPROM has been loaded */
2636         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2637
2638         /* Apparently the data is read from end to start */
2639         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2640                                         (u32 *)&rt2x00dev->eeprom[i]);
2641         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2642                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2643         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2644                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2645         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2646                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2647
2648         mutex_unlock(&rt2x00dev->csr_mutex);
2649 }
2650
2651 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2652 {
2653         unsigned int i;
2654
2655         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2656                 rt2800_efuse_read(rt2x00dev, i);
2657 }
2658 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2659
2660 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2661 {
2662         u16 word;
2663         u8 *mac;
2664         u8 default_lna_gain;
2665
2666         /*
2667          * Start validation of the data that has been read.
2668          */
2669         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2670         if (!is_valid_ether_addr(mac)) {
2671                 random_ether_addr(mac);
2672                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2673         }
2674
2675         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2676         if (word == 0xffff) {
2677                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2678                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2679                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2680                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2681                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2682         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2683                    rt2x00_rt(rt2x00dev, RT2872)) {
2684                 /*
2685                  * There is a max of 2 RX streams for RT28x0 series
2686                  */
2687                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2688                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2689                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2690         }
2691
2692         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2693         if (word == 0xffff) {
2694                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2695                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2696                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2697                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2698                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2699                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2700                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2701                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2702                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2703                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2704                 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2705                 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2706                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2707                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2708         }
2709
2710         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2711         if ((word & 0x00ff) == 0x00ff) {
2712                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2713                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2714                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2715         }
2716         if ((word & 0xff00) == 0xff00) {
2717                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2718                                    LED_MODE_TXRX_ACTIVITY);
2719                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2720                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2721                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2722                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2723                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2724                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2725         }
2726
2727         /*
2728          * During the LNA validation we are going to use
2729          * lna0 as correct value. Note that EEPROM_LNA
2730          * is never validated.
2731          */
2732         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2733         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2734
2735         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2736         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2737                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2738         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2739                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2740         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2741
2742         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2743         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2744                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2745         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2746             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2747                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2748                                    default_lna_gain);
2749         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2750
2751         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2752         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2753                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2754         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2755                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2756         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2757
2758         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2759         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2760                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2761         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2762             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2763                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2764                                    default_lna_gain);
2765         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2766
2767         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2768         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2769                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2770         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2771                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2772         rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2773
2774         return 0;
2775 }
2776 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2777
2778 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2779 {
2780         u32 reg;
2781         u16 value;
2782         u16 eeprom;
2783
2784         /*
2785          * Read EEPROM word for configuration.
2786          */
2787         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2788
2789         /*
2790          * Identify RF chipset.
2791          */
2792         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2793         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2794
2795         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2796                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2797
2798         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2799             !rt2x00_rt(rt2x00dev, RT2872) &&
2800             !rt2x00_rt(rt2x00dev, RT2883) &&
2801             !rt2x00_rt(rt2x00dev, RT3070) &&
2802             !rt2x00_rt(rt2x00dev, RT3071) &&
2803             !rt2x00_rt(rt2x00dev, RT3090) &&
2804             !rt2x00_rt(rt2x00dev, RT3390) &&
2805             !rt2x00_rt(rt2x00dev, RT3572)) {
2806                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2807                 return -ENODEV;
2808         }
2809
2810         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2811             !rt2x00_rf(rt2x00dev, RF2850) &&
2812             !rt2x00_rf(rt2x00dev, RF2720) &&
2813             !rt2x00_rf(rt2x00dev, RF2750) &&
2814             !rt2x00_rf(rt2x00dev, RF3020) &&
2815             !rt2x00_rf(rt2x00dev, RF2020) &&
2816             !rt2x00_rf(rt2x00dev, RF3021) &&
2817             !rt2x00_rf(rt2x00dev, RF3022) &&
2818             !rt2x00_rf(rt2x00dev, RF3052)) {
2819                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2820                 return -ENODEV;
2821         }
2822
2823         /*
2824          * Identify default antenna configuration.
2825          */
2826         rt2x00dev->default_ant.tx =
2827             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2828         rt2x00dev->default_ant.rx =
2829             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2830
2831         /*
2832          * Read frequency offset and RF programming sequence.
2833          */
2834         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2835         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2836
2837         /*
2838          * Read external LNA informations.
2839          */
2840         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2841
2842         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2843                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2844         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2845                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2846
2847         /*
2848          * Detect if this device has an hardware controlled radio.
2849          */
2850         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2851                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2852
2853         /*
2854          * Store led settings, for correct led behaviour.
2855          */
2856 #ifdef CONFIG_RT2X00_LIB_LEDS
2857         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2858         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2859         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2860
2861         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2862 #endif /* CONFIG_RT2X00_LIB_LEDS */
2863
2864         return 0;
2865 }
2866 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2867
2868 /*
2869  * RF value list for rt28xx
2870  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2871  */
2872 static const struct rf_channel rf_vals[] = {
2873         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2874         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2875         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2876         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2877         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2878         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2879         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2880         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2881         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2882         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2883         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2884         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2885         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2886         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2887
2888         /* 802.11 UNI / HyperLan 2 */
2889         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2890         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2891         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2892         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2893         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2894         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2895         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2896         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2897         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2898         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2899         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2900         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2901
2902         /* 802.11 HyperLan 2 */
2903         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2904         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2905         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2906         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2907         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2908         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2909         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2910         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2911         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2912         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2913         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2914         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2915         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2916         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2917         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2918         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2919
2920         /* 802.11 UNII */
2921         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2922         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2923         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2924         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2925         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2926         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2927         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2928         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2929         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2930         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2931         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2932
2933         /* 802.11 Japan */
2934         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2935         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2936         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2937         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2938         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2939         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2940         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2941 };
2942
2943 /*
2944  * RF value list for rt3xxx
2945  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2946  */
2947 static const struct rf_channel rf_vals_3x[] = {
2948         {1,  241, 2, 2 },
2949         {2,  241, 2, 7 },
2950         {3,  242, 2, 2 },
2951         {4,  242, 2, 7 },
2952         {5,  243, 2, 2 },
2953         {6,  243, 2, 7 },
2954         {7,  244, 2, 2 },
2955         {8,  244, 2, 7 },
2956         {9,  245, 2, 2 },
2957         {10, 245, 2, 7 },
2958         {11, 246, 2, 2 },
2959         {12, 246, 2, 7 },
2960         {13, 247, 2, 2 },
2961         {14, 248, 2, 4 },
2962
2963         /* 802.11 UNI / HyperLan 2 */
2964         {36, 0x56, 0, 4},
2965         {38, 0x56, 0, 6},
2966         {40, 0x56, 0, 8},
2967         {44, 0x57, 0, 0},
2968         {46, 0x57, 0, 2},
2969         {48, 0x57, 0, 4},
2970         {52, 0x57, 0, 8},
2971         {54, 0x57, 0, 10},
2972         {56, 0x58, 0, 0},
2973         {60, 0x58, 0, 4},
2974         {62, 0x58, 0, 6},
2975         {64, 0x58, 0, 8},
2976
2977         /* 802.11 HyperLan 2 */
2978         {100, 0x5b, 0, 8},
2979         {102, 0x5b, 0, 10},
2980         {104, 0x5c, 0, 0},
2981         {108, 0x5c, 0, 4},
2982         {110, 0x5c, 0, 6},
2983         {112, 0x5c, 0, 8},
2984         {116, 0x5d, 0, 0},
2985         {118, 0x5d, 0, 2},
2986         {120, 0x5d, 0, 4},
2987         {124, 0x5d, 0, 8},
2988         {126, 0x5d, 0, 10},
2989         {128, 0x5e, 0, 0},
2990         {132, 0x5e, 0, 4},
2991         {134, 0x5e, 0, 6},
2992         {136, 0x5e, 0, 8},
2993         {140, 0x5f, 0, 0},
2994
2995         /* 802.11 UNII */
2996         {149, 0x5f, 0, 9},
2997         {151, 0x5f, 0, 11},
2998         {153, 0x60, 0, 1},
2999         {157, 0x60, 0, 5},
3000         {159, 0x60, 0, 7},
3001         {161, 0x60, 0, 9},
3002         {165, 0x61, 0, 1},
3003         {167, 0x61, 0, 3},
3004         {169, 0x61, 0, 5},
3005         {171, 0x61, 0, 7},
3006         {173, 0x61, 0, 9},
3007 };
3008
3009 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3010 {
3011         struct hw_mode_spec *spec = &rt2x00dev->spec;
3012         struct channel_info *info;
3013         char *default_power1;
3014         char *default_power2;
3015         unsigned int i;
3016         unsigned short max_power;
3017         u16 eeprom;
3018
3019         /*
3020          * Disable powersaving as default on PCI devices.
3021          */
3022         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3023                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3024
3025         /*
3026          * Initialize all hw fields.
3027          */
3028         rt2x00dev->hw->flags =
3029             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3030             IEEE80211_HW_SIGNAL_DBM |
3031             IEEE80211_HW_SUPPORTS_PS |
3032             IEEE80211_HW_PS_NULLFUNC_STACK |
3033             IEEE80211_HW_AMPDU_AGGREGATION;
3034
3035         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3036         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3037                                 rt2x00_eeprom_addr(rt2x00dev,
3038                                                    EEPROM_MAC_ADDR_0));
3039
3040         /*
3041          * As rt2800 has a global fallback table we cannot specify
3042          * more then one tx rate per frame but since the hw will
3043          * try several rates (based on the fallback table) we should
3044          * still initialize max_rates to the maximum number of rates
3045          * we are going to try. Otherwise mac80211 will truncate our
3046          * reported tx rates and the rc algortihm will end up with
3047          * incorrect data.
3048          */
3049         rt2x00dev->hw->max_rates = 7;
3050         rt2x00dev->hw->max_rate_tries = 1;
3051
3052         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3053
3054         /*
3055          * Initialize hw_mode information.
3056          */
3057         spec->supported_bands = SUPPORT_BAND_2GHZ;
3058         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3059
3060         if (rt2x00_rf(rt2x00dev, RF2820) ||
3061             rt2x00_rf(rt2x00dev, RF2720)) {
3062                 spec->num_channels = 14;
3063                 spec->channels = rf_vals;
3064         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3065                    rt2x00_rf(rt2x00dev, RF2750)) {
3066                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3067                 spec->num_channels = ARRAY_SIZE(rf_vals);
3068                 spec->channels = rf_vals;
3069         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3070                    rt2x00_rf(rt2x00dev, RF2020) ||
3071                    rt2x00_rf(rt2x00dev, RF3021) ||
3072                    rt2x00_rf(rt2x00dev, RF3022)) {
3073                 spec->num_channels = 14;
3074                 spec->channels = rf_vals_3x;
3075         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3076                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3077                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3078                 spec->channels = rf_vals_3x;
3079         }
3080
3081         /*
3082          * Initialize HT information.
3083          */
3084         if (!rt2x00_rf(rt2x00dev, RF2020))
3085                 spec->ht.ht_supported = true;
3086         else
3087                 spec->ht.ht_supported = false;
3088
3089         spec->ht.cap =
3090             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3091             IEEE80211_HT_CAP_GRN_FLD |
3092             IEEE80211_HT_CAP_SGI_20 |
3093             IEEE80211_HT_CAP_SGI_40;
3094
3095         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3096                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3097
3098         spec->ht.cap |=
3099             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3100                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3101
3102         spec->ht.ampdu_factor = 3;
3103         spec->ht.ampdu_density = 4;
3104         spec->ht.mcs.tx_params =
3105             IEEE80211_HT_MCS_TX_DEFINED |
3106             IEEE80211_HT_MCS_TX_RX_DIFF |
3107             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3108                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3109
3110         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3111         case 3:
3112                 spec->ht.mcs.rx_mask[2] = 0xff;
3113         case 2:
3114                 spec->ht.mcs.rx_mask[1] = 0xff;
3115         case 1:
3116                 spec->ht.mcs.rx_mask[0] = 0xff;
3117                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3118                 break;
3119         }
3120
3121         /*
3122          * Create channel information array
3123          */
3124         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
3125         if (!info)
3126                 return -ENOMEM;
3127
3128         spec->channels_info = info;
3129
3130         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3131         max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3132         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3133         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3134
3135         for (i = 0; i < 14; i++) {
3136                 info[i].max_power = max_power;
3137                 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3138                 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3139         }
3140
3141         if (spec->num_channels > 14) {
3142                 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3143                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3144                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3145
3146                 for (i = 14; i < spec->num_channels; i++) {
3147                         info[i].max_power = max_power;
3148                         info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3149                         info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3150                 }
3151         }
3152
3153         return 0;
3154 }
3155 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3156
3157 /*
3158  * IEEE80211 stack callback functions.
3159  */
3160 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3161                          u16 *iv16)
3162 {
3163         struct rt2x00_dev *rt2x00dev = hw->priv;
3164         struct mac_iveiv_entry iveiv_entry;
3165         u32 offset;
3166
3167         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3168         rt2800_register_multiread(rt2x00dev, offset,
3169                                       &iveiv_entry, sizeof(iveiv_entry));
3170
3171         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3172         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3173 }
3174 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3175
3176 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3177 {
3178         struct rt2x00_dev *rt2x00dev = hw->priv;
3179         u32 reg;
3180         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3181
3182         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3183         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3184         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3185
3186         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3187         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3188         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3189
3190         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3191         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3192         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3193
3194         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3195         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3196         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3197
3198         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3199         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3200         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3201
3202         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3203         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3204         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3205
3206         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3207         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3208         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3209
3210         return 0;
3211 }
3212 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3213
3214 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3215                    const struct ieee80211_tx_queue_params *params)
3216 {
3217         struct rt2x00_dev *rt2x00dev = hw->priv;
3218         struct data_queue *queue;
3219         struct rt2x00_field32 field;
3220         int retval;
3221         u32 reg;
3222         u32 offset;
3223
3224         /*
3225          * First pass the configuration through rt2x00lib, that will
3226          * update the queue settings and validate the input. After that
3227          * we are free to update the registers based on the value
3228          * in the queue parameter.
3229          */
3230         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3231         if (retval)
3232                 return retval;
3233
3234         /*
3235          * We only need to perform additional register initialization
3236          * for WMM queues/
3237          */
3238         if (queue_idx >= 4)
3239                 return 0;
3240
3241         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3242
3243         /* Update WMM TXOP register */
3244         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3245         field.bit_offset = (queue_idx & 1) * 16;
3246         field.bit_mask = 0xffff << field.bit_offset;
3247
3248         rt2800_register_read(rt2x00dev, offset, &reg);
3249         rt2x00_set_field32(&reg, field, queue->txop);
3250         rt2800_register_write(rt2x00dev, offset, reg);
3251
3252         /* Update WMM registers */
3253         field.bit_offset = queue_idx * 4;
3254         field.bit_mask = 0xf << field.bit_offset;
3255
3256         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3257         rt2x00_set_field32(&reg, field, queue->aifs);
3258         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3259
3260         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3261         rt2x00_set_field32(&reg, field, queue->cw_min);
3262         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3263
3264         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3265         rt2x00_set_field32(&reg, field, queue->cw_max);
3266         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3267
3268         /* Update EDCA registers */
3269         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3270
3271         rt2800_register_read(rt2x00dev, offset, &reg);
3272         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3273         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3274         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3275         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3276         rt2800_register_write(rt2x00dev, offset, reg);
3277
3278         return 0;
3279 }
3280 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3281
3282 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3283 {
3284         struct rt2x00_dev *rt2x00dev = hw->priv;
3285         u64 tsf;
3286         u32 reg;
3287
3288         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3289         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3290         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3291         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3292
3293         return tsf;
3294 }
3295 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3296
3297 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3298                         enum ieee80211_ampdu_mlme_action action,
3299                         struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3300 {
3301         int ret = 0;
3302
3303         switch (action) {
3304         case IEEE80211_AMPDU_RX_START:
3305         case IEEE80211_AMPDU_RX_STOP:
3306                 /* we don't support RX aggregation yet */
3307                 ret = -ENOTSUPP;
3308                 break;
3309         case IEEE80211_AMPDU_TX_START:
3310                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3311                 break;
3312         case IEEE80211_AMPDU_TX_STOP:
3313                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3314                 break;
3315         case IEEE80211_AMPDU_TX_OPERATIONAL:
3316                 break;
3317         default:
3318                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3319         }
3320
3321         return ret;
3322 }
3323 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3324
3325 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3326 MODULE_VERSION(DRV_VERSION);
3327 MODULE_DESCRIPTION("Ralink RT2800 library");
3328 MODULE_LICENSE("GPL");