drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 265                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 266                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 267                         return 0;
 268
 269                 msleep(1);
 270         }
 271
 272         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 273         return -EACCES;
 274 }
 275 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 276
 277 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 278 {
 279         u16 fw_crc;
 280         u16 crc;
 281
 282         /*
 283          * The last 2 bytes in the firmware array are the crc checksum itself,
 284          * this means that we should never pass those 2 bytes to the crc
 285          * algorithm.
 286          */
 287         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 288
 289         /*
 290          * Use the crc ccitt algorithm.
 291          * This will return the same value as the legacy driver which
 292          * used bit ordering reversion on the both the firmware bytes
 293          * before input input as well as on the final output.
 294          * Obviously using crc ccitt directly is much more efficient.
 295          */
 296         crc = crc_ccitt(~0, data, len - 2);
 297
 298         /*
 299          * There is a small difference between the crc-itu-t + bitrev and
 300          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 301          * will be swapped, use swab16 to convert the crc to the correct
 302          * value.
 303          */
 304         crc = swab16(crc);
 305
 306         return fw_crc == crc;
 307 }
 308
 309 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 310                           const u8 *data, const size_t len)
 311 {
 312         size_t offset = 0;
 313         size_t fw_len;
 314         bool multiple;
 315
 316         /*
 317          * PCI(e) & SOC devices require firmware with a length
 318          * of 8kb. USB devices require firmware files with a length
 319          * of 4kb. Certain USB chipsets however require different firmware,
 320          * which Ralink only provides attached to the original firmware
 321          * file. Thus for USB devices, firmware files have a length
 322          * which is a multiple of 4kb.
 323          */
 324         if (rt2x00_is_usb(rt2x00dev)) {
 325                 fw_len = 4096;
 326                 multiple = true;
 327         } else {
 328                 fw_len = 8192;
 329                 multiple = true;
 330         }
 331
 332         /*
 333          * Validate the firmware length
 334          */
 335         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 336                 return FW_BAD_LENGTH;
 337
 338         /*
 339          * Check if the chipset requires one of the upper parts
 340          * of the firmware.
 341          */
 342         if (rt2x00_is_usb(rt2x00dev) &&
 343             !rt2x00_rt(rt2x00dev, RT2860) &&
 344             !rt2x00_rt(rt2x00dev, RT2872) &&
 345             !rt2x00_rt(rt2x00dev, RT3070) &&
 346             ((len / fw_len) == 1))
 347                 return FW_BAD_VERSION;
 348
 349         /*
 350          * 8kb firmware files must be checked as if it were
 351          * 2 separate firmware files.
 352          */
 353         while (offset < len) {
 354                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 355                         return FW_BAD_CRC;
 356
 357                 offset += fw_len;
 358         }
 359
 360         return FW_OK;
 361 }
 362 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 363
 364 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 365                          const u8 *data, const size_t len)
 366 {
 367         unsigned int i;
 368         u32 reg;
 369
 370         /*
 371          * Wait for stable hardware.
 372          */
 373         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 374                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 375                 if (reg && reg != ~0)
 376                         break;
 377                 msleep(1);
 378         }
 379
 380         if (i == REGISTER_BUSY_COUNT) {
 381                 ERROR(rt2x00dev, "Unstable hardware.\n");
 382                 return -EBUSY;
 383         }
 384
 385         if (rt2x00_is_pci(rt2x00dev))
 386                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 387
 388         /*
 389          * Disable DMA, will be reenabled later when enabling
 390          * the radio.
 391          */
 392         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 393         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 394         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 395         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 396         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 397         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 398         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 399
 400         /*
 401          * Write firmware to the device.
 402          */
 403         rt2800_drv_write_firmware(rt2x00dev, data, len);
 404
 405         /*
 406          * Wait for device to stabilize.
 407          */
 408         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 409                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 410                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 411                         break;
 412                 msleep(1);
 413         }
 414
 415         if (i == REGISTER_BUSY_COUNT) {
 416                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 417                 return -EBUSY;
 418         }
 419
 420         /*
 421          * Initialize firmware.
 422          */
 423         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 424         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 425         msleep(1);
 426
 427         return 0;
 428 }
 429 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 430
 431 void rt2800_write_tx_data(struct queue_entry *entry,
 432                           struct txentry_desc *txdesc)
 433 {
 434         __le32 *txwi = rt2800_drv_get_txwi(entry);
 435         u32 word;
 436
 437         /*
 438          * Initialize TX Info descriptor
 439          */
 440         rt2x00_desc_read(txwi, 0, &word);
 441         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 442                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 443         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 444                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 445         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 446         rt2x00_set_field32(&word, TXWI_W0_TS,
 447                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 448         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 449                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 450         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 451         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
 452         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 453         rt2x00_set_field32(&word, TXWI_W0_BW,
 454                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 455         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 456                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 457         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 458         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 459         rt2x00_desc_write(txwi, 0, word);
 460
 461         rt2x00_desc_read(txwi, 1, &word);
 462         rt2x00_set_field32(&word, TXWI_W1_ACK,
 463                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 464         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 465                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 466         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 467         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 468                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 469                            txdesc->key_idx : 0xff);
 470         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 471                            txdesc->length);
 472         rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
 473         rt2x00_desc_write(txwi, 1, word);
 474
 475         /*
 476          * Always write 0 to IV/EIV fields, hardware will insert the IV
 477          * from the IVEIV register when TXD_W3_WIV is set to 0.
 478          * When TXD_W3_WIV is set to 1 it will use the IV data
 479          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 480          * crypto entry in the registers should be used to encrypt the frame.
 481          */
 482         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 483         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 486
 487 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
 488 {
 489         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 490         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 491         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 492         u16 eeprom;
 493         u8 offset0;
 494         u8 offset1;
 495         u8 offset2;
 496
 497         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 498                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 499                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 500                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 501                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 502                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 503         } else {
 504                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 505                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 506                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 507                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 508                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 509         }
 510
 511         /*
 512          * Convert the value from the descriptor into the RSSI value
 513          * If the value in the descriptor is 0, it is considered invalid
 514          * and the default (extremely low) rssi value is assumed
 515          */
 516         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 517         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 518         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 519
 520         /*
 521          * mac80211 only accepts a single RSSI value. Calculating the
 522          * average doesn't deliver a fair answer either since -60:-60 would
 523          * be considered equally good as -50:-70 while the second is the one
 524          * which gives less energy...
 525          */
 526         rssi0 = max(rssi0, rssi1);
 527         return max(rssi0, rssi2);
 528 }
 529
 530 void rt2800_process_rxwi(struct queue_entry *entry,
 531                          struct rxdone_entry_desc *rxdesc)
 532 {
 533         __le32 *rxwi = (__le32 *) entry->skb->data;
 534         u32 word;
 535
 536         rt2x00_desc_read(rxwi, 0, &word);
 537
 538         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 539         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 540
 541         rt2x00_desc_read(rxwi, 1, &word);
 542
 543         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 544                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 545
 546         if (rt2x00_get_field32(word, RXWI_W1_BW))
 547                 rxdesc->flags |= RX_FLAG_40MHZ;
 548
 549         /*
 550          * Detect RX rate, always use MCS as signal type.
 551          */
 552         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 553         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 554         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 555
 556         /*
 557          * Mask of 0x8 bit to remove the short preamble flag.
 558          */
 559         if (rxdesc->rate_mode == RATE_MODE_CCK)
 560                 rxdesc->signal &= ~0x8;
 561
 562         rt2x00_desc_read(rxwi, 2, &word);
 563
 564         /*
 565          * Convert descriptor AGC value to RSSI value.
 566          */
 567         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 568
 569         /*
 570          * Remove RXWI descriptor from start of buffer.
 571          */
 572         skb_pull(entry->skb, RXWI_DESC_SIZE);
 573 }
 574 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 575
 576 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 577 {
 578         struct data_queue *queue;
 579         struct queue_entry *entry;
 580         __le32 *txwi;
 581         struct txdone_entry_desc txdesc;
 582         u32 word;
 583         u32 reg;
 584         int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
 585         u16 mcs, real_mcs;
 586         int i;
 587
 588         /*
 589          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 590          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 591          * flag is not set anymore.
 592          *
 593          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 594          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 595          * tx ring size for now.
 596          */
 597         for (i = 0; i < TX_ENTRIES; i++) {
 598                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 599                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 600                         break;
 601
 602                 wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 603                 ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 604                 pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 605
 606                 /*
 607                  * Skip this entry when it contains an invalid
 608                  * queue identication number.
 609                  */
 610                 if (pid <= 0 || pid > QID_RX)
 611                         continue;
 612
 613                 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
 614                 if (unlikely(!queue))
 615                         continue;
 616
 617                 /*
 618                  * Inside each queue, we process each entry in a chronological
 619                  * order. We first check that the queue is not empty.
 620                  */
 621                 entry = NULL;
 622                 while (!rt2x00queue_empty(queue)) {
 623                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 624                         if (!test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
 625                                 break;
 626
 627                         rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 628                 }
 629
 630                 if (!entry || rt2x00queue_empty(queue))
 631                         break;
 632
 633                 /*
 634                  * Check if we got a match by looking at WCID/ACK/PID
 635                  * fields
 636                  */
 637                 txwi = rt2800_drv_get_txwi(entry);
 638
 639                 rt2x00_desc_read(txwi, 1, &word);
 640                 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 641                 tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 642                 tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 643
 644                 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
 645                         WARNING(rt2x00dev, "invalid TX_STA_FIFO content");
 646
 647                 /*
 648                  * Obtain the status about this packet.
 649                  */
 650                 txdesc.flags = 0;
 651                 rt2x00_desc_read(txwi, 0, &word);
 652                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 653                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 654
 655                 /*
 656                  * Ralink has a retry mechanism using a global fallback
 657                  * table. We setup this fallback table to try the immediate
 658                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 659                  * always contains the MCS used for the last transmission, be
 660                  * it successful or not.
 661                  */
 662                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 663                         /*
 664                          * Transmission succeeded. The number of retries is
 665                          * mcs - real_mcs
 666                          */
 667                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 668                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 669                 } else {
 670                         /*
 671                          * Transmission failed. The number of retries is
 672                          * always 7 in this case (for a total number of 8
 673                          * frames sent).
 674                          */
 675                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 676                         txdesc.retry = rt2x00dev->long_retry;
 677                 }
 678
 679                 /*
 680                  * the frame was retried at least once
 681                  * -> hw used fallback rates
 682                  */
 683                 if (txdesc.retry)
 684                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 685
 686                 rt2x00lib_txdone(entry, &txdesc);
 687         }
 688 }
 689 EXPORT_SYMBOL_GPL(rt2800_txdone);
 690
 691 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 692 {
 693         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 694         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 695         unsigned int beacon_base;
 696         u32 reg;
 697
 698         /*
 699          * Disable beaconing while we are reloading the beacon data,
 700          * otherwise we might be sending out invalid data.
 701          */
 702         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 703         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 704         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 705
 706         /*
 707          * Add space for the TXWI in front of the skb.
 708          */
 709         skb_push(entry->skb, TXWI_DESC_SIZE);
 710         memset(entry->skb, 0, TXWI_DESC_SIZE);
 711
 712         /*
 713          * Register descriptor details in skb frame descriptor.
 714          */
 715         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 716         skbdesc->desc = entry->skb->data;
 717         skbdesc->desc_len = TXWI_DESC_SIZE;
 718
 719         /*
 720          * Add the TXWI for the beacon to the skb.
 721          */
 722         rt2800_write_tx_data(entry, txdesc);
 723
 724         /*
 725          * Dump beacon to userspace through debugfs.
 726          */
 727         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 728
 729         /*
 730          * Write entire beacon with TXWI to register.
 731          */
 732         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 733         rt2800_register_multiwrite(rt2x00dev, beacon_base,
 734                                    entry->skb->data, entry->skb->len);
 735
 736         /*
 737          * Enable beaconing again.
 738          */
 739         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 740         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 741         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 742         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 743
 744         /*
 745          * Clean up beacon skb.
 746          */
 747         dev_kfree_skb_any(entry->skb);
 748         entry->skb = NULL;
 749 }
 750 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 751
 752 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
 753                                        unsigned int beacon_base)
 754 {
 755         int i;
 756
 757         /*
 758          * For the Beacon base registers we only need to clear
 759          * the whole TXWI which (when set to 0) will invalidate
 760          * the entire beacon.
 761          */
 762         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 763                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 764 }
 765
 766 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 767 const struct rt2x00debug rt2800_rt2x00debug = {
 768         .owner  = THIS_MODULE,
 769         .csr    = {
 770                 .read           = rt2800_register_read,
 771                 .write          = rt2800_register_write,
 772                 .flags          = RT2X00DEBUGFS_OFFSET,
 773                 .word_base      = CSR_REG_BASE,
 774                 .word_size      = sizeof(u32),
 775                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 776         },
 777         .eeprom = {
 778                 .read           = rt2x00_eeprom_read,
 779                 .write          = rt2x00_eeprom_write,
 780                 .word_base      = EEPROM_BASE,
 781                 .word_size      = sizeof(u16),
 782                 .word_count     = EEPROM_SIZE / sizeof(u16),
 783         },
 784         .bbp    = {
 785                 .read           = rt2800_bbp_read,
 786                 .write          = rt2800_bbp_write,
 787                 .word_base      = BBP_BASE,
 788                 .word_size      = sizeof(u8),
 789                 .word_count     = BBP_SIZE / sizeof(u8),
 790         },
 791         .rf     = {
 792                 .read           = rt2x00_rf_read,
 793                 .write          = rt2800_rf_write,
 794                 .word_base      = RF_BASE,
 795                 .word_size      = sizeof(u32),
 796                 .word_count     = RF_SIZE / sizeof(u32),
 797         },
 798 };
 799 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 800 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 801
 802 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 803 {
 804         u32 reg;
 805
 806         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 807         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 808 }
 809 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 810
 811 #ifdef CONFIG_RT2X00_LIB_LEDS
 812 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 813                                   enum led_brightness brightness)
 814 {
 815         struct rt2x00_led *led =
 816             container_of(led_cdev, struct rt2x00_led, led_dev);
 817         unsigned int enabled = brightness != LED_OFF;
 818         unsigned int bg_mode =
 819             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 820         unsigned int polarity =
 821                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 822                                    EEPROM_FREQ_LED_POLARITY);
 823         unsigned int ledmode =
 824                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 825                                    EEPROM_FREQ_LED_MODE);
 826
 827         if (led->type == LED_TYPE_RADIO) {
 828                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 829                                       enabled ? 0x20 : 0);
 830         } else if (led->type == LED_TYPE_ASSOC) {
 831                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 832                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 833         } else if (led->type == LED_TYPE_QUALITY) {
 834                 /*
 835                  * The brightness is divided into 6 levels (0 - 5),
 836                  * The specs tell us the following levels:
 837                  *      0, 1 ,3, 7, 15, 31
 838                  * to determine the level in a simple way we can simply
 839                  * work with bitshifting:
 840                  *      (1 << level) - 1
 841                  */
 842                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 843                                       (1 << brightness / (LED_FULL / 6)) - 1,
 844                                       polarity);
 845         }
 846 }
 847
 848 static int rt2800_blink_set(struct led_classdev *led_cdev,
 849                             unsigned long *delay_on, unsigned long *delay_off)
 850 {
 851         struct rt2x00_led *led =
 852             container_of(led_cdev, struct rt2x00_led, led_dev);
 853         u32 reg;
 854
 855         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 856         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 857         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 858         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 859
 860         return 0;
 861 }
 862
 863 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 864                      struct rt2x00_led *led, enum led_type type)
 865 {
 866         led->rt2x00dev = rt2x00dev;
 867         led->type = type;
 868         led->led_dev.brightness_set = rt2800_brightness_set;
 869         led->led_dev.blink_set = rt2800_blink_set;
 870         led->flags = LED_INITIALIZED;
 871 }
 872 #endif /* CONFIG_RT2X00_LIB_LEDS */
 873
 874 /*
 875  * Configuration handlers.
 876  */
 877 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 878                                     struct rt2x00lib_crypto *crypto,
 879                                     struct ieee80211_key_conf *key)
 880 {
 881         struct mac_wcid_entry wcid_entry;
 882         struct mac_iveiv_entry iveiv_entry;
 883         u32 offset;
 884         u32 reg;
 885
 886         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 887
 888         if (crypto->cmd == SET_KEY) {
 889                 rt2800_register_read(rt2x00dev, offset, &reg);
 890                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 891                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 892                 /*
 893                  * Both the cipher as the BSS Idx numbers are split in a main
 894                  * value of 3 bits, and a extended field for adding one additional
 895                  * bit to the value.
 896                  */
 897                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 898                                    (crypto->cipher & 0x7));
 899                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 900                                    (crypto->cipher & 0x8) >> 3);
 901                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 902                                    (crypto->bssidx & 0x7));
 903                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 904                                    (crypto->bssidx & 0x8) >> 3);
 905                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 906                 rt2800_register_write(rt2x00dev, offset, reg);
 907         } else {
 908                 rt2800_register_write(rt2x00dev, offset, 0);
 909         }
 910
 911         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 912
 913         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 914         if ((crypto->cipher == CIPHER_TKIP) ||
 915             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 916             (crypto->cipher == CIPHER_AES))
 917                 iveiv_entry.iv[3] |= 0x20;
 918         iveiv_entry.iv[3] |= key->keyidx << 6;
 919         rt2800_register_multiwrite(rt2x00dev, offset,
 920                                       &iveiv_entry, sizeof(iveiv_entry));
 921
 922         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 923
 924         memset(&wcid_entry, 0, sizeof(wcid_entry));
 925         if (crypto->cmd == SET_KEY)
 926                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 927         rt2800_register_multiwrite(rt2x00dev, offset,
 928                                       &wcid_entry, sizeof(wcid_entry));
 929 }
 930
 931 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 932                              struct rt2x00lib_crypto *crypto,
 933                              struct ieee80211_key_conf *key)
 934 {
 935         struct hw_key_entry key_entry;
 936         struct rt2x00_field32 field;
 937         u32 offset;
 938         u32 reg;
 939
 940         if (crypto->cmd == SET_KEY) {
 941                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 942
 943                 memcpy(key_entry.key, crypto->key,
 944                        sizeof(key_entry.key));
 945                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 946                        sizeof(key_entry.tx_mic));
 947                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 948                        sizeof(key_entry.rx_mic));
 949
 950                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 951                 rt2800_register_multiwrite(rt2x00dev, offset,
 952                                               &key_entry, sizeof(key_entry));
 953         }
 954
 955         /*
 956          * The cipher types are stored over multiple registers
 957          * starting with SHARED_KEY_MODE_BASE each word will have
 958          * 32 bits and contains the cipher types for 2 bssidx each.
 959          * Using the correct defines correctly will cause overhead,
 960          * so just calculate the correct offset.
 961          */
 962         field.bit_offset = 4 * (key->hw_key_idx % 8);
 963         field.bit_mask = 0x7 << field.bit_offset;
 964
 965         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 966
 967         rt2800_register_read(rt2x00dev, offset, &reg);
 968         rt2x00_set_field32(&reg, field,
 969                            (crypto->cmd == SET_KEY) * crypto->cipher);
 970         rt2800_register_write(rt2x00dev, offset, reg);
 971
 972         /*
 973          * Update WCID information
 974          */
 975         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 976
 977         return 0;
 978 }
 979 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 980
 981 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 982                                struct rt2x00lib_crypto *crypto,
 983                                struct ieee80211_key_conf *key)
 984 {
 985         struct hw_key_entry key_entry;
 986         u32 offset;
 987
 988         if (crypto->cmd == SET_KEY) {
 989                 /*
 990                  * 1 pairwise key is possible per AID, this means that the AID
 991                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 992                  * last possible shared key entry.
 993                  */
 994                 if (crypto->aid > (256 - 32))
 995                         return -ENOSPC;
 996
 997                 key->hw_key_idx = 32 + crypto->aid;
 998
 999                 memcpy(key_entry.key, crypto->key,
1000                        sizeof(key_entry.key));
1001                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1002                        sizeof(key_entry.tx_mic));
1003                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1004                        sizeof(key_entry.rx_mic));
1005
1006                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1007                 rt2800_register_multiwrite(rt2x00dev, offset,
1008                                               &key_entry, sizeof(key_entry));
1009         }
1010
1011         /*
1012          * Update WCID information
1013          */
1014         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1015
1016         return 0;
1017 }
1018 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1019
1020 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1021                           const unsigned int filter_flags)
1022 {
1023         u32 reg;
1024
1025         /*
1026          * Start configuration steps.
1027          * Note that the version error will always be dropped
1028          * and broadcast frames will always be accepted since
1029          * there is no filter for it at this time.
1030          */
1031         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1032         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1033                            !(filter_flags & FIF_FCSFAIL));
1034         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1035                            !(filter_flags & FIF_PLCPFAIL));
1036         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1037                            !(filter_flags & FIF_PROMISC_IN_BSS));
1038         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1039         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1040         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1041                            !(filter_flags & FIF_ALLMULTI));
1042         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1043         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1044         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1045                            !(filter_flags & FIF_CONTROL));
1046         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1047                            !(filter_flags & FIF_CONTROL));
1048         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1049                            !(filter_flags & FIF_CONTROL));
1050         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1051                            !(filter_flags & FIF_CONTROL));
1052         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1053                            !(filter_flags & FIF_CONTROL));
1054         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1055                            !(filter_flags & FIF_PSPOLL));
1056         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1057         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1058         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1059                            !(filter_flags & FIF_CONTROL));
1060         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1061 }
1062 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1063
1064 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1065                         struct rt2x00intf_conf *conf, const unsigned int flags)
1066 {
1067         u32 reg;
1068
1069         if (flags & CONFIG_UPDATE_TYPE) {
1070                 /*
1071                  * Clear current synchronisation setup.
1072                  */
1073                 rt2800_clear_beacon(rt2x00dev,
1074                                     HW_BEACON_OFFSET(intf->beacon->entry_idx));
1075                 /*
1076                  * Enable synchronisation.
1077                  */
1078                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1079                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1080                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1081                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1082                                    (conf->sync == TSF_SYNC_ADHOC ||
1083                                     conf->sync == TSF_SYNC_AP_NONE));
1084                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1085
1086                 /*
1087                  * Enable pre tbtt interrupt for beaconing modes
1088                  */
1089                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1090                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1091                                    (conf->sync == TSF_SYNC_AP_NONE));
1092                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1093
1094         }
1095
1096         if (flags & CONFIG_UPDATE_MAC) {
1097                 reg = le32_to_cpu(conf->mac[1]);
1098                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1099                 conf->mac[1] = cpu_to_le32(reg);
1100
1101                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1102                                               conf->mac, sizeof(conf->mac));
1103         }
1104
1105         if (flags & CONFIG_UPDATE_BSSID) {
1106                 reg = le32_to_cpu(conf->bssid[1]);
1107                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1108                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1109                 conf->bssid[1] = cpu_to_le32(reg);
1110
1111                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1112                                               conf->bssid, sizeof(conf->bssid));
1113         }
1114 }
1115 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1116
1117 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
1118 {
1119         u32 reg;
1120
1121         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1122         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1123                            !!erp->short_preamble);
1124         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1125                            !!erp->short_preamble);
1126         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1127
1128         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1129         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1130                            erp->cts_protection ? 2 : 0);
1131         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1132
1133         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1134                                  erp->basic_rates);
1135         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1136
1137         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1138         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
1139         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1140
1141         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1142         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1143         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1144
1145         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1146         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1147                            erp->beacon_int * 16);
1148         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149 }
1150 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1151
1152 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1153 {
1154         u8 r1;
1155         u8 r3;
1156
1157         rt2800_bbp_read(rt2x00dev, 1, &r1);
1158         rt2800_bbp_read(rt2x00dev, 3, &r3);
1159
1160         /*
1161          * Configure the TX antenna.
1162          */
1163         switch ((int)ant->tx) {
1164         case 1:
1165                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1166                 break;
1167         case 2:
1168                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1169                 break;
1170         case 3:
1171                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1172                 break;
1173         }
1174
1175         /*
1176          * Configure the RX antenna.
1177          */
1178         switch ((int)ant->rx) {
1179         case 1:
1180                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1181                 break;
1182         case 2:
1183                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1184                 break;
1185         case 3:
1186                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1187                 break;
1188         }
1189
1190         rt2800_bbp_write(rt2x00dev, 3, r3);
1191         rt2800_bbp_write(rt2x00dev, 1, r1);
1192 }
1193 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1194
1195 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1196                                    struct rt2x00lib_conf *libconf)
1197 {
1198         u16 eeprom;
1199         short lna_gain;
1200
1201         if (libconf->rf.channel <= 14) {
1202                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1203                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1204         } else if (libconf->rf.channel <= 64) {
1205                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1206                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1207         } else if (libconf->rf.channel <= 128) {
1208                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1209                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1210         } else {
1211                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1212                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1213         }
1214
1215         rt2x00dev->lna_gain = lna_gain;
1216 }
1217
1218 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1219                                          struct ieee80211_conf *conf,
1220                                          struct rf_channel *rf,
1221                                          struct channel_info *info)
1222 {
1223         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1224
1225         if (rt2x00dev->default_ant.tx == 1)
1226                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1227
1228         if (rt2x00dev->default_ant.rx == 1) {
1229                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1230                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1231         } else if (rt2x00dev->default_ant.rx == 2)
1232                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1233
1234         if (rf->channel > 14) {
1235                 /*
1236                  * When TX power is below 0, we should increase it by 7 to
1237                  * make it a positive value (Minumum value is -7).
1238                  * However this means that values between 0 and 7 have
1239                  * double meaning, and we should set a 7DBm boost flag.
1240                  */
1241                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1242                                    (info->tx_power1 >= 0));
1243
1244                 if (info->tx_power1 < 0)
1245                         info->tx_power1 += 7;
1246
1247                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
1248                                    TXPOWER_A_TO_DEV(info->tx_power1));
1249
1250                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1251                                    (info->tx_power2 >= 0));
1252
1253                 if (info->tx_power2 < 0)
1254                         info->tx_power2 += 7;
1255
1256                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
1257                                    TXPOWER_A_TO_DEV(info->tx_power2));
1258         } else {
1259                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
1260                                    TXPOWER_G_TO_DEV(info->tx_power1));
1261                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
1262                                    TXPOWER_G_TO_DEV(info->tx_power2));
1263         }
1264
1265         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1266
1267         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1268         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1269         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1270         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1271
1272         udelay(200);
1273
1274         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1275         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1276         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1277         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1278
1279         udelay(200);
1280
1281         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1282         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1283         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1284         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1285 }
1286
1287 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1288                                          struct ieee80211_conf *conf,
1289                                          struct rf_channel *rf,
1290                                          struct channel_info *info)
1291 {
1292         u8 rfcsr;
1293
1294         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1295         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1296
1297         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1298         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1299         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1300
1301         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1302         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1303                           TXPOWER_G_TO_DEV(info->tx_power1));
1304         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1305
1306         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1307         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1308                           TXPOWER_G_TO_DEV(info->tx_power2));
1309         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1310
1311         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1312         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1313         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1314
1315         rt2800_rfcsr_write(rt2x00dev, 24,
1316                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1317
1318         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1319         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1320         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1321 }
1322
1323 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1324                                   struct ieee80211_conf *conf,
1325                                   struct rf_channel *rf,
1326                                   struct channel_info *info)
1327 {
1328         u32 reg;
1329         unsigned int tx_pin;
1330         u8 bbp;
1331
1332         if (rt2x00_rf(rt2x00dev, RF2020) ||
1333             rt2x00_rf(rt2x00dev, RF3020) ||
1334             rt2x00_rf(rt2x00dev, RF3021) ||
1335             rt2x00_rf(rt2x00dev, RF3022))
1336                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1337         else
1338                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1339
1340         /*
1341          * Change BBP settings
1342          */
1343         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1344         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1345         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1346         rt2800_bbp_write(rt2x00dev, 86, 0);
1347
1348         if (rf->channel <= 14) {
1349                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1350                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1351                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1352                 } else {
1353                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1354                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1355                 }
1356         } else {
1357                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1358
1359                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1360                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1361                 else
1362                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1363         }
1364
1365         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1366         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1367         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1368         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1369         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1370
1371         tx_pin = 0;
1372
1373         /* Turn on unused PA or LNA when not using 1T or 1R */
1374         if (rt2x00dev->default_ant.tx != 1) {
1375                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1376                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1377         }
1378
1379         /* Turn on unused PA or LNA when not using 1T or 1R */
1380         if (rt2x00dev->default_ant.rx != 1) {
1381                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1382                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1383         }
1384
1385         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1386         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1387         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1388         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1389         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1390         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1391
1392         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1393
1394         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1395         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1396         rt2800_bbp_write(rt2x00dev, 4, bbp);
1397
1398         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1399         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1400         rt2800_bbp_write(rt2x00dev, 3, bbp);
1401
1402         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1403                 if (conf_is_ht40(conf)) {
1404                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1405                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1406                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1407                 } else {
1408                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1409                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1410                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1411                 }
1412         }
1413
1414         msleep(1);
1415 }
1416
1417 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1418                                   const int max_txpower)
1419 {
1420         u8 txpower;
1421         u8 max_value = (u8)max_txpower;
1422         u16 eeprom;
1423         int i;
1424         u32 reg;
1425         u8 r1;
1426         u32 offset;
1427
1428         /*
1429          * set to normal tx power mode: +/- 0dBm
1430          */
1431         rt2800_bbp_read(rt2x00dev, 1, &r1);
1432         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1433         rt2800_bbp_write(rt2x00dev, 1, r1);
1434
1435         /*
1436          * The eeprom contains the tx power values for each rate. These
1437          * values map to 100% tx power. Each 16bit word contains four tx
1438          * power values and the order is the same as used in the TX_PWR_CFG
1439          * registers.
1440          */
1441         offset = TX_PWR_CFG_0;
1442
1443         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1444                 /* just to be safe */
1445                 if (offset > TX_PWR_CFG_4)
1446                         break;
1447
1448                 rt2800_register_read(rt2x00dev, offset, &reg);
1449
1450                 /* read the next four txpower values */
1451                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1452                                    &eeprom);
1453
1454                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1455                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1456                  * TX_PWR_CFG_4: unknown */
1457                 txpower = rt2x00_get_field16(eeprom,
1458                                              EEPROM_TXPOWER_BYRATE_RATE0);
1459                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1460                                    min(txpower, max_value));
1461
1462                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1463                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1464                  * TX_PWR_CFG_4: unknown */
1465                 txpower = rt2x00_get_field16(eeprom,
1466                                              EEPROM_TXPOWER_BYRATE_RATE1);
1467                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1468                                    min(txpower, max_value));
1469
1470                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1471                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1472                  * TX_PWR_CFG_4: unknown */
1473                 txpower = rt2x00_get_field16(eeprom,
1474                                              EEPROM_TXPOWER_BYRATE_RATE2);
1475                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1476                                    min(txpower, max_value));
1477
1478                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1479                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1480                  * TX_PWR_CFG_4: unknown */
1481                 txpower = rt2x00_get_field16(eeprom,
1482                                              EEPROM_TXPOWER_BYRATE_RATE3);
1483                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1484                                    min(txpower, max_value));
1485
1486                 /* read the next four txpower values */
1487                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1488                                    &eeprom);
1489
1490                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1491                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1492                  * TX_PWR_CFG_4: unknown */
1493                 txpower = rt2x00_get_field16(eeprom,
1494                                              EEPROM_TXPOWER_BYRATE_RATE0);
1495                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1496                                    min(txpower, max_value));
1497
1498                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1499                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1500                  * TX_PWR_CFG_4: unknown */
1501                 txpower = rt2x00_get_field16(eeprom,
1502                                              EEPROM_TXPOWER_BYRATE_RATE1);
1503                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1504                                    min(txpower, max_value));
1505
1506                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1507                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1508                  * TX_PWR_CFG_4: unknown */
1509                 txpower = rt2x00_get_field16(eeprom,
1510                                              EEPROM_TXPOWER_BYRATE_RATE2);
1511                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1512                                    min(txpower, max_value));
1513
1514                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1515                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1516                  * TX_PWR_CFG_4: unknown */
1517                 txpower = rt2x00_get_field16(eeprom,
1518                                              EEPROM_TXPOWER_BYRATE_RATE3);
1519                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1520                                    min(txpower, max_value));
1521
1522                 rt2800_register_write(rt2x00dev, offset, reg);
1523
1524                 /* next TX_PWR_CFG register */
1525                 offset += 4;
1526         }
1527 }
1528
1529 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1530                                       struct rt2x00lib_conf *libconf)
1531 {
1532         u32 reg;
1533
1534         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1535         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1536                            libconf->conf->short_frame_max_tx_count);
1537         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1538                            libconf->conf->long_frame_max_tx_count);
1539         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1540 }
1541
1542 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1543                              struct rt2x00lib_conf *libconf)
1544 {
1545         enum dev_state state =
1546             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1547                 STATE_SLEEP : STATE_AWAKE;
1548         u32 reg;
1549
1550         if (state == STATE_SLEEP) {
1551                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1552
1553                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1554                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1555                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1556                                    libconf->conf->listen_interval - 1);
1557                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1558                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1559
1560                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1561         } else {
1562                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1563                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1564                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1565                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1566                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1567
1568                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1569         }
1570 }
1571
1572 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1573                    struct rt2x00lib_conf *libconf,
1574                    const unsigned int flags)
1575 {
1576         /* Always recalculate LNA gain before changing configuration */
1577         rt2800_config_lna_gain(rt2x00dev, libconf);
1578
1579         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1580                 rt2800_config_channel(rt2x00dev, libconf->conf,
1581                                       &libconf->rf, &libconf->channel);
1582         if (flags & IEEE80211_CONF_CHANGE_POWER)
1583                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1584         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1585                 rt2800_config_retry_limit(rt2x00dev, libconf);
1586         if (flags & IEEE80211_CONF_CHANGE_PS)
1587                 rt2800_config_ps(rt2x00dev, libconf);
1588 }
1589 EXPORT_SYMBOL_GPL(rt2800_config);
1590
1591 /*
1592  * Link tuning
1593  */
1594 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1595 {
1596         u32 reg;
1597
1598         /*
1599          * Update FCS error count from register.
1600          */
1601         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1602         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1603 }
1604 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1605
1606 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1607 {
1608         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1609                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1610                     rt2x00_rt(rt2x00dev, RT3071) ||
1611                     rt2x00_rt(rt2x00dev, RT3090) ||
1612                     rt2x00_rt(rt2x00dev, RT3390))
1613                         return 0x1c + (2 * rt2x00dev->lna_gain);
1614                 else
1615                         return 0x2e + rt2x00dev->lna_gain;
1616         }
1617
1618         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1619                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1620         else
1621                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1622 }
1623
1624 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1625                                   struct link_qual *qual, u8 vgc_level)
1626 {
1627         if (qual->vgc_level != vgc_level) {
1628                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1629                 qual->vgc_level = vgc_level;
1630                 qual->vgc_level_reg = vgc_level;
1631         }
1632 }
1633
1634 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1635 {
1636         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1637 }
1638 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1639
1640 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1641                        const u32 count)
1642 {
1643         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1644                 return;
1645
1646         /*
1647          * When RSSI is better then -80 increase VGC level with 0x10
1648          */
1649         rt2800_set_vgc(rt2x00dev, qual,
1650                        rt2800_get_default_vgc(rt2x00dev) +
1651                        ((qual->rssi > -80) * 0x10));
1652 }
1653 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1654
1655 /*
1656  * Initialization functions.
1657  */
1658 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1659 {
1660         u32 reg;
1661         u16 eeprom;
1662         unsigned int i;
1663         int ret;
1664
1665         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1666         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1667         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1668         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1669         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1670         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1671         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1672
1673         ret = rt2800_drv_init_registers(rt2x00dev);
1674         if (ret)
1675                 return ret;
1676
1677         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1678         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1679         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1680         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1681         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1682         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1683
1684         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1685         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1686         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1687         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1688         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1689         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1690
1691         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1692         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1693
1694         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1695
1696         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1697         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1698         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1699         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1700         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1701         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1702         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1703         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1704
1705         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1706
1707         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1708         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1709         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1710         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1711
1712         if (rt2x00_rt(rt2x00dev, RT3071) ||
1713             rt2x00_rt(rt2x00dev, RT3090) ||
1714             rt2x00_rt(rt2x00dev, RT3390)) {
1715                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1716                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1717                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1718                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1719                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1720                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1721                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1722                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1723                                                       0x0000002c);
1724                         else
1725                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1726                                                       0x0000000f);
1727                 } else {
1728                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1729                 }
1730         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1731                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1732
1733                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1734                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1735                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1736                 } else {
1737                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1738                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1739                 }
1740         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1741                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1742                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1743                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1744         } else {
1745                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1746                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1747         }
1748
1749         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1750         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1751         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1752         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1753         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1754         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1755         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1756         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1757         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1758         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1759
1760         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1761         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1762         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1763         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1764         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1765
1766         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1767         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1768         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1769             rt2x00_rt(rt2x00dev, RT2883) ||
1770             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1771                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1772         else
1773                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1774         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1775         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1776         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1777
1778         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1779         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1780         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1781         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1782         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1783         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1784         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1785         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1786         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1787
1788         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1789
1790         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1791         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1792         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1793         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1794         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1795         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1796         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1797         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1798
1799         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1800         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1801         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1802         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1803         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1804         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1805         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1806         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1807         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1808
1809         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1810         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1811         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1812         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1813         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1814         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1815         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1816         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1817         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1818         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1819         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1820         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1821
1822         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1823         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1824         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1825         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1826         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1827         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1828         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1829         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1830         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1831         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1832         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1833         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1834
1835         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1836         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1837         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1838         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1839         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1840         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1841         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1842         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1843         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1844         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1845         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1846         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1847
1848         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1849         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1850         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1851                            !rt2x00_is_usb(rt2x00dev));
1852         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1853         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1854         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1855         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1856         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1857         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1858         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1859         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1860         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1861
1862         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1863         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1864         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1865         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1866         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1867         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1868         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1869         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1870         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1871         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1872         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1873         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1874
1875         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1876         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1877         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1878         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1879         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1880         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1881         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1882         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1883         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1884         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1885         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1886         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1887
1888         if (rt2x00_is_usb(rt2x00dev)) {
1889                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1890
1891                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1892                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1893                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1894                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1895                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1896                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1897                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1898                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1899                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1900                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1901                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1902         }
1903
1904         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1905         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1906
1907         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1908         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1909         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1910                            IEEE80211_MAX_RTS_THRESHOLD);
1911         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1912         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1913
1914         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1915
1916         /*
1917          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1918          * time should be set to 16. However, the original Ralink driver uses
1919          * 16 for both and indeed using a value of 10 for CCK SIFS results in
1920          * connection problems with 11g + CTS protection. Hence, use the same
1921          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1922          */
1923         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1924         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1925         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1926         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1927         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1928         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1929         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1930
1931         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1932
1933         /*
1934          * ASIC will keep garbage value after boot, clear encryption keys.
1935          */
1936         for (i = 0; i < 4; i++)
1937                 rt2800_register_write(rt2x00dev,
1938                                          SHARED_KEY_MODE_ENTRY(i), 0);
1939
1940         for (i = 0; i < 256; i++) {
1941                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1942                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1943                                               wcid, sizeof(wcid));
1944
1945                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1946                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1947         }
1948
1949         /*
1950          * Clear all beacons
1951          */
1952         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1953         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1954         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1955         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1956         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1957         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1958         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1959         rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
1960
1961         if (rt2x00_is_usb(rt2x00dev)) {
1962                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1963                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1964                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
1965         }
1966
1967         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1968         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1969         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1970         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1971         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1972         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1973         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1974         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1975         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1976         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1977
1978         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1979         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1980         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1981         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1982         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1983         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1984         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1985         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1986         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1987         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1988
1989         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1990         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1991         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1992         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1993         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1994         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1995         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1996         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1997         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1998         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1999
2000         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2001         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2002         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2003         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2004         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2005         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2006
2007         /*
2008          * We must clear the error counters.
2009          * These registers are cleared on read,
2010          * so we may pass a useless variable to store the value.
2011          */
2012         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2013         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2014         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2015         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2016         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2017         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2018
2019         /*
2020          * Setup leadtime for pre tbtt interrupt to 6ms
2021          */
2022         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2023         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2024         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2025
2026         return 0;
2027 }
2028 EXPORT_SYMBOL_GPL(rt2800_init_registers);
2029
2030 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2031 {
2032         unsigned int i;
2033         u32 reg;
2034
2035         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2036                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2037                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2038                         return 0;
2039
2040                 udelay(REGISTER_BUSY_DELAY);
2041         }
2042
2043         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2044         return -EACCES;
2045 }
2046
2047 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2048 {
2049         unsigned int i;
2050         u8 value;
2051
2052         /*
2053          * BBP was enabled after firmware was loaded,
2054          * but we need to reactivate it now.
2055          */
2056         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2057         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2058         msleep(1);
2059
2060         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2061                 rt2800_bbp_read(rt2x00dev, 0, &value);
2062                 if ((value != 0xff) && (value != 0x00))
2063                         return 0;
2064                 udelay(REGISTER_BUSY_DELAY);
2065         }
2066
2067         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2068         return -EACCES;
2069 }
2070
2071 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2072 {
2073         unsigned int i;
2074         u16 eeprom;
2075         u8 reg_id;
2076         u8 value;
2077
2078         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2079                      rt2800_wait_bbp_ready(rt2x00dev)))
2080                 return -EACCES;
2081
2082         if (rt2800_is_305x_soc(rt2x00dev))
2083                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2084
2085         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2086         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2087
2088         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2089                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2090                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2091         } else {
2092                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2093                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2094         }
2095
2096         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2097
2098         if (rt2x00_rt(rt2x00dev, RT3070) ||
2099             rt2x00_rt(rt2x00dev, RT3071) ||
2100             rt2x00_rt(rt2x00dev, RT3090) ||
2101             rt2x00_rt(rt2x00dev, RT3390)) {
2102                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2103                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2104                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2105         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2106                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2107                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2108         } else {
2109                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2110         }
2111
2112         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2113         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2114
2115         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2116                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2117         else
2118                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2119
2120         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2121         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2122         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2123
2124         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2125             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2126             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2127             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2128             rt2800_is_305x_soc(rt2x00dev))
2129                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2130         else
2131                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2132
2133         if (rt2800_is_305x_soc(rt2x00dev))
2134                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2135         else
2136                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2137         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2138
2139         if (rt2x00_rt(rt2x00dev, RT3071) ||
2140             rt2x00_rt(rt2x00dev, RT3090) ||
2141             rt2x00_rt(rt2x00dev, RT3390)) {
2142                 rt2800_bbp_read(rt2x00dev, 138, &value);
2143
2144                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2145                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2146                         value |= 0x20;
2147                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2148                         value &= ~0x02;
2149
2150                 rt2800_bbp_write(rt2x00dev, 138, value);
2151         }
2152
2153
2154         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2155                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2156
2157                 if (eeprom != 0xffff && eeprom != 0x0000) {
2158                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2159                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2160                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2161                 }
2162         }
2163
2164         return 0;
2165 }
2166 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
2167
2168 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2169                                 bool bw40, u8 rfcsr24, u8 filter_target)
2170 {
2171         unsigned int i;
2172         u8 bbp;
2173         u8 rfcsr;
2174         u8 passband;
2175         u8 stopband;
2176         u8 overtuned = 0;
2177
2178         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2179
2180         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2181         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2182         rt2800_bbp_write(rt2x00dev, 4, bbp);
2183
2184         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2185         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2186         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2187
2188         /*
2189          * Set power & frequency of passband test tone
2190          */
2191         rt2800_bbp_write(rt2x00dev, 24, 0);
2192
2193         for (i = 0; i < 100; i++) {
2194                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2195                 msleep(1);
2196
2197                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2198                 if (passband)
2199                         break;
2200         }
2201
2202         /*
2203          * Set power & frequency of stopband test tone
2204          */
2205         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2206
2207         for (i = 0; i < 100; i++) {
2208                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2209                 msleep(1);
2210
2211                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2212
2213                 if ((passband - stopband) <= filter_target) {
2214                         rfcsr24++;
2215                         overtuned += ((passband - stopband) == filter_target);
2216                 } else
2217                         break;
2218
2219                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2220         }
2221
2222         rfcsr24 -= !!overtuned;
2223
2224         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2225         return rfcsr24;
2226 }
2227
2228 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2229 {
2230         u8 rfcsr;
2231         u8 bbp;
2232         u32 reg;
2233         u16 eeprom;
2234
2235         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2236             !rt2x00_rt(rt2x00dev, RT3071) &&
2237             !rt2x00_rt(rt2x00dev, RT3090) &&
2238             !rt2x00_rt(rt2x00dev, RT3390) &&
2239             !rt2800_is_305x_soc(rt2x00dev))
2240                 return 0;
2241
2242         /*
2243          * Init RF calibration.
2244          */
2245         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2246         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2247         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2248         msleep(1);
2249         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2250         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2251
2252         if (rt2x00_rt(rt2x00dev, RT3070) ||
2253             rt2x00_rt(rt2x00dev, RT3071) ||
2254             rt2x00_rt(rt2x00dev, RT3090)) {
2255                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2256                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2257                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2258                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2259                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2260                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2261                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2262                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2263                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2264                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2265                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2266                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2267                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2268                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2269                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2270                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2271                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2272                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2273                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2274         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2275                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2276                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2277                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2278                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2279                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2280                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2281                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2282                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2283                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2284                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2285                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2286                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2287                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2288                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2289                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2290                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2291                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2292                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2293                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2294                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2295                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2296                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2297                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2298                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2299                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2300                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2301                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2302                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2303                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2304                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2305                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2306                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2307         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2308                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2309                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2310                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2311                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2312                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2313                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2314                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2315                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2316                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2317                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2318                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2319                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2320                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2321                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2322                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2323                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2324                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2325                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2326                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2327                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2328                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2329                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2330                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2331                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2332                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2333                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2334                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2335                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2336                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2337                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2338                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2339                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2340                 return 0;
2341         }
2342
2343         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2344                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2345                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2346                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2347                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2348         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2349                    rt2x00_rt(rt2x00dev, RT3090)) {
2350                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2351                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2352                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2353
2354                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2355
2356                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2357                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2358                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2359                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2360                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2361                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2362                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2363                         else
2364                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2365                 }
2366                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2367         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2368                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2369                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2370                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2371         }
2372
2373         /*
2374          * Set RX Filter calibration for 20MHz and 40MHz
2375          */
2376         if (rt2x00_rt(rt2x00dev, RT3070)) {
2377                 rt2x00dev->calibration[0] =
2378                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2379                 rt2x00dev->calibration[1] =
2380                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2381         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2382                    rt2x00_rt(rt2x00dev, RT3090) ||
2383                    rt2x00_rt(rt2x00dev, RT3390)) {
2384                 rt2x00dev->calibration[0] =
2385                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2386                 rt2x00dev->calibration[1] =
2387                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2388         }
2389
2390         /*
2391          * Set back to initial state
2392          */
2393         rt2800_bbp_write(rt2x00dev, 24, 0);
2394
2395         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2396         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2397         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2398
2399         /*
2400          * set BBP back to BW20
2401          */
2402         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2403         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2404         rt2800_bbp_write(rt2x00dev, 4, bbp);
2405
2406         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2407             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2408             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2409             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2410                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2411
2412         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2413         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2414         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2415
2416         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2417         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2418         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2419             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2420             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2421                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2422                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2423         }
2424         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2425         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2426                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2427                                   rt2x00_get_field16(eeprom,
2428                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2429         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2430
2431         if (rt2x00_rt(rt2x00dev, RT3090)) {
2432                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2433
2434                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2435                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2436                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2437                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2438                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2439
2440                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2441         }
2442
2443         if (rt2x00_rt(rt2x00dev, RT3071) ||
2444             rt2x00_rt(rt2x00dev, RT3090) ||
2445             rt2x00_rt(rt2x00dev, RT3390)) {
2446                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2447                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2448                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2449                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2450                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2451                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2452                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2453
2454                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2455                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2456                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2457
2458                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2459                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2460                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2461
2462                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2463                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2464                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2465         }
2466
2467         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2468                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2469                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2470                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2471                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2472                 else
2473                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2474                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2475                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2476                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2477                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2478         }
2479
2480         return 0;
2481 }
2482 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2483
2484 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2485 {
2486         u32 reg;
2487
2488         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2489
2490         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2491 }
2492 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2493
2494 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2495 {
2496         u32 reg;
2497
2498         mutex_lock(&rt2x00dev->csr_mutex);
2499
2500         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2501         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2502         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2503         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2504         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2505
2506         /* Wait until the EEPROM has been loaded */
2507         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2508
2509         /* Apparently the data is read from end to start */
2510         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2511                                         (u32 *)&rt2x00dev->eeprom[i]);
2512         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2513                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2514         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2515                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2516         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2517                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2518
2519         mutex_unlock(&rt2x00dev->csr_mutex);
2520 }
2521
2522 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2523 {
2524         unsigned int i;
2525
2526         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2527                 rt2800_efuse_read(rt2x00dev, i);
2528 }
2529 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2530
2531 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2532 {
2533         u16 word;
2534         u8 *mac;
2535         u8 default_lna_gain;
2536
2537         /*
2538          * Start validation of the data that has been read.
2539          */
2540         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2541         if (!is_valid_ether_addr(mac)) {
2542                 random_ether_addr(mac);
2543                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2544         }
2545
2546         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2547         if (word == 0xffff) {
2548                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2549                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2550                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2551                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2552                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2553         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2554                    rt2x00_rt(rt2x00dev, RT2872)) {
2555                 /*
2556                  * There is a max of 2 RX streams for RT28x0 series
2557                  */
2558                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2559                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2560                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2561         }
2562
2563         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2564         if (word == 0xffff) {
2565                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2566                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2567                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2568                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2569                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2570                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2571                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2572                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2573                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2574                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2575                 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2576                 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2577                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2578                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2579         }
2580
2581         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2582         if ((word & 0x00ff) == 0x00ff) {
2583                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2584                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2585                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2586         }
2587         if ((word & 0xff00) == 0xff00) {
2588                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2589                                    LED_MODE_TXRX_ACTIVITY);
2590                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2591                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2592                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2593                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2594                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2595                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2596         }
2597
2598         /*
2599          * During the LNA validation we are going to use
2600          * lna0 as correct value. Note that EEPROM_LNA
2601          * is never validated.
2602          */
2603         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2604         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2605
2606         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2607         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2608                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2609         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2610                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2611         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2612
2613         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2614         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2615                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2616         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2617             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2618                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2619                                    default_lna_gain);
2620         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2621
2622         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2623         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2624                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2625         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2626                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2627         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2628
2629         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2630         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2631                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2632         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2633             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2634                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2635                                    default_lna_gain);
2636         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2637
2638         return 0;
2639 }
2640 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2641
2642 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2643 {
2644         u32 reg;
2645         u16 value;
2646         u16 eeprom;
2647
2648         /*
2649          * Read EEPROM word for configuration.
2650          */
2651         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2652
2653         /*
2654          * Identify RF chipset.
2655          */
2656         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2657         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2658
2659         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2660                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2661
2662         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2663             !rt2x00_rt(rt2x00dev, RT2872) &&
2664             !rt2x00_rt(rt2x00dev, RT2883) &&
2665             !rt2x00_rt(rt2x00dev, RT3070) &&
2666             !rt2x00_rt(rt2x00dev, RT3071) &&
2667             !rt2x00_rt(rt2x00dev, RT3090) &&
2668             !rt2x00_rt(rt2x00dev, RT3390) &&
2669             !rt2x00_rt(rt2x00dev, RT3572)) {
2670                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2671                 return -ENODEV;
2672         }
2673
2674         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2675             !rt2x00_rf(rt2x00dev, RF2850) &&
2676             !rt2x00_rf(rt2x00dev, RF2720) &&
2677             !rt2x00_rf(rt2x00dev, RF2750) &&
2678             !rt2x00_rf(rt2x00dev, RF3020) &&
2679             !rt2x00_rf(rt2x00dev, RF2020) &&
2680             !rt2x00_rf(rt2x00dev, RF3021) &&
2681             !rt2x00_rf(rt2x00dev, RF3022) &&
2682             !rt2x00_rf(rt2x00dev, RF3052)) {
2683                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2684                 return -ENODEV;
2685         }
2686
2687         /*
2688          * Identify default antenna configuration.
2689          */
2690         rt2x00dev->default_ant.tx =
2691             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2692         rt2x00dev->default_ant.rx =
2693             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2694
2695         /*
2696          * Read frequency offset and RF programming sequence.
2697          */
2698         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2699         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2700
2701         /*
2702          * Read external LNA informations.
2703          */
2704         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2705
2706         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2707                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2708         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2709                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2710
2711         /*
2712          * Detect if this device has an hardware controlled radio.
2713          */
2714         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2715                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2716
2717         /*
2718          * Store led settings, for correct led behaviour.
2719          */
2720 #ifdef CONFIG_RT2X00_LIB_LEDS
2721         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2722         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2723         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2724
2725         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2726 #endif /* CONFIG_RT2X00_LIB_LEDS */
2727
2728         return 0;
2729 }
2730 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2731
2732 /*
2733  * RF value list for rt28xx
2734  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2735  */
2736 static const struct rf_channel rf_vals[] = {
2737         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2738         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2739         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2740         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2741         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2742         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2743         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2744         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2745         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2746         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2747         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2748         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2749         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2750         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2751
2752         /* 802.11 UNI / HyperLan 2 */
2753         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2754         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2755         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2756         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2757         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2758         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2759         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2760         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2761         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2762         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2763         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2764         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2765
2766         /* 802.11 HyperLan 2 */
2767         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2768         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2769         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2770         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2771         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2772         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2773         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2774         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2775         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2776         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2777         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2778         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2779         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2780         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2781         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2782         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2783
2784         /* 802.11 UNII */
2785         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2786         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2787         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2788         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2789         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2790         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2791         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2792         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2793         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2794         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2795         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2796
2797         /* 802.11 Japan */
2798         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2799         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2800         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2801         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2802         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2803         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2804         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2805 };
2806
2807 /*
2808  * RF value list for rt3xxx
2809  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2810  */
2811 static const struct rf_channel rf_vals_3x[] = {
2812         {1,  241, 2, 2 },
2813         {2,  241, 2, 7 },
2814         {3,  242, 2, 2 },
2815         {4,  242, 2, 7 },
2816         {5,  243, 2, 2 },
2817         {6,  243, 2, 7 },
2818         {7,  244, 2, 2 },
2819         {8,  244, 2, 7 },
2820         {9,  245, 2, 2 },
2821         {10, 245, 2, 7 },
2822         {11, 246, 2, 2 },
2823         {12, 246, 2, 7 },
2824         {13, 247, 2, 2 },
2825         {14, 248, 2, 4 },
2826
2827         /* 802.11 UNI / HyperLan 2 */
2828         {36, 0x56, 0, 4},
2829         {38, 0x56, 0, 6},
2830         {40, 0x56, 0, 8},
2831         {44, 0x57, 0, 0},
2832         {46, 0x57, 0, 2},
2833         {48, 0x57, 0, 4},
2834         {52, 0x57, 0, 8},
2835         {54, 0x57, 0, 10},
2836         {56, 0x58, 0, 0},
2837         {60, 0x58, 0, 4},
2838         {62, 0x58, 0, 6},
2839         {64, 0x58, 0, 8},
2840
2841         /* 802.11 HyperLan 2 */
2842         {100, 0x5b, 0, 8},
2843         {102, 0x5b, 0, 10},
2844         {104, 0x5c, 0, 0},
2845         {108, 0x5c, 0, 4},
2846         {110, 0x5c, 0, 6},
2847         {112, 0x5c, 0, 8},
2848         {116, 0x5d, 0, 0},
2849         {118, 0x5d, 0, 2},
2850         {120, 0x5d, 0, 4},
2851         {124, 0x5d, 0, 8},
2852         {126, 0x5d, 0, 10},
2853         {128, 0x5e, 0, 0},
2854         {132, 0x5e, 0, 4},
2855         {134, 0x5e, 0, 6},
2856         {136, 0x5e, 0, 8},
2857         {140, 0x5f, 0, 0},
2858
2859         /* 802.11 UNII */
2860         {149, 0x5f, 0, 9},
2861         {151, 0x5f, 0, 11},
2862         {153, 0x60, 0, 1},
2863         {157, 0x60, 0, 5},
2864         {159, 0x60, 0, 7},
2865         {161, 0x60, 0, 9},
2866         {165, 0x61, 0, 1},
2867         {167, 0x61, 0, 3},
2868         {169, 0x61, 0, 5},
2869         {171, 0x61, 0, 7},
2870         {173, 0x61, 0, 9},
2871 };
2872
2873 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2874 {
2875         struct hw_mode_spec *spec = &rt2x00dev->spec;
2876         struct channel_info *info;
2877         char *tx_power1;
2878         char *tx_power2;
2879         unsigned int i;
2880         u16 eeprom;
2881
2882         /*
2883          * Disable powersaving as default on PCI devices.
2884          */
2885         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2886                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2887
2888         /*
2889          * Initialize all hw fields.
2890          */
2891         rt2x00dev->hw->flags =
2892             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2893             IEEE80211_HW_SIGNAL_DBM |
2894             IEEE80211_HW_SUPPORTS_PS |
2895             IEEE80211_HW_PS_NULLFUNC_STACK |
2896             IEEE80211_HW_AMPDU_AGGREGATION;
2897
2898         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2899         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2900                                 rt2x00_eeprom_addr(rt2x00dev,
2901                                                    EEPROM_MAC_ADDR_0));
2902
2903         /*
2904          * As rt2800 has a global fallback table we cannot specify
2905          * more then one tx rate per frame but since the hw will
2906          * try several rates (based on the fallback table) we should
2907          * still initialize max_rates to the maximum number of rates
2908          * we are going to try. Otherwise mac80211 will truncate our
2909          * reported tx rates and the rc algortihm will end up with
2910          * incorrect data.
2911          */
2912         rt2x00dev->hw->max_rates = 7;
2913         rt2x00dev->hw->max_rate_tries = 1;
2914
2915         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2916
2917         /*
2918          * Initialize hw_mode information.
2919          */
2920         spec->supported_bands = SUPPORT_BAND_2GHZ;
2921         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2922
2923         if (rt2x00_rf(rt2x00dev, RF2820) ||
2924             rt2x00_rf(rt2x00dev, RF2720)) {
2925                 spec->num_channels = 14;
2926                 spec->channels = rf_vals;
2927         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2928                    rt2x00_rf(rt2x00dev, RF2750)) {
2929                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2930                 spec->num_channels = ARRAY_SIZE(rf_vals);
2931                 spec->channels = rf_vals;
2932         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2933                    rt2x00_rf(rt2x00dev, RF2020) ||
2934                    rt2x00_rf(rt2x00dev, RF3021) ||
2935                    rt2x00_rf(rt2x00dev, RF3022)) {
2936                 spec->num_channels = 14;
2937                 spec->channels = rf_vals_3x;
2938         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2939                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2940                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2941                 spec->channels = rf_vals_3x;
2942         }
2943
2944         /*
2945          * Initialize HT information.
2946          */
2947         if (!rt2x00_rf(rt2x00dev, RF2020))
2948                 spec->ht.ht_supported = true;
2949         else
2950                 spec->ht.ht_supported = false;
2951
2952         spec->ht.cap =
2953             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2954             IEEE80211_HT_CAP_GRN_FLD |
2955             IEEE80211_HT_CAP_SGI_20 |
2956             IEEE80211_HT_CAP_SGI_40;
2957
2958         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2959                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2960
2961         spec->ht.cap |=
2962             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
2963                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
2964
2965         spec->ht.ampdu_factor = 3;
2966         spec->ht.ampdu_density = 4;
2967         spec->ht.mcs.tx_params =
2968             IEEE80211_HT_MCS_TX_DEFINED |
2969             IEEE80211_HT_MCS_TX_RX_DIFF |
2970             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2971                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2972
2973         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2974         case 3:
2975                 spec->ht.mcs.rx_mask[2] = 0xff;
2976         case 2:
2977                 spec->ht.mcs.rx_mask[1] = 0xff;
2978         case 1:
2979                 spec->ht.mcs.rx_mask[0] = 0xff;
2980                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2981                 break;
2982         }
2983
2984         /*
2985          * Create channel information array
2986          */
2987         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2988         if (!info)
2989                 return -ENOMEM;
2990
2991         spec->channels_info = info;
2992
2993         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2994         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2995
2996         for (i = 0; i < 14; i++) {
2997                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2998                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2999         }
3000
3001         if (spec->num_channels > 14) {
3002                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3003                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3004
3005                 for (i = 14; i < spec->num_channels; i++) {
3006                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
3007                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
3008                 }
3009         }
3010
3011         return 0;
3012 }
3013 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3014
3015 /*
3016  * IEEE80211 stack callback functions.
3017  */
3018 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3019                          u16 *iv16)
3020 {
3021         struct rt2x00_dev *rt2x00dev = hw->priv;
3022         struct mac_iveiv_entry iveiv_entry;
3023         u32 offset;
3024
3025         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3026         rt2800_register_multiread(rt2x00dev, offset,
3027                                       &iveiv_entry, sizeof(iveiv_entry));
3028
3029         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3030         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3031 }
3032 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3033
3034 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3035 {
3036         struct rt2x00_dev *rt2x00dev = hw->priv;
3037         u32 reg;
3038         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3039
3040         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3041         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3042         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3043
3044         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3045         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3046         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3047
3048         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3049         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3050         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3051
3052         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3053         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3054         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3055
3056         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3057         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3058         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3059
3060         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3061         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3062         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3063
3064         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3065         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3066         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3067
3068         return 0;
3069 }
3070 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3071
3072 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3073                    const struct ieee80211_tx_queue_params *params)
3074 {
3075         struct rt2x00_dev *rt2x00dev = hw->priv;
3076         struct data_queue *queue;
3077         struct rt2x00_field32 field;
3078         int retval;
3079         u32 reg;
3080         u32 offset;
3081
3082         /*
3083          * First pass the configuration through rt2x00lib, that will
3084          * update the queue settings and validate the input. After that
3085          * we are free to update the registers based on the value
3086          * in the queue parameter.
3087          */
3088         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3089         if (retval)
3090                 return retval;
3091
3092         /*
3093          * We only need to perform additional register initialization
3094          * for WMM queues/
3095          */
3096         if (queue_idx >= 4)
3097                 return 0;
3098
3099         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3100
3101         /* Update WMM TXOP register */
3102         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3103         field.bit_offset = (queue_idx & 1) * 16;
3104         field.bit_mask = 0xffff << field.bit_offset;
3105
3106         rt2800_register_read(rt2x00dev, offset, &reg);
3107         rt2x00_set_field32(&reg, field, queue->txop);
3108         rt2800_register_write(rt2x00dev, offset, reg);
3109
3110         /* Update WMM registers */
3111         field.bit_offset = queue_idx * 4;
3112         field.bit_mask = 0xf << field.bit_offset;
3113
3114         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3115         rt2x00_set_field32(&reg, field, queue->aifs);
3116         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3117
3118         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3119         rt2x00_set_field32(&reg, field, queue->cw_min);
3120         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3121
3122         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3123         rt2x00_set_field32(&reg, field, queue->cw_max);
3124         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3125
3126         /* Update EDCA registers */
3127         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3128
3129         rt2800_register_read(rt2x00dev, offset, &reg);
3130         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3131         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3132         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3133         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3134         rt2800_register_write(rt2x00dev, offset, reg);
3135
3136         return 0;
3137 }
3138 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3139
3140 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3141 {
3142         struct rt2x00_dev *rt2x00dev = hw->priv;
3143         u64 tsf;
3144         u32 reg;
3145
3146         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3147         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3148         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3149         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3150
3151         return tsf;
3152 }
3153 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3154
3155 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3156                         enum ieee80211_ampdu_mlme_action action,
3157                         struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3158 {
3159         int ret = 0;
3160
3161         switch (action) {
3162         case IEEE80211_AMPDU_RX_START:
3163         case IEEE80211_AMPDU_RX_STOP:
3164                 /* we don't support RX aggregation yet */
3165                 ret = -ENOTSUPP;
3166                 break;
3167         case IEEE80211_AMPDU_TX_START:
3168                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3169                 break;
3170         case IEEE80211_AMPDU_TX_STOP:
3171                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3172                 break;
3173         case IEEE80211_AMPDU_TX_OPERATIONAL:
3174                 break;
3175         default:
3176                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3177         }
3178
3179         return ret;
3180 }
3181 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3182
3183 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3184 MODULE_VERSION(DRV_VERSION);
3185 MODULE_DESCRIPTION("Ralink RT2800 library");
3186 MODULE_LICENSE("GPL");