drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34 #include <linux/slab.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt2500pci.h"
  39
  40 /*
  41  * Register access.
  42  * All access to the CSR registers will go through the methods
  43  * rt2x00pci_register_read and rt2x00pci_register_write.
  44  * BBP and RF register require indirect register access,
  45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  46  * These indirect registers work with busy bits,
  47  * and we will try maximal REGISTER_BUSY_COUNT times to access
  48  * the register while taking a REGISTER_BUSY_DELAY us delay
  49  * between each attampt. When the busy bit is still set at that time,
  50  * the access attempt is considered to have failed,
  51  * and we will print an error.
  52  */
  53 #define WAIT_FOR_BBP(__dev, __reg) \
  54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  55 #define WAIT_FOR_RF(__dev, __reg) \
  56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  57
  58 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  59                                 const unsigned int word, const u8 value)
  60 {
  61         u32 reg;
  62
  63         mutex_lock(&rt2x00dev->csr_mutex);
  64
  65         /*
  66          * Wait until the BBP becomes available, afterwards we
  67          * can safely write the new data into the register.
  68          */
  69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  70                 reg = 0;
  71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  75
  76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  77         }
  78
  79         mutex_unlock(&rt2x00dev->csr_mutex);
  80 }
  81
  82 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  83                                const unsigned int word, u8 *value)
  84 {
  85         u32 reg;
  86
  87         mutex_lock(&rt2x00dev->csr_mutex);
  88
  89         /*
  90          * Wait until the BBP becomes available, afterwards we
  91          * can safely write the read request into the register.
  92          * After the data has been written, we wait until hardware
  93          * returns the correct value, if at any time the register
  94          * doesn't become available in time, reg will be 0xffffffff
  95          * which means we return 0xff to the caller.
  96          */
  97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  98                 reg = 0;
  99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 102
 103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 104
 105                 WAIT_FOR_BBP(rt2x00dev, &reg);
 106         }
 107
 108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 114                                const unsigned int word, const u32 value)
 115 {
 116         u32 reg;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the RF becomes available, afterwards we
 122          * can safely write the new data into the register.
 123          */
 124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 125                 reg = 0;
 126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 130
 131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 132                 rt2x00_rf_write(rt2x00dev, word, value);
 133         }
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 139 {
 140         struct rt2x00_dev *rt2x00dev = eeprom->data;
 141         u32 reg;
 142
 143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 144
 145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 147         eeprom->reg_data_clock =
 148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 149         eeprom->reg_chip_select =
 150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 151 }
 152
 153 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 154 {
 155         struct rt2x00_dev *rt2x00dev = eeprom->data;
 156         u32 reg = 0;
 157
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 161                            !!eeprom->reg_data_clock);
 162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 163                            !!eeprom->reg_chip_select);
 164
 165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 166 }
 167
 168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 169 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 170         .owner  = THIS_MODULE,
 171         .csr    = {
 172                 .read           = rt2x00pci_register_read,
 173                 .write          = rt2x00pci_register_write,
 174                 .flags          = RT2X00DEBUGFS_OFFSET,
 175                 .word_base      = CSR_REG_BASE,
 176                 .word_size      = sizeof(u32),
 177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 178         },
 179         .eeprom = {
 180                 .read           = rt2x00_eeprom_read,
 181                 .write          = rt2x00_eeprom_write,
 182                 .word_base      = EEPROM_BASE,
 183                 .word_size      = sizeof(u16),
 184                 .word_count     = EEPROM_SIZE / sizeof(u16),
 185         },
 186         .bbp    = {
 187                 .read           = rt2500pci_bbp_read,
 188                 .write          = rt2500pci_bbp_write,
 189                 .word_base      = BBP_BASE,
 190                 .word_size      = sizeof(u8),
 191                 .word_count     = BBP_SIZE / sizeof(u8),
 192         },
 193         .rf     = {
 194                 .read           = rt2x00_rf_read,
 195                 .write          = rt2500pci_rf_write,
 196                 .word_base      = RF_BASE,
 197                 .word_size      = sizeof(u32),
 198                 .word_count     = RF_SIZE / sizeof(u32),
 199         },
 200 };
 201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 202
 203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 209 }
 210
 211 #ifdef CONFIG_RT2X00_LIB_LEDS
 212 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 213                                      enum led_brightness brightness)
 214 {
 215         struct rt2x00_led *led =
 216             container_of(led_cdev, struct rt2x00_led, led_dev);
 217         unsigned int enabled = brightness != LED_OFF;
 218         u32 reg;
 219
 220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 221
 222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 224         else if (led->type == LED_TYPE_ACTIVITY)
 225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 226
 227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 228 }
 229
 230 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 231                                unsigned long *delay_on,
 232                                unsigned long *delay_off)
 233 {
 234         struct rt2x00_led *led =
 235             container_of(led_cdev, struct rt2x00_led, led_dev);
 236         u32 reg;
 237
 238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 242
 243         return 0;
 244 }
 245
 246 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 247                                struct rt2x00_led *led,
 248                                enum led_type type)
 249 {
 250         led->rt2x00dev = rt2x00dev;
 251         led->type = type;
 252         led->led_dev.brightness_set = rt2500pci_brightness_set;
 253         led->led_dev.blink_set = rt2500pci_blink_set;
 254         led->flags = LED_INITIALIZED;
 255 }
 256 #endif /* CONFIG_RT2X00_LIB_LEDS */
 257
 258 /*
 259  * Configuration handlers.
 260  */
 261 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 262                                     const unsigned int filter_flags)
 263 {
 264         u32 reg;
 265
 266         /*
 267          * Start configuration steps.
 268          * Note that the version error will always be dropped
 269          * and broadcast frames will always be accepted since
 270          * there is no filter for it at this time.
 271          */
 272         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 273         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 274                            !(filter_flags & FIF_FCSFAIL));
 275         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 276                            !(filter_flags & FIF_PLCPFAIL));
 277         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 278                            !(filter_flags & FIF_CONTROL));
 279         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 280                            !(filter_flags & FIF_PROMISC_IN_BSS));
 281         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 282                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 283                            !rt2x00dev->intf_ap_count);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 286                            !(filter_flags & FIF_ALLMULTI));
 287         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 288         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 289 }
 290
 291 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 292                                   struct rt2x00_intf *intf,
 293                                   struct rt2x00intf_conf *conf,
 294                                   const unsigned int flags)
 295 {
 296         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 297         unsigned int bcn_preload;
 298         u32 reg;
 299
 300         if (flags & CONFIG_UPDATE_TYPE) {
 301                 /*
 302                  * Enable beacon config
 303                  */
 304                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 305                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 306                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 307                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 309
 310                 /*
 311                  * Enable synchronisation.
 312                  */
 313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 318         }
 319
 320         if (flags & CONFIG_UPDATE_MAC)
 321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 322                                               conf->mac, sizeof(conf->mac));
 323
 324         if (flags & CONFIG_UPDATE_BSSID)
 325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 326                                               conf->bssid, sizeof(conf->bssid));
 327 }
 328
 329 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 330                                  struct rt2x00lib_erp *erp)
 331 {
 332         int preamble_mask;
 333         u32 reg;
 334
 335         /*
 336          * When short preamble is enabled, we should set bit 0x08
 337          */
 338         preamble_mask = erp->short_preamble << 3;
 339
 340         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 341         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 342         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 343         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 344         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 345         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 346
 347         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 348         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 349         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 351         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 352
 353         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 354         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 355         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 357         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 358
 359         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 360         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 361         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 363         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 364
 365         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 366         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 367         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 369         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 370
 371         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 372
 373         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 374         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 375         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 378         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
 379         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
 380         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 381
 382         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 383         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 384         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 385         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 386
 387         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 388         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 389         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 390         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 391 }
 392
 393 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 394                                  struct antenna_setup *ant)
 395 {
 396         u32 reg;
 397         u8 r14;
 398         u8 r2;
 399
 400         /*
 401          * We should never come here because rt2x00lib is supposed
 402          * to catch this and send us the correct antenna explicitely.
 403          */
 404         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 405                ant->tx == ANTENNA_SW_DIVERSITY);
 406
 407         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 408         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 409         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 410
 411         /*
 412          * Configure the TX antenna.
 413          */
 414         switch (ant->tx) {
 415         case ANTENNA_A:
 416                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 417                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 418                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 419                 break;
 420         case ANTENNA_B:
 421         default:
 422                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 423                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 424                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 425                 break;
 426         }
 427
 428         /*
 429          * Configure the RX antenna.
 430          */
 431         switch (ant->rx) {
 432         case ANTENNA_A:
 433                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 434                 break;
 435         case ANTENNA_B:
 436         default:
 437                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 438                 break;
 439         }
 440
 441         /*
 442          * RT2525E and RT5222 need to flip TX I/Q
 443          */
 444         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 445                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 446                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 447                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 448
 449                 /*
 450                  * RT2525E does not need RX I/Q Flip.
 451                  */
 452                 if (rt2x00_rf(rt2x00dev, RF2525E))
 453                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 454         } else {
 455                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 456                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 457         }
 458
 459         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 460         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 461         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 462 }
 463
 464 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 465                                      struct rf_channel *rf, const int txpower)
 466 {
 467         u8 r70;
 468
 469         /*
 470          * Set TXpower.
 471          */
 472         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 473
 474         /*
 475          * Switch on tuning bits.
 476          * For RT2523 devices we do not need to update the R1 register.
 477          */
 478         if (!rt2x00_rf(rt2x00dev, RF2523))
 479                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 480         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 481
 482         /*
 483          * For RT2525 we should first set the channel to half band higher.
 484          */
 485         if (rt2x00_rf(rt2x00dev, RF2525)) {
 486                 static const u32 vals[] = {
 487                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 488                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 489                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 490                         0x00080d2e, 0x00080d3a
 491                 };
 492
 493                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 494                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 495                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 496                 if (rf->rf4)
 497                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 498         }
 499
 500         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 501         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 502         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 503         if (rf->rf4)
 504                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 505
 506         /*
 507          * Channel 14 requires the Japan filter bit to be set.
 508          */
 509         r70 = 0x46;
 510         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 511         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 512
 513         msleep(1);
 514
 515         /*
 516          * Switch off tuning bits.
 517          * For RT2523 devices we do not need to update the R1 register.
 518          */
 519         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 520                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 521                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 522         }
 523
 524         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 525         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 526
 527         /*
 528          * Clear false CRC during channel switch.
 529          */
 530         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 531 }
 532
 533 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 534                                      const int txpower)
 535 {
 536         u32 rf3;
 537
 538         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 539         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 540         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 541 }
 542
 543 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 544                                          struct rt2x00lib_conf *libconf)
 545 {
 546         u32 reg;
 547
 548         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 549         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 550                            libconf->conf->long_frame_max_tx_count);
 551         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 552                            libconf->conf->short_frame_max_tx_count);
 553         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 554 }
 555
 556 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 557                                 struct rt2x00lib_conf *libconf)
 558 {
 559         enum dev_state state =
 560             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 561                 STATE_SLEEP : STATE_AWAKE;
 562         u32 reg;
 563
 564         if (state == STATE_SLEEP) {
 565                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 566                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 567                                    (rt2x00dev->beacon_int - 20) * 16);
 568                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 569                                    libconf->conf->listen_interval - 1);
 570
 571                 /* We must first disable autowake before it can be enabled */
 572                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 573                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 574
 575                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 576                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 577         }
 578
 579         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 580 }
 581
 582 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 583                              struct rt2x00lib_conf *libconf,
 584                              const unsigned int flags)
 585 {
 586         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 587                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 588                                          libconf->conf->power_level);
 589         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 590             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 591                 rt2500pci_config_txpower(rt2x00dev,
 592                                          libconf->conf->power_level);
 593         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 594                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 595         if (flags & IEEE80211_CONF_CHANGE_PS)
 596                 rt2500pci_config_ps(rt2x00dev, libconf);
 597 }
 598
 599 /*
 600  * Link tuning
 601  */
 602 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 603                                  struct link_qual *qual)
 604 {
 605         u32 reg;
 606
 607         /*
 608          * Update FCS error count from register.
 609          */
 610         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 611         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 612
 613         /*
 614          * Update False CCA count from register.
 615          */
 616         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 617         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 618 }
 619
 620 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 621                                      struct link_qual *qual, u8 vgc_level)
 622 {
 623         if (qual->vgc_level_reg != vgc_level) {
 624                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 625                 qual->vgc_level_reg = vgc_level;
 626         }
 627 }
 628
 629 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 630                                   struct link_qual *qual)
 631 {
 632         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 633 }
 634
 635 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 636                                  struct link_qual *qual, const u32 count)
 637 {
 638         /*
 639          * To prevent collisions with MAC ASIC on chipsets
 640          * up to version C the link tuning should halt after 20
 641          * seconds while being associated.
 642          */
 643         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 644             rt2x00dev->intf_associated && count > 20)
 645                 return;
 646
 647         /*
 648          * Chipset versions C and lower should directly continue
 649          * to the dynamic CCA tuning. Chipset version D and higher
 650          * should go straight to dynamic CCA tuning when they
 651          * are not associated.
 652          */
 653         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 654             !rt2x00dev->intf_associated)
 655                 goto dynamic_cca_tune;
 656
 657         /*
 658          * A too low RSSI will cause too much false CCA which will
 659          * then corrupt the R17 tuning. To remidy this the tuning should
 660          * be stopped (While making sure the R17 value will not exceed limits)
 661          */
 662         if (qual->rssi < -80 && count > 20) {
 663                 if (qual->vgc_level_reg >= 0x41)
 664                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 665                 return;
 666         }
 667
 668         /*
 669          * Special big-R17 for short distance
 670          */
 671         if (qual->rssi >= -58) {
 672                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 673                 return;
 674         }
 675
 676         /*
 677          * Special mid-R17 for middle distance
 678          */
 679         if (qual->rssi >= -74) {
 680                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 681                 return;
 682         }
 683
 684         /*
 685          * Leave short or middle distance condition, restore r17
 686          * to the dynamic tuning range.
 687          */
 688         if (qual->vgc_level_reg >= 0x41) {
 689                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 690                 return;
 691         }
 692
 693 dynamic_cca_tune:
 694
 695         /*
 696          * R17 is inside the dynamic tuning range,
 697          * start tuning the link based on the false cca counter.
 698          */
 699         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
 700                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 701                 qual->vgc_level = qual->vgc_level_reg;
 702         } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
 703                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 704                 qual->vgc_level = qual->vgc_level_reg;
 705         }
 706 }
 707
 708 /*
 709  * Initialization functions.
 710  */
 711 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 712 {
 713         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 714         u32 word;
 715
 716         if (entry->queue->qid == QID_RX) {
 717                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 718
 719                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 720         } else {
 721                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 722
 723                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 724                         rt2x00_get_field32(word, TXD_W0_VALID));
 725         }
 726 }
 727
 728 static void rt2500pci_clear_entry(struct queue_entry *entry)
 729 {
 730         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 731         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 732         u32 word;
 733
 734         if (entry->queue->qid == QID_RX) {
 735                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 736                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 737                 rt2x00_desc_write(entry_priv->desc, 1, word);
 738
 739                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 740                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 741                 rt2x00_desc_write(entry_priv->desc, 0, word);
 742         } else {
 743                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 744                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 745                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 746                 rt2x00_desc_write(entry_priv->desc, 0, word);
 747         }
 748 }
 749
 750 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 751 {
 752         struct queue_entry_priv_pci *entry_priv;
 753         u32 reg;
 754
 755         /*
 756          * Initialize registers.
 757          */
 758         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 759         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 760         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 761         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 762         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 763         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 764
 765         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 766         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 767         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 768                            entry_priv->desc_dma);
 769         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 770
 771         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 772         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 773         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 774                            entry_priv->desc_dma);
 775         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 776
 777         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 778         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 779         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 780                            entry_priv->desc_dma);
 781         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 782
 783         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 784         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 785         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 786                            entry_priv->desc_dma);
 787         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 788
 789         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 790         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 791         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 792         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 793
 794         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 795         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 796         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 797                            entry_priv->desc_dma);
 798         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 799
 800         return 0;
 801 }
 802
 803 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 804 {
 805         u32 reg;
 806
 807         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 808         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 809         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 810         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 811
 812         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 813         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 814         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 815         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 816         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 817
 818         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 819         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 820                            rt2x00dev->rx->data_size / 128);
 821         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 822
 823         /*
 824          * Always use CWmin and CWmax set in descriptor.
 825          */
 826         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 827         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 828         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 829
 830         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 831         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 832         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 833         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 834         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 835         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 836         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 837         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 838         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 839         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 840
 841         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 842
 843         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 844         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 845         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 846         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 847         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 848         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 849         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 850         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 851         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 852         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 853
 854         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 855         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 856         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 857         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 858         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 859         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 860
 861         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 862         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 863         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 864         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 865         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 866         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 867
 868         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 869         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 870         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 871         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 872         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 873         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 874
 875         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 876         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 877         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 878         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 879         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 880         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 881         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 882         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 883         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 884         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 885
 886         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 887         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 888         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 889         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 890         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 891         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 892         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 893         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 894         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 895
 896         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 897
 898         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 899         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 900
 901         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 902                 return -EBUSY;
 903
 904         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 905         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 906
 907         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 908         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 909         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 910
 911         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 912         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 913         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 914         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 915         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 916         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 917         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 918         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 919
 920         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 921
 922         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 923
 924         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 925         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 926         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 927         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 928         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 929
 930         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 931         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 932         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 933         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 934
 935         /*
 936          * We must clear the FCS and FIFO error count.
 937          * These registers are cleared on read,
 938          * so we may pass a useless variable to store the value.
 939          */
 940         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 941         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 942
 943         return 0;
 944 }
 945
 946 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 947 {
 948         unsigned int i;
 949         u8 value;
 950
 951         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 952                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 953                 if ((value != 0xff) && (value != 0x00))
 954                         return 0;
 955                 udelay(REGISTER_BUSY_DELAY);
 956         }
 957
 958         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 959         return -EACCES;
 960 }
 961
 962 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 963 {
 964         unsigned int i;
 965         u16 eeprom;
 966         u8 reg_id;
 967         u8 value;
 968
 969         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 970                 return -EACCES;
 971
 972         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 973         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 974         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 975         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 976         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 977         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 978         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 979         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 980         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 981         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 982         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 983         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 984         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 985         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 986         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 987         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 988         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 989         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 990         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 991         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 992         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 993         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 994         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 995         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 996         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 997         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 998         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 999         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1000         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1001         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1002
1003         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1004                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1005
1006                 if (eeprom != 0xffff && eeprom != 0x0000) {
1007                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1008                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1009                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1010                 }
1011         }
1012
1013         return 0;
1014 }
1015
1016 /*
1017  * Device state switch handlers.
1018  */
1019 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1020                                 enum dev_state state)
1021 {
1022         u32 reg;
1023
1024         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1025         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1026                            (state == STATE_RADIO_RX_OFF) ||
1027                            (state == STATE_RADIO_RX_OFF_LINK));
1028         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1029 }
1030
1031 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1032                                  enum dev_state state)
1033 {
1034         int mask = (state == STATE_RADIO_IRQ_OFF);
1035         u32 reg;
1036
1037         /*
1038          * When interrupts are being enabled, the interrupt registers
1039          * should clear the register to assure a clean state.
1040          */
1041         if (state == STATE_RADIO_IRQ_ON) {
1042                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1043                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1044         }
1045
1046         /*
1047          * Only toggle the interrupts bits we are going to use.
1048          * Non-checked interrupt bits are disabled by default.
1049          */
1050         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1051         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1052         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1053         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1054         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1055         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1056         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1057 }
1058
1059 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1060 {
1061         /*
1062          * Initialize all registers.
1063          */
1064         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1065                      rt2500pci_init_registers(rt2x00dev) ||
1066                      rt2500pci_init_bbp(rt2x00dev)))
1067                 return -EIO;
1068
1069         return 0;
1070 }
1071
1072 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1073 {
1074         /*
1075          * Disable power
1076          */
1077         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1078 }
1079
1080 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1081                                enum dev_state state)
1082 {
1083         u32 reg;
1084         unsigned int i;
1085         char put_to_sleep;
1086         char bbp_state;
1087         char rf_state;
1088
1089         put_to_sleep = (state != STATE_AWAKE);
1090
1091         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1092         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1093         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1094         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1095         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1096         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1097
1098         /*
1099          * Device is not guaranteed to be in the requested state yet.
1100          * We must wait until the register indicates that the
1101          * device has entered the correct state.
1102          */
1103         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1104                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1105                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1106                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1107                 if (bbp_state == state && rf_state == state)
1108                         return 0;
1109                 msleep(10);
1110         }
1111
1112         return -EBUSY;
1113 }
1114
1115 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1116                                       enum dev_state state)
1117 {
1118         int retval = 0;
1119
1120         switch (state) {
1121         case STATE_RADIO_ON:
1122                 retval = rt2500pci_enable_radio(rt2x00dev);
1123                 break;
1124         case STATE_RADIO_OFF:
1125                 rt2500pci_disable_radio(rt2x00dev);
1126                 break;
1127         case STATE_RADIO_RX_ON:
1128         case STATE_RADIO_RX_ON_LINK:
1129         case STATE_RADIO_RX_OFF:
1130         case STATE_RADIO_RX_OFF_LINK:
1131                 rt2500pci_toggle_rx(rt2x00dev, state);
1132                 break;
1133         case STATE_RADIO_IRQ_ON:
1134         case STATE_RADIO_IRQ_OFF:
1135                 rt2500pci_toggle_irq(rt2x00dev, state);
1136                 break;
1137         case STATE_DEEP_SLEEP:
1138         case STATE_SLEEP:
1139         case STATE_STANDBY:
1140         case STATE_AWAKE:
1141                 retval = rt2500pci_set_state(rt2x00dev, state);
1142                 break;
1143         default:
1144                 retval = -ENOTSUPP;
1145                 break;
1146         }
1147
1148         if (unlikely(retval))
1149                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1150                       state, retval);
1151
1152         return retval;
1153 }
1154
1155 /*
1156  * TX descriptor initialization
1157  */
1158 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1159                                     struct sk_buff *skb,
1160                                     struct txentry_desc *txdesc)
1161 {
1162         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1163         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1164         __le32 *txd = skbdesc->desc;
1165         u32 word;
1166
1167         /*
1168          * Start writing the descriptor words.
1169          */
1170         rt2x00_desc_read(entry_priv->desc, 1, &word);
1171         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1172         rt2x00_desc_write(entry_priv->desc, 1, word);
1173
1174         rt2x00_desc_read(txd, 2, &word);
1175         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1176         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1177         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1178         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1179         rt2x00_desc_write(txd, 2, word);
1180
1181         rt2x00_desc_read(txd, 3, &word);
1182         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1183         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1184         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1185         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1186         rt2x00_desc_write(txd, 3, word);
1187
1188         rt2x00_desc_read(txd, 10, &word);
1189         rt2x00_set_field32(&word, TXD_W10_RTS,
1190                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1191         rt2x00_desc_write(txd, 10, word);
1192
1193         rt2x00_desc_read(txd, 0, &word);
1194         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1195         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1196         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1197                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1198         rt2x00_set_field32(&word, TXD_W0_ACK,
1199                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1200         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1201                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1202         rt2x00_set_field32(&word, TXD_W0_OFDM,
1203                            (txdesc->rate_mode == RATE_MODE_OFDM));
1204         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1205         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1206         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1207                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1208         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1209         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1210         rt2x00_desc_write(txd, 0, word);
1211 }
1212
1213 /*
1214  * TX data initialization
1215  */
1216 static void rt2500pci_write_beacon(struct queue_entry *entry)
1217 {
1218         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1219         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1220         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1221         u32 word;
1222         u32 reg;
1223
1224         /*
1225          * Disable beaconing while we are reloading the beacon data,
1226          * otherwise we might be sending out invalid data.
1227          */
1228         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1229         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1230         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1231
1232         /*
1233          * Replace rt2x00lib allocated descriptor with the
1234          * pointer to the _real_ hardware descriptor.
1235          * After that, map the beacon to DMA and update the
1236          * descriptor.
1237          */
1238         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1239         skbdesc->desc = entry_priv->desc;
1240
1241         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1242
1243         rt2x00_desc_read(entry_priv->desc, 1, &word);
1244         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1245         rt2x00_desc_write(entry_priv->desc, 1, word);
1246 }
1247
1248 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1249                                     const enum data_queue_qid queue)
1250 {
1251         u32 reg;
1252
1253         if (queue == QID_BEACON) {
1254                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1255                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1256                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1257                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1258                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1259                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1260                 }
1261                 return;
1262         }
1263
1264         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1265         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1266         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1267         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1268         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1269 }
1270
1271 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1272                                     const enum data_queue_qid qid)
1273 {
1274         u32 reg;
1275
1276         if (qid == QID_BEACON) {
1277                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1278         } else {
1279                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1280                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1281                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1282         }
1283 }
1284
1285 /*
1286  * RX control handlers
1287  */
1288 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1289                                   struct rxdone_entry_desc *rxdesc)
1290 {
1291         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1292         u32 word0;
1293         u32 word2;
1294
1295         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1296         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1297
1298         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1299                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1300         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1301                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1302
1303         /*
1304          * Obtain the status about this packet.
1305          * When frame was received with an OFDM bitrate,
1306          * the signal is the PLCP value. If it was received with
1307          * a CCK bitrate the signal is the rate in 100kbit/s.
1308          */
1309         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1310         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1311             entry->queue->rt2x00dev->rssi_offset;
1312         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1313
1314         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1315                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1316         else
1317                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1318         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1319                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1320 }
1321
1322 /*
1323  * Interrupt functions.
1324  */
1325 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1326                              const enum data_queue_qid queue_idx)
1327 {
1328         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1329         struct queue_entry_priv_pci *entry_priv;
1330         struct queue_entry *entry;
1331         struct txdone_entry_desc txdesc;
1332         u32 word;
1333
1334         while (!rt2x00queue_empty(queue)) {
1335                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1336                 entry_priv = entry->priv_data;
1337                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1338
1339                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1340                     !rt2x00_get_field32(word, TXD_W0_VALID))
1341                         break;
1342
1343                 /*
1344                  * Obtain the status about this packet.
1345                  */
1346                 txdesc.flags = 0;
1347                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1348                 case 0: /* Success */
1349                 case 1: /* Success with retry */
1350                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1351                         break;
1352                 case 2: /* Failure, excessive retries */
1353                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1354                         /* Don't break, this is a failed frame! */
1355                 default: /* Failure */
1356                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1357                 }
1358                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1359
1360                 rt2x00lib_txdone(entry, &txdesc);
1361         }
1362 }
1363
1364 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1365 {
1366         struct rt2x00_dev *rt2x00dev = dev_instance;
1367         u32 reg;
1368
1369         /*
1370          * Get the interrupt sources & saved to local variable.
1371          * Write register value back to clear pending interrupts.
1372          */
1373         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1374         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1375
1376         if (!reg)
1377                 return IRQ_NONE;
1378
1379         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1380                 return IRQ_HANDLED;
1381
1382         /*
1383          * Handle interrupts, walk through all bits
1384          * and run the tasks, the bits are checked in order of
1385          * priority.
1386          */
1387
1388         /*
1389          * 1 - Beacon timer expired interrupt.
1390          */
1391         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1392                 rt2x00lib_beacondone(rt2x00dev);
1393
1394         /*
1395          * 2 - Rx ring done interrupt.
1396          */
1397         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1398                 rt2x00pci_rxdone(rt2x00dev);
1399
1400         /*
1401          * 3 - Atim ring transmit done interrupt.
1402          */
1403         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1404                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1405
1406         /*
1407          * 4 - Priority ring transmit done interrupt.
1408          */
1409         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1410                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1411
1412         /*
1413          * 5 - Tx ring transmit done interrupt.
1414          */
1415         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1416                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1417
1418         return IRQ_HANDLED;
1419 }
1420
1421 /*
1422  * Device probe functions.
1423  */
1424 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1425 {
1426         struct eeprom_93cx6 eeprom;
1427         u32 reg;
1428         u16 word;
1429         u8 *mac;
1430
1431         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1432
1433         eeprom.data = rt2x00dev;
1434         eeprom.register_read = rt2500pci_eepromregister_read;
1435         eeprom.register_write = rt2500pci_eepromregister_write;
1436         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1437             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1438         eeprom.reg_data_in = 0;
1439         eeprom.reg_data_out = 0;
1440         eeprom.reg_data_clock = 0;
1441         eeprom.reg_chip_select = 0;
1442
1443         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1444                                EEPROM_SIZE / sizeof(u16));
1445
1446         /*
1447          * Start validation of the data that has been read.
1448          */
1449         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1450         if (!is_valid_ether_addr(mac)) {
1451                 random_ether_addr(mac);
1452                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1453         }
1454
1455         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1456         if (word == 0xffff) {
1457                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1458                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1459                                    ANTENNA_SW_DIVERSITY);
1460                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1461                                    ANTENNA_SW_DIVERSITY);
1462                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1463                                    LED_MODE_DEFAULT);
1464                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1465                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1466                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1467                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1468                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1469         }
1470
1471         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1472         if (word == 0xffff) {
1473                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1474                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1475                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1476                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1477                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1478         }
1479
1480         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1481         if (word == 0xffff) {
1482                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1483                                    DEFAULT_RSSI_OFFSET);
1484                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1485                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1486         }
1487
1488         return 0;
1489 }
1490
1491 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1492 {
1493         u32 reg;
1494         u16 value;
1495         u16 eeprom;
1496
1497         /*
1498          * Read EEPROM word for configuration.
1499          */
1500         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1501
1502         /*
1503          * Identify RF chipset.
1504          */
1505         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1506         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1507         rt2x00_set_chip(rt2x00dev, RT2560, value,
1508                         rt2x00_get_field32(reg, CSR0_REVISION));
1509
1510         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1511             !rt2x00_rf(rt2x00dev, RF2523) &&
1512             !rt2x00_rf(rt2x00dev, RF2524) &&
1513             !rt2x00_rf(rt2x00dev, RF2525) &&
1514             !rt2x00_rf(rt2x00dev, RF2525E) &&
1515             !rt2x00_rf(rt2x00dev, RF5222)) {
1516                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1517                 return -ENODEV;
1518         }
1519
1520         /*
1521          * Identify default antenna configuration.
1522          */
1523         rt2x00dev->default_ant.tx =
1524             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1525         rt2x00dev->default_ant.rx =
1526             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1527
1528         /*
1529          * Store led mode, for correct led behaviour.
1530          */
1531 #ifdef CONFIG_RT2X00_LIB_LEDS
1532         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1533
1534         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1535         if (value == LED_MODE_TXRX_ACTIVITY ||
1536             value == LED_MODE_DEFAULT ||
1537             value == LED_MODE_ASUS)
1538                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1539                                    LED_TYPE_ACTIVITY);
1540 #endif /* CONFIG_RT2X00_LIB_LEDS */
1541
1542         /*
1543          * Detect if this device has an hardware controlled radio.
1544          */
1545         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1546                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1547
1548         /*
1549          * Check if the BBP tuning should be enabled.
1550          */
1551         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1552
1553         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1554                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1555
1556         /*
1557          * Read the RSSI <-> dBm offset information.
1558          */
1559         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1560         rt2x00dev->rssi_offset =
1561             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1562
1563         return 0;
1564 }
1565
1566 /*
1567  * RF value list for RF2522
1568  * Supports: 2.4 GHz
1569  */
1570 static const struct rf_channel rf_vals_bg_2522[] = {
1571         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1572         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1573         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1574         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1575         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1576         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1577         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1578         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1579         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1580         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1581         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1582         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1583         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1584         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1585 };
1586
1587 /*
1588  * RF value list for RF2523
1589  * Supports: 2.4 GHz
1590  */
1591 static const struct rf_channel rf_vals_bg_2523[] = {
1592         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1593         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1594         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1595         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1596         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1597         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1598         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1599         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1600         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1601         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1602         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1603         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1604         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1605         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1606 };
1607
1608 /*
1609  * RF value list for RF2524
1610  * Supports: 2.4 GHz
1611  */
1612 static const struct rf_channel rf_vals_bg_2524[] = {
1613         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1614         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1615         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1616         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1617         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1618         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1619         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1620         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1621         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1622         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1623         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1624         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1625         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1626         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1627 };
1628
1629 /*
1630  * RF value list for RF2525
1631  * Supports: 2.4 GHz
1632  */
1633 static const struct rf_channel rf_vals_bg_2525[] = {
1634         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1635         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1636         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1637         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1638         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1639         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1640         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1641         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1642         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1643         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1644         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1645         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1646         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1647         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1648 };
1649
1650 /*
1651  * RF value list for RF2525e
1652  * Supports: 2.4 GHz
1653  */
1654 static const struct rf_channel rf_vals_bg_2525e[] = {
1655         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1656         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1657         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1658         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1659         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1660         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1661         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1662         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1663         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1664         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1665         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1666         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1667         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1668         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1669 };
1670
1671 /*
1672  * RF value list for RF5222
1673  * Supports: 2.4 GHz & 5.2 GHz
1674  */
1675 static const struct rf_channel rf_vals_5222[] = {
1676         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1677         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1678         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1679         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1680         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1681         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1682         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1683         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1684         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1685         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1686         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1687         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1688         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1689         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1690
1691         /* 802.11 UNI / HyperLan 2 */
1692         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1693         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1694         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1695         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1696         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1697         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1698         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1699         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1700
1701         /* 802.11 HyperLan 2 */
1702         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1703         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1704         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1705         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1706         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1707         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1708         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1709         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1710         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1711         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1712
1713         /* 802.11 UNII */
1714         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1715         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1716         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1717         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1718         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1719 };
1720
1721 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1722 {
1723         struct hw_mode_spec *spec = &rt2x00dev->spec;
1724         struct channel_info *info;
1725         char *tx_power;
1726         unsigned int i;
1727
1728         /*
1729          * Initialize all hw fields.
1730          */
1731         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1732                                IEEE80211_HW_SIGNAL_DBM |
1733                                IEEE80211_HW_SUPPORTS_PS |
1734                                IEEE80211_HW_PS_NULLFUNC_STACK;
1735
1736         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1737         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1738                                 rt2x00_eeprom_addr(rt2x00dev,
1739                                                    EEPROM_MAC_ADDR_0));
1740
1741         /*
1742          * Initialize hw_mode information.
1743          */
1744         spec->supported_bands = SUPPORT_BAND_2GHZ;
1745         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1746
1747         if (rt2x00_rf(rt2x00dev, RF2522)) {
1748                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1749                 spec->channels = rf_vals_bg_2522;
1750         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1751                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1752                 spec->channels = rf_vals_bg_2523;
1753         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1754                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1755                 spec->channels = rf_vals_bg_2524;
1756         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1757                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1758                 spec->channels = rf_vals_bg_2525;
1759         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1760                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1761                 spec->channels = rf_vals_bg_2525e;
1762         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1763                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1764                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1765                 spec->channels = rf_vals_5222;
1766         }
1767
1768         /*
1769          * Create channel information array
1770          */
1771         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1772         if (!info)
1773                 return -ENOMEM;
1774
1775         spec->channels_info = info;
1776
1777         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1778         for (i = 0; i < 14; i++)
1779                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1780
1781         if (spec->num_channels > 14) {
1782                 for (i = 14; i < spec->num_channels; i++)
1783                         info[i].tx_power1 = DEFAULT_TXPOWER;
1784         }
1785
1786         return 0;
1787 }
1788
1789 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1790 {
1791         int retval;
1792
1793         /*
1794          * Allocate eeprom data.
1795          */
1796         retval = rt2500pci_validate_eeprom(rt2x00dev);
1797         if (retval)
1798                 return retval;
1799
1800         retval = rt2500pci_init_eeprom(rt2x00dev);
1801         if (retval)
1802                 return retval;
1803
1804         /*
1805          * Initialize hw specifications.
1806          */
1807         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1808         if (retval)
1809                 return retval;
1810
1811         /*
1812          * This device requires the atim queue and DMA-mapped skbs.
1813          */
1814         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1815         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1816
1817         /*
1818          * Set the rssi offset.
1819          */
1820         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1821
1822         return 0;
1823 }
1824
1825 /*
1826  * IEEE80211 stack callback functions.
1827  */
1828 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1829 {
1830         struct rt2x00_dev *rt2x00dev = hw->priv;
1831         u64 tsf;
1832         u32 reg;
1833
1834         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1835         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1836         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1837         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1838
1839         return tsf;
1840 }
1841
1842 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1843 {
1844         struct rt2x00_dev *rt2x00dev = hw->priv;
1845         u32 reg;
1846
1847         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1848         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1849 }
1850
1851 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1852         .tx                     = rt2x00mac_tx,
1853         .start                  = rt2x00mac_start,
1854         .stop                   = rt2x00mac_stop,
1855         .add_interface          = rt2x00mac_add_interface,
1856         .remove_interface       = rt2x00mac_remove_interface,
1857         .config                 = rt2x00mac_config,
1858         .configure_filter       = rt2x00mac_configure_filter,
1859         .set_tim                = rt2x00mac_set_tim,
1860         .get_stats              = rt2x00mac_get_stats,
1861         .bss_info_changed       = rt2x00mac_bss_info_changed,
1862         .conf_tx                = rt2x00mac_conf_tx,
1863         .get_tsf                = rt2500pci_get_tsf,
1864         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1865         .rfkill_poll            = rt2x00mac_rfkill_poll,
1866 };
1867
1868 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1869         .irq_handler            = rt2500pci_interrupt,
1870         .probe_hw               = rt2500pci_probe_hw,
1871         .initialize             = rt2x00pci_initialize,
1872         .uninitialize           = rt2x00pci_uninitialize,
1873         .get_entry_state        = rt2500pci_get_entry_state,
1874         .clear_entry            = rt2500pci_clear_entry,
1875         .set_device_state       = rt2500pci_set_device_state,
1876         .rfkill_poll            = rt2500pci_rfkill_poll,
1877         .link_stats             = rt2500pci_link_stats,
1878         .reset_tuner            = rt2500pci_reset_tuner,
1879         .link_tuner             = rt2500pci_link_tuner,
1880         .write_tx_desc          = rt2500pci_write_tx_desc,
1881         .write_tx_data          = rt2x00pci_write_tx_data,
1882         .write_beacon           = rt2500pci_write_beacon,
1883         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1884         .kill_tx_queue          = rt2500pci_kill_tx_queue,
1885         .fill_rxdone            = rt2500pci_fill_rxdone,
1886         .config_filter          = rt2500pci_config_filter,
1887         .config_intf            = rt2500pci_config_intf,
1888         .config_erp             = rt2500pci_config_erp,
1889         .config_ant             = rt2500pci_config_ant,
1890         .config                 = rt2500pci_config,
1891 };
1892
1893 static const struct data_queue_desc rt2500pci_queue_rx = {
1894         .entry_num              = RX_ENTRIES,
1895         .data_size              = DATA_FRAME_SIZE,
1896         .desc_size              = RXD_DESC_SIZE,
1897         .priv_size              = sizeof(struct queue_entry_priv_pci),
1898 };
1899
1900 static const struct data_queue_desc rt2500pci_queue_tx = {
1901         .entry_num              = TX_ENTRIES,
1902         .data_size              = DATA_FRAME_SIZE,
1903         .desc_size              = TXD_DESC_SIZE,
1904         .priv_size              = sizeof(struct queue_entry_priv_pci),
1905 };
1906
1907 static const struct data_queue_desc rt2500pci_queue_bcn = {
1908         .entry_num              = BEACON_ENTRIES,
1909         .data_size              = MGMT_FRAME_SIZE,
1910         .desc_size              = TXD_DESC_SIZE,
1911         .priv_size              = sizeof(struct queue_entry_priv_pci),
1912 };
1913
1914 static const struct data_queue_desc rt2500pci_queue_atim = {
1915         .entry_num              = ATIM_ENTRIES,
1916         .data_size              = DATA_FRAME_SIZE,
1917         .desc_size              = TXD_DESC_SIZE,
1918         .priv_size              = sizeof(struct queue_entry_priv_pci),
1919 };
1920
1921 static const struct rt2x00_ops rt2500pci_ops = {
1922         .name                   = KBUILD_MODNAME,
1923         .max_sta_intf           = 1,
1924         .max_ap_intf            = 1,
1925         .eeprom_size            = EEPROM_SIZE,
1926         .rf_size                = RF_SIZE,
1927         .tx_queues              = NUM_TX_QUEUES,
1928         .extra_tx_headroom      = 0,
1929         .rx                     = &rt2500pci_queue_rx,
1930         .tx                     = &rt2500pci_queue_tx,
1931         .bcn                    = &rt2500pci_queue_bcn,
1932         .atim                   = &rt2500pci_queue_atim,
1933         .lib                    = &rt2500pci_rt2x00_ops,
1934         .hw                     = &rt2500pci_mac80211_ops,
1935 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1936         .debugfs                = &rt2500pci_rt2x00debug,
1937 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1938 };
1939
1940 /*
1941  * RT2500pci module information.
1942  */
1943 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
1944         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1945         { 0, }
1946 };
1947
1948 MODULE_AUTHOR(DRV_PROJECT);
1949 MODULE_VERSION(DRV_VERSION);
1950 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1951 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1952 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1953 MODULE_LICENSE("GPL");
1954
1955 static struct pci_driver rt2500pci_driver = {
1956         .name           = KBUILD_MODNAME,
1957         .id_table       = rt2500pci_device_table,
1958         .probe          = rt2x00pci_probe,
1959         .remove         = __devexit_p(rt2x00pci_remove),
1960         .suspend        = rt2x00pci_suspend,
1961         .resume         = rt2x00pci_resume,
1962 };
1963
1964 static int __init rt2500pci_init(void)
1965 {
1966         return pci_register_driver(&rt2500pci_driver);
1967 }
1968
1969 static void __exit rt2500pci_exit(void)
1970 {
1971         pci_unregister_driver(&rt2500pci_driver);
1972 }
1973
1974 module_init(rt2500pci_init);
1975 module_exit(rt2500pci_exit);