drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         unsigned int activity =
 254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
 255         u32 reg;
 256
 257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 258
 259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
 260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
 262         }
 263
 264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 265 }
 266 #else
 267 #define rt2400pci_led_brightness        NULL
 268 #endif /* CONFIG_RT2400PCI_LEDS */
 269
 270 /*
 271  * Configuration handlers.
 272  */
 273 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 274                                     const unsigned int filter_flags)
 275 {
 276         u32 reg;
 277
 278         /*
 279          * Start configuration steps.
 280          * Note that the version error will always be dropped
 281          * since there is no filter for it at this time.
 282          */
 283         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 284         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 285                            !(filter_flags & FIF_FCSFAIL));
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 287                            !(filter_flags & FIF_PLCPFAIL));
 288         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 289                            !(filter_flags & FIF_CONTROL));
 290         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 291                            !(filter_flags & FIF_PROMISC_IN_BSS));
 292         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 293                            !(filter_flags & FIF_PROMISC_IN_BSS));
 294         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 295         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 296 }
 297
 298 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 299                                   struct rt2x00_intf *intf,
 300                                   struct rt2x00intf_conf *conf,
 301                                   const unsigned int flags)
 302 {
 303         unsigned int bcn_preload;
 304         u32 reg;
 305
 306         if (flags & CONFIG_UPDATE_TYPE) {
 307                 /*
 308                  * Enable beacon config
 309                  */
 310                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 311                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 312                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 313                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 314
 315                 /*
 316                  * Enable synchronisation.
 317                  */
 318                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 319                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 320                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 321                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 322                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 323         }
 324
 325         if (flags & CONFIG_UPDATE_MAC)
 326                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 327                                               conf->mac, sizeof(conf->mac));
 328
 329         if (flags & CONFIG_UPDATE_BSSID)
 330                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 331                                               conf->bssid, sizeof(conf->bssid));
 332 }
 333
 334 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 335                                  struct rt2x00lib_erp *erp)
 336 {
 337         int preamble_mask;
 338         u32 reg;
 339
 340         /*
 341          * When short preamble is enabled, we should set bit 0x08
 342          */
 343         preamble_mask = erp->short_preamble << 3;
 344
 345         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 346         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 347                            erp->ack_timeout);
 348         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 349                            erp->ack_consume_time);
 350         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 351
 352         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 353         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 354         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 355         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 356         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 357
 358         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 359         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 360         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 361         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 362         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 363
 364         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 365         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 366         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 367         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 368         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 369
 370         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 371         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 372         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 373         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 374         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 375 }
 376
 377 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 378                                      const int basic_rate_mask)
 379 {
 380         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 381 }
 382
 383 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 384                                      struct rf_channel *rf)
 385 {
 386         /*
 387          * Switch on tuning bits.
 388          */
 389         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 390         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 391
 392         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 393         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 394         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 395
 396         /*
 397          * RF2420 chipset don't need any additional actions.
 398          */
 399         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 400                 return;
 401
 402         /*
 403          * For the RT2421 chipsets we need to write an invalid
 404          * reference clock rate to activate auto_tune.
 405          * After that we set the value back to the correct channel.
 406          */
 407         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 408         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 409         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 410
 411         msleep(1);
 412
 413         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 414         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 415         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 416
 417         msleep(1);
 418
 419         /*
 420          * Switch off tuning bits.
 421          */
 422         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 423         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 424
 425         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 426         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 427
 428         /*
 429          * Clear false CRC during channel switch.
 430          */
 431         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 432 }
 433
 434 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 435 {
 436         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 437 }
 438
 439 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 440                                      struct antenna_setup *ant)
 441 {
 442         u8 r1;
 443         u8 r4;
 444
 445         /*
 446          * We should never come here because rt2x00lib is supposed
 447          * to catch this and send us the correct antenna explicitely.
 448          */
 449         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 450                ant->tx == ANTENNA_SW_DIVERSITY);
 451
 452         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 453         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 454
 455         /*
 456          * Configure the TX antenna.
 457          */
 458         switch (ant->tx) {
 459         case ANTENNA_HW_DIVERSITY:
 460                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 461                 break;
 462         case ANTENNA_A:
 463                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 464                 break;
 465         case ANTENNA_B:
 466         default:
 467                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 468                 break;
 469         }
 470
 471         /*
 472          * Configure the RX antenna.
 473          */
 474         switch (ant->rx) {
 475         case ANTENNA_HW_DIVERSITY:
 476                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 477                 break;
 478         case ANTENNA_A:
 479                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 480                 break;
 481         case ANTENNA_B:
 482         default:
 483                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 484                 break;
 485         }
 486
 487         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 488         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 489 }
 490
 491 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 492                                       struct rt2x00lib_conf *libconf)
 493 {
 494         u32 reg;
 495
 496         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 497         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 498         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 499
 500         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 501         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 502         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 503         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 504
 505         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 506         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 507         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 508         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 509
 510         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 511         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 512         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 513         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 514
 515         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 516         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 517                            libconf->conf->beacon_int * 16);
 518         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 519                            libconf->conf->beacon_int * 16);
 520         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 521 }
 522
 523 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 524                              struct rt2x00lib_conf *libconf,
 525                              const unsigned int flags)
 526 {
 527         if (flags & CONFIG_UPDATE_PHYMODE)
 528                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 529         if (flags & CONFIG_UPDATE_CHANNEL)
 530                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 531         if (flags & CONFIG_UPDATE_TXPOWER)
 532                 rt2400pci_config_txpower(rt2x00dev,
 533                                          libconf->conf->power_level);
 534         if (flags & CONFIG_UPDATE_ANTENNA)
 535                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 536         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 537                 rt2400pci_config_duration(rt2x00dev, libconf);
 538 }
 539
 540 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 541                                 const int cw_min, const int cw_max)
 542 {
 543         u32 reg;
 544
 545         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 546         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 547         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 548         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 549 }
 550
 551 /*
 552  * Link tuning
 553  */
 554 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 555                                  struct link_qual *qual)
 556 {
 557         u32 reg;
 558         u8 bbp;
 559
 560         /*
 561          * Update FCS error count from register.
 562          */
 563         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 564         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 565
 566         /*
 567          * Update False CCA count from register.
 568          */
 569         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 570         qual->false_cca = bbp;
 571 }
 572
 573 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 574 {
 575         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 576         rt2x00dev->link.vgc_level = 0x08;
 577 }
 578
 579 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 580 {
 581         u8 reg;
 582
 583         /*
 584          * The link tuner should not run longer then 60 seconds,
 585          * and should run once every 2 seconds.
 586          */
 587         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 588                 return;
 589
 590         /*
 591          * Base r13 link tuning on the false cca count.
 592          */
 593         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 594
 595         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 596                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 597                 rt2x00dev->link.vgc_level = reg;
 598         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 599                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 600                 rt2x00dev->link.vgc_level = reg;
 601         }
 602 }
 603
 604 /*
 605  * Initialization functions.
 606  */
 607 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 608                                    struct queue_entry *entry)
 609 {
 610         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 611         u32 word;
 612
 613         rt2x00_desc_read(priv_rx->desc, 2, &word);
 614         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 615                            entry->queue->data_size);
 616         rt2x00_desc_write(priv_rx->desc, 2, word);
 617
 618         rt2x00_desc_read(priv_rx->desc, 1, &word);
 619         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 620         rt2x00_desc_write(priv_rx->desc, 1, word);
 621
 622         rt2x00_desc_read(priv_rx->desc, 0, &word);
 623         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 624         rt2x00_desc_write(priv_rx->desc, 0, word);
 625 }
 626
 627 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 628                                    struct queue_entry *entry)
 629 {
 630         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 631         u32 word;
 632
 633         rt2x00_desc_read(priv_tx->desc, 1, &word);
 634         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 635         rt2x00_desc_write(priv_tx->desc, 1, word);
 636
 637         rt2x00_desc_read(priv_tx->desc, 2, &word);
 638         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 639                            entry->queue->data_size);
 640         rt2x00_desc_write(priv_tx->desc, 2, word);
 641
 642         rt2x00_desc_read(priv_tx->desc, 0, &word);
 643         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 644         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 645         rt2x00_desc_write(priv_tx->desc, 0, word);
 646 }
 647
 648 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 649 {
 650         struct queue_entry_priv_pci_rx *priv_rx;
 651         struct queue_entry_priv_pci_tx *priv_tx;
 652         u32 reg;
 653
 654         /*
 655          * Initialize registers.
 656          */
 657         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 658         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 659         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 660         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 661         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 662         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 663
 664         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 665         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 666         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 667                            priv_tx->desc_dma);
 668         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 669
 670         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 671         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 672         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 673                            priv_tx->desc_dma);
 674         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 675
 676         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 677         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 678         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 679                            priv_tx->desc_dma);
 680         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 681
 682         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 683         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 684         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 685                            priv_tx->desc_dma);
 686         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 687
 688         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 689         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 690         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 691         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 692
 693         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 694         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 695         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 696         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 697
 698         return 0;
 699 }
 700
 701 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 702 {
 703         u32 reg;
 704
 705         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 706         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 707         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 708         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 709
 710         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 711         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 712         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 713         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 714         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 715
 716         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 717         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 718                            (rt2x00dev->rx->data_size / 128));
 719         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 720
 721         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 722         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 723         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 724         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 725
 726         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 727
 728         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 729         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 730         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 731         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 732         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 733         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 734
 735         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 736         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 737         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 738         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 739         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 740         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 741         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 742         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 743
 744         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 745
 746         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 747                 return -EBUSY;
 748
 749         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 750         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 751
 752         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 753         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 754         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 755
 756         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 757         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 758         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 759         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 760         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 761         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 762
 763         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 764         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 765         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 766         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 767         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 768
 769         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 770         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 771         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 772         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 773
 774         /*
 775          * We must clear the FCS and FIFO error count.
 776          * These registers are cleared on read,
 777          * so we may pass a useless variable to store the value.
 778          */
 779         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 780         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 781
 782         return 0;
 783 }
 784
 785 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 786 {
 787         unsigned int i;
 788         u16 eeprom;
 789         u8 reg_id;
 790         u8 value;
 791
 792         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 793                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 794                 if ((value != 0xff) && (value != 0x00))
 795                         goto continue_csr_init;
 796                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 797                 udelay(REGISTER_BUSY_DELAY);
 798         }
 799
 800         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 801         return -EACCES;
 802
 803 continue_csr_init:
 804         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 805         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 806         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 807         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 808         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 809         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 810         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 811         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 812         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 813         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 814         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 815         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 816         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 817         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 818
 819         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 820                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 821
 822                 if (eeprom != 0xffff && eeprom != 0x0000) {
 823                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 824                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 825                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 826                 }
 827         }
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * Device state switch handlers.
 834  */
 835 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 836                                 enum dev_state state)
 837 {
 838         u32 reg;
 839
 840         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 841         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 842                            state == STATE_RADIO_RX_OFF);
 843         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 844 }
 845
 846 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 847                                  enum dev_state state)
 848 {
 849         int mask = (state == STATE_RADIO_IRQ_OFF);
 850         u32 reg;
 851
 852         /*
 853          * When interrupts are being enabled, the interrupt registers
 854          * should clear the register to assure a clean state.
 855          */
 856         if (state == STATE_RADIO_IRQ_ON) {
 857                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 858                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 859         }
 860
 861         /*
 862          * Only toggle the interrupts bits we are going to use.
 863          * Non-checked interrupt bits are disabled by default.
 864          */
 865         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 866         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 867         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 868         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 869         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 870         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 871         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 872 }
 873
 874 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 875 {
 876         /*
 877          * Initialize all registers.
 878          */
 879         if (rt2400pci_init_queues(rt2x00dev) ||
 880             rt2400pci_init_registers(rt2x00dev) ||
 881             rt2400pci_init_bbp(rt2x00dev)) {
 882                 ERROR(rt2x00dev, "Register initialization failed.\n");
 883                 return -EIO;
 884         }
 885
 886         /*
 887          * Enable interrupts.
 888          */
 889         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 890
 891         return 0;
 892 }
 893
 894 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 895 {
 896         u32 reg;
 897
 898         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 899
 900         /*
 901          * Disable synchronisation.
 902          */
 903         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 904
 905         /*
 906          * Cancel RX and TX.
 907          */
 908         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 909         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 910         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 911
 912         /*
 913          * Disable interrupts.
 914          */
 915         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 916 }
 917
 918 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 919                                enum dev_state state)
 920 {
 921         u32 reg;
 922         unsigned int i;
 923         char put_to_sleep;
 924         char bbp_state;
 925         char rf_state;
 926
 927         put_to_sleep = (state != STATE_AWAKE);
 928
 929         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 930         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 931         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 932         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 933         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 934         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 935
 936         /*
 937          * Device is not guaranteed to be in the requested state yet.
 938          * We must wait until the register indicates that the
 939          * device has entered the correct state.
 940          */
 941         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 942                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 943                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 944                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 945                 if (bbp_state == state && rf_state == state)
 946                         return 0;
 947                 msleep(10);
 948         }
 949
 950         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 951                "current device state: bbp %d and rf %d.\n",
 952                state, bbp_state, rf_state);
 953
 954         return -EBUSY;
 955 }
 956
 957 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 958                                       enum dev_state state)
 959 {
 960         int retval = 0;
 961
 962         switch (state) {
 963         case STATE_RADIO_ON:
 964                 retval = rt2400pci_enable_radio(rt2x00dev);
 965                 break;
 966         case STATE_RADIO_OFF:
 967                 rt2400pci_disable_radio(rt2x00dev);
 968                 break;
 969         case STATE_RADIO_RX_ON:
 970         case STATE_RADIO_RX_ON_LINK:
 971                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
 972                 break;
 973         case STATE_RADIO_RX_OFF:
 974         case STATE_RADIO_RX_OFF_LINK:
 975                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
 976                 break;
 977         case STATE_DEEP_SLEEP:
 978         case STATE_SLEEP:
 979         case STATE_STANDBY:
 980         case STATE_AWAKE:
 981                 retval = rt2400pci_set_state(rt2x00dev, state);
 982                 break;
 983         default:
 984                 retval = -ENOTSUPP;
 985                 break;
 986         }
 987
 988         return retval;
 989 }
 990
 991 /*
 992  * TX descriptor initialization
 993  */
 994 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 995                                     struct sk_buff *skb,
 996                                     struct txentry_desc *txdesc,
 997                                     struct ieee80211_tx_control *control)
 998 {
 999         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1000         __le32 *txd = skbdesc->desc;
1001         u32 word;
1002
1003         /*
1004          * Start writing the descriptor words.
1005          */
1006         rt2x00_desc_read(txd, 2, &word);
1007         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1008         rt2x00_desc_write(txd, 2, word);
1009
1010         rt2x00_desc_read(txd, 3, &word);
1011         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1012         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1013         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1014         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1015         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1016         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1017         rt2x00_desc_write(txd, 3, word);
1018
1019         rt2x00_desc_read(txd, 4, &word);
1020         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1021         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1022         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1023         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1025         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1026         rt2x00_desc_write(txd, 4, word);
1027
1028         rt2x00_desc_read(txd, 0, &word);
1029         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1030         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1031         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1032                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1033         rt2x00_set_field32(&word, TXD_W0_ACK,
1034                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1035         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1036                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1037         rt2x00_set_field32(&word, TXD_W0_RTS,
1038                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1039         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1040         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1041                            !!(control->flags &
1042                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1043         rt2x00_desc_write(txd, 0, word);
1044 }
1045
1046 /*
1047  * TX data initialization
1048  */
1049 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1050                                     const unsigned int queue)
1051 {
1052         u32 reg;
1053
1054         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1055                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1056                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1057                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1058                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1059                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1060                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1061                 }
1062                 return;
1063         }
1064
1065         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1066         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1067                            (queue == IEEE80211_TX_QUEUE_DATA0));
1068         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1069                            (queue == IEEE80211_TX_QUEUE_DATA1));
1070         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1071                            (queue == RT2X00_BCN_QUEUE_ATIM));
1072         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1073 }
1074
1075 /*
1076  * RX control handlers
1077  */
1078 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1079                                   struct rxdone_entry_desc *rxdesc)
1080 {
1081         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1082         u32 word0;
1083         u32 word2;
1084         u32 word3;
1085
1086         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1087         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1088         rt2x00_desc_read(priv_rx->desc, 3, &word3);
1089
1090         rxdesc->flags = 0;
1091         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1092                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1093         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1094                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1095
1096         /*
1097          * Obtain the status about this packet.
1098          * The signal is the PLCP value, and needs to be stripped
1099          * of the preamble bit (0x08).
1100          */
1101         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1102         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1103             entry->queue->rt2x00dev->rssi_offset;
1104         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1105
1106         rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;
1107         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1108                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1109 }
1110
1111 /*
1112  * Interrupt functions.
1113  */
1114 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1115                              const enum ieee80211_tx_queue queue_idx)
1116 {
1117         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1118         struct queue_entry_priv_pci_tx *priv_tx;
1119         struct queue_entry *entry;
1120         struct txdone_entry_desc txdesc;
1121         u32 word;
1122
1123         while (!rt2x00queue_empty(queue)) {
1124                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1125                 priv_tx = entry->priv_data;
1126                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1127
1128                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1129                     !rt2x00_get_field32(word, TXD_W0_VALID))
1130                         break;
1131
1132                 /*
1133                  * Obtain the status about this packet.
1134                  */
1135                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1136                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1137
1138                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1139         }
1140 }
1141
1142 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1143 {
1144         struct rt2x00_dev *rt2x00dev = dev_instance;
1145         u32 reg;
1146
1147         /*
1148          * Get the interrupt sources & saved to local variable.
1149          * Write register value back to clear pending interrupts.
1150          */
1151         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1152         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1153
1154         if (!reg)
1155                 return IRQ_NONE;
1156
1157         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1158                 return IRQ_HANDLED;
1159
1160         /*
1161          * Handle interrupts, walk through all bits
1162          * and run the tasks, the bits are checked in order of
1163          * priority.
1164          */
1165
1166         /*
1167          * 1 - Beacon timer expired interrupt.
1168          */
1169         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1170                 rt2x00lib_beacondone(rt2x00dev);
1171
1172         /*
1173          * 2 - Rx ring done interrupt.
1174          */
1175         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1176                 rt2x00pci_rxdone(rt2x00dev);
1177
1178         /*
1179          * 3 - Atim ring transmit done interrupt.
1180          */
1181         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1182                 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1183
1184         /*
1185          * 4 - Priority ring transmit done interrupt.
1186          */
1187         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1188                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1189
1190         /*
1191          * 5 - Tx ring transmit done interrupt.
1192          */
1193         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1194                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 /*
1200  * Device probe functions.
1201  */
1202 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1203 {
1204         struct eeprom_93cx6 eeprom;
1205         u32 reg;
1206         u16 word;
1207         u8 *mac;
1208
1209         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1210
1211         eeprom.data = rt2x00dev;
1212         eeprom.register_read = rt2400pci_eepromregister_read;
1213         eeprom.register_write = rt2400pci_eepromregister_write;
1214         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1215             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1216         eeprom.reg_data_in = 0;
1217         eeprom.reg_data_out = 0;
1218         eeprom.reg_data_clock = 0;
1219         eeprom.reg_chip_select = 0;
1220
1221         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1222                                EEPROM_SIZE / sizeof(u16));
1223
1224         /*
1225          * Start validation of the data that has been read.
1226          */
1227         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1228         if (!is_valid_ether_addr(mac)) {
1229                 DECLARE_MAC_BUF(macbuf);
1230
1231                 random_ether_addr(mac);
1232                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1233         }
1234
1235         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1236         if (word == 0xffff) {
1237                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1238                 return -EINVAL;
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1245 {
1246         u32 reg;
1247         u16 value;
1248         u16 eeprom;
1249
1250         /*
1251          * Read EEPROM word for configuration.
1252          */
1253         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1254
1255         /*
1256          * Identify RF chipset.
1257          */
1258         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1259         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1260         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1261
1262         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1263             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1264                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1265                 return -ENODEV;
1266         }
1267
1268         /*
1269          * Identify default antenna configuration.
1270          */
1271         rt2x00dev->default_ant.tx =
1272             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1273         rt2x00dev->default_ant.rx =
1274             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1275
1276         /*
1277          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1278          * I am not 100% sure about this, but the legacy drivers do not
1279          * indicate antenna swapping in software is required when
1280          * diversity is enabled.
1281          */
1282         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1283                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1284         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1285                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1286
1287         /*
1288          * Store led mode, for correct led behaviour.
1289          */
1290 #ifdef CONFIG_RT2400PCI_LEDS
1291         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1292
1293         switch (value) {
1294         case LED_MODE_ASUS:
1295         case LED_MODE_ALPHA:
1296         case LED_MODE_DEFAULT:
1297                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1298                 break;
1299         case LED_MODE_TXRX_ACTIVITY:
1300                 rt2x00dev->led_flags =
1301                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1302                 break;
1303         case LED_MODE_SIGNAL_STRENGTH:
1304                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1305                 break;
1306         }
1307 #endif /* CONFIG_RT2400PCI_LEDS */
1308
1309         /*
1310          * Detect if this device has an hardware controlled radio.
1311          */
1312 #ifdef CONFIG_RT2400PCI_RFKILL
1313         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1314                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1315 #endif /* CONFIG_RT2400PCI_RFKILL */
1316
1317         /*
1318          * Check if the BBP tuning should be enabled.
1319          */
1320         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1321                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1322
1323         return 0;
1324 }
1325
1326 /*
1327  * RF value list for RF2420 & RF2421
1328  * Supports: 2.4 GHz
1329  */
1330 static const struct rf_channel rf_vals_bg[] = {
1331         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1332         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1333         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1334         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1335         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1336         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1337         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1338         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1339         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1340         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1341         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1342         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1343         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1344         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1345 };
1346
1347 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1348 {
1349         struct hw_mode_spec *spec = &rt2x00dev->spec;
1350         u8 *txpower;
1351         unsigned int i;
1352
1353         /*
1354          * Initialize all hw fields.
1355          */
1356         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1357         rt2x00dev->hw->extra_tx_headroom = 0;
1358         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1359         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1360         rt2x00dev->hw->queues = 2;
1361
1362         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1363         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1364                                 rt2x00_eeprom_addr(rt2x00dev,
1365                                                    EEPROM_MAC_ADDR_0));
1366
1367         /*
1368          * Convert tx_power array in eeprom.
1369          */
1370         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1371         for (i = 0; i < 14; i++)
1372                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1373
1374         /*
1375          * Initialize hw_mode information.
1376          */
1377         spec->supported_bands = SUPPORT_BAND_2GHZ;
1378         spec->supported_rates = SUPPORT_RATE_CCK;
1379         spec->tx_power_a = NULL;
1380         spec->tx_power_bg = txpower;
1381         spec->tx_power_default = DEFAULT_TXPOWER;
1382
1383         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1384         spec->channels = rf_vals_bg;
1385 }
1386
1387 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1388 {
1389         int retval;
1390
1391         /*
1392          * Allocate eeprom data.
1393          */
1394         retval = rt2400pci_validate_eeprom(rt2x00dev);
1395         if (retval)
1396                 return retval;
1397
1398         retval = rt2400pci_init_eeprom(rt2x00dev);
1399         if (retval)
1400                 return retval;
1401
1402         /*
1403          * Initialize hw specifications.
1404          */
1405         rt2400pci_probe_hw_mode(rt2x00dev);
1406
1407         /*
1408          * This device requires the atim queue
1409          */
1410         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1411
1412         /*
1413          * Set the rssi offset.
1414          */
1415         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1416
1417         return 0;
1418 }
1419
1420 /*
1421  * IEEE80211 stack callback functions.
1422  */
1423 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1424                                      u32 short_retry, u32 long_retry)
1425 {
1426         struct rt2x00_dev *rt2x00dev = hw->priv;
1427         u32 reg;
1428
1429         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1430         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1431         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1432         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1433
1434         return 0;
1435 }
1436
1437 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1438                              int queue,
1439                              const struct ieee80211_tx_queue_params *params)
1440 {
1441         struct rt2x00_dev *rt2x00dev = hw->priv;
1442
1443         /*
1444          * We don't support variating cw_min and cw_max variables
1445          * per queue. So by default we only configure the TX queue,
1446          * and ignore all other configurations.
1447          */
1448         if (queue != IEEE80211_TX_QUEUE_DATA0)
1449                 return -EINVAL;
1450
1451         if (rt2x00mac_conf_tx(hw, queue, params))
1452                 return -EINVAL;
1453
1454         /*
1455          * Write configuration to register.
1456          */
1457         rt2400pci_config_cw(rt2x00dev,
1458                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1459
1460         return 0;
1461 }
1462
1463 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1464 {
1465         struct rt2x00_dev *rt2x00dev = hw->priv;
1466         u64 tsf;
1467         u32 reg;
1468
1469         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1470         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1471         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1472         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1473
1474         return tsf;
1475 }
1476
1477 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1478                                    struct ieee80211_tx_control *control)
1479 {
1480         struct rt2x00_dev *rt2x00dev = hw->priv;
1481         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1482         struct queue_entry_priv_pci_tx *priv_tx;
1483         struct skb_frame_desc *skbdesc;
1484         u32 reg;
1485
1486         if (unlikely(!intf->beacon))
1487                 return -ENOBUFS;
1488         priv_tx = intf->beacon->priv_data;
1489
1490         /*
1491          * Fill in skb descriptor
1492          */
1493         skbdesc = get_skb_frame_desc(skb);
1494         memset(skbdesc, 0, sizeof(*skbdesc));
1495         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1496         skbdesc->data = skb->data;
1497         skbdesc->data_len = skb->len;
1498         skbdesc->desc = priv_tx->desc;
1499         skbdesc->desc_len = intf->beacon->queue->desc_size;
1500         skbdesc->entry = intf->beacon;
1501
1502         /*
1503          * Disable beaconing while we are reloading the beacon data,
1504          * otherwise we might be sending out invalid data.
1505          */
1506         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1507         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1508         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1509         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1510         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1511
1512         /*
1513          * mac80211 doesn't provide the control->queue variable
1514          * for beacons. Set our own queue identification so
1515          * it can be used during descriptor initialization.
1516          */
1517         control->queue = RT2X00_BCN_QUEUE_BEACON;
1518         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1519
1520         /*
1521          * Enable beacon generation.
1522          * Write entire beacon with descriptor to register,
1523          * and kick the beacon generator.
1524          */
1525         memcpy(priv_tx->data, skb->data, skb->len);
1526         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1527
1528         return 0;
1529 }
1530
1531 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1532 {
1533         struct rt2x00_dev *rt2x00dev = hw->priv;
1534         u32 reg;
1535
1536         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1537         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1538 }
1539
1540 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1541         .tx                     = rt2x00mac_tx,
1542         .start                  = rt2x00mac_start,
1543         .stop                   = rt2x00mac_stop,
1544         .add_interface          = rt2x00mac_add_interface,
1545         .remove_interface       = rt2x00mac_remove_interface,
1546         .config                 = rt2x00mac_config,
1547         .config_interface       = rt2x00mac_config_interface,
1548         .configure_filter       = rt2x00mac_configure_filter,
1549         .get_stats              = rt2x00mac_get_stats,
1550         .set_retry_limit        = rt2400pci_set_retry_limit,
1551         .bss_info_changed       = rt2x00mac_bss_info_changed,
1552         .conf_tx                = rt2400pci_conf_tx,
1553         .get_tx_stats           = rt2x00mac_get_tx_stats,
1554         .get_tsf                = rt2400pci_get_tsf,
1555         .beacon_update          = rt2400pci_beacon_update,
1556         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1557 };
1558
1559 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1560         .irq_handler            = rt2400pci_interrupt,
1561         .probe_hw               = rt2400pci_probe_hw,
1562         .initialize             = rt2x00pci_initialize,
1563         .uninitialize           = rt2x00pci_uninitialize,
1564         .init_rxentry           = rt2400pci_init_rxentry,
1565         .init_txentry           = rt2400pci_init_txentry,
1566         .set_device_state       = rt2400pci_set_device_state,
1567         .rfkill_poll            = rt2400pci_rfkill_poll,
1568         .link_stats             = rt2400pci_link_stats,
1569         .reset_tuner            = rt2400pci_reset_tuner,
1570         .link_tuner             = rt2400pci_link_tuner,
1571         .led_brightness         = rt2400pci_led_brightness,
1572         .write_tx_desc          = rt2400pci_write_tx_desc,
1573         .write_tx_data          = rt2x00pci_write_tx_data,
1574         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1575         .fill_rxdone            = rt2400pci_fill_rxdone,
1576         .config_filter          = rt2400pci_config_filter,
1577         .config_intf            = rt2400pci_config_intf,
1578         .config_erp             = rt2400pci_config_erp,
1579         .config                 = rt2400pci_config,
1580 };
1581
1582 static const struct data_queue_desc rt2400pci_queue_rx = {
1583         .entry_num              = RX_ENTRIES,
1584         .data_size              = DATA_FRAME_SIZE,
1585         .desc_size              = RXD_DESC_SIZE,
1586         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1587 };
1588
1589 static const struct data_queue_desc rt2400pci_queue_tx = {
1590         .entry_num              = TX_ENTRIES,
1591         .data_size              = DATA_FRAME_SIZE,
1592         .desc_size              = TXD_DESC_SIZE,
1593         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1594 };
1595
1596 static const struct data_queue_desc rt2400pci_queue_bcn = {
1597         .entry_num              = BEACON_ENTRIES,
1598         .data_size              = MGMT_FRAME_SIZE,
1599         .desc_size              = TXD_DESC_SIZE,
1600         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1601 };
1602
1603 static const struct data_queue_desc rt2400pci_queue_atim = {
1604         .entry_num              = ATIM_ENTRIES,
1605         .data_size              = DATA_FRAME_SIZE,
1606         .desc_size              = TXD_DESC_SIZE,
1607         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1608 };
1609
1610 static const struct rt2x00_ops rt2400pci_ops = {
1611         .name           = KBUILD_MODNAME,
1612         .max_sta_intf   = 1,
1613         .max_ap_intf    = 1,
1614         .eeprom_size    = EEPROM_SIZE,
1615         .rf_size        = RF_SIZE,
1616         .rx             = &rt2400pci_queue_rx,
1617         .tx             = &rt2400pci_queue_tx,
1618         .bcn            = &rt2400pci_queue_bcn,
1619         .atim           = &rt2400pci_queue_atim,
1620         .lib            = &rt2400pci_rt2x00_ops,
1621         .hw             = &rt2400pci_mac80211_ops,
1622 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1623         .debugfs        = &rt2400pci_rt2x00debug,
1624 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1625 };
1626
1627 /*
1628  * RT2400pci module information.
1629  */
1630 static struct pci_device_id rt2400pci_device_table[] = {
1631         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1632         { 0, }
1633 };
1634
1635 MODULE_AUTHOR(DRV_PROJECT);
1636 MODULE_VERSION(DRV_VERSION);
1637 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1638 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1639 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1640 MODULE_LICENSE("GPL");
1641
1642 static struct pci_driver rt2400pci_driver = {
1643         .name           = KBUILD_MODNAME,
1644         .id_table       = rt2400pci_device_table,
1645         .probe          = rt2x00pci_probe,
1646         .remove         = __devexit_p(rt2x00pci_remove),
1647         .suspend        = rt2x00pci_suspend,
1648         .resume         = rt2x00pci_resume,
1649 };
1650
1651 static int __init rt2400pci_init(void)
1652 {
1653         return pci_register_driver(&rt2400pci_driver);
1654 }
1655
1656 static void __exit rt2400pci_exit(void)
1657 {
1658         pci_unregister_driver(&rt2400pci_driver);
1659 }
1660
1661 module_init(rt2400pci_init);
1662 module_exit(rt2400pci_exit);