drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34 #include <linux/slab.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt2400pci.h"
  39
  40 /*
  41  * Register access.
  42  * All access to the CSR registers will go through the methods
  43  * rt2x00pci_register_read and rt2x00pci_register_write.
  44  * BBP and RF register require indirect register access,
  45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  46  * These indirect registers work with busy bits,
  47  * and we will try maximal REGISTER_BUSY_COUNT times to access
  48  * the register while taking a REGISTER_BUSY_DELAY us delay
  49  * between each attampt. When the busy bit is still set at that time,
  50  * the access attempt is considered to have failed,
  51  * and we will print an error.
  52  */
  53 #define WAIT_FOR_BBP(__dev, __reg) \
  54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  55 #define WAIT_FOR_RF(__dev, __reg) \
  56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  57
  58 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  59                                 const unsigned int word, const u8 value)
  60 {
  61         u32 reg;
  62
  63         mutex_lock(&rt2x00dev->csr_mutex);
  64
  65         /*
  66          * Wait until the BBP becomes available, afterwards we
  67          * can safely write the new data into the register.
  68          */
  69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  70                 reg = 0;
  71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  75
  76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  77         }
  78
  79         mutex_unlock(&rt2x00dev->csr_mutex);
  80 }
  81
  82 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  83                                const unsigned int word, u8 *value)
  84 {
  85         u32 reg;
  86
  87         mutex_lock(&rt2x00dev->csr_mutex);
  88
  89         /*
  90          * Wait until the BBP becomes available, afterwards we
  91          * can safely write the read request into the register.
  92          * After the data has been written, we wait until hardware
  93          * returns the correct value, if at any time the register
  94          * doesn't become available in time, reg will be 0xffffffff
  95          * which means we return 0xff to the caller.
  96          */
  97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  98                 reg = 0;
  99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 102
 103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 104
 105                 WAIT_FOR_BBP(rt2x00dev, &reg);
 106         }
 107
 108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 114                                const unsigned int word, const u32 value)
 115 {
 116         u32 reg;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the RF becomes available, afterwards we
 122          * can safely write the new data into the register.
 123          */
 124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 125                 reg = 0;
 126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 130
 131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 132                 rt2x00_rf_write(rt2x00dev, word, value);
 133         }
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 139 {
 140         struct rt2x00_dev *rt2x00dev = eeprom->data;
 141         u32 reg;
 142
 143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 144
 145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 147         eeprom->reg_data_clock =
 148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 149         eeprom->reg_chip_select =
 150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 151 }
 152
 153 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 154 {
 155         struct rt2x00_dev *rt2x00dev = eeprom->data;
 156         u32 reg = 0;
 157
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 161                            !!eeprom->reg_data_clock);
 162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 163                            !!eeprom->reg_chip_select);
 164
 165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 166 }
 167
 168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 169 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 170         .owner  = THIS_MODULE,
 171         .csr    = {
 172                 .read           = rt2x00pci_register_read,
 173                 .write          = rt2x00pci_register_write,
 174                 .flags          = RT2X00DEBUGFS_OFFSET,
 175                 .word_base      = CSR_REG_BASE,
 176                 .word_size      = sizeof(u32),
 177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 178         },
 179         .eeprom = {
 180                 .read           = rt2x00_eeprom_read,
 181                 .write          = rt2x00_eeprom_write,
 182                 .word_base      = EEPROM_BASE,
 183                 .word_size      = sizeof(u16),
 184                 .word_count     = EEPROM_SIZE / sizeof(u16),
 185         },
 186         .bbp    = {
 187                 .read           = rt2400pci_bbp_read,
 188                 .write          = rt2400pci_bbp_write,
 189                 .word_base      = BBP_BASE,
 190                 .word_size      = sizeof(u8),
 191                 .word_count     = BBP_SIZE / sizeof(u8),
 192         },
 193         .rf     = {
 194                 .read           = rt2x00_rf_read,
 195                 .write          = rt2400pci_rf_write,
 196                 .word_base      = RF_BASE,
 197                 .word_size      = sizeof(u32),
 198                 .word_count     = RF_SIZE / sizeof(u32),
 199         },
 200 };
 201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 202
 203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 209 }
 210
 211 #ifdef CONFIG_RT2X00_LIB_LEDS
 212 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 213                                      enum led_brightness brightness)
 214 {
 215         struct rt2x00_led *led =
 216             container_of(led_cdev, struct rt2x00_led, led_dev);
 217         unsigned int enabled = brightness != LED_OFF;
 218         u32 reg;
 219
 220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 221
 222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 224         else if (led->type == LED_TYPE_ACTIVITY)
 225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 226
 227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 228 }
 229
 230 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 231                                unsigned long *delay_on,
 232                                unsigned long *delay_off)
 233 {
 234         struct rt2x00_led *led =
 235             container_of(led_cdev, struct rt2x00_led, led_dev);
 236         u32 reg;
 237
 238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 242
 243         return 0;
 244 }
 245
 246 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 247                                struct rt2x00_led *led,
 248                                enum led_type type)
 249 {
 250         led->rt2x00dev = rt2x00dev;
 251         led->type = type;
 252         led->led_dev.brightness_set = rt2400pci_brightness_set;
 253         led->led_dev.blink_set = rt2400pci_blink_set;
 254         led->flags = LED_INITIALIZED;
 255 }
 256 #endif /* CONFIG_RT2X00_LIB_LEDS */
 257
 258 /*
 259  * Configuration handlers.
 260  */
 261 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 262                                     const unsigned int filter_flags)
 263 {
 264         u32 reg;
 265
 266         /*
 267          * Start configuration steps.
 268          * Note that the version error will always be dropped
 269          * since there is no filter for it at this time.
 270          */
 271         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 272         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 273                            !(filter_flags & FIF_FCSFAIL));
 274         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 275                            !(filter_flags & FIF_PLCPFAIL));
 276         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 277                            !(filter_flags & FIF_CONTROL));
 278         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 279                            !(filter_flags & FIF_PROMISC_IN_BSS));
 280         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 281                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 282                            !rt2x00dev->intf_ap_count);
 283         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 284         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 285 }
 286
 287 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 288                                   struct rt2x00_intf *intf,
 289                                   struct rt2x00intf_conf *conf,
 290                                   const unsigned int flags)
 291 {
 292         unsigned int bcn_preload;
 293         u32 reg;
 294
 295         if (flags & CONFIG_UPDATE_TYPE) {
 296                 /*
 297                  * Enable beacon config
 298                  */
 299                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 300                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 301                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 302                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 303
 304                 /*
 305                  * Enable synchronisation.
 306                  */
 307                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 308                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 309                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 310                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 311                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 312         }
 313
 314         if (flags & CONFIG_UPDATE_MAC)
 315                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 316                                               conf->mac, sizeof(conf->mac));
 317
 318         if (flags & CONFIG_UPDATE_BSSID)
 319                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 320                                               conf->bssid, sizeof(conf->bssid));
 321 }
 322
 323 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 324                                  struct rt2x00lib_erp *erp)
 325 {
 326         int preamble_mask;
 327         u32 reg;
 328
 329         /*
 330          * When short preamble is enabled, we should set bit 0x08
 331          */
 332         preamble_mask = erp->short_preamble << 3;
 333
 334         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 335         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
 336         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
 337         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 338         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 339         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 340
 341         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 342         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 343         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 344         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 345         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 346
 347         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 348         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 349         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 351         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 352
 353         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 354         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 355         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 357         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 358
 359         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 360         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 361         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 363         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 364
 365         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 366
 367         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 368         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 369         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 370
 371         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 372         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
 373         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
 374         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 375
 376         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 377         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 378         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 379         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 380
 381         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 382         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 383         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 384         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 385 }
 386
 387 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 388                                  struct antenna_setup *ant)
 389 {
 390         u8 r1;
 391         u8 r4;
 392
 393         /*
 394          * We should never come here because rt2x00lib is supposed
 395          * to catch this and send us the correct antenna explicitely.
 396          */
 397         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 398                ant->tx == ANTENNA_SW_DIVERSITY);
 399
 400         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 401         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 402
 403         /*
 404          * Configure the TX antenna.
 405          */
 406         switch (ant->tx) {
 407         case ANTENNA_HW_DIVERSITY:
 408                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 409                 break;
 410         case ANTENNA_A:
 411                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 412                 break;
 413         case ANTENNA_B:
 414         default:
 415                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 416                 break;
 417         }
 418
 419         /*
 420          * Configure the RX antenna.
 421          */
 422         switch (ant->rx) {
 423         case ANTENNA_HW_DIVERSITY:
 424                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 425                 break;
 426         case ANTENNA_A:
 427                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 428                 break;
 429         case ANTENNA_B:
 430         default:
 431                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 432                 break;
 433         }
 434
 435         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 436         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 437 }
 438
 439 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 440                                      struct rf_channel *rf)
 441 {
 442         /*
 443          * Switch on tuning bits.
 444          */
 445         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 446         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 447
 448         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 449         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 450         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 451
 452         /*
 453          * RF2420 chipset don't need any additional actions.
 454          */
 455         if (rt2x00_rf(rt2x00dev, RF2420))
 456                 return;
 457
 458         /*
 459          * For the RT2421 chipsets we need to write an invalid
 460          * reference clock rate to activate auto_tune.
 461          * After that we set the value back to the correct channel.
 462          */
 463         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 464         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 465         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 466
 467         msleep(1);
 468
 469         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 470         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 471         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 472
 473         msleep(1);
 474
 475         /*
 476          * Switch off tuning bits.
 477          */
 478         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 479         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 480
 481         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 482         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 483
 484         /*
 485          * Clear false CRC during channel switch.
 486          */
 487         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 488 }
 489
 490 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 491 {
 492         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 493 }
 494
 495 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 496                                          struct rt2x00lib_conf *libconf)
 497 {
 498         u32 reg;
 499
 500         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 501         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 502                            libconf->conf->long_frame_max_tx_count);
 503         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 504                            libconf->conf->short_frame_max_tx_count);
 505         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 506 }
 507
 508 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
 509                                 struct rt2x00lib_conf *libconf)
 510 {
 511         enum dev_state state =
 512             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 513                 STATE_SLEEP : STATE_AWAKE;
 514         u32 reg;
 515
 516         if (state == STATE_SLEEP) {
 517                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 518                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 519                                    (rt2x00dev->beacon_int - 20) * 16);
 520                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 521                                    libconf->conf->listen_interval - 1);
 522
 523                 /* We must first disable autowake before it can be enabled */
 524                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 525                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 526
 527                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 528                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 529         } else {
 530                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 531                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 532                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 533         }
 534
 535         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 536 }
 537
 538 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 539                              struct rt2x00lib_conf *libconf,
 540                              const unsigned int flags)
 541 {
 542         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 543                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 544         if (flags & IEEE80211_CONF_CHANGE_POWER)
 545                 rt2400pci_config_txpower(rt2x00dev,
 546                                          libconf->conf->power_level);
 547         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 548                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
 549         if (flags & IEEE80211_CONF_CHANGE_PS)
 550                 rt2400pci_config_ps(rt2x00dev, libconf);
 551 }
 552
 553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 554                                 const int cw_min, const int cw_max)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 560         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 561         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 562 }
 563
 564 /*
 565  * Link tuning
 566  */
 567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 568                                  struct link_qual *qual)
 569 {
 570         u32 reg;
 571         u8 bbp;
 572
 573         /*
 574          * Update FCS error count from register.
 575          */
 576         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 577         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 578
 579         /*
 580          * Update False CCA count from register.
 581          */
 582         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 583         qual->false_cca = bbp;
 584 }
 585
 586 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 587                                      struct link_qual *qual, u8 vgc_level)
 588 {
 589         if (qual->vgc_level_reg != vgc_level) {
 590                 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
 591                 qual->vgc_level = vgc_level;
 592                 qual->vgc_level_reg = vgc_level;
 593         }
 594 }
 595
 596 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 597                                   struct link_qual *qual)
 598 {
 599         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
 600 }
 601
 602 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 603                                  struct link_qual *qual, const u32 count)
 604 {
 605         /*
 606          * The link tuner should not run longer then 60 seconds,
 607          * and should run once every 2 seconds.
 608          */
 609         if (count > 60 || !(count & 1))
 610                 return;
 611
 612         /*
 613          * Base r13 link tuning on the false cca count.
 614          */
 615         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
 616                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
 617         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
 618                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
 619 }
 620
 621 /*
 622  * Initialization functions.
 623  */
 624 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
 625 {
 626         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 627         u32 word;
 628
 629         if (entry->queue->qid == QID_RX) {
 630                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 631
 632                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 633         } else {
 634                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 635
 636                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 637                         rt2x00_get_field32(word, TXD_W0_VALID));
 638         }
 639 }
 640
 641 static void rt2400pci_clear_entry(struct queue_entry *entry)
 642 {
 643         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 644         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 645         u32 word;
 646
 647         if (entry->queue->qid == QID_RX) {
 648                 rt2x00_desc_read(entry_priv->desc, 2, &word);
 649                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 650                 rt2x00_desc_write(entry_priv->desc, 2, word);
 651
 652                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 653                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 654                 rt2x00_desc_write(entry_priv->desc, 1, word);
 655
 656                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 657                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 658                 rt2x00_desc_write(entry_priv->desc, 0, word);
 659         } else {
 660                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 661                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 662                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 663                 rt2x00_desc_write(entry_priv->desc, 0, word);
 664         }
 665 }
 666
 667 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 668 {
 669         struct queue_entry_priv_pci *entry_priv;
 670         u32 reg;
 671
 672         /*
 673          * Initialize registers.
 674          */
 675         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 676         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 677         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 678         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 679         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 680         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 681
 682         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 683         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 684         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 685                            entry_priv->desc_dma);
 686         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 687
 688         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 689         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 690         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 691                            entry_priv->desc_dma);
 692         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 693
 694         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 695         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 696         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 697                            entry_priv->desc_dma);
 698         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 699
 700         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 701         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 702         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 703                            entry_priv->desc_dma);
 704         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 705
 706         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 707         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 708         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 709         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 710
 711         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 712         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 713         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 714                            entry_priv->desc_dma);
 715         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 716
 717         return 0;
 718 }
 719
 720 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 721 {
 722         u32 reg;
 723
 724         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 725         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 726         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 727         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 728
 729         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 730         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 731         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 732         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 733         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 734
 735         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 736         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 737                            (rt2x00dev->rx->data_size / 128));
 738         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 739
 740         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 741         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 742         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 743         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 744         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 745         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 746         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 747         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 748         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 749         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 750
 751         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 752
 753         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 754         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 755         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 756         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 757         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 758         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 759
 760         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 761         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 762         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 763         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 764         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 765         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 766         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 767         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 768
 769         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 770
 771         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 772                 return -EBUSY;
 773
 774         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 775         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 776
 777         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 778         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 779         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 780
 781         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 782         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 783         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 784         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 785         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 786         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 787
 788         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 789         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 790         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 791         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 792         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 793
 794         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 795         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 796         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 797         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 798
 799         /*
 800          * We must clear the FCS and FIFO error count.
 801          * These registers are cleared on read,
 802          * so we may pass a useless variable to store the value.
 803          */
 804         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 805         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 806
 807         return 0;
 808 }
 809
 810 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 811 {
 812         unsigned int i;
 813         u8 value;
 814
 815         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 816                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 817                 if ((value != 0xff) && (value != 0x00))
 818                         return 0;
 819                 udelay(REGISTER_BUSY_DELAY);
 820         }
 821
 822         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 823         return -EACCES;
 824 }
 825
 826 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 827 {
 828         unsigned int i;
 829         u16 eeprom;
 830         u8 reg_id;
 831         u8 value;
 832
 833         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 834                 return -EACCES;
 835
 836         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 837         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 838         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 839         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 840         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 841         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 842         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 843         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 844         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 845         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 846         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 847         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 848         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 849         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 850
 851         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 852                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 853
 854                 if (eeprom != 0xffff && eeprom != 0x0000) {
 855                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 856                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 857                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 858                 }
 859         }
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * Device state switch handlers.
 866  */
 867 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 868                                 enum dev_state state)
 869 {
 870         u32 reg;
 871
 872         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 873         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 874                            (state == STATE_RADIO_RX_OFF) ||
 875                            (state == STATE_RADIO_RX_OFF_LINK));
 876         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 877 }
 878
 879 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 880                                  enum dev_state state)
 881 {
 882         int mask = (state == STATE_RADIO_IRQ_OFF) ||
 883                    (state == STATE_RADIO_IRQ_OFF_ISR);
 884         u32 reg;
 885
 886         /*
 887          * When interrupts are being enabled, the interrupt registers
 888          * should clear the register to assure a clean state.
 889          */
 890         if (state == STATE_RADIO_IRQ_ON) {
 891                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 892                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 893         }
 894
 895         /*
 896          * Only toggle the interrupts bits we are going to use.
 897          * Non-checked interrupt bits are disabled by default.
 898          */
 899         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 900         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 901         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 902         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 903         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 904         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 905         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 906 }
 907
 908 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 909 {
 910         /*
 911          * Initialize all registers.
 912          */
 913         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 914                      rt2400pci_init_registers(rt2x00dev) ||
 915                      rt2400pci_init_bbp(rt2x00dev)))
 916                 return -EIO;
 917
 918         return 0;
 919 }
 920
 921 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 922 {
 923         /*
 924          * Disable power
 925          */
 926         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 927 }
 928
 929 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 930                                enum dev_state state)
 931 {
 932         u32 reg, reg2;
 933         unsigned int i;
 934         char put_to_sleep;
 935         char bbp_state;
 936         char rf_state;
 937
 938         put_to_sleep = (state != STATE_AWAKE);
 939
 940         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 941         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 942         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 943         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 944         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 945         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 946
 947         /*
 948          * Device is not guaranteed to be in the requested state yet.
 949          * We must wait until the register indicates that the
 950          * device has entered the correct state.
 951          */
 952         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 953                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
 954                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
 955                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
 956                 if (bbp_state == state && rf_state == state)
 957                         return 0;
 958                 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 959                 msleep(10);
 960         }
 961
 962         return -EBUSY;
 963 }
 964
 965 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 966                                       enum dev_state state)
 967 {
 968         int retval = 0;
 969
 970         switch (state) {
 971         case STATE_RADIO_ON:
 972                 retval = rt2400pci_enable_radio(rt2x00dev);
 973                 break;
 974         case STATE_RADIO_OFF:
 975                 rt2400pci_disable_radio(rt2x00dev);
 976                 break;
 977         case STATE_RADIO_RX_ON:
 978         case STATE_RADIO_RX_ON_LINK:
 979         case STATE_RADIO_RX_OFF:
 980         case STATE_RADIO_RX_OFF_LINK:
 981                 rt2400pci_toggle_rx(rt2x00dev, state);
 982                 break;
 983         case STATE_RADIO_IRQ_ON:
 984         case STATE_RADIO_IRQ_ON_ISR:
 985         case STATE_RADIO_IRQ_OFF:
 986         case STATE_RADIO_IRQ_OFF_ISR:
 987                 rt2400pci_toggle_irq(rt2x00dev, state);
 988                 break;
 989         case STATE_DEEP_SLEEP:
 990         case STATE_SLEEP:
 991         case STATE_STANDBY:
 992         case STATE_AWAKE:
 993                 retval = rt2400pci_set_state(rt2x00dev, state);
 994                 break;
 995         default:
 996                 retval = -ENOTSUPP;
 997                 break;
 998         }
 999
1000         if (unlikely(retval))
1001                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1002                       state, retval);
1003
1004         return retval;
1005 }
1006
1007 /*
1008  * TX descriptor initialization
1009  */
1010 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1011                                     struct txentry_desc *txdesc)
1012 {
1013         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1014         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1015         __le32 *txd = entry_priv->desc;
1016         u32 word;
1017
1018         /*
1019          * Start writing the descriptor words.
1020          */
1021         rt2x00_desc_read(txd, 1, &word);
1022         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1023         rt2x00_desc_write(txd, 1, word);
1024
1025         rt2x00_desc_read(txd, 2, &word);
1026         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1027         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1028         rt2x00_desc_write(txd, 2, word);
1029
1030         rt2x00_desc_read(txd, 3, &word);
1031         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1032         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1033         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1034         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1036         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1037         rt2x00_desc_write(txd, 3, word);
1038
1039         rt2x00_desc_read(txd, 4, &word);
1040         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1041         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1042         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1043         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1044         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1045         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1046         rt2x00_desc_write(txd, 4, word);
1047
1048         /*
1049          * Writing TXD word 0 must the last to prevent a race condition with
1050          * the device, whereby the device may take hold of the TXD before we
1051          * finished updating it.
1052          */
1053         rt2x00_desc_read(txd, 0, &word);
1054         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1055         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1056         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1057                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1058         rt2x00_set_field32(&word, TXD_W0_ACK,
1059                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1060         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1061                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1062         rt2x00_set_field32(&word, TXD_W0_RTS,
1063                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1064         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1065         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1066                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1067         rt2x00_desc_write(txd, 0, word);
1068
1069         /*
1070          * Register descriptor details in skb frame descriptor.
1071          */
1072         skbdesc->desc = txd;
1073         skbdesc->desc_len = TXD_DESC_SIZE;
1074 }
1075
1076 /*
1077  * TX data initialization
1078  */
1079 static void rt2400pci_write_beacon(struct queue_entry *entry,
1080                                    struct txentry_desc *txdesc)
1081 {
1082         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1083         u32 reg;
1084
1085         /*
1086          * Disable beaconing while we are reloading the beacon data,
1087          * otherwise we might be sending out invalid data.
1088          */
1089         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1090         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1091         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1092
1093         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1094
1095         /*
1096          * Write the TX descriptor for the beacon.
1097          */
1098         rt2400pci_write_tx_desc(entry, txdesc);
1099
1100         /*
1101          * Dump beacon to userspace through debugfs.
1102          */
1103         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1104
1105         /*
1106          * Enable beaconing again.
1107          */
1108         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1109         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1110         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1111         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1112 }
1113
1114 static void rt2400pci_kick_tx_queue(struct data_queue *queue)
1115 {
1116         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1117         u32 reg;
1118
1119         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1120         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE));
1121         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK));
1122         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM));
1123         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1124 }
1125
1126 static void rt2400pci_kill_tx_queue(struct data_queue *queue)
1127 {
1128         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1129         u32 reg;
1130
1131         if (queue->qid == QID_BEACON) {
1132                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1133         } else {
1134                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1135                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1136                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1137         }
1138 }
1139
1140 /*
1141  * RX control handlers
1142  */
1143 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1144                                   struct rxdone_entry_desc *rxdesc)
1145 {
1146         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1147         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1148         u32 word0;
1149         u32 word2;
1150         u32 word3;
1151         u32 word4;
1152         u64 tsf;
1153         u32 rx_low;
1154         u32 rx_high;
1155
1156         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1157         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1158         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1159         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1160
1161         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1162                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1163         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1164                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1165
1166         /*
1167          * We only get the lower 32bits from the timestamp,
1168          * to get the full 64bits we must complement it with
1169          * the timestamp from get_tsf().
1170          * Note that when a wraparound of the lower 32bits
1171          * has occurred between the frame arrival and the get_tsf()
1172          * call, we must decrease the higher 32bits with 1 to get
1173          * to correct value.
1174          */
1175         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1176         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1177         rx_high = upper_32_bits(tsf);
1178
1179         if ((u32)tsf <= rx_low)
1180                 rx_high--;
1181
1182         /*
1183          * Obtain the status about this packet.
1184          * The signal is the PLCP value, and needs to be stripped
1185          * of the preamble bit (0x08).
1186          */
1187         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1188         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1189         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1190             entry->queue->rt2x00dev->rssi_offset;
1191         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1192
1193         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1194         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1195                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1196 }
1197
1198 /*
1199  * Interrupt functions.
1200  */
1201 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1202                              const enum data_queue_qid queue_idx)
1203 {
1204         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1205         struct queue_entry_priv_pci *entry_priv;
1206         struct queue_entry *entry;
1207         struct txdone_entry_desc txdesc;
1208         u32 word;
1209
1210         while (!rt2x00queue_empty(queue)) {
1211                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1212                 entry_priv = entry->priv_data;
1213                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1214
1215                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1216                     !rt2x00_get_field32(word, TXD_W0_VALID))
1217                         break;
1218
1219                 /*
1220                  * Obtain the status about this packet.
1221                  */
1222                 txdesc.flags = 0;
1223                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1224                 case 0: /* Success */
1225                 case 1: /* Success with retry */
1226                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1227                         break;
1228                 case 2: /* Failure, excessive retries */
1229                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1230                         /* Don't break, this is a failed frame! */
1231                 default: /* Failure */
1232                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1233                 }
1234                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1235
1236                 rt2x00lib_txdone(entry, &txdesc);
1237         }
1238 }
1239
1240 static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
1241 {
1242         struct rt2x00_dev *rt2x00dev = dev_instance;
1243         u32 reg = rt2x00dev->irqvalue[0];
1244
1245         /*
1246          * Handle interrupts, walk through all bits
1247          * and run the tasks, the bits are checked in order of
1248          * priority.
1249          */
1250
1251         /*
1252          * 1 - Beacon timer expired interrupt.
1253          */
1254         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1255                 rt2x00lib_beacondone(rt2x00dev);
1256
1257         /*
1258          * 2 - Rx ring done interrupt.
1259          */
1260         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1261                 rt2x00pci_rxdone(rt2x00dev);
1262
1263         /*
1264          * 3 - Atim ring transmit done interrupt.
1265          */
1266         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1267                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1268
1269         /*
1270          * 4 - Priority ring transmit done interrupt.
1271          */
1272         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1273                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1274
1275         /*
1276          * 5 - Tx ring transmit done interrupt.
1277          */
1278         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1279                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1280
1281         /* Enable interrupts again. */
1282         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1283                                               STATE_RADIO_IRQ_ON_ISR);
1284         return IRQ_HANDLED;
1285 }
1286
1287 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1288 {
1289         struct rt2x00_dev *rt2x00dev = dev_instance;
1290         u32 reg;
1291
1292         /*
1293          * Get the interrupt sources & saved to local variable.
1294          * Write register value back to clear pending interrupts.
1295          */
1296         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1297         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1298
1299         if (!reg)
1300                 return IRQ_NONE;
1301
1302         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1303                 return IRQ_HANDLED;
1304
1305         /* Store irqvalues for use in the interrupt thread. */
1306         rt2x00dev->irqvalue[0] = reg;
1307
1308         /* Disable interrupts, will be enabled again in the interrupt thread. */
1309         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1310                                               STATE_RADIO_IRQ_OFF_ISR);
1311
1312         return IRQ_WAKE_THREAD;
1313 }
1314
1315 /*
1316  * Device probe functions.
1317  */
1318 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1319 {
1320         struct eeprom_93cx6 eeprom;
1321         u32 reg;
1322         u16 word;
1323         u8 *mac;
1324
1325         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1326
1327         eeprom.data = rt2x00dev;
1328         eeprom.register_read = rt2400pci_eepromregister_read;
1329         eeprom.register_write = rt2400pci_eepromregister_write;
1330         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1331             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1332         eeprom.reg_data_in = 0;
1333         eeprom.reg_data_out = 0;
1334         eeprom.reg_data_clock = 0;
1335         eeprom.reg_chip_select = 0;
1336
1337         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1338                                EEPROM_SIZE / sizeof(u16));
1339
1340         /*
1341          * Start validation of the data that has been read.
1342          */
1343         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1344         if (!is_valid_ether_addr(mac)) {
1345                 random_ether_addr(mac);
1346                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1347         }
1348
1349         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1350         if (word == 0xffff) {
1351                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1352                 return -EINVAL;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1359 {
1360         u32 reg;
1361         u16 value;
1362         u16 eeprom;
1363
1364         /*
1365          * Read EEPROM word for configuration.
1366          */
1367         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1368
1369         /*
1370          * Identify RF chipset.
1371          */
1372         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1373         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1374         rt2x00_set_chip(rt2x00dev, RT2460, value,
1375                         rt2x00_get_field32(reg, CSR0_REVISION));
1376
1377         if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1378                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1379                 return -ENODEV;
1380         }
1381
1382         /*
1383          * Identify default antenna configuration.
1384          */
1385         rt2x00dev->default_ant.tx =
1386             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1387         rt2x00dev->default_ant.rx =
1388             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1389
1390         /*
1391          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1392          * I am not 100% sure about this, but the legacy drivers do not
1393          * indicate antenna swapping in software is required when
1394          * diversity is enabled.
1395          */
1396         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1397                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1398         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1399                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1400
1401         /*
1402          * Store led mode, for correct led behaviour.
1403          */
1404 #ifdef CONFIG_RT2X00_LIB_LEDS
1405         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1406
1407         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1408         if (value == LED_MODE_TXRX_ACTIVITY ||
1409             value == LED_MODE_DEFAULT ||
1410             value == LED_MODE_ASUS)
1411                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1412                                    LED_TYPE_ACTIVITY);
1413 #endif /* CONFIG_RT2X00_LIB_LEDS */
1414
1415         /*
1416          * Detect if this device has an hardware controlled radio.
1417          */
1418         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1419                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1420
1421         /*
1422          * Check if the BBP tuning should be enabled.
1423          */
1424         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1425                 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1426
1427         return 0;
1428 }
1429
1430 /*
1431  * RF value list for RF2420 & RF2421
1432  * Supports: 2.4 GHz
1433  */
1434 static const struct rf_channel rf_vals_b[] = {
1435         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1436         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1437         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1438         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1439         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1440         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1441         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1442         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1443         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1444         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1445         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1446         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1447         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1448         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1449 };
1450
1451 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1452 {
1453         struct hw_mode_spec *spec = &rt2x00dev->spec;
1454         struct channel_info *info;
1455         char *tx_power;
1456         unsigned int i;
1457
1458         /*
1459          * Initialize all hw fields.
1460          */
1461         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1462                                IEEE80211_HW_SIGNAL_DBM |
1463                                IEEE80211_HW_SUPPORTS_PS |
1464                                IEEE80211_HW_PS_NULLFUNC_STACK;
1465
1466         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1467         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1468                                 rt2x00_eeprom_addr(rt2x00dev,
1469                                                    EEPROM_MAC_ADDR_0));
1470
1471         /*
1472          * Initialize hw_mode information.
1473          */
1474         spec->supported_bands = SUPPORT_BAND_2GHZ;
1475         spec->supported_rates = SUPPORT_RATE_CCK;
1476
1477         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1478         spec->channels = rf_vals_b;
1479
1480         /*
1481          * Create channel information array
1482          */
1483         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1484         if (!info)
1485                 return -ENOMEM;
1486
1487         spec->channels_info = info;
1488
1489         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1490         for (i = 0; i < 14; i++) {
1491                 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1492                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1493         }
1494
1495         return 0;
1496 }
1497
1498 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1499 {
1500         int retval;
1501
1502         /*
1503          * Allocate eeprom data.
1504          */
1505         retval = rt2400pci_validate_eeprom(rt2x00dev);
1506         if (retval)
1507                 return retval;
1508
1509         retval = rt2400pci_init_eeprom(rt2x00dev);
1510         if (retval)
1511                 return retval;
1512
1513         /*
1514          * Initialize hw specifications.
1515          */
1516         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1517         if (retval)
1518                 return retval;
1519
1520         /*
1521          * This device requires the atim queue and DMA-mapped skbs.
1522          */
1523         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1524         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1525
1526         /*
1527          * Set the rssi offset.
1528          */
1529         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1530
1531         return 0;
1532 }
1533
1534 /*
1535  * IEEE80211 stack callback functions.
1536  */
1537 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1538                              const struct ieee80211_tx_queue_params *params)
1539 {
1540         struct rt2x00_dev *rt2x00dev = hw->priv;
1541
1542         /*
1543          * We don't support variating cw_min and cw_max variables
1544          * per queue. So by default we only configure the TX queue,
1545          * and ignore all other configurations.
1546          */
1547         if (queue != 0)
1548                 return -EINVAL;
1549
1550         if (rt2x00mac_conf_tx(hw, queue, params))
1551                 return -EINVAL;
1552
1553         /*
1554          * Write configuration to register.
1555          */
1556         rt2400pci_config_cw(rt2x00dev,
1557                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1558
1559         return 0;
1560 }
1561
1562 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1563 {
1564         struct rt2x00_dev *rt2x00dev = hw->priv;
1565         u64 tsf;
1566         u32 reg;
1567
1568         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1569         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1570         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1571         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1572
1573         return tsf;
1574 }
1575
1576 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1577 {
1578         struct rt2x00_dev *rt2x00dev = hw->priv;
1579         u32 reg;
1580
1581         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1582         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1583 }
1584
1585 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1586         .tx                     = rt2x00mac_tx,
1587         .start                  = rt2x00mac_start,
1588         .stop                   = rt2x00mac_stop,
1589         .add_interface          = rt2x00mac_add_interface,
1590         .remove_interface       = rt2x00mac_remove_interface,
1591         .config                 = rt2x00mac_config,
1592         .configure_filter       = rt2x00mac_configure_filter,
1593         .sw_scan_start          = rt2x00mac_sw_scan_start,
1594         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1595         .get_stats              = rt2x00mac_get_stats,
1596         .bss_info_changed       = rt2x00mac_bss_info_changed,
1597         .conf_tx                = rt2400pci_conf_tx,
1598         .get_tsf                = rt2400pci_get_tsf,
1599         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1600         .rfkill_poll            = rt2x00mac_rfkill_poll,
1601 };
1602
1603 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1604         .irq_handler            = rt2400pci_interrupt,
1605         .irq_handler_thread     = rt2400pci_interrupt_thread,
1606         .probe_hw               = rt2400pci_probe_hw,
1607         .initialize             = rt2x00pci_initialize,
1608         .uninitialize           = rt2x00pci_uninitialize,
1609         .get_entry_state        = rt2400pci_get_entry_state,
1610         .clear_entry            = rt2400pci_clear_entry,
1611         .set_device_state       = rt2400pci_set_device_state,
1612         .rfkill_poll            = rt2400pci_rfkill_poll,
1613         .link_stats             = rt2400pci_link_stats,
1614         .reset_tuner            = rt2400pci_reset_tuner,
1615         .link_tuner             = rt2400pci_link_tuner,
1616         .write_tx_desc          = rt2400pci_write_tx_desc,
1617         .write_beacon           = rt2400pci_write_beacon,
1618         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1619         .kill_tx_queue          = rt2400pci_kill_tx_queue,
1620         .fill_rxdone            = rt2400pci_fill_rxdone,
1621         .config_filter          = rt2400pci_config_filter,
1622         .config_intf            = rt2400pci_config_intf,
1623         .config_erp             = rt2400pci_config_erp,
1624         .config_ant             = rt2400pci_config_ant,
1625         .config                 = rt2400pci_config,
1626 };
1627
1628 static const struct data_queue_desc rt2400pci_queue_rx = {
1629         .entry_num              = RX_ENTRIES,
1630         .data_size              = DATA_FRAME_SIZE,
1631         .desc_size              = RXD_DESC_SIZE,
1632         .priv_size              = sizeof(struct queue_entry_priv_pci),
1633 };
1634
1635 static const struct data_queue_desc rt2400pci_queue_tx = {
1636         .entry_num              = TX_ENTRIES,
1637         .data_size              = DATA_FRAME_SIZE,
1638         .desc_size              = TXD_DESC_SIZE,
1639         .priv_size              = sizeof(struct queue_entry_priv_pci),
1640 };
1641
1642 static const struct data_queue_desc rt2400pci_queue_bcn = {
1643         .entry_num              = BEACON_ENTRIES,
1644         .data_size              = MGMT_FRAME_SIZE,
1645         .desc_size              = TXD_DESC_SIZE,
1646         .priv_size              = sizeof(struct queue_entry_priv_pci),
1647 };
1648
1649 static const struct data_queue_desc rt2400pci_queue_atim = {
1650         .entry_num              = ATIM_ENTRIES,
1651         .data_size              = DATA_FRAME_SIZE,
1652         .desc_size              = TXD_DESC_SIZE,
1653         .priv_size              = sizeof(struct queue_entry_priv_pci),
1654 };
1655
1656 static const struct rt2x00_ops rt2400pci_ops = {
1657         .name                   = KBUILD_MODNAME,
1658         .max_sta_intf           = 1,
1659         .max_ap_intf            = 1,
1660         .eeprom_size            = EEPROM_SIZE,
1661         .rf_size                = RF_SIZE,
1662         .tx_queues              = NUM_TX_QUEUES,
1663         .extra_tx_headroom      = 0,
1664         .rx                     = &rt2400pci_queue_rx,
1665         .tx                     = &rt2400pci_queue_tx,
1666         .bcn                    = &rt2400pci_queue_bcn,
1667         .atim                   = &rt2400pci_queue_atim,
1668         .lib                    = &rt2400pci_rt2x00_ops,
1669         .hw                     = &rt2400pci_mac80211_ops,
1670 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1671         .debugfs                = &rt2400pci_rt2x00debug,
1672 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1673 };
1674
1675 /*
1676  * RT2400pci module information.
1677  */
1678 static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1679         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1680         { 0, }
1681 };
1682
1683 MODULE_AUTHOR(DRV_PROJECT);
1684 MODULE_VERSION(DRV_VERSION);
1685 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1686 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1687 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1688 MODULE_LICENSE("GPL");
1689
1690 static struct pci_driver rt2400pci_driver = {
1691         .name           = KBUILD_MODNAME,
1692         .id_table       = rt2400pci_device_table,
1693         .probe          = rt2x00pci_probe,
1694         .remove         = __devexit_p(rt2x00pci_remove),
1695         .suspend        = rt2x00pci_suspend,
1696         .resume         = rt2x00pci_resume,
1697 };
1698
1699 static int __init rt2400pci_init(void)
1700 {
1701         return pci_register_driver(&rt2400pci_driver);
1702 }
1703
1704 static void __exit rt2400pci_exit(void)
1705 {
1706         pci_unregister_driver(&rt2400pci_driver);
1707 }
1708
1709 module_init(rt2400pci_init);
1710 module_exit(rt2400pci_exit);