drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         unsigned int activity =
 254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
 255         u32 reg;
 256
 257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 258
 259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
 260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
 262         }
 263
 264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 265 }
 266 #else
 267 #define rt2400pci_led_brightness        NULL
 268 #endif /* CONFIG_RT2400PCI_LEDS */
 269
 270 /*
 271  * Configuration handlers.
 272  */
 273 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 274                                   struct rt2x00_intf *intf,
 275                                   struct rt2x00intf_conf *conf,
 276                                   const unsigned int flags)
 277 {
 278         unsigned int bcn_preload;
 279         u32 reg;
 280
 281         if (flags & CONFIG_UPDATE_TYPE) {
 282                 /*
 283                  * Enable beacon config
 284                  */
 285                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 286                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 287                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 288                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 289
 290                 /*
 291                  * Enable synchronisation.
 292                  */
 293                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 294                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 295                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 296                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 297                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 298         }
 299
 300         if (flags & CONFIG_UPDATE_MAC)
 301                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 302                                               conf->mac, sizeof(conf->mac));
 303
 304         if (flags & CONFIG_UPDATE_BSSID)
 305                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 306                                               conf->bssid, sizeof(conf->bssid));
 307 }
 308
 309 static int rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 310                                 struct rt2x00lib_erp *erp)
 311 {
 312         int preamble_mask;
 313         u32 reg;
 314
 315         /*
 316          * When short preamble is enabled, we should set bit 0x08
 317          */
 318         preamble_mask = erp->short_preamble << 3;
 319
 320         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 321         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 322                            erp->ack_timeout);
 323         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 324                            erp->ack_consume_time);
 325         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 326
 327         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 328         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 329         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 330         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 331         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 332
 333         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 334         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 335         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 336         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 337         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 338
 339         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 340         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 341         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 342         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 343         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 344
 345         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 346         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 347         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 348         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 349         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 350
 351         return 0;
 352 }
 353
 354 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 355                                      const int basic_rate_mask)
 356 {
 357         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 358 }
 359
 360 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 361                                      struct rf_channel *rf)
 362 {
 363         /*
 364          * Switch on tuning bits.
 365          */
 366         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 367         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 368
 369         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 370         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 371         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 372
 373         /*
 374          * RF2420 chipset don't need any additional actions.
 375          */
 376         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 377                 return;
 378
 379         /*
 380          * For the RT2421 chipsets we need to write an invalid
 381          * reference clock rate to activate auto_tune.
 382          * After that we set the value back to the correct channel.
 383          */
 384         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 385         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 386         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 387
 388         msleep(1);
 389
 390         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 391         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 392         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 393
 394         msleep(1);
 395
 396         /*
 397          * Switch off tuning bits.
 398          */
 399         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 400         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 401
 402         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 403         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 404
 405         /*
 406          * Clear false CRC during channel switch.
 407          */
 408         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 409 }
 410
 411 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 412 {
 413         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 414 }
 415
 416 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 417                                      struct antenna_setup *ant)
 418 {
 419         u8 r1;
 420         u8 r4;
 421
 422         /*
 423          * We should never come here because rt2x00lib is supposed
 424          * to catch this and send us the correct antenna explicitely.
 425          */
 426         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 427                ant->tx == ANTENNA_SW_DIVERSITY);
 428
 429         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 430         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 431
 432         /*
 433          * Configure the TX antenna.
 434          */
 435         switch (ant->tx) {
 436         case ANTENNA_HW_DIVERSITY:
 437                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 438                 break;
 439         case ANTENNA_A:
 440                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 441                 break;
 442         case ANTENNA_B:
 443         default:
 444                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 445                 break;
 446         }
 447
 448         /*
 449          * Configure the RX antenna.
 450          */
 451         switch (ant->rx) {
 452         case ANTENNA_HW_DIVERSITY:
 453                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 454                 break;
 455         case ANTENNA_A:
 456                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 457                 break;
 458         case ANTENNA_B:
 459         default:
 460                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 461                 break;
 462         }
 463
 464         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 465         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 466 }
 467
 468 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 469                                       struct rt2x00lib_conf *libconf)
 470 {
 471         u32 reg;
 472
 473         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 474         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 475         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 476
 477         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 478         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 479         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 480         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 481
 482         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 483         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 484         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 485         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 486
 487         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 488         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 489         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 490         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 491
 492         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 493         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 494                            libconf->conf->beacon_int * 16);
 495         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 496                            libconf->conf->beacon_int * 16);
 497         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 498 }
 499
 500 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 501                              struct rt2x00lib_conf *libconf,
 502                              const unsigned int flags)
 503 {
 504         if (flags & CONFIG_UPDATE_PHYMODE)
 505                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 506         if (flags & CONFIG_UPDATE_CHANNEL)
 507                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 508         if (flags & CONFIG_UPDATE_TXPOWER)
 509                 rt2400pci_config_txpower(rt2x00dev,
 510                                          libconf->conf->power_level);
 511         if (flags & CONFIG_UPDATE_ANTENNA)
 512                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 513         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 514                 rt2400pci_config_duration(rt2x00dev, libconf);
 515 }
 516
 517 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 518                                 const int cw_min, const int cw_max)
 519 {
 520         u32 reg;
 521
 522         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 523         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 524         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 525         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 526 }
 527
 528 /*
 529  * Link tuning
 530  */
 531 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 532                                  struct link_qual *qual)
 533 {
 534         u32 reg;
 535         u8 bbp;
 536
 537         /*
 538          * Update FCS error count from register.
 539          */
 540         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 541         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 542
 543         /*
 544          * Update False CCA count from register.
 545          */
 546         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 547         qual->false_cca = bbp;
 548 }
 549
 550 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 551 {
 552         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 553         rt2x00dev->link.vgc_level = 0x08;
 554 }
 555
 556 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 557 {
 558         u8 reg;
 559
 560         /*
 561          * The link tuner should not run longer then 60 seconds,
 562          * and should run once every 2 seconds.
 563          */
 564         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 565                 return;
 566
 567         /*
 568          * Base r13 link tuning on the false cca count.
 569          */
 570         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 571
 572         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 573                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 574                 rt2x00dev->link.vgc_level = reg;
 575         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 576                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 577                 rt2x00dev->link.vgc_level = reg;
 578         }
 579 }
 580
 581 /*
 582  * Initialization functions.
 583  */
 584 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 585                                    struct queue_entry *entry)
 586 {
 587         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 588         u32 word;
 589
 590         rt2x00_desc_read(priv_rx->desc, 2, &word);
 591         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 592                            entry->queue->data_size);
 593         rt2x00_desc_write(priv_rx->desc, 2, word);
 594
 595         rt2x00_desc_read(priv_rx->desc, 1, &word);
 596         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 597         rt2x00_desc_write(priv_rx->desc, 1, word);
 598
 599         rt2x00_desc_read(priv_rx->desc, 0, &word);
 600         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 601         rt2x00_desc_write(priv_rx->desc, 0, word);
 602 }
 603
 604 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 605                                    struct queue_entry *entry)
 606 {
 607         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 608         u32 word;
 609
 610         rt2x00_desc_read(priv_tx->desc, 1, &word);
 611         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 612         rt2x00_desc_write(priv_tx->desc, 1, word);
 613
 614         rt2x00_desc_read(priv_tx->desc, 2, &word);
 615         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 616                            entry->queue->data_size);
 617         rt2x00_desc_write(priv_tx->desc, 2, word);
 618
 619         rt2x00_desc_read(priv_tx->desc, 0, &word);
 620         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 621         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 622         rt2x00_desc_write(priv_tx->desc, 0, word);
 623 }
 624
 625 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 626 {
 627         struct queue_entry_priv_pci_rx *priv_rx;
 628         struct queue_entry_priv_pci_tx *priv_tx;
 629         u32 reg;
 630
 631         /*
 632          * Initialize registers.
 633          */
 634         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 635         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 636         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 637         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 638         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 639         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 640
 641         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 642         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 643         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 644                            priv_tx->desc_dma);
 645         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 646
 647         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 648         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 649         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 650                            priv_tx->desc_dma);
 651         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 652
 653         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 654         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 655         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 656                            priv_tx->desc_dma);
 657         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 658
 659         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 660         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 661         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 662                            priv_tx->desc_dma);
 663         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 664
 665         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 666         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 667         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 668         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 669
 670         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 671         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 672         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 673         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 674
 675         return 0;
 676 }
 677
 678 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 679 {
 680         u32 reg;
 681
 682         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 683         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 684         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 685         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 686
 687         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 688         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 689         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 690         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 691         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 692
 693         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 694         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 695                            (rt2x00dev->rx->data_size / 128));
 696         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 697
 698         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 699         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 700         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 701         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 702
 703         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 704
 705         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 706         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 707         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 708         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 709         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 710         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 711
 712         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 713         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 714         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 715         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 716         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 717         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 718         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 719         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 720
 721         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 722
 723         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 724                 return -EBUSY;
 725
 726         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 727         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 728
 729         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 730         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 731         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 732
 733         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 734         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 735         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 736         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 737         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 738         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 739
 740         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 741         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 742         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 743         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 744         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 745
 746         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 747         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 748         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 749         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 750
 751         /*
 752          * We must clear the FCS and FIFO error count.
 753          * These registers are cleared on read,
 754          * so we may pass a useless variable to store the value.
 755          */
 756         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 757         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 758
 759         return 0;
 760 }
 761
 762 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 763 {
 764         unsigned int i;
 765         u16 eeprom;
 766         u8 reg_id;
 767         u8 value;
 768
 769         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 770                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 771                 if ((value != 0xff) && (value != 0x00))
 772                         goto continue_csr_init;
 773                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 774                 udelay(REGISTER_BUSY_DELAY);
 775         }
 776
 777         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 778         return -EACCES;
 779
 780 continue_csr_init:
 781         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 782         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 783         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 784         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 785         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 786         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 787         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 788         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 789         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 790         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 791         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 792         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 793         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 794         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 795
 796         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 797                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 798
 799                 if (eeprom != 0xffff && eeprom != 0x0000) {
 800                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 801                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 802                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 803                 }
 804         }
 805
 806         return 0;
 807 }
 808
 809 /*
 810  * Device state switch handlers.
 811  */
 812 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 813                                 enum dev_state state)
 814 {
 815         u32 reg;
 816
 817         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 818         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 819                            state == STATE_RADIO_RX_OFF);
 820         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 821 }
 822
 823 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 824                                  enum dev_state state)
 825 {
 826         int mask = (state == STATE_RADIO_IRQ_OFF);
 827         u32 reg;
 828
 829         /*
 830          * When interrupts are being enabled, the interrupt registers
 831          * should clear the register to assure a clean state.
 832          */
 833         if (state == STATE_RADIO_IRQ_ON) {
 834                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 835                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 836         }
 837
 838         /*
 839          * Only toggle the interrupts bits we are going to use.
 840          * Non-checked interrupt bits are disabled by default.
 841          */
 842         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 843         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 844         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 845         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 846         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 847         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 848         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 849 }
 850
 851 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 852 {
 853         /*
 854          * Initialize all registers.
 855          */
 856         if (rt2400pci_init_queues(rt2x00dev) ||
 857             rt2400pci_init_registers(rt2x00dev) ||
 858             rt2400pci_init_bbp(rt2x00dev)) {
 859                 ERROR(rt2x00dev, "Register initialization failed.\n");
 860                 return -EIO;
 861         }
 862
 863         /*
 864          * Enable interrupts.
 865          */
 866         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 867
 868         return 0;
 869 }
 870
 871 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 872 {
 873         u32 reg;
 874
 875         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 876
 877         /*
 878          * Disable synchronisation.
 879          */
 880         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 881
 882         /*
 883          * Cancel RX and TX.
 884          */
 885         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 886         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 887         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 888
 889         /*
 890          * Disable interrupts.
 891          */
 892         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 893 }
 894
 895 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 896                                enum dev_state state)
 897 {
 898         u32 reg;
 899         unsigned int i;
 900         char put_to_sleep;
 901         char bbp_state;
 902         char rf_state;
 903
 904         put_to_sleep = (state != STATE_AWAKE);
 905
 906         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 907         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 908         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 909         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 910         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 911         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 912
 913         /*
 914          * Device is not guaranteed to be in the requested state yet.
 915          * We must wait until the register indicates that the
 916          * device has entered the correct state.
 917          */
 918         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 919                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 920                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 921                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 922                 if (bbp_state == state && rf_state == state)
 923                         return 0;
 924                 msleep(10);
 925         }
 926
 927         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 928                "current device state: bbp %d and rf %d.\n",
 929                state, bbp_state, rf_state);
 930
 931         return -EBUSY;
 932 }
 933
 934 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 935                                       enum dev_state state)
 936 {
 937         int retval = 0;
 938
 939         switch (state) {
 940         case STATE_RADIO_ON:
 941                 retval = rt2400pci_enable_radio(rt2x00dev);
 942                 break;
 943         case STATE_RADIO_OFF:
 944                 rt2400pci_disable_radio(rt2x00dev);
 945                 break;
 946         case STATE_RADIO_RX_ON:
 947         case STATE_RADIO_RX_ON_LINK:
 948                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
 949                 break;
 950         case STATE_RADIO_RX_OFF:
 951         case STATE_RADIO_RX_OFF_LINK:
 952                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
 953                 break;
 954         case STATE_DEEP_SLEEP:
 955         case STATE_SLEEP:
 956         case STATE_STANDBY:
 957         case STATE_AWAKE:
 958                 retval = rt2400pci_set_state(rt2x00dev, state);
 959                 break;
 960         default:
 961                 retval = -ENOTSUPP;
 962                 break;
 963         }
 964
 965         return retval;
 966 }
 967
 968 /*
 969  * TX descriptor initialization
 970  */
 971 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 972                                     struct sk_buff *skb,
 973                                     struct txentry_desc *txdesc,
 974                                     struct ieee80211_tx_control *control)
 975 {
 976         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 977         __le32 *txd = skbdesc->desc;
 978         u32 word;
 979
 980         /*
 981          * Start writing the descriptor words.
 982          */
 983         rt2x00_desc_read(txd, 2, &word);
 984         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
 985         rt2x00_desc_write(txd, 2, word);
 986
 987         rt2x00_desc_read(txd, 3, &word);
 988         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
 989         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
 990         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
 991         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
 992         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
 993         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
 994         rt2x00_desc_write(txd, 3, word);
 995
 996         rt2x00_desc_read(txd, 4, &word);
 997         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
 998         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
 999         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1000         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1001         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1002         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1003         rt2x00_desc_write(txd, 4, word);
1004
1005         rt2x00_desc_read(txd, 0, &word);
1006         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1007         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1008         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1009                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1010         rt2x00_set_field32(&word, TXD_W0_ACK,
1011                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1012         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1013                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1014         rt2x00_set_field32(&word, TXD_W0_RTS,
1015                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1016         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1017         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1018                            !!(control->flags &
1019                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1020         rt2x00_desc_write(txd, 0, word);
1021 }
1022
1023 /*
1024  * TX data initialization
1025  */
1026 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1027                                     const unsigned int queue)
1028 {
1029         u32 reg;
1030
1031         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1032                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1033                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1034                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1035                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1036                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1037                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1038                 }
1039                 return;
1040         }
1041
1042         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1043         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1044                            (queue == IEEE80211_TX_QUEUE_DATA0));
1045         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1046                            (queue == IEEE80211_TX_QUEUE_DATA1));
1047         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1048                            (queue == RT2X00_BCN_QUEUE_ATIM));
1049         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1050 }
1051
1052 /*
1053  * RX control handlers
1054  */
1055 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1056                                   struct rxdone_entry_desc *rxdesc)
1057 {
1058         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1059         u32 word0;
1060         u32 word2;
1061         u32 word3;
1062
1063         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1064         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1065         rt2x00_desc_read(priv_rx->desc, 3, &word3);
1066
1067         rxdesc->flags = 0;
1068         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1069                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1070         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1071                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1072
1073         /*
1074          * Obtain the status about this packet.
1075          * The signal is the PLCP value, and needs to be stripped
1076          * of the preamble bit (0x08).
1077          */
1078         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1079         rxdesc->signal_plcp = 1;
1080         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1081             entry->queue->rt2x00dev->rssi_offset;
1082         rxdesc->ofdm = 0;
1083         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1084         rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1085 }
1086
1087 /*
1088  * Interrupt functions.
1089  */
1090 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1091                              const enum ieee80211_tx_queue queue_idx)
1092 {
1093         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1094         struct queue_entry_priv_pci_tx *priv_tx;
1095         struct queue_entry *entry;
1096         struct txdone_entry_desc txdesc;
1097         u32 word;
1098
1099         while (!rt2x00queue_empty(queue)) {
1100                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1101                 priv_tx = entry->priv_data;
1102                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1103
1104                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1105                     !rt2x00_get_field32(word, TXD_W0_VALID))
1106                         break;
1107
1108                 /*
1109                  * Obtain the status about this packet.
1110                  */
1111                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1112                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1113
1114                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1115         }
1116 }
1117
1118 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1119 {
1120         struct rt2x00_dev *rt2x00dev = dev_instance;
1121         u32 reg;
1122
1123         /*
1124          * Get the interrupt sources & saved to local variable.
1125          * Write register value back to clear pending interrupts.
1126          */
1127         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1128         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1129
1130         if (!reg)
1131                 return IRQ_NONE;
1132
1133         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1134                 return IRQ_HANDLED;
1135
1136         /*
1137          * Handle interrupts, walk through all bits
1138          * and run the tasks, the bits are checked in order of
1139          * priority.
1140          */
1141
1142         /*
1143          * 1 - Beacon timer expired interrupt.
1144          */
1145         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1146                 rt2x00lib_beacondone(rt2x00dev);
1147
1148         /*
1149          * 2 - Rx ring done interrupt.
1150          */
1151         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1152                 rt2x00pci_rxdone(rt2x00dev);
1153
1154         /*
1155          * 3 - Atim ring transmit done interrupt.
1156          */
1157         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1158                 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1159
1160         /*
1161          * 4 - Priority ring transmit done interrupt.
1162          */
1163         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1164                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1165
1166         /*
1167          * 5 - Tx ring transmit done interrupt.
1168          */
1169         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1170                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1171
1172         return IRQ_HANDLED;
1173 }
1174
1175 /*
1176  * Device probe functions.
1177  */
1178 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1179 {
1180         struct eeprom_93cx6 eeprom;
1181         u32 reg;
1182         u16 word;
1183         u8 *mac;
1184
1185         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1186
1187         eeprom.data = rt2x00dev;
1188         eeprom.register_read = rt2400pci_eepromregister_read;
1189         eeprom.register_write = rt2400pci_eepromregister_write;
1190         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1191             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1192         eeprom.reg_data_in = 0;
1193         eeprom.reg_data_out = 0;
1194         eeprom.reg_data_clock = 0;
1195         eeprom.reg_chip_select = 0;
1196
1197         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1198                                EEPROM_SIZE / sizeof(u16));
1199
1200         /*
1201          * Start validation of the data that has been read.
1202          */
1203         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1204         if (!is_valid_ether_addr(mac)) {
1205                 DECLARE_MAC_BUF(macbuf);
1206
1207                 random_ether_addr(mac);
1208                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1209         }
1210
1211         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1212         if (word == 0xffff) {
1213                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1214                 return -EINVAL;
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1221 {
1222         u32 reg;
1223         u16 value;
1224         u16 eeprom;
1225
1226         /*
1227          * Read EEPROM word for configuration.
1228          */
1229         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1230
1231         /*
1232          * Identify RF chipset.
1233          */
1234         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1235         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1236         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1237
1238         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1239             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1240                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1241                 return -ENODEV;
1242         }
1243
1244         /*
1245          * Identify default antenna configuration.
1246          */
1247         rt2x00dev->default_ant.tx =
1248             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1249         rt2x00dev->default_ant.rx =
1250             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1251
1252         /*
1253          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1254          * I am not 100% sure about this, but the legacy drivers do not
1255          * indicate antenna swapping in software is required when
1256          * diversity is enabled.
1257          */
1258         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1259                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1260         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1261                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1262
1263         /*
1264          * Store led mode, for correct led behaviour.
1265          */
1266 #ifdef CONFIG_RT2400PCI_LEDS
1267         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1268
1269         switch (value) {
1270         case LED_MODE_ASUS:
1271         case LED_MODE_ALPHA:
1272         case LED_MODE_DEFAULT:
1273                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1274                 break;
1275         case LED_MODE_TXRX_ACTIVITY:
1276                 rt2x00dev->led_flags =
1277                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1278                 break;
1279         case LED_MODE_SIGNAL_STRENGTH:
1280                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1281                 break;
1282         }
1283 #endif /* CONFIG_RT2400PCI_LEDS */
1284
1285         /*
1286          * Detect if this device has an hardware controlled radio.
1287          */
1288 #ifdef CONFIG_RT2400PCI_RFKILL
1289         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1290                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1291 #endif /* CONFIG_RT2400PCI_RFKILL */
1292
1293         /*
1294          * Check if the BBP tuning should be enabled.
1295          */
1296         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1297                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1298
1299         return 0;
1300 }
1301
1302 /*
1303  * RF value list for RF2420 & RF2421
1304  * Supports: 2.4 GHz
1305  */
1306 static const struct rf_channel rf_vals_bg[] = {
1307         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1308         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1309         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1310         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1311         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1312         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1313         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1314         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1315         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1316         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1317         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1318         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1319         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1320         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1321 };
1322
1323 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1324 {
1325         struct hw_mode_spec *spec = &rt2x00dev->spec;
1326         u8 *txpower;
1327         unsigned int i;
1328
1329         /*
1330          * Initialize all hw fields.
1331          */
1332         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1333         rt2x00dev->hw->extra_tx_headroom = 0;
1334         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1335         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1336         rt2x00dev->hw->queues = 2;
1337
1338         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1339         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1340                                 rt2x00_eeprom_addr(rt2x00dev,
1341                                                    EEPROM_MAC_ADDR_0));
1342
1343         /*
1344          * Convert tx_power array in eeprom.
1345          */
1346         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1347         for (i = 0; i < 14; i++)
1348                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1349
1350         /*
1351          * Initialize hw_mode information.
1352          */
1353         spec->supported_bands = SUPPORT_BAND_2GHZ;
1354         spec->supported_rates = SUPPORT_RATE_CCK;
1355         spec->tx_power_a = NULL;
1356         spec->tx_power_bg = txpower;
1357         spec->tx_power_default = DEFAULT_TXPOWER;
1358
1359         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1360         spec->channels = rf_vals_bg;
1361 }
1362
1363 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1364 {
1365         int retval;
1366
1367         /*
1368          * Allocate eeprom data.
1369          */
1370         retval = rt2400pci_validate_eeprom(rt2x00dev);
1371         if (retval)
1372                 return retval;
1373
1374         retval = rt2400pci_init_eeprom(rt2x00dev);
1375         if (retval)
1376                 return retval;
1377
1378         /*
1379          * Initialize hw specifications.
1380          */
1381         rt2400pci_probe_hw_mode(rt2x00dev);
1382
1383         /*
1384          * This device requires the atim queue
1385          */
1386         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1387
1388         /*
1389          * Set the rssi offset.
1390          */
1391         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1392
1393         return 0;
1394 }
1395
1396 /*
1397  * IEEE80211 stack callback functions.
1398  */
1399 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1400                                        unsigned int changed_flags,
1401                                        unsigned int *total_flags,
1402                                        int mc_count,
1403                                        struct dev_addr_list *mc_list)
1404 {
1405         struct rt2x00_dev *rt2x00dev = hw->priv;
1406         u32 reg;
1407
1408         /*
1409          * Mask off any flags we are going to ignore from
1410          * the total_flags field.
1411          */
1412         *total_flags &=
1413             FIF_ALLMULTI |
1414             FIF_FCSFAIL |
1415             FIF_PLCPFAIL |
1416             FIF_CONTROL |
1417             FIF_OTHER_BSS |
1418             FIF_PROMISC_IN_BSS;
1419
1420         /*
1421          * Apply some rules to the filters:
1422          * - Some filters imply different filters to be set.
1423          * - Some things we can't filter out at all.
1424          */
1425         *total_flags |= FIF_ALLMULTI;
1426         if (*total_flags & FIF_OTHER_BSS ||
1427             *total_flags & FIF_PROMISC_IN_BSS)
1428                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1429
1430         /*
1431          * Check if there is any work left for us.
1432          */
1433         if (rt2x00dev->packet_filter == *total_flags)
1434                 return;
1435         rt2x00dev->packet_filter = *total_flags;
1436
1437         /*
1438          * Start configuration steps.
1439          * Note that the version error will always be dropped
1440          * since there is no filter for it at this time.
1441          */
1442         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1443         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1444                            !(*total_flags & FIF_FCSFAIL));
1445         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1446                            !(*total_flags & FIF_PLCPFAIL));
1447         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1448                            !(*total_flags & FIF_CONTROL));
1449         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1450                            !(*total_flags & FIF_PROMISC_IN_BSS));
1451         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1452                            !(*total_flags & FIF_PROMISC_IN_BSS));
1453         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1454         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1455 }
1456
1457 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1458                                      u32 short_retry, u32 long_retry)
1459 {
1460         struct rt2x00_dev *rt2x00dev = hw->priv;
1461         u32 reg;
1462
1463         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1464         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1465         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1466         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1467
1468         return 0;
1469 }
1470
1471 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1472                              int queue,
1473                              const struct ieee80211_tx_queue_params *params)
1474 {
1475         struct rt2x00_dev *rt2x00dev = hw->priv;
1476
1477         /*
1478          * We don't support variating cw_min and cw_max variables
1479          * per queue. So by default we only configure the TX queue,
1480          * and ignore all other configurations.
1481          */
1482         if (queue != IEEE80211_TX_QUEUE_DATA0)
1483                 return -EINVAL;
1484
1485         if (rt2x00mac_conf_tx(hw, queue, params))
1486                 return -EINVAL;
1487
1488         /*
1489          * Write configuration to register.
1490          */
1491         rt2400pci_config_cw(rt2x00dev,
1492                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1493
1494         return 0;
1495 }
1496
1497 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1498 {
1499         struct rt2x00_dev *rt2x00dev = hw->priv;
1500         u64 tsf;
1501         u32 reg;
1502
1503         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1504         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1505         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1506         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1507
1508         return tsf;
1509 }
1510
1511 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1512                                    struct ieee80211_tx_control *control)
1513 {
1514         struct rt2x00_dev *rt2x00dev = hw->priv;
1515         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1516         struct queue_entry_priv_pci_tx *priv_tx;
1517         struct skb_frame_desc *skbdesc;
1518         u32 reg;
1519
1520         if (unlikely(!intf->beacon))
1521                 return -ENOBUFS;
1522         priv_tx = intf->beacon->priv_data;
1523
1524         /*
1525          * Fill in skb descriptor
1526          */
1527         skbdesc = get_skb_frame_desc(skb);
1528         memset(skbdesc, 0, sizeof(*skbdesc));
1529         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1530         skbdesc->data = skb->data;
1531         skbdesc->data_len = skb->len;
1532         skbdesc->desc = priv_tx->desc;
1533         skbdesc->desc_len = intf->beacon->queue->desc_size;
1534         skbdesc->entry = intf->beacon;
1535
1536         /*
1537          * Disable beaconing while we are reloading the beacon data,
1538          * otherwise we might be sending out invalid data.
1539          */
1540         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1541         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1542         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1543         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1544         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1545
1546         /*
1547          * mac80211 doesn't provide the control->queue variable
1548          * for beacons. Set our own queue identification so
1549          * it can be used during descriptor initialization.
1550          */
1551         control->queue = RT2X00_BCN_QUEUE_BEACON;
1552         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1553
1554         /*
1555          * Enable beacon generation.
1556          * Write entire beacon with descriptor to register,
1557          * and kick the beacon generator.
1558          */
1559         memcpy(priv_tx->data, skb->data, skb->len);
1560         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1561
1562         return 0;
1563 }
1564
1565 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1566 {
1567         struct rt2x00_dev *rt2x00dev = hw->priv;
1568         u32 reg;
1569
1570         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1571         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1572 }
1573
1574 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1575         .tx                     = rt2x00mac_tx,
1576         .start                  = rt2x00mac_start,
1577         .stop                   = rt2x00mac_stop,
1578         .add_interface          = rt2x00mac_add_interface,
1579         .remove_interface       = rt2x00mac_remove_interface,
1580         .config                 = rt2x00mac_config,
1581         .config_interface       = rt2x00mac_config_interface,
1582         .configure_filter       = rt2400pci_configure_filter,
1583         .get_stats              = rt2x00mac_get_stats,
1584         .set_retry_limit        = rt2400pci_set_retry_limit,
1585         .bss_info_changed       = rt2x00mac_bss_info_changed,
1586         .conf_tx                = rt2400pci_conf_tx,
1587         .get_tx_stats           = rt2x00mac_get_tx_stats,
1588         .get_tsf                = rt2400pci_get_tsf,
1589         .beacon_update          = rt2400pci_beacon_update,
1590         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1591 };
1592
1593 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1594         .irq_handler            = rt2400pci_interrupt,
1595         .probe_hw               = rt2400pci_probe_hw,
1596         .initialize             = rt2x00pci_initialize,
1597         .uninitialize           = rt2x00pci_uninitialize,
1598         .init_rxentry           = rt2400pci_init_rxentry,
1599         .init_txentry           = rt2400pci_init_txentry,
1600         .set_device_state       = rt2400pci_set_device_state,
1601         .rfkill_poll            = rt2400pci_rfkill_poll,
1602         .link_stats             = rt2400pci_link_stats,
1603         .reset_tuner            = rt2400pci_reset_tuner,
1604         .link_tuner             = rt2400pci_link_tuner,
1605         .led_brightness         = rt2400pci_led_brightness,
1606         .write_tx_desc          = rt2400pci_write_tx_desc,
1607         .write_tx_data          = rt2x00pci_write_tx_data,
1608         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1609         .fill_rxdone            = rt2400pci_fill_rxdone,
1610         .config_intf            = rt2400pci_config_intf,
1611         .config_erp             = rt2400pci_config_erp,
1612         .config                 = rt2400pci_config,
1613 };
1614
1615 static const struct data_queue_desc rt2400pci_queue_rx = {
1616         .entry_num              = RX_ENTRIES,
1617         .data_size              = DATA_FRAME_SIZE,
1618         .desc_size              = RXD_DESC_SIZE,
1619         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1620 };
1621
1622 static const struct data_queue_desc rt2400pci_queue_tx = {
1623         .entry_num              = TX_ENTRIES,
1624         .data_size              = DATA_FRAME_SIZE,
1625         .desc_size              = TXD_DESC_SIZE,
1626         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1627 };
1628
1629 static const struct data_queue_desc rt2400pci_queue_bcn = {
1630         .entry_num              = BEACON_ENTRIES,
1631         .data_size              = MGMT_FRAME_SIZE,
1632         .desc_size              = TXD_DESC_SIZE,
1633         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1634 };
1635
1636 static const struct data_queue_desc rt2400pci_queue_atim = {
1637         .entry_num              = ATIM_ENTRIES,
1638         .data_size              = DATA_FRAME_SIZE,
1639         .desc_size              = TXD_DESC_SIZE,
1640         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1641 };
1642
1643 static const struct rt2x00_ops rt2400pci_ops = {
1644         .name           = KBUILD_MODNAME,
1645         .max_sta_intf   = 1,
1646         .max_ap_intf    = 1,
1647         .eeprom_size    = EEPROM_SIZE,
1648         .rf_size        = RF_SIZE,
1649         .rx             = &rt2400pci_queue_rx,
1650         .tx             = &rt2400pci_queue_tx,
1651         .bcn            = &rt2400pci_queue_bcn,
1652         .atim           = &rt2400pci_queue_atim,
1653         .lib            = &rt2400pci_rt2x00_ops,
1654         .hw             = &rt2400pci_mac80211_ops,
1655 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1656         .debugfs        = &rt2400pci_rt2x00debug,
1657 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1658 };
1659
1660 /*
1661  * RT2400pci module information.
1662  */
1663 static struct pci_device_id rt2400pci_device_table[] = {
1664         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1665         { 0, }
1666 };
1667
1668 MODULE_AUTHOR(DRV_PROJECT);
1669 MODULE_VERSION(DRV_VERSION);
1670 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1671 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1672 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1673 MODULE_LICENSE("GPL");
1674
1675 static struct pci_driver rt2400pci_driver = {
1676         .name           = KBUILD_MODNAME,
1677         .id_table       = rt2400pci_device_table,
1678         .probe          = rt2x00pci_probe,
1679         .remove         = __devexit_p(rt2x00pci_remove),
1680         .suspend        = rt2x00pci_suspend,
1681         .resume         = rt2x00pci_resume,
1682 };
1683
1684 static int __init rt2400pci_init(void)
1685 {
1686         return pci_register_driver(&rt2400pci_driver);
1687 }
1688
1689 static void __exit rt2400pci_exit(void)
1690 {
1691         pci_unregister_driver(&rt2400pci_driver);
1692 }
1693
1694 module_init(rt2400pci_init);
1695 module_exit(rt2400pci_exit);