drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280
 281 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 282                                struct rt2x00_led *led,
 283                                enum led_type type)
 284 {
 285         led->rt2x00dev = rt2x00dev;
 286         led->type = type;
 287         led->led_dev.brightness_set = rt2400pci_brightness_set;
 288         led->led_dev.blink_set = rt2400pci_blink_set;
 289         led->flags = LED_INITIALIZED;
 290 }
 291 #endif /* CONFIG_RT2400PCI_LEDS */
 292
 293 /*
 294  * Configuration handlers.
 295  */
 296 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 297                                     const unsigned int filter_flags)
 298 {
 299         u32 reg;
 300
 301         /*
 302          * Start configuration steps.
 303          * Note that the version error will always be dropped
 304          * since there is no filter for it at this time.
 305          */
 306         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 307         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 308                            !(filter_flags & FIF_FCSFAIL));
 309         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 310                            !(filter_flags & FIF_PLCPFAIL));
 311         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 312                            !(filter_flags & FIF_CONTROL));
 313         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 314                            !(filter_flags & FIF_PROMISC_IN_BSS));
 315         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 316                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 317                            !rt2x00dev->intf_ap_count);
 318         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 319         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 320 }
 321
 322 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 323                                   struct rt2x00_intf *intf,
 324                                   struct rt2x00intf_conf *conf,
 325                                   const unsigned int flags)
 326 {
 327         unsigned int bcn_preload;
 328         u32 reg;
 329
 330         if (flags & CONFIG_UPDATE_TYPE) {
 331                 /*
 332                  * Enable beacon config
 333                  */
 334                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 335                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 336                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 337                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 338
 339                 /*
 340                  * Enable synchronisation.
 341                  */
 342                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 343                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 344                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 345                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 346                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 347         }
 348
 349         if (flags & CONFIG_UPDATE_MAC)
 350                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 351                                               conf->mac, sizeof(conf->mac));
 352
 353         if (flags & CONFIG_UPDATE_BSSID)
 354                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 355                                               conf->bssid, sizeof(conf->bssid));
 356 }
 357
 358 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 359                                  struct rt2x00lib_erp *erp)
 360 {
 361         int preamble_mask;
 362         u32 reg;
 363
 364         /*
 365          * When short preamble is enabled, we should set bit 0x08
 366          */
 367         preamble_mask = erp->short_preamble << 3;
 368
 369         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 370         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 371                            erp->ack_timeout);
 372         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 373                            erp->ack_consume_time);
 374         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 375
 376         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 377         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 378         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 379         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 380         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 381
 382         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 383         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 384         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 385         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 386         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 387
 388         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 389         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 390         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 391         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 392         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 393
 394         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 395         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 396         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 397         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 398         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 399 }
 400
 401 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 402                                      const int basic_rate_mask)
 403 {
 404         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 405 }
 406
 407 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 408                                      struct rf_channel *rf)
 409 {
 410         /*
 411          * Switch on tuning bits.
 412          */
 413         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 414         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 415
 416         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 417         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 418         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 419
 420         /*
 421          * RF2420 chipset don't need any additional actions.
 422          */
 423         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 424                 return;
 425
 426         /*
 427          * For the RT2421 chipsets we need to write an invalid
 428          * reference clock rate to activate auto_tune.
 429          * After that we set the value back to the correct channel.
 430          */
 431         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 432         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 433         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 434
 435         msleep(1);
 436
 437         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 438         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 439         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 440
 441         msleep(1);
 442
 443         /*
 444          * Switch off tuning bits.
 445          */
 446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 448
 449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 450         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 451
 452         /*
 453          * Clear false CRC during channel switch.
 454          */
 455         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 456 }
 457
 458 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 459 {
 460         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 461 }
 462
 463 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 464                                      struct antenna_setup *ant)
 465 {
 466         u8 r1;
 467         u8 r4;
 468
 469         /*
 470          * We should never come here because rt2x00lib is supposed
 471          * to catch this and send us the correct antenna explicitely.
 472          */
 473         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 474                ant->tx == ANTENNA_SW_DIVERSITY);
 475
 476         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 477         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 478
 479         /*
 480          * Configure the TX antenna.
 481          */
 482         switch (ant->tx) {
 483         case ANTENNA_HW_DIVERSITY:
 484                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 485                 break;
 486         case ANTENNA_A:
 487                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 488                 break;
 489         case ANTENNA_B:
 490         default:
 491                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 492                 break;
 493         }
 494
 495         /*
 496          * Configure the RX antenna.
 497          */
 498         switch (ant->rx) {
 499         case ANTENNA_HW_DIVERSITY:
 500                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 501                 break;
 502         case ANTENNA_A:
 503                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 504                 break;
 505         case ANTENNA_B:
 506         default:
 507                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 508                 break;
 509         }
 510
 511         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 512         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 513 }
 514
 515 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 516                                       struct rt2x00lib_conf *libconf)
 517 {
 518         u32 reg;
 519
 520         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 521         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 522         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 523
 524         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 525         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 526         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 527         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 528
 529         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 530         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 531         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 532         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 533
 534         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 535         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 536         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 537         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 538
 539         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 540         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 541                            libconf->conf->beacon_int * 16);
 542         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 543                            libconf->conf->beacon_int * 16);
 544         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 545 }
 546
 547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 548                              struct rt2x00lib_conf *libconf,
 549                              const unsigned int flags)
 550 {
 551         if (flags & CONFIG_UPDATE_PHYMODE)
 552                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 553         if (flags & CONFIG_UPDATE_CHANNEL)
 554                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 555         if (flags & CONFIG_UPDATE_TXPOWER)
 556                 rt2400pci_config_txpower(rt2x00dev,
 557                                          libconf->conf->power_level);
 558         if (flags & CONFIG_UPDATE_ANTENNA)
 559                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 560         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 561                 rt2400pci_config_duration(rt2x00dev, libconf);
 562 }
 563
 564 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 565                                 const int cw_min, const int cw_max)
 566 {
 567         u32 reg;
 568
 569         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 570         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 571         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 572         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 573 }
 574
 575 /*
 576  * Link tuning
 577  */
 578 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 579                                  struct link_qual *qual)
 580 {
 581         u32 reg;
 582         u8 bbp;
 583
 584         /*
 585          * Update FCS error count from register.
 586          */
 587         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 588         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 589
 590         /*
 591          * Update False CCA count from register.
 592          */
 593         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 594         qual->false_cca = bbp;
 595 }
 596
 597 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 598 {
 599         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 600         rt2x00dev->link.vgc_level = 0x08;
 601 }
 602
 603 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 604 {
 605         u8 reg;
 606
 607         /*
 608          * The link tuner should not run longer then 60 seconds,
 609          * and should run once every 2 seconds.
 610          */
 611         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 612                 return;
 613
 614         /*
 615          * Base r13 link tuning on the false cca count.
 616          */
 617         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 618
 619         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 620                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 621                 rt2x00dev->link.vgc_level = reg;
 622         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 623                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 624                 rt2x00dev->link.vgc_level = reg;
 625         }
 626 }
 627
 628 /*
 629  * Initialization functions.
 630  */
 631 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 632                                    struct queue_entry *entry)
 633 {
 634         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 635         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 636         u32 word;
 637
 638         rt2x00_desc_read(entry_priv->desc, 2, &word);
 639         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 640         rt2x00_desc_write(entry_priv->desc, 2, word);
 641
 642         rt2x00_desc_read(entry_priv->desc, 1, &word);
 643         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 644         rt2x00_desc_write(entry_priv->desc, 1, word);
 645
 646         rt2x00_desc_read(entry_priv->desc, 0, &word);
 647         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 648         rt2x00_desc_write(entry_priv->desc, 0, word);
 649 }
 650
 651 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 652                                    struct queue_entry *entry)
 653 {
 654         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 655         u32 word;
 656
 657         rt2x00_desc_read(entry_priv->desc, 0, &word);
 658         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 659         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 660         rt2x00_desc_write(entry_priv->desc, 0, word);
 661 }
 662
 663 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 664 {
 665         struct queue_entry_priv_pci *entry_priv;
 666         u32 reg;
 667
 668         /*
 669          * Initialize registers.
 670          */
 671         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 672         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 673         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 674         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 675         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 676         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 677
 678         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 679         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 680         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 681                            entry_priv->desc_dma);
 682         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 683
 684         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 685         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 686         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 687                            entry_priv->desc_dma);
 688         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 689
 690         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 691         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 692         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 693                            entry_priv->desc_dma);
 694         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 695
 696         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 697         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 698         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 699                            entry_priv->desc_dma);
 700         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 701
 702         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 703         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 704         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 705         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 706
 707         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 708         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 709         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 710                            entry_priv->desc_dma);
 711         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 712
 713         return 0;
 714 }
 715
 716 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 717 {
 718         u32 reg;
 719
 720         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 721         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 722         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 723         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 724
 725         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 726         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 727         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 728         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 729         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 730
 731         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 732         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 733                            (rt2x00dev->rx->data_size / 128));
 734         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 735
 736         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 737         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 738         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 739         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 740         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 741         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 742         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 743         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 744         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 745         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 746
 747         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 748
 749         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 750         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 751         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 752         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 753         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 754         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 755
 756         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 757         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 758         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 761         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 762         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 763         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 764
 765         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 766
 767         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 768                 return -EBUSY;
 769
 770         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 771         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 772
 773         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 774         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 775         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 776
 777         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 778         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 779         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 780         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 781         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 782         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 783
 784         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 785         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 786         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 787         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 788         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 789
 790         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 791         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 792         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 793         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 794
 795         /*
 796          * We must clear the FCS and FIFO error count.
 797          * These registers are cleared on read,
 798          * so we may pass a useless variable to store the value.
 799          */
 800         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 801         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 802
 803         return 0;
 804 }
 805
 806 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 807 {
 808         unsigned int i;
 809         u8 value;
 810
 811         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 812                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 813                 if ((value != 0xff) && (value != 0x00))
 814                         return 0;
 815                 udelay(REGISTER_BUSY_DELAY);
 816         }
 817
 818         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 819         return -EACCES;
 820 }
 821
 822 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 823 {
 824         unsigned int i;
 825         u16 eeprom;
 826         u8 reg_id;
 827         u8 value;
 828
 829         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 830                 return -EACCES;
 831
 832         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 833         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 834         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 835         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 836         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 837         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 838         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 839         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 840         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 841         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 842         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 843         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 844         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 845         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 846
 847         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 848                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 849
 850                 if (eeprom != 0xffff && eeprom != 0x0000) {
 851                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 852                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 853                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 854                 }
 855         }
 856
 857         return 0;
 858 }
 859
 860 /*
 861  * Device state switch handlers.
 862  */
 863 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 864                                 enum dev_state state)
 865 {
 866         u32 reg;
 867
 868         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 869         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 870                            (state == STATE_RADIO_RX_OFF) ||
 871                            (state == STATE_RADIO_RX_OFF_LINK));
 872         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 873 }
 874
 875 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 876                                  enum dev_state state)
 877 {
 878         int mask = (state == STATE_RADIO_IRQ_OFF);
 879         u32 reg;
 880
 881         /*
 882          * When interrupts are being enabled, the interrupt registers
 883          * should clear the register to assure a clean state.
 884          */
 885         if (state == STATE_RADIO_IRQ_ON) {
 886                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 887                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 888         }
 889
 890         /*
 891          * Only toggle the interrupts bits we are going to use.
 892          * Non-checked interrupt bits are disabled by default.
 893          */
 894         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 895         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 896         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 897         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 898         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 899         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 900         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 901 }
 902
 903 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 904 {
 905         /*
 906          * Initialize all registers.
 907          */
 908         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 909                      rt2400pci_init_registers(rt2x00dev) ||
 910                      rt2400pci_init_bbp(rt2x00dev)))
 911                 return -EIO;
 912
 913         return 0;
 914 }
 915
 916 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 917 {
 918         u32 reg;
 919
 920         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 921
 922         /*
 923          * Disable synchronisation.
 924          */
 925         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 926
 927         /*
 928          * Cancel RX and TX.
 929          */
 930         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 931         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 932         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 933 }
 934
 935 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 936                                enum dev_state state)
 937 {
 938         u32 reg;
 939         unsigned int i;
 940         char put_to_sleep;
 941         char bbp_state;
 942         char rf_state;
 943
 944         put_to_sleep = (state != STATE_AWAKE);
 945
 946         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 947         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 948         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 949         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 950         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 951         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 952
 953         /*
 954          * Device is not guaranteed to be in the requested state yet.
 955          * We must wait until the register indicates that the
 956          * device has entered the correct state.
 957          */
 958         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 959                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 960                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 961                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 962                 if (bbp_state == state && rf_state == state)
 963                         return 0;
 964                 msleep(10);
 965         }
 966
 967         return -EBUSY;
 968 }
 969
 970 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 971                                       enum dev_state state)
 972 {
 973         int retval = 0;
 974
 975         switch (state) {
 976         case STATE_RADIO_ON:
 977                 retval = rt2400pci_enable_radio(rt2x00dev);
 978                 break;
 979         case STATE_RADIO_OFF:
 980                 rt2400pci_disable_radio(rt2x00dev);
 981                 break;
 982         case STATE_RADIO_RX_ON:
 983         case STATE_RADIO_RX_ON_LINK:
 984         case STATE_RADIO_RX_OFF:
 985         case STATE_RADIO_RX_OFF_LINK:
 986                 rt2400pci_toggle_rx(rt2x00dev, state);
 987                 break;
 988         case STATE_RADIO_IRQ_ON:
 989         case STATE_RADIO_IRQ_OFF:
 990                 rt2400pci_toggle_irq(rt2x00dev, state);
 991                 break;
 992         case STATE_DEEP_SLEEP:
 993         case STATE_SLEEP:
 994         case STATE_STANDBY:
 995         case STATE_AWAKE:
 996                 retval = rt2400pci_set_state(rt2x00dev, state);
 997                 break;
 998         default:
 999                 retval = -ENOTSUPP;
1000                 break;
1001         }
1002
1003         if (unlikely(retval))
1004                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1005                       state, retval);
1006
1007         return retval;
1008 }
1009
1010 /*
1011  * TX descriptor initialization
1012  */
1013 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1014                                     struct sk_buff *skb,
1015                                     struct txentry_desc *txdesc)
1016 {
1017         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1018         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1019         __le32 *txd = skbdesc->desc;
1020         u32 word;
1021
1022         /*
1023          * Start writing the descriptor words.
1024          */
1025         rt2x00_desc_read(entry_priv->desc, 1, &word);
1026         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1027         rt2x00_desc_write(entry_priv->desc, 1, word);
1028
1029         rt2x00_desc_read(txd, 2, &word);
1030         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1031         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1032         rt2x00_desc_write(txd, 2, word);
1033
1034         rt2x00_desc_read(txd, 3, &word);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1036         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1037         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1038         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1039         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1040         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1041         rt2x00_desc_write(txd, 3, word);
1042
1043         rt2x00_desc_read(txd, 4, &word);
1044         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1045         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1046         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1047         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1048         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1049         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1050         rt2x00_desc_write(txd, 4, word);
1051
1052         rt2x00_desc_read(txd, 0, &word);
1053         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1054         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1055         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1056                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1057         rt2x00_set_field32(&word, TXD_W0_ACK,
1058                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1059         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1060                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1061         rt2x00_set_field32(&word, TXD_W0_RTS,
1062                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1063         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1064         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1065                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1066         rt2x00_desc_write(txd, 0, word);
1067 }
1068
1069 /*
1070  * TX data initialization
1071  */
1072 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1073                                     const enum data_queue_qid queue)
1074 {
1075         u32 reg;
1076
1077         if (queue == QID_BEACON) {
1078                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1079                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1080                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1081                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1082                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1083                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1084                 }
1085                 return;
1086         }
1087
1088         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1089         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1090         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1091         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1092         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1093 }
1094
1095 /*
1096  * RX control handlers
1097  */
1098 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1099                                   struct rxdone_entry_desc *rxdesc)
1100 {
1101         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1102         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1103         u32 word0;
1104         u32 word2;
1105         u32 word3;
1106         u32 word4;
1107         u64 tsf;
1108         u32 rx_low;
1109         u32 rx_high;
1110
1111         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1112         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1113         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1114         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1115
1116         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1117                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1118         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1119                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1120
1121         /*
1122          * We only get the lower 32bits from the timestamp,
1123          * to get the full 64bits we must complement it with
1124          * the timestamp from get_tsf().
1125          * Note that when a wraparound of the lower 32bits
1126          * has occurred between the frame arrival and the get_tsf()
1127          * call, we must decrease the higher 32bits with 1 to get
1128          * to correct value.
1129          */
1130         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1131         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1132         rx_high = upper_32_bits(tsf);
1133
1134         if ((u32)tsf <= rx_low)
1135                 rx_high--;
1136
1137         /*
1138          * Obtain the status about this packet.
1139          * The signal is the PLCP value, and needs to be stripped
1140          * of the preamble bit (0x08).
1141          */
1142         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1143         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1144         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1145             entry->queue->rt2x00dev->rssi_offset;
1146         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1147
1148         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1149         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1150                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1151 }
1152
1153 /*
1154  * Interrupt functions.
1155  */
1156 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1157                              const enum data_queue_qid queue_idx)
1158 {
1159         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1160         struct queue_entry_priv_pci *entry_priv;
1161         struct queue_entry *entry;
1162         struct txdone_entry_desc txdesc;
1163         u32 word;
1164
1165         while (!rt2x00queue_empty(queue)) {
1166                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1167                 entry_priv = entry->priv_data;
1168                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1169
1170                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1171                     !rt2x00_get_field32(word, TXD_W0_VALID))
1172                         break;
1173
1174                 /*
1175                  * Obtain the status about this packet.
1176                  */
1177                 txdesc.flags = 0;
1178                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1179                 case 0: /* Success */
1180                 case 1: /* Success with retry */
1181                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1182                         break;
1183                 case 2: /* Failure, excessive retries */
1184                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1185                         /* Don't break, this is a failed frame! */
1186                 default: /* Failure */
1187                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1188                 }
1189                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1190
1191                 rt2x00lib_txdone(entry, &txdesc);
1192         }
1193 }
1194
1195 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1196 {
1197         struct rt2x00_dev *rt2x00dev = dev_instance;
1198         u32 reg;
1199
1200         /*
1201          * Get the interrupt sources & saved to local variable.
1202          * Write register value back to clear pending interrupts.
1203          */
1204         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1205         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1206
1207         if (!reg)
1208                 return IRQ_NONE;
1209
1210         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1211                 return IRQ_HANDLED;
1212
1213         /*
1214          * Handle interrupts, walk through all bits
1215          * and run the tasks, the bits are checked in order of
1216          * priority.
1217          */
1218
1219         /*
1220          * 1 - Beacon timer expired interrupt.
1221          */
1222         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1223                 rt2x00lib_beacondone(rt2x00dev);
1224
1225         /*
1226          * 2 - Rx ring done interrupt.
1227          */
1228         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1229                 rt2x00pci_rxdone(rt2x00dev);
1230
1231         /*
1232          * 3 - Atim ring transmit done interrupt.
1233          */
1234         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1235                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1236
1237         /*
1238          * 4 - Priority ring transmit done interrupt.
1239          */
1240         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1241                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1242
1243         /*
1244          * 5 - Tx ring transmit done interrupt.
1245          */
1246         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1247                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1248
1249         return IRQ_HANDLED;
1250 }
1251
1252 /*
1253  * Device probe functions.
1254  */
1255 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1256 {
1257         struct eeprom_93cx6 eeprom;
1258         u32 reg;
1259         u16 word;
1260         u8 *mac;
1261
1262         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1263
1264         eeprom.data = rt2x00dev;
1265         eeprom.register_read = rt2400pci_eepromregister_read;
1266         eeprom.register_write = rt2400pci_eepromregister_write;
1267         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1268             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1269         eeprom.reg_data_in = 0;
1270         eeprom.reg_data_out = 0;
1271         eeprom.reg_data_clock = 0;
1272         eeprom.reg_chip_select = 0;
1273
1274         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1275                                EEPROM_SIZE / sizeof(u16));
1276
1277         /*
1278          * Start validation of the data that has been read.
1279          */
1280         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1281         if (!is_valid_ether_addr(mac)) {
1282                 DECLARE_MAC_BUF(macbuf);
1283
1284                 random_ether_addr(mac);
1285                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1286         }
1287
1288         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1289         if (word == 0xffff) {
1290                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1291                 return -EINVAL;
1292         }
1293
1294         return 0;
1295 }
1296
1297 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1298 {
1299         u32 reg;
1300         u16 value;
1301         u16 eeprom;
1302
1303         /*
1304          * Read EEPROM word for configuration.
1305          */
1306         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1307
1308         /*
1309          * Identify RF chipset.
1310          */
1311         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1312         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1313         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1314
1315         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1316             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1317                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1318                 return -ENODEV;
1319         }
1320
1321         /*
1322          * Identify default antenna configuration.
1323          */
1324         rt2x00dev->default_ant.tx =
1325             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1326         rt2x00dev->default_ant.rx =
1327             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1328
1329         /*
1330          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1331          * I am not 100% sure about this, but the legacy drivers do not
1332          * indicate antenna swapping in software is required when
1333          * diversity is enabled.
1334          */
1335         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1336                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1337         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1338                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1339
1340         /*
1341          * Store led mode, for correct led behaviour.
1342          */
1343 #ifdef CONFIG_RT2400PCI_LEDS
1344         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1345
1346         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1347         if (value == LED_MODE_TXRX_ACTIVITY)
1348                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1349                                    LED_TYPE_ACTIVITY);
1350 #endif /* CONFIG_RT2400PCI_LEDS */
1351
1352         /*
1353          * Detect if this device has an hardware controlled radio.
1354          */
1355 #ifdef CONFIG_RT2400PCI_RFKILL
1356         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1357                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1358 #endif /* CONFIG_RT2400PCI_RFKILL */
1359
1360         /*
1361          * Check if the BBP tuning should be enabled.
1362          */
1363         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1364                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1365
1366         return 0;
1367 }
1368
1369 /*
1370  * RF value list for RF2420 & RF2421
1371  * Supports: 2.4 GHz
1372  */
1373 static const struct rf_channel rf_vals_bg[] = {
1374         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1375         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1376         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1377         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1378         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1379         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1380         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1381         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1382         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1383         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1384         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1385         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1386         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1387         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1388 };
1389
1390 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1391 {
1392         struct hw_mode_spec *spec = &rt2x00dev->spec;
1393         u8 *txpower;
1394         unsigned int i;
1395
1396         /*
1397          * Initialize all hw fields.
1398          */
1399         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1400                                IEEE80211_HW_SIGNAL_DBM;
1401         rt2x00dev->hw->extra_tx_headroom = 0;
1402
1403         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1404         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1405                                 rt2x00_eeprom_addr(rt2x00dev,
1406                                                    EEPROM_MAC_ADDR_0));
1407
1408         /*
1409          * Convert tx_power array in eeprom.
1410          */
1411         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1412         for (i = 0; i < 14; i++)
1413                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1414
1415         /*
1416          * Initialize hw_mode information.
1417          */
1418         spec->supported_bands = SUPPORT_BAND_2GHZ;
1419         spec->supported_rates = SUPPORT_RATE_CCK;
1420         spec->tx_power_a = NULL;
1421         spec->tx_power_bg = txpower;
1422         spec->tx_power_default = DEFAULT_TXPOWER;
1423
1424         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1425         spec->channels = rf_vals_bg;
1426 }
1427
1428 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1429 {
1430         int retval;
1431
1432         /*
1433          * Allocate eeprom data.
1434          */
1435         retval = rt2400pci_validate_eeprom(rt2x00dev);
1436         if (retval)
1437                 return retval;
1438
1439         retval = rt2400pci_init_eeprom(rt2x00dev);
1440         if (retval)
1441                 return retval;
1442
1443         /*
1444          * Initialize hw specifications.
1445          */
1446         rt2400pci_probe_hw_mode(rt2x00dev);
1447
1448         /*
1449          * This device requires the atim queue and DMA-mapped skbs.
1450          */
1451         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1452         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1453
1454         /*
1455          * Set the rssi offset.
1456          */
1457         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1458
1459         return 0;
1460 }
1461
1462 /*
1463  * IEEE80211 stack callback functions.
1464  */
1465 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1466                                      u32 short_retry, u32 long_retry)
1467 {
1468         struct rt2x00_dev *rt2x00dev = hw->priv;
1469         u32 reg;
1470
1471         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1472         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1473         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1474         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1475
1476         return 0;
1477 }
1478
1479 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1480                              const struct ieee80211_tx_queue_params *params)
1481 {
1482         struct rt2x00_dev *rt2x00dev = hw->priv;
1483
1484         /*
1485          * We don't support variating cw_min and cw_max variables
1486          * per queue. So by default we only configure the TX queue,
1487          * and ignore all other configurations.
1488          */
1489         if (queue != 0)
1490                 return -EINVAL;
1491
1492         if (rt2x00mac_conf_tx(hw, queue, params))
1493                 return -EINVAL;
1494
1495         /*
1496          * Write configuration to register.
1497          */
1498         rt2400pci_config_cw(rt2x00dev,
1499                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1500
1501         return 0;
1502 }
1503
1504 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1505 {
1506         struct rt2x00_dev *rt2x00dev = hw->priv;
1507         u64 tsf;
1508         u32 reg;
1509
1510         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1511         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1512         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1513         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1514
1515         return tsf;
1516 }
1517
1518 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1519 {
1520         struct rt2x00_dev *rt2x00dev = hw->priv;
1521         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1522         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1523         struct queue_entry_priv_pci *entry_priv;
1524         struct skb_frame_desc *skbdesc;
1525         struct txentry_desc txdesc;
1526         u32 reg;
1527
1528         if (unlikely(!intf->beacon))
1529                 return -ENOBUFS;
1530         entry_priv = intf->beacon->priv_data;
1531
1532         /*
1533          * Copy all TX descriptor information into txdesc,
1534          * after that we are free to use the skb->cb array
1535          * for our information.
1536          */
1537         intf->beacon->skb = skb;
1538         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1539
1540         /*
1541          * Fill in skb descriptor
1542          */
1543         skbdesc = get_skb_frame_desc(skb);
1544         memset(skbdesc, 0, sizeof(*skbdesc));
1545         skbdesc->desc = entry_priv->desc;
1546         skbdesc->desc_len = intf->beacon->queue->desc_size;
1547         skbdesc->entry = intf->beacon;
1548
1549         /*
1550          * Disable beaconing while we are reloading the beacon data,
1551          * otherwise we might be sending out invalid data.
1552          */
1553         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1554         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1555         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1556         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1557         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1558
1559         /*
1560          * Enable beacon generation.
1561          * Write entire beacon with descriptor to register,
1562          * and kick the beacon generator.
1563          */
1564         rt2x00queue_map_txskb(rt2x00dev, intf->beacon->skb);
1565         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1566         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1567
1568         return 0;
1569 }
1570
1571 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1572 {
1573         struct rt2x00_dev *rt2x00dev = hw->priv;
1574         u32 reg;
1575
1576         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1577         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1578 }
1579
1580 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1581         .tx                     = rt2x00mac_tx,
1582         .start                  = rt2x00mac_start,
1583         .stop                   = rt2x00mac_stop,
1584         .add_interface          = rt2x00mac_add_interface,
1585         .remove_interface       = rt2x00mac_remove_interface,
1586         .config                 = rt2x00mac_config,
1587         .config_interface       = rt2x00mac_config_interface,
1588         .configure_filter       = rt2x00mac_configure_filter,
1589         .get_stats              = rt2x00mac_get_stats,
1590         .set_retry_limit        = rt2400pci_set_retry_limit,
1591         .bss_info_changed       = rt2x00mac_bss_info_changed,
1592         .conf_tx                = rt2400pci_conf_tx,
1593         .get_tx_stats           = rt2x00mac_get_tx_stats,
1594         .get_tsf                = rt2400pci_get_tsf,
1595         .beacon_update          = rt2400pci_beacon_update,
1596         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1597 };
1598
1599 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1600         .irq_handler            = rt2400pci_interrupt,
1601         .probe_hw               = rt2400pci_probe_hw,
1602         .initialize             = rt2x00pci_initialize,
1603         .uninitialize           = rt2x00pci_uninitialize,
1604         .init_rxentry           = rt2400pci_init_rxentry,
1605         .init_txentry           = rt2400pci_init_txentry,
1606         .set_device_state       = rt2400pci_set_device_state,
1607         .rfkill_poll            = rt2400pci_rfkill_poll,
1608         .link_stats             = rt2400pci_link_stats,
1609         .reset_tuner            = rt2400pci_reset_tuner,
1610         .link_tuner             = rt2400pci_link_tuner,
1611         .write_tx_desc          = rt2400pci_write_tx_desc,
1612         .write_tx_data          = rt2x00pci_write_tx_data,
1613         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1614         .fill_rxdone            = rt2400pci_fill_rxdone,
1615         .config_filter          = rt2400pci_config_filter,
1616         .config_intf            = rt2400pci_config_intf,
1617         .config_erp             = rt2400pci_config_erp,
1618         .config                 = rt2400pci_config,
1619 };
1620
1621 static const struct data_queue_desc rt2400pci_queue_rx = {
1622         .entry_num              = RX_ENTRIES,
1623         .data_size              = DATA_FRAME_SIZE,
1624         .desc_size              = RXD_DESC_SIZE,
1625         .priv_size              = sizeof(struct queue_entry_priv_pci),
1626 };
1627
1628 static const struct data_queue_desc rt2400pci_queue_tx = {
1629         .entry_num              = TX_ENTRIES,
1630         .data_size              = DATA_FRAME_SIZE,
1631         .desc_size              = TXD_DESC_SIZE,
1632         .priv_size              = sizeof(struct queue_entry_priv_pci),
1633 };
1634
1635 static const struct data_queue_desc rt2400pci_queue_bcn = {
1636         .entry_num              = BEACON_ENTRIES,
1637         .data_size              = MGMT_FRAME_SIZE,
1638         .desc_size              = TXD_DESC_SIZE,
1639         .priv_size              = sizeof(struct queue_entry_priv_pci),
1640 };
1641
1642 static const struct data_queue_desc rt2400pci_queue_atim = {
1643         .entry_num              = ATIM_ENTRIES,
1644         .data_size              = DATA_FRAME_SIZE,
1645         .desc_size              = TXD_DESC_SIZE,
1646         .priv_size              = sizeof(struct queue_entry_priv_pci),
1647 };
1648
1649 static const struct rt2x00_ops rt2400pci_ops = {
1650         .name           = KBUILD_MODNAME,
1651         .max_sta_intf   = 1,
1652         .max_ap_intf    = 1,
1653         .eeprom_size    = EEPROM_SIZE,
1654         .rf_size        = RF_SIZE,
1655         .tx_queues      = NUM_TX_QUEUES,
1656         .rx             = &rt2400pci_queue_rx,
1657         .tx             = &rt2400pci_queue_tx,
1658         .bcn            = &rt2400pci_queue_bcn,
1659         .atim           = &rt2400pci_queue_atim,
1660         .lib            = &rt2400pci_rt2x00_ops,
1661         .hw             = &rt2400pci_mac80211_ops,
1662 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1663         .debugfs        = &rt2400pci_rt2x00debug,
1664 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1665 };
1666
1667 /*
1668  * RT2400pci module information.
1669  */
1670 static struct pci_device_id rt2400pci_device_table[] = {
1671         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1672         { 0, }
1673 };
1674
1675 MODULE_AUTHOR(DRV_PROJECT);
1676 MODULE_VERSION(DRV_VERSION);
1677 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1678 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1679 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1680 MODULE_LICENSE("GPL");
1681
1682 static struct pci_driver rt2400pci_driver = {
1683         .name           = KBUILD_MODNAME,
1684         .id_table       = rt2400pci_device_table,
1685         .probe          = rt2x00pci_probe,
1686         .remove         = __devexit_p(rt2x00pci_remove),
1687         .suspend        = rt2x00pci_suspend,
1688         .resume         = rt2x00pci_resume,
1689 };
1690
1691 static int __init rt2400pci_init(void)
1692 {
1693         return pci_register_driver(&rt2400pci_driver);
1694 }
1695
1696 static void __exit rt2400pci_exit(void)
1697 {
1698         pci_unregister_driver(&rt2400pci_driver);
1699 }
1700
1701 module_init(rt2400pci_init);
1702 module_exit(rt2400pci_exit);