1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
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43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
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48 * from this software without specific prior written permission.
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
64 #include "iwl-trans.h"
66 #include "iwl-helpers.h"
67 /*TODO remove uneeded includes when the transport layer tx_free will be here */
70 static int iwl_trans_rx_alloc(struct iwl_priv *priv)
72 struct iwl_rx_queue *rxq = &priv->rxq;
73 struct device *dev = priv->bus.dev;
75 memset(&priv->rxq, 0, sizeof(priv->rxq));
77 spin_lock_init(&rxq->lock);
78 INIT_LIST_HEAD(&rxq->rx_free);
79 INIT_LIST_HEAD(&rxq->rx_used);
81 if (WARN_ON(rxq->bd || rxq->rb_stts))
84 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
85 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
86 &rxq->bd_dma, GFP_KERNEL);
89 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
91 /*Allocate the driver's pointer to receive buffer status */
92 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
93 &rxq->rb_stts_dma, GFP_KERNEL);
96 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
101 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
102 rxq->bd, rxq->bd_dma);
103 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
109 static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv *priv)
111 struct iwl_rx_queue *rxq = &priv->rxq;
114 /* Fill the rx_used queue with _all_ of the Rx buffers */
115 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
116 /* In the reset function, these buffers may have been allocated
117 * to an SKB, so we need to unmap and free potential storage */
118 if (rxq->pool[i].page != NULL) {
119 dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma,
120 PAGE_SIZE << priv->hw_params.rx_page_order,
122 __iwl_free_pages(priv, rxq->pool[i].page);
123 rxq->pool[i].page = NULL;
125 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
129 static int iwl_trans_rx_init(struct iwl_priv *priv)
131 struct iwl_rx_queue *rxq = &priv->rxq;
136 err = iwl_trans_rx_alloc(priv);
141 spin_lock_irqsave(&rxq->lock, flags);
142 INIT_LIST_HEAD(&rxq->rx_free);
143 INIT_LIST_HEAD(&rxq->rx_used);
145 iwl_trans_rxq_free_rx_bufs(priv);
147 for (i = 0; i < RX_QUEUE_SIZE; i++)
148 rxq->queue[i] = NULL;
150 /* Set us so that we have processed and used all buffers, but have
151 * not restocked the Rx queue with fresh buffers */
152 rxq->read = rxq->write = 0;
153 rxq->write_actual = 0;
155 spin_unlock_irqrestore(&rxq->lock, flags);
160 static void iwl_trans_rx_free(struct iwl_priv *priv)
162 struct iwl_rx_queue *rxq = &priv->rxq;
165 /*if rxq->bd is NULL, it means that nothing has been allocated,
168 IWL_DEBUG_INFO(priv, "Free NULL rx context\n");
172 spin_lock_irqsave(&rxq->lock, flags);
173 iwl_trans_rxq_free_rx_bufs(priv);
174 spin_unlock_irqrestore(&rxq->lock, flags);
176 dma_free_coherent(priv->bus.dev, sizeof(__le32) * RX_QUEUE_SIZE,
177 rxq->bd, rxq->bd_dma);
178 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
182 dma_free_coherent(priv->bus.dev,
183 sizeof(struct iwl_rb_status),
184 rxq->rb_stts, rxq->rb_stts_dma);
186 IWL_DEBUG_INFO(priv, "Free rxq->rb_stts which is NULL\n");
187 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
191 /* TODO:remove this code duplication */
192 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
193 struct iwl_dma_ptr *ptr, size_t size)
195 if (WARN_ON(ptr->addr))
198 ptr->addr = dma_alloc_coherent(priv->bus.dev, size,
199 &ptr->dma, GFP_KERNEL);
206 static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
207 int slots_num, u32 txq_id)
209 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
212 if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
215 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
217 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
220 if (!txq->meta || !txq->cmd)
223 for (i = 0; i < slots_num; i++) {
224 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
230 /* Alloc driver data array and TFD circular buffer */
231 /* Driver private data, only for Tx (not command) queues,
232 * not shared with device. */
233 if (txq_id != priv->cmd_queue) {
234 txq->txb = kzalloc(sizeof(txq->txb[0]) *
235 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
237 IWL_ERR(priv, "kmalloc for auxiliary BD "
238 "structures failed\n");
245 /* Circular buffer of transmit frame descriptors (TFDs),
246 * shared with device */
247 txq->tfds = dma_alloc_coherent(priv->bus.dev, tfd_sz, &txq->q.dma_addr,
250 IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
259 /* since txq->cmd has been zeroed,
260 * all non allocated cmd[i] will be NULL */
262 for (i = 0; i < slots_num; i++)
273 static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
274 int slots_num, u32 txq_id)
278 txq->need_update = 0;
279 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
282 * For the default queues 0-3, set up the swq_id
283 * already -- all others need to get one later
284 * (if they need one at all).
287 iwl_set_swq_id(txq, txq_id, txq_id);
289 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
290 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
291 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
293 /* Initialize queue's high/low-water marks, and head/tail indexes */
294 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
300 * Tell nic where to find circular buffer of Tx Frame Descriptors for
301 * given Tx queue, and enable the DMA channel used for that queue.
302 * Circular buffer (TFD queue in DRAM) physical base address */
303 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
304 txq->q.dma_addr >> 8);
310 * iwl_trans_tx_alloc - allocate TX context
311 * Allocate all Tx DMA structures and initialize them
316 static int iwl_trans_tx_alloc(struct iwl_priv *priv)
319 int txq_id, slots_num;
321 /*It is not allowed to alloc twice, so warn when this happens.
322 * We cannot rely on the previous allocation, so free and fail */
323 if (WARN_ON(priv->txq)) {
328 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
329 priv->hw_params.scd_bc_tbls_size);
331 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
335 /* Alloc keep-warm buffer */
336 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
338 IWL_ERR(priv, "Keep Warm allocation failed\n");
342 priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
343 priv->cfg->base_params->num_of_queues, GFP_KERNEL);
345 IWL_ERR(priv, "Not enough memory for txq\n");
350 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
351 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
352 slots_num = (txq_id == priv->cmd_queue) ?
353 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
354 ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
357 IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
365 iwlagn_hw_txq_ctx_free(priv);
369 static int iwl_trans_tx_init(struct iwl_priv *priv)
372 int txq_id, slots_num;
377 ret = iwl_trans_tx_alloc(priv);
383 spin_lock_irqsave(&priv->lock, flags);
385 /* Turn off all Tx DMA fifos */
386 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, 0);
388 /* Tell NIC where to find the "keep warm" buffer */
389 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
391 spin_unlock_irqrestore(&priv->lock, flags);
393 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
394 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
395 slots_num = (txq_id == priv->cmd_queue) ?
396 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
397 ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
400 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
407 /*Upon error, free only if we allocated something */
409 iwlagn_hw_txq_ctx_free(priv);
413 static const struct iwl_trans_ops trans_ops = {
414 .rx_init = iwl_trans_rx_init,
415 .rx_free = iwl_trans_rx_free,
417 .tx_init = iwl_trans_tx_init,
420 void iwl_trans_register(struct iwl_trans *trans)
422 trans->ops = &trans_ops;