drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 /*TODO: Remove include to iwl-core.h*/
  34 #include "iwl-core.h"
  35 #include "iwl-io.h"
  36 #include "iwl-trans-pcie-int.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  85  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  86  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  87  *   were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rx_queue_alloc()   Allocates rx_free
  93  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_rx_queue_restock
  95  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_rx_queue_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /**
 111  * iwl_rx_queue_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 114 {
 115         int s = q->read - q->write;
 116         if (s <= 0)
 117                 s += RX_QUEUE_SIZE;
 118         /* keep some buffer to not confuse full and empty queue */
 119         s -= 2;
 120         if (s < 0)
 121                 s = 0;
 122         return s;
 123 }
 124
 125 /**
 126  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 127  */
 128 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 129                         struct iwl_rx_queue *q)
 130 {
 131         unsigned long flags;
 132         u32 reg;
 133
 134         spin_lock_irqsave(&q->lock, flags);
 135
 136         if (q->need_update == 0)
 137                 goto exit_unlock;
 138
 139         if (hw_params(trans).shadow_reg_enable) {
 140                 /* shadow register enabled */
 141                 /* Device expects a multiple of 8 */
 142                 q->write_actual = (q->write & ~0x7);
 143                 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
 144         } else {
 145                 /* If power-saving is in use, make sure device is awake */
 146                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 147                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 148
 149                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 150                                 IWL_DEBUG_INFO(trans,
 151                                         "Rx queue requesting wakeup,"
 152                                         " GP1 = 0x%x\n", reg);
 153                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 154                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 155                                 goto exit_unlock;
 156                         }
 157
 158                         q->write_actual = (q->write & ~0x7);
 159                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 160                                         q->write_actual);
 161
 162                 /* Else device is assumed to be awake */
 163                 } else {
 164                         /* Device expects a multiple of 8 */
 165                         q->write_actual = (q->write & ~0x7);
 166                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 167                                 q->write_actual);
 168                 }
 169         }
 170         q->need_update = 0;
 171
 172  exit_unlock:
 173         spin_unlock_irqrestore(&q->lock, flags);
 174 }
 175
 176 /**
 177  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 178  */
 179 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 180 {
 181         return cpu_to_le32((u32)(dma_addr >> 8));
 182 }
 183
 184 /**
 185  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 186  *
 187  * If there are slots in the RX queue that need to be restocked,
 188  * and we have free pre-allocated buffers, fill the ranks as much
 189  * as we can, pulling from rx_free.
 190  *
 191  * This moves the 'write' index forward to catch up with 'processed', and
 192  * also updates the memory address in the firmware to reference the new
 193  * target buffer.
 194  */
 195 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 196 {
 197         struct iwl_trans_pcie *trans_pcie =
 198                 IWL_TRANS_GET_PCIE_TRANS(trans);
 199
 200         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 201         struct list_head *element;
 202         struct iwl_rx_mem_buffer *rxb;
 203         unsigned long flags;
 204
 205         spin_lock_irqsave(&rxq->lock, flags);
 206         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 207                 /* The overwritten rxb must be a used one */
 208                 rxb = rxq->queue[rxq->write];
 209                 BUG_ON(rxb && rxb->page);
 210
 211                 /* Get next free Rx buffer, remove from free list */
 212                 element = rxq->rx_free.next;
 213                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 214                 list_del(element);
 215
 216                 /* Point to Rx buffer via next RBD in circular buffer */
 217                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 218                 rxq->queue[rxq->write] = rxb;
 219                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 220                 rxq->free_count--;
 221         }
 222         spin_unlock_irqrestore(&rxq->lock, flags);
 223         /* If the pre-allocated buffer pool is dropping low, schedule to
 224          * refill it */
 225         if (rxq->free_count <= RX_LOW_WATERMARK)
 226                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 227
 228
 229         /* If we've added more space for the firmware to place data, tell it.
 230          * Increment device's write pointer in multiples of 8. */
 231         if (rxq->write_actual != (rxq->write & ~0x7)) {
 232                 spin_lock_irqsave(&rxq->lock, flags);
 233                 rxq->need_update = 1;
 234                 spin_unlock_irqrestore(&rxq->lock, flags);
 235                 iwl_rx_queue_update_write_ptr(trans, rxq);
 236         }
 237 }
 238
 239 /**
 240  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 241  *
 242  * When moving to rx_free an SKB is allocated for the slot.
 243  *
 244  * Also restock the Rx queue via iwl_rx_queue_restock.
 245  * This is called as a scheduled work item (except for during initialization)
 246  */
 247 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 248 {
 249         struct iwl_trans_pcie *trans_pcie =
 250                 IWL_TRANS_GET_PCIE_TRANS(trans);
 251
 252         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 253         struct list_head *element;
 254         struct iwl_rx_mem_buffer *rxb;
 255         struct page *page;
 256         unsigned long flags;
 257         gfp_t gfp_mask = priority;
 258
 259         while (1) {
 260                 spin_lock_irqsave(&rxq->lock, flags);
 261                 if (list_empty(&rxq->rx_used)) {
 262                         spin_unlock_irqrestore(&rxq->lock, flags);
 263                         return;
 264                 }
 265                 spin_unlock_irqrestore(&rxq->lock, flags);
 266
 267                 if (rxq->free_count > RX_LOW_WATERMARK)
 268                         gfp_mask |= __GFP_NOWARN;
 269
 270                 if (hw_params(trans).rx_page_order > 0)
 271                         gfp_mask |= __GFP_COMP;
 272
 273                 /* Alloc a new receive buffer */
 274                 page = alloc_pages(gfp_mask,
 275                                   hw_params(trans).rx_page_order);
 276                 if (!page) {
 277                         if (net_ratelimit())
 278                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 279                                            "order: %d\n",
 280                                            hw_params(trans).rx_page_order);
 281
 282                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 283                             net_ratelimit())
 284                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 285                                          "Only %u free buffers remaining.\n",
 286                                          priority == GFP_ATOMIC ?
 287                                          "GFP_ATOMIC" : "GFP_KERNEL",
 288                                          rxq->free_count);
 289                         /* We don't reschedule replenish work here -- we will
 290                          * call the restock method and if it still needs
 291                          * more buffers it will schedule replenish */
 292                         return;
 293                 }
 294
 295                 spin_lock_irqsave(&rxq->lock, flags);
 296
 297                 if (list_empty(&rxq->rx_used)) {
 298                         spin_unlock_irqrestore(&rxq->lock, flags);
 299                         __free_pages(page, hw_params(trans).rx_page_order);
 300                         return;
 301                 }
 302                 element = rxq->rx_used.next;
 303                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 304                 list_del(element);
 305
 306                 spin_unlock_irqrestore(&rxq->lock, flags);
 307
 308                 BUG_ON(rxb->page);
 309                 rxb->page = page;
 310                 /* Get physical address of the RB */
 311                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 312                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 313                                 DMA_FROM_DEVICE);
 314                 if (dma_mapping_error(bus(trans)->dev, rxb->page_dma)) {
 315                         rxb->page = NULL;
 316                         spin_lock_irqsave(&rxq->lock, flags);
 317                         list_add(&rxb->list, &rxq->rx_used);
 318                         spin_unlock_irqrestore(&rxq->lock, flags);
 319                         __free_pages(page, hw_params(trans).rx_page_order);
 320                         return;
 321                 }
 322                 /* dma address must be no more than 36 bits */
 323                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 324                 /* and also 256 byte aligned! */
 325                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 326
 327                 spin_lock_irqsave(&rxq->lock, flags);
 328
 329                 list_add_tail(&rxb->list, &rxq->rx_free);
 330                 rxq->free_count++;
 331
 332                 spin_unlock_irqrestore(&rxq->lock, flags);
 333         }
 334 }
 335
 336 void iwlagn_rx_replenish(struct iwl_trans *trans)
 337 {
 338         unsigned long flags;
 339
 340         iwlagn_rx_allocate(trans, GFP_KERNEL);
 341
 342         spin_lock_irqsave(&trans->shrd->lock, flags);
 343         iwlagn_rx_queue_restock(trans);
 344         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 345 }
 346
 347 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 348 {
 349         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 350
 351         iwlagn_rx_queue_restock(trans);
 352 }
 353
 354 void iwl_bg_rx_replenish(struct work_struct *data)
 355 {
 356         struct iwl_trans_pcie *trans_pcie =
 357             container_of(data, struct iwl_trans_pcie, rx_replenish);
 358         struct iwl_trans *trans = trans_pcie->trans;
 359
 360         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 361                 return;
 362
 363         mutex_lock(&trans->shrd->mutex);
 364         iwlagn_rx_replenish(trans);
 365         mutex_unlock(&trans->shrd->mutex);
 366 }
 367
 368 /**
 369  * iwl_rx_handle - Main entry function for receiving responses from uCode
 370  *
 371  * Uses the priv->rx_handlers callback function array to invoke
 372  * the appropriate handlers, including command responses,
 373  * frame-received notifications, and other notifications.
 374  */
 375 static void iwl_rx_handle(struct iwl_trans *trans)
 376 {
 377         struct iwl_rx_mem_buffer *rxb;
 378         struct iwl_rx_packet *pkt;
 379         struct iwl_trans_pcie *trans_pcie =
 380                 IWL_TRANS_GET_PCIE_TRANS(trans);
 381         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 382         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
 383         struct iwl_device_cmd *cmd;
 384         u32 r, i;
 385         int reclaim;
 386         unsigned long flags;
 387         u8 fill_rx = 0;
 388         u32 count = 8;
 389         int total_empty;
 390         int index, cmd_index;
 391
 392         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 393          * buffer that the driver may process (last buffer filled by ucode). */
 394         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 395         i = rxq->read;
 396
 397         /* Rx interrupt, but nothing sent from uCode */
 398         if (i == r)
 399                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 400
 401         /* calculate total frames need to be restock after handling RX */
 402         total_empty = r - rxq->write_actual;
 403         if (total_empty < 0)
 404                 total_empty += RX_QUEUE_SIZE;
 405
 406         if (total_empty > (RX_QUEUE_SIZE / 2))
 407                 fill_rx = 1;
 408
 409         while (i != r) {
 410                 int len, err;
 411                 u16 sequence;
 412
 413                 rxb = rxq->queue[i];
 414
 415                 /* If an RXB doesn't have a Rx queue slot associated with it,
 416                  * then a bug has been introduced in the queue refilling
 417                  * routines -- catch it here */
 418                 if (WARN_ON(rxb == NULL)) {
 419                         i = (i + 1) & RX_QUEUE_MASK;
 420                         continue;
 421                 }
 422
 423                 rxq->queue[i] = NULL;
 424
 425                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 426                                PAGE_SIZE << hw_params(trans).rx_page_order,
 427                                DMA_FROM_DEVICE);
 428                 pkt = rxb_addr(rxb);
 429
 430                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 431                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 432
 433                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 434                 len += sizeof(u32); /* account for status word */
 435                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 436
 437                 /* Reclaim a command buffer only if this packet is a response
 438                  *   to a (driver-originated) command.
 439                  * If the packet (e.g. Rx frame) originated from uCode,
 440                  *   there is no command buffer to reclaim.
 441                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 442                  *   but apparently a few don't get set; catch them here. */
 443                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 444                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 445                         (pkt->hdr.cmd != REPLY_RX) &&
 446                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 447                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 448                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 449                         (pkt->hdr.cmd != REPLY_TX);
 450
 451                 sequence = le16_to_cpu(pkt->hdr.sequence);
 452                 index = SEQ_TO_INDEX(sequence);
 453                 cmd_index = get_cmd_index(&txq->q, index);
 454
 455                 if (reclaim)
 456                         cmd = txq->cmd[cmd_index];
 457                 else
 458                         cmd = NULL;
 459
 460                 /* warn if this is cmd response / notification and the uCode
 461                  * didn't set the SEQ_RX_FRAME for a frame that is
 462                  * uCode-originated
 463                  * If you saw this code after the second half of 2012, then
 464                  * please remove it
 465                  */
 466                 WARN(pkt->hdr.cmd != REPLY_TX && reclaim == false &&
 467                      (!(pkt->hdr.sequence & SEQ_RX_FRAME)),
 468                      "reclaim is false, SEQ_RX_FRAME unset: %s\n",
 469                      get_cmd_string(pkt->hdr.cmd));
 470
 471                 err = iwl_rx_dispatch(priv(trans), rxb, cmd);
 472
 473                 /*
 474                  * XXX: After here, we should always check rxb->page
 475                  * against NULL before touching it or its virtual
 476                  * memory (pkt). Because some rx_handler might have
 477                  * already taken or freed the pages.
 478                  */
 479
 480                 if (reclaim) {
 481                         /* Invoke any callbacks, transfer the buffer to caller,
 482                          * and fire off the (possibly) blocking
 483                          * iwl_trans_send_cmd()
 484                          * as we reclaim the driver command queue */
 485                         if (rxb->page)
 486                                 iwl_tx_cmd_complete(trans, rxb, err);
 487                         else
 488                                 IWL_WARN(trans, "Claim null rxb?\n");
 489                 }
 490
 491                 /* Reuse the page if possible. For notification packets and
 492                  * SKBs that fail to Rx correctly, add them back into the
 493                  * rx_free list for reuse later. */
 494                 spin_lock_irqsave(&rxq->lock, flags);
 495                 if (rxb->page != NULL) {
 496                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 497                                 0, PAGE_SIZE <<
 498                                     hw_params(trans).rx_page_order,
 499                                 DMA_FROM_DEVICE);
 500                         if (dma_mapping_error(bus(trans)->dev, rxb->page_dma)) {
 501                                 /*
 502                                  * free the page(s) as well to not break
 503                                  * the invariant that the items on the used
 504                                  * list have no page(s)
 505                                  */
 506                                 __free_pages(rxb->page, hw_params(trans).rx_page_order);
 507                                 rxb->page = NULL;
 508                                 list_add_tail(&rxb->list, &rxq->rx_used);
 509                         } else {
 510                                 list_add_tail(&rxb->list, &rxq->rx_free);
 511                                 rxq->free_count++;
 512                         }
 513                 } else
 514                         list_add_tail(&rxb->list, &rxq->rx_used);
 515
 516                 spin_unlock_irqrestore(&rxq->lock, flags);
 517
 518                 i = (i + 1) & RX_QUEUE_MASK;
 519                 /* If there are a lot of unused frames,
 520                  * restock the Rx queue so ucode wont assert. */
 521                 if (fill_rx) {
 522                         count++;
 523                         if (count >= 8) {
 524                                 rxq->read = i;
 525                                 iwlagn_rx_replenish_now(trans);
 526                                 count = 0;
 527                         }
 528                 }
 529         }
 530
 531         /* Backtrack one entry */
 532         rxq->read = i;
 533         if (fill_rx)
 534                 iwlagn_rx_replenish_now(trans);
 535         else
 536                 iwlagn_rx_queue_restock(trans);
 537 }
 538
 539 static const char * const desc_lookup_text[] = {
 540         "OK",
 541         "FAIL",
 542         "BAD_PARAM",
 543         "BAD_CHECKSUM",
 544         "NMI_INTERRUPT_WDG",
 545         "SYSASSERT",
 546         "FATAL_ERROR",
 547         "BAD_COMMAND",
 548         "HW_ERROR_TUNE_LOCK",
 549         "HW_ERROR_TEMPERATURE",
 550         "ILLEGAL_CHAN_FREQ",
 551         "VCC_NOT_STABLE",
 552         "FH_ERROR",
 553         "NMI_INTERRUPT_HOST",
 554         "NMI_INTERRUPT_ACTION_PT",
 555         "NMI_INTERRUPT_UNKNOWN",
 556         "UCODE_VERSION_MISMATCH",
 557         "HW_ERROR_ABS_LOCK",
 558         "HW_ERROR_CAL_LOCK_FAIL",
 559         "NMI_INTERRUPT_INST_ACTION_PT",
 560         "NMI_INTERRUPT_DATA_ACTION_PT",
 561         "NMI_TRM_HW_ER",
 562         "NMI_INTERRUPT_TRM",
 563         "NMI_INTERRUPT_BREAK_POINT",
 564         "DEBUG_0",
 565         "DEBUG_1",
 566         "DEBUG_2",
 567         "DEBUG_3",
 568 };
 569
 570 static struct { char *name; u8 num; } advanced_lookup[] = {
 571         { "NMI_INTERRUPT_WDG", 0x34 },
 572         { "SYSASSERT", 0x35 },
 573         { "UCODE_VERSION_MISMATCH", 0x37 },
 574         { "BAD_COMMAND", 0x38 },
 575         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 576         { "FATAL_ERROR", 0x3D },
 577         { "NMI_TRM_HW_ERR", 0x46 },
 578         { "NMI_INTERRUPT_TRM", 0x4C },
 579         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 580         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 581         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 582         { "NMI_INTERRUPT_HOST", 0x66 },
 583         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 584         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 585         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 586         { "ADVANCED_SYSASSERT", 0 },
 587 };
 588
 589 static const char *desc_lookup(u32 num)
 590 {
 591         int i;
 592         int max = ARRAY_SIZE(desc_lookup_text);
 593
 594         if (num < max)
 595                 return desc_lookup_text[num];
 596
 597         max = ARRAY_SIZE(advanced_lookup) - 1;
 598         for (i = 0; i < max; i++) {
 599                 if (advanced_lookup[i].num == num)
 600                         break;
 601         }
 602         return advanced_lookup[i].name;
 603 }
 604
 605 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 606 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 607
 608 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 609 {
 610         u32 base;
 611         struct iwl_error_event_table table;
 612         struct iwl_priv *priv = priv(trans);
 613         struct iwl_trans_pcie *trans_pcie =
 614                 IWL_TRANS_GET_PCIE_TRANS(trans);
 615
 616         base = priv->device_pointers.error_event_table;
 617         if (priv->ucode_type == IWL_UCODE_INIT) {
 618                 if (!base)
 619                         base = priv->init_errlog_ptr;
 620         } else {
 621                 if (!base)
 622                         base = priv->inst_errlog_ptr;
 623         }
 624
 625         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 626                 IWL_ERR(trans,
 627                         "Not valid error log pointer 0x%08X for %s uCode\n",
 628                         base,
 629                         (priv->ucode_type == IWL_UCODE_INIT)
 630                                         ? "Init" : "RT");
 631                 return;
 632         }
 633
 634         iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
 635
 636         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 637                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 638                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 639                         trans->shrd->status, table.valid);
 640         }
 641
 642         trans_pcie->isr_stats.err_code = table.error_id;
 643
 644         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
 645                                       table.data1, table.data2, table.line,
 646                                       table.blink1, table.blink2, table.ilink1,
 647                                       table.ilink2, table.bcon_time, table.gp1,
 648                                       table.gp2, table.gp3, table.ucode_ver,
 649                                       table.hw_ver, table.brd_ver);
 650         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 651                 desc_lookup(table.error_id));
 652         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 653         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 654         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 655         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 656         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 657         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 658         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 659         IWL_ERR(trans, "0x%08X | line\n", table.line);
 660         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 661         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 662         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 663         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 664         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 665         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 666         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 667         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 668         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 669         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 670 }
 671
 672 /**
 673  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 674  */
 675 static void iwl_irq_handle_error(struct iwl_trans *trans)
 676 {
 677         struct iwl_priv *priv = priv(trans);
 678         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 679         if (priv->cfg->internal_wimax_coex &&
 680             (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
 681                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 682              (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
 683                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 684                 /*
 685                  * Keep the restart process from trying to send host
 686                  * commands by clearing the ready bit.
 687                  */
 688                 clear_bit(STATUS_READY, &trans->shrd->status);
 689                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 690                 wake_up(&priv->shrd->wait_command_queue);
 691                 IWL_ERR(trans, "RF is used by WiMAX\n");
 692                 return;
 693         }
 694
 695         IWL_ERR(trans, "Loaded firmware version: %s\n",
 696                 priv->hw->wiphy->fw_version);
 697
 698         iwl_dump_nic_error_log(trans);
 699         iwl_dump_csr(trans);
 700         iwl_dump_fh(trans, NULL);
 701         iwl_dump_nic_event_log(trans, false, NULL, false);
 702 #ifdef CONFIG_IWLWIFI_DEBUG
 703         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
 704                 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
 705 #endif
 706
 707         iwlagn_fw_error(priv, false);
 708 }
 709
 710 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 711
 712 /**
 713  * iwl_print_event_log - Dump error event log to syslog
 714  *
 715  */
 716 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 717                                u32 num_events, u32 mode,
 718                                int pos, char **buf, size_t bufsz)
 719 {
 720         u32 i;
 721         u32 base;       /* SRAM byte address of event log header */
 722         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 723         u32 ptr;        /* SRAM byte address of log data */
 724         u32 ev, time, data; /* event log data */
 725         unsigned long reg_flags;
 726         struct iwl_priv *priv = priv(trans);
 727
 728         if (num_events == 0)
 729                 return pos;
 730
 731         base = priv->device_pointers.log_event_table;
 732         if (priv->ucode_type == IWL_UCODE_INIT) {
 733                 if (!base)
 734                         base = priv->init_evtlog_ptr;
 735         } else {
 736                 if (!base)
 737                         base = priv->inst_evtlog_ptr;
 738         }
 739
 740         if (mode == 0)
 741                 event_size = 2 * sizeof(u32);
 742         else
 743                 event_size = 3 * sizeof(u32);
 744
 745         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 746
 747         /* Make sure device is powered up for SRAM reads */
 748         spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
 749         iwl_grab_nic_access(bus(trans));
 750
 751         /* Set starting address; reads will auto-increment */
 752         iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
 753         rmb();
 754
 755         /* "time" is actually "data" for mode 0 (no timestamp).
 756         * place event id # at far right for easier visual parsing. */
 757         for (i = 0; i < num_events; i++) {
 758                 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 759                 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 760                 if (mode == 0) {
 761                         /* data, ev */
 762                         if (bufsz) {
 763                                 pos += scnprintf(*buf + pos, bufsz - pos,
 764                                                 "EVT_LOG:0x%08x:%04u\n",
 765                                                 time, ev);
 766                         } else {
 767                                 trace_iwlwifi_dev_ucode_event(priv, 0,
 768                                         time, ev);
 769                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 770                                         time, ev);
 771                         }
 772                 } else {
 773                         data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 774                         if (bufsz) {
 775                                 pos += scnprintf(*buf + pos, bufsz - pos,
 776                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 777                                                  time, data, ev);
 778                         } else {
 779                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 780                                         time, data, ev);
 781                                 trace_iwlwifi_dev_ucode_event(priv, time,
 782                                         data, ev);
 783                         }
 784                 }
 785         }
 786
 787         /* Allow device to power down */
 788         iwl_release_nic_access(bus(trans));
 789         spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
 790         return pos;
 791 }
 792
 793 /**
 794  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 795  */
 796 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 797                                     u32 num_wraps, u32 next_entry,
 798                                     u32 size, u32 mode,
 799                                     int pos, char **buf, size_t bufsz)
 800 {
 801         /*
 802          * display the newest DEFAULT_LOG_ENTRIES entries
 803          * i.e the entries just before the next ont that uCode would fill.
 804          */
 805         if (num_wraps) {
 806                 if (next_entry < size) {
 807                         pos = iwl_print_event_log(trans,
 808                                                 capacity - (size - next_entry),
 809                                                 size - next_entry, mode,
 810                                                 pos, buf, bufsz);
 811                         pos = iwl_print_event_log(trans, 0,
 812                                                   next_entry, mode,
 813                                                   pos, buf, bufsz);
 814                 } else
 815                         pos = iwl_print_event_log(trans, next_entry - size,
 816                                                   size, mode, pos, buf, bufsz);
 817         } else {
 818                 if (next_entry < size) {
 819                         pos = iwl_print_event_log(trans, 0, next_entry,
 820                                                   mode, pos, buf, bufsz);
 821                 } else {
 822                         pos = iwl_print_event_log(trans, next_entry - size,
 823                                                   size, mode, pos, buf, bufsz);
 824                 }
 825         }
 826         return pos;
 827 }
 828
 829 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 830
 831 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 832                             char **buf, bool display)
 833 {
 834         u32 base;       /* SRAM byte address of event log header */
 835         u32 capacity;   /* event log capacity in # entries */
 836         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 837         u32 num_wraps;  /* # times uCode wrapped to top of log */
 838         u32 next_entry; /* index of next entry to be written by uCode */
 839         u32 size;       /* # entries that we'll print */
 840         u32 logsize;
 841         int pos = 0;
 842         size_t bufsz = 0;
 843         struct iwl_priv *priv = priv(trans);
 844
 845         base = priv->device_pointers.log_event_table;
 846         if (priv->ucode_type == IWL_UCODE_INIT) {
 847                 logsize = priv->init_evtlog_size;
 848                 if (!base)
 849                         base = priv->init_evtlog_ptr;
 850         } else {
 851                 logsize = priv->inst_evtlog_size;
 852                 if (!base)
 853                         base = priv->inst_evtlog_ptr;
 854         }
 855
 856         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 857                 IWL_ERR(trans,
 858                         "Invalid event log pointer 0x%08X for %s uCode\n",
 859                         base,
 860                         (priv->ucode_type == IWL_UCODE_INIT)
 861                                         ? "Init" : "RT");
 862                 return -EINVAL;
 863         }
 864
 865         /* event log header */
 866         capacity = iwl_read_targ_mem(bus(trans), base);
 867         mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
 868         num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
 869         next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
 870
 871         if (capacity > logsize) {
 872                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 873                         "entries\n", capacity, logsize);
 874                 capacity = logsize;
 875         }
 876
 877         if (next_entry > logsize) {
 878                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 879                         next_entry, logsize);
 880                 next_entry = logsize;
 881         }
 882
 883         size = num_wraps ? capacity : next_entry;
 884
 885         /* bail out if nothing in log */
 886         if (size == 0) {
 887                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 888                 return pos;
 889         }
 890
 891 #ifdef CONFIG_IWLWIFI_DEBUG
 892         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
 893                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 894                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 895 #else
 896         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 897                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 898 #endif
 899         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 900                 size);
 901
 902 #ifdef CONFIG_IWLWIFI_DEBUG
 903         if (display) {
 904                 if (full_log)
 905                         bufsz = capacity * 48;
 906                 else
 907                         bufsz = size * 48;
 908                 *buf = kmalloc(bufsz, GFP_KERNEL);
 909                 if (!*buf)
 910                         return -ENOMEM;
 911         }
 912         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
 913                 /*
 914                  * if uCode has wrapped back to top of log,
 915                  * start at the oldest entry,
 916                  * i.e the next one that uCode would fill.
 917                  */
 918                 if (num_wraps)
 919                         pos = iwl_print_event_log(trans, next_entry,
 920                                                 capacity - next_entry, mode,
 921                                                 pos, buf, bufsz);
 922                 /* (then/else) start at top of log */
 923                 pos = iwl_print_event_log(trans, 0,
 924                                           next_entry, mode, pos, buf, bufsz);
 925         } else
 926                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 927                                                 next_entry, size, mode,
 928                                                 pos, buf, bufsz);
 929 #else
 930         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 931                                         next_entry, size, mode,
 932                                         pos, buf, bufsz);
 933 #endif
 934         return pos;
 935 }
 936
 937 /* tasklet for iwlagn interrupt */
 938 void iwl_irq_tasklet(struct iwl_trans *trans)
 939 {
 940         u32 inta = 0;
 941         u32 handled = 0;
 942         unsigned long flags;
 943         u32 i;
 944 #ifdef CONFIG_IWLWIFI_DEBUG
 945         u32 inta_mask;
 946 #endif
 947
 948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 949         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 950
 951
 952         spin_lock_irqsave(&trans->shrd->lock, flags);
 953
 954         /* Ack/clear/reset pending uCode interrupts.
 955          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 956          */
 957         /* There is a hardware bug in the interrupt mask function that some
 958          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 959          * they are disabled in the CSR_INT_MASK register. Furthermore the
 960          * ICT interrupt handling mechanism has another bug that might cause
 961          * these unmasked interrupts fail to be detected. We workaround the
 962          * hardware bugs here by ACKing all the possible interrupts so that
 963          * interrupt coalescing can still be achieved.
 964          */
 965         iwl_write32(bus(trans), CSR_INT,
 966                 trans_pcie->inta | ~trans_pcie->inta_mask);
 967
 968         inta = trans_pcie->inta;
 969
 970 #ifdef CONFIG_IWLWIFI_DEBUG
 971         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 972                 /* just for debug */
 973                 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
 974                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 975                                 inta, inta_mask);
 976         }
 977 #endif
 978
 979         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 980         trans_pcie->inta = 0;
 981
 982         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 983
 984         /* Now service all interrupt bits discovered above. */
 985         if (inta & CSR_INT_BIT_HW_ERR) {
 986                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 987
 988                 /* Tell the device to stop sending interrupts */
 989                 iwl_disable_interrupts(trans);
 990
 991                 isr_stats->hw++;
 992                 iwl_irq_handle_error(trans);
 993
 994                 handled |= CSR_INT_BIT_HW_ERR;
 995
 996                 return;
 997         }
 998
 999 #ifdef CONFIG_IWLWIFI_DEBUG
1000         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1001                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1002                 if (inta & CSR_INT_BIT_SCD) {
1003                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
1004                                       "the frame/frames.\n");
1005                         isr_stats->sch++;
1006                 }
1007
1008                 /* Alive notification via Rx interrupt will do the real work */
1009                 if (inta & CSR_INT_BIT_ALIVE) {
1010                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1011                         isr_stats->alive++;
1012                 }
1013         }
1014 #endif
1015         /* Safely ignore these bits for debug checks below */
1016         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1017
1018         /* HW RF KILL switch toggled */
1019         if (inta & CSR_INT_BIT_RF_KILL) {
1020                 int hw_rf_kill = 0;
1021                 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1022                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1023                         hw_rf_kill = 1;
1024
1025                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1026                                 hw_rf_kill ? "disable radio" : "enable radio");
1027
1028                 isr_stats->rfkill++;
1029
1030                 /* driver only loads ucode once setting the interface up.
1031                  * the driver allows loading the ucode even if the radio
1032                  * is killed. Hence update the killswitch state here. The
1033                  * rfkill handler will care about restarting if needed.
1034                  */
1035                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1036                         if (hw_rf_kill)
1037                                 set_bit(STATUS_RF_KILL_HW,
1038                                         &trans->shrd->status);
1039                         else
1040                                 clear_bit(STATUS_RF_KILL_HW,
1041                                           &trans->shrd->status);
1042                         iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1043                 }
1044
1045                 handled |= CSR_INT_BIT_RF_KILL;
1046         }
1047
1048         /* Chip got too hot and stopped itself */
1049         if (inta & CSR_INT_BIT_CT_KILL) {
1050                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1051                 isr_stats->ctkill++;
1052                 handled |= CSR_INT_BIT_CT_KILL;
1053         }
1054
1055         /* Error detected by uCode */
1056         if (inta & CSR_INT_BIT_SW_ERR) {
1057                 IWL_ERR(trans, "Microcode SW error detected. "
1058                         " Restarting 0x%X.\n", inta);
1059                 isr_stats->sw++;
1060                 iwl_irq_handle_error(trans);
1061                 handled |= CSR_INT_BIT_SW_ERR;
1062         }
1063
1064         /* uCode wakes up after power-down sleep */
1065         if (inta & CSR_INT_BIT_WAKEUP) {
1066                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1067                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1068                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1069                         iwl_txq_update_write_ptr(trans,
1070                                                  &trans_pcie->txq[i]);
1071
1072                 isr_stats->wakeup++;
1073
1074                 handled |= CSR_INT_BIT_WAKEUP;
1075         }
1076
1077         /* All uCode command responses, including Tx command responses,
1078          * Rx "responses" (frame-received notification), and other
1079          * notifications from uCode come through here*/
1080         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1081                         CSR_INT_BIT_RX_PERIODIC)) {
1082                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1083                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1084                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1085                         iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1086                                         CSR_FH_INT_RX_MASK);
1087                 }
1088                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1089                         handled |= CSR_INT_BIT_RX_PERIODIC;
1090                         iwl_write32(bus(trans),
1091                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1092                 }
1093                 /* Sending RX interrupt require many steps to be done in the
1094                  * the device:
1095                  * 1- write interrupt to current index in ICT table.
1096                  * 2- dma RX frame.
1097                  * 3- update RX shared data to indicate last write index.
1098                  * 4- send interrupt.
1099                  * This could lead to RX race, driver could receive RX interrupt
1100                  * but the shared data changes does not reflect this;
1101                  * periodic interrupt will detect any dangling Rx activity.
1102                  */
1103
1104                 /* Disable periodic interrupt; we use it as just a one-shot. */
1105                 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1106                             CSR_INT_PERIODIC_DIS);
1107                 iwl_rx_handle(trans);
1108
1109                 /*
1110                  * Enable periodic interrupt in 8 msec only if we received
1111                  * real RX interrupt (instead of just periodic int), to catch
1112                  * any dangling Rx interrupt.  If it was just the periodic
1113                  * interrupt, there was no dangling Rx activity, and no need
1114                  * to extend the periodic interrupt; one-shot is enough.
1115                  */
1116                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1117                         iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1118                                     CSR_INT_PERIODIC_ENA);
1119
1120                 isr_stats->rx++;
1121         }
1122
1123         /* This "Tx" DMA channel is used only for loading uCode */
1124         if (inta & CSR_INT_BIT_FH_TX) {
1125                 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1126                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1127                 isr_stats->tx++;
1128                 handled |= CSR_INT_BIT_FH_TX;
1129                 /* Wake up uCode load routine, now that load is complete */
1130                 priv(trans)->ucode_write_complete = 1;
1131                 wake_up(&trans->shrd->wait_command_queue);
1132         }
1133
1134         if (inta & ~handled) {
1135                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1136                 isr_stats->unhandled++;
1137         }
1138
1139         if (inta & ~(trans_pcie->inta_mask)) {
1140                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1141                          inta & ~trans_pcie->inta_mask);
1142         }
1143
1144         /* Re-enable all interrupts */
1145         /* only Re-enable if disabled by irq */
1146         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1147                 iwl_enable_interrupts(trans);
1148         /* Re-enable RF_KILL if it occurred */
1149         else if (handled & CSR_INT_BIT_RF_KILL)
1150                 iwl_enable_rfkill_int(priv(trans));
1151 }
1152
1153 /******************************************************************************
1154  *
1155  * ICT functions
1156  *
1157  ******************************************************************************/
1158
1159 /* a device (PCI-E) page is 4096 bytes long */
1160 #define ICT_SHIFT       12
1161 #define ICT_SIZE        (1 << ICT_SHIFT)
1162 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1163
1164 /* Free dram table */
1165 void iwl_free_isr_ict(struct iwl_trans *trans)
1166 {
1167         struct iwl_trans_pcie *trans_pcie =
1168                 IWL_TRANS_GET_PCIE_TRANS(trans);
1169
1170         if (trans_pcie->ict_tbl) {
1171                 dma_free_coherent(bus(trans)->dev, ICT_SIZE,
1172                                   trans_pcie->ict_tbl,
1173                                   trans_pcie->ict_tbl_dma);
1174                 trans_pcie->ict_tbl = NULL;
1175                 trans_pcie->ict_tbl_dma = 0;
1176         }
1177 }
1178
1179
1180 /*
1181  * allocate dram shared table, it is an aligned memory
1182  * block of ICT_SIZE.
1183  * also reset all data related to ICT table interrupt.
1184  */
1185 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1186 {
1187         struct iwl_trans_pcie *trans_pcie =
1188                 IWL_TRANS_GET_PCIE_TRANS(trans);
1189
1190         trans_pcie->ict_tbl =
1191                 dma_alloc_coherent(bus(trans)->dev, ICT_SIZE,
1192                                    &trans_pcie->ict_tbl_dma,
1193                                    GFP_KERNEL);
1194         if (!trans_pcie->ict_tbl)
1195                 return -ENOMEM;
1196
1197         /* just an API sanity check ... it is guaranteed to be aligned */
1198         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1199                 iwl_free_isr_ict(trans);
1200                 return -EINVAL;
1201         }
1202
1203         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1204                       (unsigned long long)trans_pcie->ict_tbl_dma);
1205
1206         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1207
1208         /* reset table and index to all 0 */
1209         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1210         trans_pcie->ict_index = 0;
1211
1212         /* add periodic RX interrupt */
1213         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1214         return 0;
1215 }
1216
1217 /* Device is going up inform it about using ICT interrupt table,
1218  * also we need to tell the driver to start using ICT interrupt.
1219  */
1220 int iwl_reset_ict(struct iwl_trans *trans)
1221 {
1222         u32 val;
1223         unsigned long flags;
1224         struct iwl_trans_pcie *trans_pcie =
1225                 IWL_TRANS_GET_PCIE_TRANS(trans);
1226
1227         if (!trans_pcie->ict_tbl)
1228                 return 0;
1229
1230         spin_lock_irqsave(&trans->shrd->lock, flags);
1231         iwl_disable_interrupts(trans);
1232
1233         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1234
1235         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1236
1237         val |= CSR_DRAM_INT_TBL_ENABLE;
1238         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1239
1240         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1241
1242         iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1243         trans_pcie->use_ict = true;
1244         trans_pcie->ict_index = 0;
1245         iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1246         iwl_enable_interrupts(trans);
1247         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1248
1249         return 0;
1250 }
1251
1252 /* Device is going down disable ict interrupt usage */
1253 void iwl_disable_ict(struct iwl_trans *trans)
1254 {
1255         struct iwl_trans_pcie *trans_pcie =
1256                 IWL_TRANS_GET_PCIE_TRANS(trans);
1257
1258         unsigned long flags;
1259
1260         spin_lock_irqsave(&trans->shrd->lock, flags);
1261         trans_pcie->use_ict = false;
1262         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1263 }
1264
1265 static irqreturn_t iwl_isr(int irq, void *data)
1266 {
1267         struct iwl_trans *trans = data;
1268         struct iwl_trans_pcie *trans_pcie;
1269         u32 inta, inta_mask;
1270         unsigned long flags;
1271 #ifdef CONFIG_IWLWIFI_DEBUG
1272         u32 inta_fh;
1273 #endif
1274         if (!trans)
1275                 return IRQ_NONE;
1276
1277         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1278
1279         spin_lock_irqsave(&trans->shrd->lock, flags);
1280
1281         /* Disable (but don't clear!) interrupts here to avoid
1282          *    back-to-back ISRs and sporadic interrupts from our NIC.
1283          * If we have something to service, the tasklet will re-enable ints.
1284          * If we *don't* have something, we'll re-enable before leaving here. */
1285         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
1286         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1287
1288         /* Discover which interrupts are active/pending */
1289         inta = iwl_read32(bus(trans), CSR_INT);
1290
1291         if (inta & (~inta_mask)) {
1292                 IWL_DEBUG_ISR(trans,
1293                               "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1294                               inta & (~inta_mask));
1295                 iwl_write32(bus(trans), CSR_INT, inta & (~inta_mask));
1296                 inta &= inta_mask;
1297         }
1298
1299         /* Ignore interrupt if there's nothing in NIC to service.
1300          * This may be due to IRQ shared with another device,
1301          * or due to sporadic interrupts thrown from our NIC. */
1302         if (!inta) {
1303                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1304                 goto none;
1305         }
1306
1307         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1308                 /* Hardware disappeared. It might have already raised
1309                  * an interrupt */
1310                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1311                 goto unplugged;
1312         }
1313
1314 #ifdef CONFIG_IWLWIFI_DEBUG
1315         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1316                 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1317                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1318                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1319         }
1320 #endif
1321
1322         trans_pcie->inta |= inta;
1323         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1324         if (likely(inta))
1325                 tasklet_schedule(&trans_pcie->irq_tasklet);
1326         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1327                         !trans_pcie->inta)
1328                 iwl_enable_interrupts(trans);
1329
1330  unplugged:
1331         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1332         return IRQ_HANDLED;
1333
1334  none:
1335         /* re-enable interrupts here since we don't have anything to service. */
1336         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1337         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1338                 !trans_pcie->inta)
1339                 iwl_enable_interrupts(trans);
1340
1341         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1342         return IRQ_NONE;
1343 }
1344
1345 /* interrupt handler using ict table, with this interrupt driver will
1346  * stop using INTA register to get device's interrupt, reading this register
1347  * is expensive, device will write interrupts in ICT dram table, increment
1348  * index then will fire interrupt to driver, driver will OR all ICT table
1349  * entries from current index up to table entry with 0 value. the result is
1350  * the interrupt we need to service, driver will set the entries back to 0 and
1351  * set index.
1352  */
1353 irqreturn_t iwl_isr_ict(int irq, void *data)
1354 {
1355         struct iwl_trans *trans = data;
1356         struct iwl_trans_pcie *trans_pcie;
1357         u32 inta, inta_mask;
1358         u32 val = 0;
1359         unsigned long flags;
1360
1361         if (!trans)
1362                 return IRQ_NONE;
1363
1364         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1365
1366         /* dram interrupt table not set yet,
1367          * use legacy interrupt.
1368          */
1369         if (!trans_pcie->use_ict)
1370                 return iwl_isr(irq, data);
1371
1372         spin_lock_irqsave(&trans->shrd->lock, flags);
1373
1374         /* Disable (but don't clear!) interrupts here to avoid
1375          * back-to-back ISRs and sporadic interrupts from our NIC.
1376          * If we have something to service, the tasklet will re-enable ints.
1377          * If we *don't* have something, we'll re-enable before leaving here.
1378          */
1379         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
1380         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1381
1382
1383         /* Ignore interrupt if there's nothing in NIC to service.
1384          * This may be due to IRQ shared with another device,
1385          * or due to sporadic interrupts thrown from our NIC. */
1386         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1387                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1388                 goto none;
1389         }
1390
1391         /* read all entries that not 0 start with ict_index */
1392         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1393
1394                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1395                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1396                                 trans_pcie->ict_index,
1397                                 le32_to_cpu(
1398                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
1399                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1400                 trans_pcie->ict_index =
1401                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1402
1403         }
1404
1405         /* We should not get this value, just ignore it. */
1406         if (val == 0xffffffff)
1407                 val = 0;
1408
1409         /*
1410          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1411          * (bit 15 before shifting it to 31) to clear when using interrupt
1412          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1413          * so we use them to decide on the real state of the Rx bit.
1414          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1415          */
1416         if (val & 0xC0000)
1417                 val |= 0x8000;
1418
1419         inta = (0xff & val) | ((0xff00 & val) << 16);
1420         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1421                         inta, inta_mask, val);
1422
1423         inta &= trans_pcie->inta_mask;
1424         trans_pcie->inta |= inta;
1425
1426         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1427         if (likely(inta))
1428                 tasklet_schedule(&trans_pcie->irq_tasklet);
1429         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1430                         !trans_pcie->inta) {
1431                 /* Allow interrupt if was disabled by this handler and
1432                  * no tasklet was schedules, We should not enable interrupt,
1433                  * tasklet will enable it.
1434                  */
1435                 iwl_enable_interrupts(trans);
1436         }
1437
1438         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1439         return IRQ_HANDLED;
1440
1441  none:
1442         /* re-enable interrupts here since we don't have anything to service.
1443          * only Re-enable if disabled by irq.
1444          */
1445         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1446                 !trans_pcie->inta)
1447                 iwl_enable_interrupts(trans);
1448
1449         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1450         return IRQ_NONE;
1451 }