1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
38 #include "iwl-shared.h"
39 #include "iwl-trans.h"
40 #include "iwl-debug.h"
47 /*This file includes the declaration that are internal to the
51 * struct isr_statistics - interrupt statistics
54 struct isr_statistics {
69 * struct iwl_rx_queue - Rx queue
70 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
71 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
74 * @read: Shared index to newest available Rx buffer
75 * @write: Shared index to oldest written Rx packet
76 * @free_count: Number of pre-allocated buffers in rx_free
78 * @rx_free: list of free SKBs for use
79 * @rx_used: List of Rx buffers with no SKB
80 * @need_update: flag to indicate we need to update read/write index
81 * @rb_stts: driver's pointer to receive buffer status
82 * @rb_stts_dma: bus address of receive buffer status
85 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
90 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
91 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
96 struct list_head rx_free;
97 struct list_head rx_used;
99 struct iwl_rb_status *rb_stts;
100 dma_addr_t rb_stts_dma;
111 * This queue number is required for proper operation
112 * because the ucode will stop/start the scheduler as
115 #define IWL_IPAN_MCAST_QUEUE 8
118 * struct iwl_trans_pcie - PCIe transport specific data
119 * @rxq: all the RX queue data
120 * @rx_replenish: work that will be called when buffers need to be allocated
121 * @trans: pointer to the generic transport area
122 * @scd_base_addr: scheduler sram base address in SRAM
123 * @scd_bc_tbls: pointer to the byte count table of the scheduler
124 * @kw: keep warm address
125 * @ac_to_fifo: to what fifo is a specifc AC mapped ?
126 * @ac_to_queue: to what tx queue is a specifc AC mapped ?
128 * @txq: Tx DMA processing queues
129 * @txq_ctx_active_msk: what queue is active
130 * queue_stopped: tracks what queue is stopped
131 * queue_stop_count: tracks what SW queue is stopped
133 struct iwl_trans_pcie {
134 struct iwl_rx_queue rxq;
135 struct work_struct rx_replenish;
136 struct iwl_trans *trans;
141 dma_addr_t ict_tbl_dma;
142 dma_addr_t aligned_ict_tbl_dma;
146 struct tasklet_struct irq_tasklet;
147 struct isr_statistics isr_stats;
151 struct iwl_dma_ptr scd_bc_tbls;
152 struct iwl_dma_ptr kw;
154 const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
155 const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
156 u8 mcast_queue[NUM_IWL_RXON_CTX];
158 struct iwl_tx_queue *txq;
159 unsigned long txq_ctx_active_msk;
160 #define IWL_MAX_HW_QUEUES 32
161 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
162 atomic_t queue_stop_count[4];
165 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
166 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
168 /*****************************************************
170 ******************************************************/
171 void iwl_bg_rx_replenish(struct work_struct *data);
172 void iwl_irq_tasklet(struct iwl_trans *trans);
173 void iwlagn_rx_replenish(struct iwl_trans *trans);
174 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
175 struct iwl_rx_queue *q);
177 /*****************************************************
179 ******************************************************/
180 int iwl_reset_ict(struct iwl_trans *trans);
181 void iwl_disable_ict(struct iwl_trans *trans);
182 int iwl_alloc_isr_ict(struct iwl_trans *trans);
183 void iwl_free_isr_ict(struct iwl_trans *trans);
184 irqreturn_t iwl_isr_ict(int irq, void *data);
186 /*****************************************************
188 ******************************************************/
189 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
190 struct iwl_tx_queue *txq);
191 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
192 struct iwl_tx_queue *txq,
193 dma_addr_t addr, u16 len, u8 reset);
194 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
195 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
196 int __must_check iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id,
197 u32 flags, u16 len, const void *data);
198 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
199 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
200 struct iwl_tx_queue *txq,
202 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id);
203 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
204 enum iwl_rxon_context_id ctx, int sta_id,
206 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
207 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
208 struct iwl_tx_queue *txq,
209 int tx_fifo_id, int scd_retry);
210 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
211 enum iwl_rxon_context_id ctx, int sta_id,
213 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
214 enum iwl_rxon_context_id ctx,
215 int sta_id, int tid, int frame_limit);
216 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
218 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
219 struct sk_buff_head *skbs);
220 int iwl_queue_space(const struct iwl_queue *q);
222 /*****************************************************
224 ******************************************************/
225 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
226 char **buf, bool display);
227 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
228 void iwl_dump_csr(struct iwl_trans *trans);
230 /*****************************************************
232 ******************************************************/
233 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
235 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
237 /* disable interrupts from uCode/NIC to host */
238 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
240 /* acknowledge/clear/reset any interrupts still pending
241 * from uCode or flow handler (Rx/Tx DMA) */
242 iwl_write32(bus(trans), CSR_INT, 0xffffffff);
243 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
244 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
247 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
249 struct iwl_trans_pcie *trans_pcie =
250 IWL_TRANS_GET_PCIE_TRANS(trans);
252 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
253 set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
254 iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
258 * we have 8 bits used like this:
262 * | | | | | | +-+-------- AC queue (0-3)
264 * | +-+-+-+-+------------ HW queue ID
266 * +---------------------- unused
268 static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
270 BUG_ON(ac > 3); /* only have 2 bits */
271 BUG_ON(hwq > 31); /* only use 5 bits */
273 txq->swq_id = (hwq << 2) | ac;
276 static inline void iwl_wake_queue(struct iwl_trans *trans,
277 struct iwl_tx_queue *txq)
279 u8 queue = txq->swq_id;
281 u8 hwq = (queue >> 2) & 0x1f;
282 struct iwl_trans_pcie *trans_pcie =
283 IWL_TRANS_GET_PCIE_TRANS(trans);
285 if (unlikely(!trans->shrd->mac80211_registered))
288 if (test_and_clear_bit(hwq, trans_pcie->queue_stopped))
289 if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0)
290 ieee80211_wake_queue(trans->shrd->hw, ac);
293 static inline void iwl_stop_queue(struct iwl_trans *trans,
294 struct iwl_tx_queue *txq)
296 u8 queue = txq->swq_id;
298 u8 hwq = (queue >> 2) & 0x1f;
299 struct iwl_trans_pcie *trans_pcie =
300 IWL_TRANS_GET_PCIE_TRANS(trans);
302 if (unlikely(!trans->shrd->mac80211_registered))
305 if (!test_and_set_bit(hwq, trans_pcie->queue_stopped))
306 if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0)
307 ieee80211_stop_queue(trans->shrd->hw, ac);
310 #ifdef ieee80211_stop_queue
311 #undef ieee80211_stop_queue
314 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
316 #ifdef ieee80211_wake_queue
317 #undef ieee80211_wake_queue
320 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
322 static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
325 set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
328 static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
331 clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
334 static inline int iwl_queue_used(const struct iwl_queue *q, int i)
336 return q->write_ptr >= q->read_ptr ?
337 (i >= q->read_ptr && i < q->write_ptr) :
338 !(i < q->read_ptr && i >= q->write_ptr);
341 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
343 return index & (q->n_window - 1);
346 #endif /* __iwl_trans_int_pcie_h__ */