1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
69 #include <net/mac80211.h>
71 #include "iwl-commands.h"
74 #include "iwl-debug.h"
75 #include "iwl-eeprom.h"
78 /************************** EEPROM BANDS ****************************
80 * The iwl_eeprom_band definitions below provide the mapping from the
81 * EEPROM contents to the specific channel number supported for each
84 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
85 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
86 * The specific geography and calibration information for that channel
87 * is contained in the eeprom map itself.
89 * During init, we copy the eeprom information and channel map
90 * information into priv->channel_info_24/52 and priv->channel_map_24/52
92 * channel_map_24/52 provides the index in the channel_info array for a
93 * given channel. We have to have two separate maps as there is channel
94 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * A value of 0xff stored in the channel_map indicates that the channel
98 * is not supported by the hardware at all.
100 * A value of 0xfe in the channel_map indicates that the channel is not
101 * valid for Tx with the current hardware. This means that
102 * while the system can tune and receive on a given channel, it may not
103 * be able to associate or transmit any frames on that
104 * channel. There is no corresponding channel information for that
107 *********************************************************************/
110 const u8 iwl_eeprom_band_1[14] = {
111 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
115 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
116 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
120 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
124 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
128 145, 149, 153, 157, 161, 165
131 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
135 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
136 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
139 /******************************************************************************
141 * EEPROM related functions
143 ******************************************************************************/
146 * The device's EEPROM semaphore prevents conflicts between driver and uCode
147 * when accessing the EEPROM; each access is a series of pulses to/from the
148 * EEPROM chip, not a single event, so even reads could conflict if they
149 * weren't arbitrated by the semaphore.
151 static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
156 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
157 /* Request semaphore */
158 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
159 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
161 /* See if we got it */
162 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
163 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
167 IWL_DEBUG_EEPROM(priv,
168 "Acquired semaphore after %d tries.\n",
177 static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
179 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
180 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
184 static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
186 u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
189 IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
191 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
192 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
193 IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
198 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
199 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
200 if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
201 IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
205 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
207 IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
208 "EEPROM_GP=0x%08x\n",
209 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
210 ? "OTP" : "EEPROM", gp);
217 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
219 iwl_read32(priv, CSR_OTP_GP_REG);
221 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
222 iwl_clear_bit(priv, CSR_OTP_GP_REG,
223 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
225 iwl_set_bit(priv, CSR_OTP_GP_REG,
226 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
229 static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
234 /* OTP only valid for CP/PP and after */
235 switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
236 case CSR_HW_REV_TYPE_NONE:
237 IWL_ERR(priv, "Unknown hardware type\n");
239 case CSR_HW_REV_TYPE_5300:
240 case CSR_HW_REV_TYPE_5350:
241 case CSR_HW_REV_TYPE_5100:
242 case CSR_HW_REV_TYPE_5150:
243 nvm_type = NVM_DEVICE_TYPE_EEPROM;
246 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
247 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
248 nvm_type = NVM_DEVICE_TYPE_OTP;
250 nvm_type = NVM_DEVICE_TYPE_EEPROM;
256 static int iwl_init_otp_access(struct iwl_priv *priv)
260 /* Enable 40MHz radio clock */
261 iwl_write32(priv, CSR_GP_CNTRL,
262 iwl_read32(priv, CSR_GP_CNTRL) |
263 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
265 /* wait for clock to be ready */
266 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
267 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
268 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
271 IWL_ERR(priv, "Time out access OTP\n");
273 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
274 APMG_PS_CTRL_VAL_RESET_REQ);
276 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
277 APMG_PS_CTRL_VAL_RESET_REQ);
280 * CSR auto clock gate disable bit -
281 * this is only applicable for HW with OTP shadow RAM
283 if (priv->cfg->base_params->shadow_ram_support)
284 iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
285 CSR_RESET_LINK_PWR_MGMT_DISABLED);
290 static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data)
296 iwl_write32(priv, CSR_EEPROM_REG,
297 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
298 ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
299 CSR_EEPROM_REG_READ_VALID_MSK,
300 CSR_EEPROM_REG_READ_VALID_MSK,
301 IWL_EEPROM_ACCESS_TIMEOUT);
303 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
306 r = iwl_read32(priv, CSR_EEPROM_REG);
307 /* check for ECC errors: */
308 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
309 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
310 /* stop in this case */
311 /* set the uncorrectable OTP ECC bit for acknowledgement */
312 iwl_set_bit(priv, CSR_OTP_GP_REG,
313 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
314 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
317 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
318 /* continue in this case */
319 /* set the correctable OTP ECC bit for acknowledgement */
320 iwl_set_bit(priv, CSR_OTP_GP_REG,
321 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
322 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
324 *eeprom_data = cpu_to_le16(r >> 16);
329 * iwl_is_otp_empty: check for empty OTP
331 static bool iwl_is_otp_empty(struct iwl_priv *priv)
333 u16 next_link_addr = 0;
335 bool is_empty = false;
337 /* locate the beginning of OTP link list */
338 if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
340 IWL_ERR(priv, "OTP is empty\n");
344 IWL_ERR(priv, "Unable to read first block of OTP list.\n");
353 * iwl_find_otp_image: find EEPROM image in OTP
354 * finding the OTP block that contains the EEPROM image.
355 * the last valid block on the link list (the block _before_ the last block)
356 * is the block we should read and used to configure the device.
357 * If all the available OTP blocks are full, the last block will be the block
358 * we should read and used to configure the device.
359 * only perform this operation if shadow RAM is disabled
361 static int iwl_find_otp_image(struct iwl_priv *priv,
364 u16 next_link_addr = 0, valid_addr;
365 __le16 link_value = 0;
368 /* set addressing mode to absolute to traverse the link list */
369 iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
371 /* checking for empty OTP or error */
372 if (iwl_is_otp_empty(priv))
376 * start traverse link list
377 * until reach the max number of OTP blocks
378 * different devices have different number of OTP blocks
381 /* save current valid block address
382 * check for more block on the link list
384 valid_addr = next_link_addr;
385 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
386 IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n",
387 usedblocks, next_link_addr);
388 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
392 * reach the end of link list, return success and
393 * set address point to the starting address
396 *validblockaddr = valid_addr;
397 /* skip first 2 bytes (link list pointer) */
398 *validblockaddr += 2;
401 /* more in the link list, continue */
403 } while (usedblocks <= priv->cfg->base_params->max_ll_items);
405 /* OTP has no valid blocks */
406 IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n");
410 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
412 return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
415 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
419 return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
423 * iwl_eeprom_init - read EEPROM contents
425 * Load the EEPROM contents from adapter into priv->eeprom
427 * NOTE: This routine uses the non-debug IO access functions.
429 int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
432 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
436 u16 validblockaddr = 0;
439 priv->nvm_device_type = iwlcore_get_nvm_type(priv, hw_rev);
440 if (priv->nvm_device_type == -ENOENT)
442 /* allocate eeprom */
443 sz = priv->cfg->base_params->eeprom_size;
444 IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
445 priv->eeprom = kzalloc(sz, GFP_KERNEL);
450 e = (__le16 *)priv->eeprom;
452 priv->cfg->ops->lib->apm_ops.init(priv);
454 ret = iwl_eeprom_verify_signature(priv);
456 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
461 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
462 ret = iwl_eeprom_acquire_semaphore(priv);
464 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
469 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
471 ret = iwl_init_otp_access(priv);
473 IWL_ERR(priv, "Failed to initialize OTP access.\n");
477 iwl_write32(priv, CSR_EEPROM_GP,
478 iwl_read32(priv, CSR_EEPROM_GP) &
479 ~CSR_EEPROM_GP_IF_OWNER_MSK);
481 iwl_set_bit(priv, CSR_OTP_GP_REG,
482 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
483 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
484 /* traversing the linked list if no shadow ram supported */
485 if (!priv->cfg->base_params->shadow_ram_support) {
486 if (iwl_find_otp_image(priv, &validblockaddr)) {
491 for (addr = validblockaddr; addr < validblockaddr + sz;
492 addr += sizeof(u16)) {
495 ret = iwl_read_otp_word(priv, addr, &eeprom_data);
498 e[cache_addr / 2] = eeprom_data;
499 cache_addr += sizeof(u16);
502 /* eeprom is an array of 16bit values */
503 for (addr = 0; addr < sz; addr += sizeof(u16)) {
506 iwl_write32(priv, CSR_EEPROM_REG,
507 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
509 ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
510 CSR_EEPROM_REG_READ_VALID_MSK,
511 CSR_EEPROM_REG_READ_VALID_MSK,
512 IWL_EEPROM_ACCESS_TIMEOUT);
514 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
517 r = iwl_read32(priv, CSR_EEPROM_REG);
518 e[addr / 2] = cpu_to_le16(r >> 16);
522 IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
523 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
525 iwl_eeprom_query16(priv, EEPROM_VERSION));
529 iwl_eeprom_release_semaphore(priv);
533 iwl_eeprom_free(priv);
534 /* Reset chip to save power until we load uCode during "up". */
540 void iwl_eeprom_free(struct iwl_priv *priv)
546 static void iwl_init_band_reference(const struct iwl_priv *priv,
547 int eep_band, int *eeprom_ch_count,
548 const struct iwl_eeprom_channel **eeprom_ch_info,
549 const u8 **eeprom_ch_index)
551 u32 offset = priv->cfg->ops->lib->
552 eeprom_ops.regulatory_bands[eep_band - 1];
554 case 1: /* 2.4GHz band */
555 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
556 *eeprom_ch_info = (struct iwl_eeprom_channel *)
557 iwl_eeprom_query_addr(priv, offset);
558 *eeprom_ch_index = iwl_eeprom_band_1;
560 case 2: /* 4.9GHz band */
561 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
562 *eeprom_ch_info = (struct iwl_eeprom_channel *)
563 iwl_eeprom_query_addr(priv, offset);
564 *eeprom_ch_index = iwl_eeprom_band_2;
566 case 3: /* 5.2GHz band */
567 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
568 *eeprom_ch_info = (struct iwl_eeprom_channel *)
569 iwl_eeprom_query_addr(priv, offset);
570 *eeprom_ch_index = iwl_eeprom_band_3;
572 case 4: /* 5.5GHz band */
573 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
574 *eeprom_ch_info = (struct iwl_eeprom_channel *)
575 iwl_eeprom_query_addr(priv, offset);
576 *eeprom_ch_index = iwl_eeprom_band_4;
578 case 5: /* 5.7GHz band */
579 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
580 *eeprom_ch_info = (struct iwl_eeprom_channel *)
581 iwl_eeprom_query_addr(priv, offset);
582 *eeprom_ch_index = iwl_eeprom_band_5;
584 case 6: /* 2.4GHz ht40 channels */
585 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
586 *eeprom_ch_info = (struct iwl_eeprom_channel *)
587 iwl_eeprom_query_addr(priv, offset);
588 *eeprom_ch_index = iwl_eeprom_band_6;
590 case 7: /* 5 GHz ht40 channels */
591 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
592 *eeprom_ch_info = (struct iwl_eeprom_channel *)
593 iwl_eeprom_query_addr(priv, offset);
594 *eeprom_ch_index = iwl_eeprom_band_7;
602 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
605 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
607 * Does not set up a command, or touch hardware.
609 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
610 enum ieee80211_band band, u16 channel,
611 const struct iwl_eeprom_channel *eeprom_ch,
612 u8 clear_ht40_extension_channel)
614 struct iwl_channel_info *ch_info;
616 ch_info = (struct iwl_channel_info *)
617 iwl_get_channel_info(priv, band, channel);
619 if (!is_channel_valid(ch_info))
622 IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
623 " Ad-Hoc %ssupported\n",
625 is_channel_a_band(ch_info) ?
627 CHECK_AND_PRINT(IBSS),
628 CHECK_AND_PRINT(ACTIVE),
629 CHECK_AND_PRINT(RADAR),
630 CHECK_AND_PRINT(WIDE),
631 CHECK_AND_PRINT(DFS),
633 eeprom_ch->max_power_avg,
634 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
635 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
638 ch_info->ht40_eeprom = *eeprom_ch;
639 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
640 ch_info->ht40_flags = eeprom_ch->flags;
641 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
642 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
647 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
651 * iwl_init_channel_map - Set up driver's info for all possible channels
653 int iwl_init_channel_map(struct iwl_priv *priv)
655 int eeprom_ch_count = 0;
656 const u8 *eeprom_ch_index = NULL;
657 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
659 struct iwl_channel_info *ch_info;
661 if (priv->channel_count) {
662 IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
666 IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
668 priv->channel_count =
669 ARRAY_SIZE(iwl_eeprom_band_1) +
670 ARRAY_SIZE(iwl_eeprom_band_2) +
671 ARRAY_SIZE(iwl_eeprom_band_3) +
672 ARRAY_SIZE(iwl_eeprom_band_4) +
673 ARRAY_SIZE(iwl_eeprom_band_5);
675 IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
676 priv->channel_count);
678 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
679 priv->channel_count, GFP_KERNEL);
680 if (!priv->channel_info) {
681 IWL_ERR(priv, "Could not allocate channel_info\n");
682 priv->channel_count = 0;
686 ch_info = priv->channel_info;
688 /* Loop through the 5 EEPROM bands adding them in order to the
689 * channel map we maintain (that contains additional information than
690 * what just in the EEPROM) */
691 for (band = 1; band <= 5; band++) {
693 iwl_init_band_reference(priv, band, &eeprom_ch_count,
694 &eeprom_ch_info, &eeprom_ch_index);
696 /* Loop through each band adding each of the channels */
697 for (ch = 0; ch < eeprom_ch_count; ch++) {
698 ch_info->channel = eeprom_ch_index[ch];
699 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
702 /* permanently store EEPROM's channel regulatory flags
703 * and max power in channel info database. */
704 ch_info->eeprom = eeprom_ch_info[ch];
706 /* Copy the run-time flags so they are there even on
707 * invalid channels */
708 ch_info->flags = eeprom_ch_info[ch].flags;
709 /* First write that ht40 is not enabled, and then enable
711 ch_info->ht40_extension_channel =
712 IEEE80211_CHAN_NO_HT40;
714 if (!(is_channel_valid(ch_info))) {
715 IWL_DEBUG_EEPROM(priv,
716 "Ch. %d Flags %x [%sGHz] - "
720 is_channel_a_band(ch_info) ?
726 /* Initialize regulatory-based run-time data */
727 ch_info->max_power_avg = ch_info->curr_txpow =
728 eeprom_ch_info[ch].max_power_avg;
729 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
730 ch_info->min_power = 0;
732 IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
733 "%s%s%s%s%s%s(0x%02x %ddBm):"
734 " Ad-Hoc %ssupported\n",
736 is_channel_a_band(ch_info) ?
738 CHECK_AND_PRINT_I(VALID),
739 CHECK_AND_PRINT_I(IBSS),
740 CHECK_AND_PRINT_I(ACTIVE),
741 CHECK_AND_PRINT_I(RADAR),
742 CHECK_AND_PRINT_I(WIDE),
743 CHECK_AND_PRINT_I(DFS),
744 eeprom_ch_info[ch].flags,
745 eeprom_ch_info[ch].max_power_avg,
746 ((eeprom_ch_info[ch].
747 flags & EEPROM_CHANNEL_IBSS)
748 && !(eeprom_ch_info[ch].
749 flags & EEPROM_CHANNEL_RADAR))
756 /* Check if we do have HT40 channels */
757 if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
758 EEPROM_REGULATORY_BAND_NO_HT40 &&
759 priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
760 EEPROM_REGULATORY_BAND_NO_HT40)
763 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
764 for (band = 6; band <= 7; band++) {
765 enum ieee80211_band ieeeband;
767 iwl_init_band_reference(priv, band, &eeprom_ch_count,
768 &eeprom_ch_info, &eeprom_ch_index);
770 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
772 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
774 /* Loop through each band adding each of the channels */
775 for (ch = 0; ch < eeprom_ch_count; ch++) {
776 /* Set up driver's info for lower half */
777 iwl_mod_ht40_chan_info(priv, ieeeband,
780 IEEE80211_CHAN_NO_HT40PLUS);
782 /* Set up driver's info for upper half */
783 iwl_mod_ht40_chan_info(priv, ieeeband,
784 eeprom_ch_index[ch] + 4,
786 IEEE80211_CHAN_NO_HT40MINUS);
790 /* for newer device (6000 series and up)
791 * EEPROM contain enhanced tx power information
792 * driver need to process addition information
793 * to determine the max channel tx power limits
795 if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower)
796 priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv);
802 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
804 void iwl_free_channel_map(struct iwl_priv *priv)
806 kfree(priv->channel_info);
807 priv->channel_count = 0;
811 * iwl_get_channel_info - Find driver's private channel info
813 * Based on band and channel number.
815 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
816 enum ieee80211_band band, u16 channel)
821 case IEEE80211_BAND_5GHZ:
822 for (i = 14; i < priv->channel_count; i++) {
823 if (priv->channel_info[i].channel == channel)
824 return &priv->channel_info[i];
827 case IEEE80211_BAND_2GHZ:
828 if (channel >= 1 && channel <= 14)
829 return &priv->channel_info[channel - 1];