drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88 MODULE_ALIAS("iwl4965");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 /**
  94  * iwl_commit_rxon - commit staging_rxon to hardware
  95  *
  96  * The RXON command in staging_rxon is committed to the hardware and
  97  * the active_rxon structure is updated with the new data.  This
  98  * function correctly transitions out of the RXON_ASSOC_MSK state if
  99  * a HW tune is required based on the RXON structure changes.
 100  */
 101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 102 {
 103         /* cast away the const for active_rxon in this function */
 104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
 105         int ret;
 106         bool new_assoc =
 107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
 108         bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
 109
 110         if (!iwl_is_alive(priv))
 111                 return -EBUSY;
 112
 113         /* always get timestamp with Rx frame */
 114         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
 115
 116         ret = iwl_check_rxon_cmd(priv, ctx);
 117         if (ret) {
 118                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
 119                 return -EINVAL;
 120         }
 121
 122         /*
 123          * receive commit_rxon request
 124          * abort any previous channel switch if still in process
 125          */
 126         if (priv->switch_rxon.switch_in_progress &&
 127             (priv->switch_rxon.channel != ctx->staging.channel)) {
 128                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
 129                       le16_to_cpu(priv->switch_rxon.channel));
 130                 iwl_chswitch_done(priv, false);
 131         }
 132
 133         /* If we don't need to send a full RXON, we can use
 134          * iwl_rxon_assoc_cmd which is used to reconfigure filter
 135          * and other flags for the current radio configuration. */
 136         if (!iwl_full_rxon_required(priv, ctx)) {
 137                 ret = iwl_send_rxon_assoc(priv, ctx);
 138                 if (ret) {
 139                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
 140                         return ret;
 141                 }
 142
 143                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 144                 iwl_print_rx_config_cmd(priv, ctx);
 145                 return 0;
 146         }
 147
 148         /* If we are currently associated and the new config requires
 149          * an RXON_ASSOC and the new config wants the associated mask enabled,
 150          * we must clear the associated from the active configuration
 151          * before we apply the new config */
 152         if (iwl_is_associated_ctx(ctx) && new_assoc) {
 153                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
 154                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 155
 156                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 157                                        sizeof(struct iwl_rxon_cmd),
 158                                        active_rxon);
 159
 160                 /* If the mask clearing failed then we set
 161                  * active_rxon back to what it was previously */
 162                 if (ret) {
 163                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
 164                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
 165                         return ret;
 166                 }
 167                 iwl_clear_ucode_stations(priv, ctx);
 168                 iwl_restore_stations(priv, ctx);
 169                 ret = iwl_restore_default_wep_keys(priv, ctx);
 170                 if (ret) {
 171                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 172                         return ret;
 173                 }
 174         }
 175
 176         IWL_DEBUG_INFO(priv, "Sending RXON\n"
 177                        "* with%s RXON_FILTER_ASSOC_MSK\n"
 178                        "* channel = %d\n"
 179                        "* bssid = %pM\n",
 180                        (new_assoc ? "" : "out"),
 181                        le16_to_cpu(ctx->staging.channel),
 182                        ctx->staging.bssid_addr);
 183
 184         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
 185
 186         if (!old_assoc) {
 187                 /*
 188                  * First of all, before setting associated, we need to
 189                  * send RXON timing so the device knows about the DTIM
 190                  * period and other timing values
 191                  */
 192                 ret = iwl_send_rxon_timing(priv, ctx);
 193                 if (ret) {
 194                         IWL_ERR(priv, "Error setting RXON timing!\n");
 195                         return ret;
 196                 }
 197         }
 198
 199         if (priv->cfg->ops->hcmd->set_pan_params) {
 200                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
 201                 if (ret)
 202                         return ret;
 203         }
 204
 205         /* Apply the new configuration
 206          * RXON unassoc clears the station table in uCode so restoration of
 207          * stations is needed after it (the RXON command) completes
 208          */
 209         if (!new_assoc) {
 210                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 211                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 212                 if (ret) {
 213                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 214                         return ret;
 215                 }
 216                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
 217                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 218                 iwl_clear_ucode_stations(priv, ctx);
 219                 iwl_restore_stations(priv, ctx);
 220                 ret = iwl_restore_default_wep_keys(priv, ctx);
 221                 if (ret) {
 222                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 223                         return ret;
 224                 }
 225         }
 226
 227         priv->start_calib = 0;
 228         if (new_assoc) {
 229                 /* Apply the new configuration
 230                  * RXON assoc doesn't clear the station table in uCode,
 231                  */
 232                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 233                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 234                 if (ret) {
 235                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 236                         return ret;
 237                 }
 238                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 239         }
 240         iwl_print_rx_config_cmd(priv, ctx);
 241
 242         iwl_init_sensitivity(priv);
 243
 244         /* If we issue a new RXON command which required a tune then we must
 245          * send a new TXPOWER command or we won't be able to Tx any frames */
 246         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
 247         if (ret) {
 248                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
 249                 return ret;
 250         }
 251
 252         return 0;
 253 }
 254
 255 void iwl_update_chain_flags(struct iwl_priv *priv)
 256 {
 257         struct iwl_rxon_context *ctx;
 258
 259         if (priv->cfg->ops->hcmd->set_rxon_chain) {
 260                 for_each_context(priv, ctx) {
 261                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 262                         iwlcore_commit_rxon(priv, ctx);
 263                 }
 264         }
 265 }
 266
 267 static void iwl_clear_free_frames(struct iwl_priv *priv)
 268 {
 269         struct list_head *element;
 270
 271         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 272                        priv->frames_count);
 273
 274         while (!list_empty(&priv->free_frames)) {
 275                 element = priv->free_frames.next;
 276                 list_del(element);
 277                 kfree(list_entry(element, struct iwl_frame, list));
 278                 priv->frames_count--;
 279         }
 280
 281         if (priv->frames_count) {
 282                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 283                             priv->frames_count);
 284                 priv->frames_count = 0;
 285         }
 286 }
 287
 288 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 289 {
 290         struct iwl_frame *frame;
 291         struct list_head *element;
 292         if (list_empty(&priv->free_frames)) {
 293                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 294                 if (!frame) {
 295                         IWL_ERR(priv, "Could not allocate frame!\n");
 296                         return NULL;
 297                 }
 298
 299                 priv->frames_count++;
 300                 return frame;
 301         }
 302
 303         element = priv->free_frames.next;
 304         list_del(element);
 305         return list_entry(element, struct iwl_frame, list);
 306 }
 307
 308 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 309 {
 310         memset(frame, 0, sizeof(*frame));
 311         list_add(&frame->list, &priv->free_frames);
 312 }
 313
 314 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 315                                           struct ieee80211_hdr *hdr,
 316                                           int left)
 317 {
 318         if (!priv->ibss_beacon)
 319                 return 0;
 320
 321         if (priv->ibss_beacon->len > left)
 322                 return 0;
 323
 324         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
 325
 326         return priv->ibss_beacon->len;
 327 }
 328
 329 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 330 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 331                 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 332                 u8 *beacon, u32 frame_size)
 333 {
 334         u16 tim_idx;
 335         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 336
 337         /*
 338          * The index is relative to frame start but we start looking at the
 339          * variable-length part of the beacon.
 340          */
 341         tim_idx = mgmt->u.beacon.variable - beacon;
 342
 343         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 344         while ((tim_idx < (frame_size - 2)) &&
 345                         (beacon[tim_idx] != WLAN_EID_TIM))
 346                 tim_idx += beacon[tim_idx+1] + 2;
 347
 348         /* If TIM field was found, set variables */
 349         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 350                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 351                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 352         } else
 353                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 354 }
 355
 356 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 357                                        struct iwl_frame *frame)
 358 {
 359         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 360         u32 frame_size;
 361         u32 rate_flags;
 362         u32 rate;
 363         /*
 364          * We have to set up the TX command, the TX Beacon command, and the
 365          * beacon contents.
 366          */
 367
 368         lockdep_assert_held(&priv->mutex);
 369
 370         if (!priv->beacon_ctx) {
 371                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 372                 return -EINVAL;
 373         }
 374
 375         /* Initialize memory */
 376         tx_beacon_cmd = &frame->u.beacon;
 377         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 378
 379         /* Set up TX beacon contents */
 380         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 381                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 382         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 383                 return 0;
 384
 385         /* Set up TX command fields */
 386         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 387         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 388         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 389         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 390                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 391
 392         /* Set up TX beacon command fields */
 393         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 394                         frame_size);
 395
 396         /* Set up packet rate and flags */
 397         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 398         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 399                                               priv->hw_params.valid_tx_ant);
 400         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 401         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 402                 rate_flags |= RATE_MCS_CCK_MSK;
 403         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 404                         rate_flags);
 405
 406         return sizeof(*tx_beacon_cmd) + frame_size;
 407 }
 408 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
 409 {
 410         struct iwl_frame *frame;
 411         unsigned int frame_size;
 412         int rc;
 413
 414         frame = iwl_get_free_frame(priv);
 415         if (!frame) {
 416                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 417                           "command.\n");
 418                 return -ENOMEM;
 419         }
 420
 421         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 422         if (!frame_size) {
 423                 IWL_ERR(priv, "Error configuring the beacon command\n");
 424                 iwl_free_frame(priv, frame);
 425                 return -EINVAL;
 426         }
 427
 428         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 429                               &frame->u.cmd[0]);
 430
 431         iwl_free_frame(priv, frame);
 432
 433         return rc;
 434 }
 435
 436 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 437 {
 438         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 439
 440         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 441         if (sizeof(dma_addr_t) > sizeof(u32))
 442                 addr |=
 443                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 444
 445         return addr;
 446 }
 447
 448 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 449 {
 450         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 451
 452         return le16_to_cpu(tb->hi_n_len) >> 4;
 453 }
 454
 455 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 456                                   dma_addr_t addr, u16 len)
 457 {
 458         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 459         u16 hi_n_len = len << 4;
 460
 461         put_unaligned_le32(addr, &tb->lo);
 462         if (sizeof(dma_addr_t) > sizeof(u32))
 463                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 464
 465         tb->hi_n_len = cpu_to_le16(hi_n_len);
 466
 467         tfd->num_tbs = idx + 1;
 468 }
 469
 470 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 471 {
 472         return tfd->num_tbs & 0x1f;
 473 }
 474
 475 /**
 476  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 477  * @priv - driver private data
 478  * @txq - tx queue
 479  *
 480  * Does NOT advance any TFD circular buffer read/write indexes
 481  * Does NOT free the TFD itself (which is within circular buffer)
 482  */
 483 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 484 {
 485         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 486         struct iwl_tfd *tfd;
 487         struct pci_dev *dev = priv->pci_dev;
 488         int index = txq->q.read_ptr;
 489         int i;
 490         int num_tbs;
 491
 492         tfd = &tfd_tmp[index];
 493
 494         /* Sanity check on number of chunks */
 495         num_tbs = iwl_tfd_get_num_tbs(tfd);
 496
 497         if (num_tbs >= IWL_NUM_OF_TBS) {
 498                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 499                 /* @todo issue fatal error, it is quite serious situation */
 500                 return;
 501         }
 502
 503         /* Unmap tx_cmd */
 504         if (num_tbs)
 505                 pci_unmap_single(dev,
 506                                 dma_unmap_addr(&txq->meta[index], mapping),
 507                                 dma_unmap_len(&txq->meta[index], len),
 508                                 PCI_DMA_BIDIRECTIONAL);
 509
 510         /* Unmap chunks, if any. */
 511         for (i = 1; i < num_tbs; i++)
 512                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 513                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 514
 515         /* free SKB */
 516         if (txq->txb) {
 517                 struct sk_buff *skb;
 518
 519                 skb = txq->txb[txq->q.read_ptr].skb;
 520
 521                 /* can be called from irqs-disabled context */
 522                 if (skb) {
 523                         dev_kfree_skb_any(skb);
 524                         txq->txb[txq->q.read_ptr].skb = NULL;
 525                 }
 526         }
 527 }
 528
 529 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 530                                  struct iwl_tx_queue *txq,
 531                                  dma_addr_t addr, u16 len,
 532                                  u8 reset, u8 pad)
 533 {
 534         struct iwl_queue *q;
 535         struct iwl_tfd *tfd, *tfd_tmp;
 536         u32 num_tbs;
 537
 538         q = &txq->q;
 539         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 540         tfd = &tfd_tmp[q->write_ptr];
 541
 542         if (reset)
 543                 memset(tfd, 0, sizeof(*tfd));
 544
 545         num_tbs = iwl_tfd_get_num_tbs(tfd);
 546
 547         /* Each TFD can point to a maximum 20 Tx buffers */
 548         if (num_tbs >= IWL_NUM_OF_TBS) {
 549                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 550                           IWL_NUM_OF_TBS);
 551                 return -EINVAL;
 552         }
 553
 554         BUG_ON(addr & ~DMA_BIT_MASK(36));
 555         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 556                 IWL_ERR(priv, "Unaligned address = %llx\n",
 557                           (unsigned long long)addr);
 558
 559         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 560
 561         return 0;
 562 }
 563
 564 /*
 565  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 566  * given Tx queue, and enable the DMA channel used for that queue.
 567  *
 568  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 569  * channels supported in hardware.
 570  */
 571 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 572                          struct iwl_tx_queue *txq)
 573 {
 574         int txq_id = txq->q.id;
 575
 576         /* Circular buffer (TFD queue in DRAM) physical base address */
 577         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 578                              txq->q.dma_addr >> 8);
 579
 580         return 0;
 581 }
 582
 583 /******************************************************************************
 584  *
 585  * Generic RX handler implementations
 586  *
 587  ******************************************************************************/
 588 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 589                                 struct iwl_rx_mem_buffer *rxb)
 590 {
 591         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 592         struct iwl_alive_resp *palive;
 593         struct delayed_work *pwork;
 594
 595         palive = &pkt->u.alive_frame;
 596
 597         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 598                        "0x%01X 0x%01X\n",
 599                        palive->is_valid, palive->ver_type,
 600                        palive->ver_subtype);
 601
 602         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 603                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 604                 memcpy(&priv->card_alive_init,
 605                        &pkt->u.alive_frame,
 606                        sizeof(struct iwl_init_alive_resp));
 607                 pwork = &priv->init_alive_start;
 608         } else {
 609                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 610                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 611                        sizeof(struct iwl_alive_resp));
 612                 pwork = &priv->alive_start;
 613         }
 614
 615         /* We delay the ALIVE response by 5ms to
 616          * give the HW RF Kill time to activate... */
 617         if (palive->is_valid == UCODE_VALID_OK)
 618                 queue_delayed_work(priv->workqueue, pwork,
 619                                    msecs_to_jiffies(5));
 620         else
 621                 IWL_WARN(priv, "uCode did not respond OK.\n");
 622 }
 623
 624 static void iwl_bg_beacon_update(struct work_struct *work)
 625 {
 626         struct iwl_priv *priv =
 627                 container_of(work, struct iwl_priv, beacon_update);
 628         struct sk_buff *beacon;
 629
 630         mutex_lock(&priv->mutex);
 631         if (!priv->beacon_ctx) {
 632                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 633                 goto out;
 634         }
 635
 636         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 637                 /*
 638                  * The ucode will send beacon notifications even in
 639                  * IBSS mode, but we don't want to process them. But
 640                  * we need to defer the type check to here due to
 641                  * requiring locking around the beacon_ctx access.
 642                  */
 643                 goto out;
 644         }
 645
 646         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 647         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 648         if (!beacon) {
 649                 IWL_ERR(priv, "update beacon failed\n");
 650                 goto out;
 651         }
 652
 653         /* new beacon skb is allocated every time; dispose previous.*/
 654         if (priv->ibss_beacon)
 655                 dev_kfree_skb(priv->ibss_beacon);
 656
 657         priv->ibss_beacon = beacon;
 658
 659         iwl_send_beacon_cmd(priv);
 660  out:
 661         mutex_unlock(&priv->mutex);
 662 }
 663
 664 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 665 {
 666         struct iwl_priv *priv =
 667                 container_of(work, struct iwl_priv, bt_runtime_config);
 668
 669         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 670                 return;
 671
 672         /* dont send host command if rf-kill is on */
 673         if (!iwl_is_ready_rf(priv))
 674                 return;
 675         priv->cfg->ops->hcmd->send_bt_config(priv);
 676 }
 677
 678 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 679 {
 680         struct iwl_priv *priv =
 681                 container_of(work, struct iwl_priv, bt_full_concurrency);
 682         struct iwl_rxon_context *ctx;
 683
 684         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 685                 return;
 686
 687         /* dont send host command if rf-kill is on */
 688         if (!iwl_is_ready_rf(priv))
 689                 return;
 690
 691         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 692                        priv->bt_full_concurrent ?
 693                        "full concurrency" : "3-wire");
 694
 695         /*
 696          * LQ & RXON updated cmds must be sent before BT Config cmd
 697          * to avoid 3-wire collisions
 698          */
 699         mutex_lock(&priv->mutex);
 700         for_each_context(priv, ctx) {
 701                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 702                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 703                 iwlcore_commit_rxon(priv, ctx);
 704         }
 705         mutex_unlock(&priv->mutex);
 706
 707         priv->cfg->ops->hcmd->send_bt_config(priv);
 708 }
 709
 710 /**
 711  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 712  *
 713  * This callback is provided in order to send a statistics request.
 714  *
 715  * This timer function is continually reset to execute within
 716  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 717  * was received.  We need to ensure we receive the statistics in order
 718  * to update the temperature used for calibrating the TXPOWER.
 719  */
 720 static void iwl_bg_statistics_periodic(unsigned long data)
 721 {
 722         struct iwl_priv *priv = (struct iwl_priv *)data;
 723
 724         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 725                 return;
 726
 727         /* dont send host command if rf-kill is on */
 728         if (!iwl_is_ready_rf(priv))
 729                 return;
 730
 731         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 732 }
 733
 734
 735 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 736                                         u32 start_idx, u32 num_events,
 737                                         u32 mode)
 738 {
 739         u32 i;
 740         u32 ptr;        /* SRAM byte address of log data */
 741         u32 ev, time, data; /* event log data */
 742         unsigned long reg_flags;
 743
 744         if (mode == 0)
 745                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 746         else
 747                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 748
 749         /* Make sure device is powered up for SRAM reads */
 750         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 751         if (iwl_grab_nic_access(priv)) {
 752                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 753                 return;
 754         }
 755
 756         /* Set starting address; reads will auto-increment */
 757         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 758         rmb();
 759
 760         /*
 761          * "time" is actually "data" for mode 0 (no timestamp).
 762          * place event id # at far right for easier visual parsing.
 763          */
 764         for (i = 0; i < num_events; i++) {
 765                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 766                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 767                 if (mode == 0) {
 768                         trace_iwlwifi_dev_ucode_cont_event(priv,
 769                                                         0, time, ev);
 770                 } else {
 771                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 772                         trace_iwlwifi_dev_ucode_cont_event(priv,
 773                                                 time, data, ev);
 774                 }
 775         }
 776         /* Allow device to power down */
 777         iwl_release_nic_access(priv);
 778         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 779 }
 780
 781 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 782 {
 783         u32 capacity;   /* event log capacity in # entries */
 784         u32 base;       /* SRAM byte address of event log header */
 785         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 786         u32 num_wraps;  /* # times uCode wrapped to top of log */
 787         u32 next_entry; /* index of next entry to be written by uCode */
 788
 789         if (priv->ucode_type == UCODE_INIT)
 790                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 791         else
 792                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 793         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 794                 capacity = iwl_read_targ_mem(priv, base);
 795                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 796                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 797                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 798         } else
 799                 return;
 800
 801         if (num_wraps == priv->event_log.num_wraps) {
 802                 iwl_print_cont_event_trace(priv,
 803                                        base, priv->event_log.next_entry,
 804                                        next_entry - priv->event_log.next_entry,
 805                                        mode);
 806                 priv->event_log.non_wraps_count++;
 807         } else {
 808                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 809                         priv->event_log.wraps_more_count++;
 810                 else
 811                         priv->event_log.wraps_once_count++;
 812                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 813                                 num_wraps - priv->event_log.num_wraps,
 814                                 next_entry, priv->event_log.next_entry);
 815                 if (next_entry < priv->event_log.next_entry) {
 816                         iwl_print_cont_event_trace(priv, base,
 817                                priv->event_log.next_entry,
 818                                capacity - priv->event_log.next_entry,
 819                                mode);
 820
 821                         iwl_print_cont_event_trace(priv, base, 0,
 822                                 next_entry, mode);
 823                 } else {
 824                         iwl_print_cont_event_trace(priv, base,
 825                                next_entry, capacity - next_entry,
 826                                mode);
 827
 828                         iwl_print_cont_event_trace(priv, base, 0,
 829                                 next_entry, mode);
 830                 }
 831         }
 832         priv->event_log.num_wraps = num_wraps;
 833         priv->event_log.next_entry = next_entry;
 834 }
 835
 836 /**
 837  * iwl_bg_ucode_trace - Timer callback to log ucode event
 838  *
 839  * The timer is continually set to execute every
 840  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 841  * this function is to perform continuous uCode event logging operation
 842  * if enabled
 843  */
 844 static void iwl_bg_ucode_trace(unsigned long data)
 845 {
 846         struct iwl_priv *priv = (struct iwl_priv *)data;
 847
 848         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 849                 return;
 850
 851         if (priv->event_log.ucode_trace) {
 852                 iwl_continuous_event_trace(priv);
 853                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 854                 mod_timer(&priv->ucode_trace,
 855                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 856         }
 857 }
 858
 859 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 860                                 struct iwl_rx_mem_buffer *rxb)
 861 {
 862         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 863         struct iwl4965_beacon_notif *beacon =
 864                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 865 #ifdef CONFIG_IWLWIFI_DEBUG
 866         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 867
 868         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 869                 "tsf %d %d rate %d\n",
 870                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 871                 beacon->beacon_notify_hdr.failure_frame,
 872                 le32_to_cpu(beacon->ibss_mgr_status),
 873                 le32_to_cpu(beacon->high_tsf),
 874                 le32_to_cpu(beacon->low_tsf), rate);
 875 #endif
 876
 877         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 878
 879         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 880                 queue_work(priv->workqueue, &priv->beacon_update);
 881 }
 882
 883 /* Handle notification from uCode that card's power state is changing
 884  * due to software, hardware, or critical temperature RFKILL */
 885 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 886                                     struct iwl_rx_mem_buffer *rxb)
 887 {
 888         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 889         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 890         unsigned long status = priv->status;
 891
 892         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 893                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 894                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 895                           (flags & CT_CARD_DISABLED) ?
 896                           "Reached" : "Not reached");
 897
 898         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 899                      CT_CARD_DISABLED)) {
 900
 901                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 902                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 903
 904                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 905                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 906
 907                 if (!(flags & RXON_CARD_DISABLED)) {
 908                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 909                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 910                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 911                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 912                 }
 913                 if (flags & CT_CARD_DISABLED)
 914                         iwl_tt_enter_ct_kill(priv);
 915         }
 916         if (!(flags & CT_CARD_DISABLED))
 917                 iwl_tt_exit_ct_kill(priv);
 918
 919         if (flags & HW_CARD_DISABLED)
 920                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 921         else
 922                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 923
 924
 925         if (!(flags & RXON_CARD_DISABLED))
 926                 iwl_scan_cancel(priv);
 927
 928         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 929              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 930                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 931                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 932         else
 933                 wake_up_interruptible(&priv->wait_command_queue);
 934 }
 935
 936 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 937 {
 938         if (src == IWL_PWR_SRC_VAUX) {
 939                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 940                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 941                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 942                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 943         } else {
 944                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 945                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 946                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 947         }
 948
 949         return 0;
 950 }
 951
 952 static void iwl_bg_tx_flush(struct work_struct *work)
 953 {
 954         struct iwl_priv *priv =
 955                 container_of(work, struct iwl_priv, tx_flush);
 956
 957         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 958                 return;
 959
 960         /* do nothing if rf-kill is on */
 961         if (!iwl_is_ready_rf(priv))
 962                 return;
 963
 964         if (priv->cfg->ops->lib->txfifo_flush) {
 965                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 966                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 967         }
 968 }
 969
 970 /**
 971  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 972  *
 973  * Setup the RX handlers for each of the reply types sent from the uCode
 974  * to the host.
 975  *
 976  * This function chains into the hardware specific files for them to setup
 977  * any hardware specific handlers as well.
 978  */
 979 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 980 {
 981         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 982         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 983         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 984         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 985                         iwl_rx_spectrum_measure_notif;
 986         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 987         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 988             iwl_rx_pm_debug_statistics_notif;
 989         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 990
 991         /*
 992          * The same handler is used for both the REPLY to a discrete
 993          * statistics request from the host as well as for the periodic
 994          * statistics notifications (after received beacons) from the uCode.
 995          */
 996         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 997         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 998
 999         iwl_setup_rx_scan_handlers(priv);
1000
1001         /* status change handler */
1002         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
1003
1004         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1005             iwl_rx_missed_beacon_notif;
1006         /* Rx handlers */
1007         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1008         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
1009         /* block ack */
1010         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
1011         /* Set up hardware specific Rx handlers */
1012         priv->cfg->ops->lib->rx_handler_setup(priv);
1013 }
1014
1015 /**
1016  * iwl_rx_handle - Main entry function for receiving responses from uCode
1017  *
1018  * Uses the priv->rx_handlers callback function array to invoke
1019  * the appropriate handlers, including command responses,
1020  * frame-received notifications, and other notifications.
1021  */
1022 void iwl_rx_handle(struct iwl_priv *priv)
1023 {
1024         struct iwl_rx_mem_buffer *rxb;
1025         struct iwl_rx_packet *pkt;
1026         struct iwl_rx_queue *rxq = &priv->rxq;
1027         u32 r, i;
1028         int reclaim;
1029         unsigned long flags;
1030         u8 fill_rx = 0;
1031         u32 count = 8;
1032         int total_empty;
1033
1034         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1035          * buffer that the driver may process (last buffer filled by ucode). */
1036         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1037         i = rxq->read;
1038
1039         /* Rx interrupt, but nothing sent from uCode */
1040         if (i == r)
1041                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1042
1043         /* calculate total frames need to be restock after handling RX */
1044         total_empty = r - rxq->write_actual;
1045         if (total_empty < 0)
1046                 total_empty += RX_QUEUE_SIZE;
1047
1048         if (total_empty > (RX_QUEUE_SIZE / 2))
1049                 fill_rx = 1;
1050
1051         while (i != r) {
1052                 int len;
1053
1054                 rxb = rxq->queue[i];
1055
1056                 /* If an RXB doesn't have a Rx queue slot associated with it,
1057                  * then a bug has been introduced in the queue refilling
1058                  * routines -- catch it here */
1059                 BUG_ON(rxb == NULL);
1060
1061                 rxq->queue[i] = NULL;
1062
1063                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1064                                PAGE_SIZE << priv->hw_params.rx_page_order,
1065                                PCI_DMA_FROMDEVICE);
1066                 pkt = rxb_addr(rxb);
1067
1068                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1069                 len += sizeof(u32); /* account for status word */
1070                 trace_iwlwifi_dev_rx(priv, pkt, len);
1071
1072                 /* Reclaim a command buffer only if this packet is a response
1073                  *   to a (driver-originated) command.
1074                  * If the packet (e.g. Rx frame) originated from uCode,
1075                  *   there is no command buffer to reclaim.
1076                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1077                  *   but apparently a few don't get set; catch them here. */
1078                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1079                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1080                         (pkt->hdr.cmd != REPLY_RX) &&
1081                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1082                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1083                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1084                         (pkt->hdr.cmd != REPLY_TX);
1085
1086                 /* Based on type of command response or notification,
1087                  *   handle those that need handling via function in
1088                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1089                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1090                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1091                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1092                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1093                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1094                 } else {
1095                         /* No handling needed */
1096                         IWL_DEBUG_RX(priv,
1097                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1098                                 r, i, get_cmd_string(pkt->hdr.cmd),
1099                                 pkt->hdr.cmd);
1100                 }
1101
1102                 /*
1103                  * XXX: After here, we should always check rxb->page
1104                  * against NULL before touching it or its virtual
1105                  * memory (pkt). Because some rx_handler might have
1106                  * already taken or freed the pages.
1107                  */
1108
1109                 if (reclaim) {
1110                         /* Invoke any callbacks, transfer the buffer to caller,
1111                          * and fire off the (possibly) blocking iwl_send_cmd()
1112                          * as we reclaim the driver command queue */
1113                         if (rxb->page)
1114                                 iwl_tx_cmd_complete(priv, rxb);
1115                         else
1116                                 IWL_WARN(priv, "Claim null rxb?\n");
1117                 }
1118
1119                 /* Reuse the page if possible. For notification packets and
1120                  * SKBs that fail to Rx correctly, add them back into the
1121                  * rx_free list for reuse later. */
1122                 spin_lock_irqsave(&rxq->lock, flags);
1123                 if (rxb->page != NULL) {
1124                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1125                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1126                                 PCI_DMA_FROMDEVICE);
1127                         list_add_tail(&rxb->list, &rxq->rx_free);
1128                         rxq->free_count++;
1129                 } else
1130                         list_add_tail(&rxb->list, &rxq->rx_used);
1131
1132                 spin_unlock_irqrestore(&rxq->lock, flags);
1133
1134                 i = (i + 1) & RX_QUEUE_MASK;
1135                 /* If there are a lot of unused frames,
1136                  * restock the Rx queue so ucode wont assert. */
1137                 if (fill_rx) {
1138                         count++;
1139                         if (count >= 8) {
1140                                 rxq->read = i;
1141                                 iwlagn_rx_replenish_now(priv);
1142                                 count = 0;
1143                         }
1144                 }
1145         }
1146
1147         /* Backtrack one entry */
1148         rxq->read = i;
1149         if (fill_rx)
1150                 iwlagn_rx_replenish_now(priv);
1151         else
1152                 iwlagn_rx_queue_restock(priv);
1153 }
1154
1155 /* call this function to flush any scheduled tasklet */
1156 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1157 {
1158         /* wait to make sure we flush pending tasklet*/
1159         synchronize_irq(priv->pci_dev->irq);
1160         tasklet_kill(&priv->irq_tasklet);
1161 }
1162
1163 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1164 {
1165         u32 inta, handled = 0;
1166         u32 inta_fh;
1167         unsigned long flags;
1168         u32 i;
1169 #ifdef CONFIG_IWLWIFI_DEBUG
1170         u32 inta_mask;
1171 #endif
1172
1173         spin_lock_irqsave(&priv->lock, flags);
1174
1175         /* Ack/clear/reset pending uCode interrupts.
1176          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1177          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1178         inta = iwl_read32(priv, CSR_INT);
1179         iwl_write32(priv, CSR_INT, inta);
1180
1181         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1182          * Any new interrupts that happen after this, either while we're
1183          * in this tasklet, or later, will show up in next ISR/tasklet. */
1184         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1185         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1186
1187 #ifdef CONFIG_IWLWIFI_DEBUG
1188         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1189                 /* just for debug */
1190                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1191                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1192                               inta, inta_mask, inta_fh);
1193         }
1194 #endif
1195
1196         spin_unlock_irqrestore(&priv->lock, flags);
1197
1198         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1199          * atomic, make sure that inta covers all the interrupts that
1200          * we've discovered, even if FH interrupt came in just after
1201          * reading CSR_INT. */
1202         if (inta_fh & CSR49_FH_INT_RX_MASK)
1203                 inta |= CSR_INT_BIT_FH_RX;
1204         if (inta_fh & CSR49_FH_INT_TX_MASK)
1205                 inta |= CSR_INT_BIT_FH_TX;
1206
1207         /* Now service all interrupt bits discovered above. */
1208         if (inta & CSR_INT_BIT_HW_ERR) {
1209                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1210
1211                 /* Tell the device to stop sending interrupts */
1212                 iwl_disable_interrupts(priv);
1213
1214                 priv->isr_stats.hw++;
1215                 iwl_irq_handle_error(priv);
1216
1217                 handled |= CSR_INT_BIT_HW_ERR;
1218
1219                 return;
1220         }
1221
1222 #ifdef CONFIG_IWLWIFI_DEBUG
1223         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1224                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1225                 if (inta & CSR_INT_BIT_SCD) {
1226                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1227                                       "the frame/frames.\n");
1228                         priv->isr_stats.sch++;
1229                 }
1230
1231                 /* Alive notification via Rx interrupt will do the real work */
1232                 if (inta & CSR_INT_BIT_ALIVE) {
1233                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1234                         priv->isr_stats.alive++;
1235                 }
1236         }
1237 #endif
1238         /* Safely ignore these bits for debug checks below */
1239         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1240
1241         /* HW RF KILL switch toggled */
1242         if (inta & CSR_INT_BIT_RF_KILL) {
1243                 int hw_rf_kill = 0;
1244                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1245                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1246                         hw_rf_kill = 1;
1247
1248                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1249                                 hw_rf_kill ? "disable radio" : "enable radio");
1250
1251                 priv->isr_stats.rfkill++;
1252
1253                 /* driver only loads ucode once setting the interface up.
1254                  * the driver allows loading the ucode even if the radio
1255                  * is killed. Hence update the killswitch state here. The
1256                  * rfkill handler will care about restarting if needed.
1257                  */
1258                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1259                         if (hw_rf_kill)
1260                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1261                         else
1262                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1263                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1264                 }
1265
1266                 handled |= CSR_INT_BIT_RF_KILL;
1267         }
1268
1269         /* Chip got too hot and stopped itself */
1270         if (inta & CSR_INT_BIT_CT_KILL) {
1271                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1272                 priv->isr_stats.ctkill++;
1273                 handled |= CSR_INT_BIT_CT_KILL;
1274         }
1275
1276         /* Error detected by uCode */
1277         if (inta & CSR_INT_BIT_SW_ERR) {
1278                 IWL_ERR(priv, "Microcode SW error detected. "
1279                         " Restarting 0x%X.\n", inta);
1280                 priv->isr_stats.sw++;
1281                 priv->isr_stats.sw_err = inta;
1282                 iwl_irq_handle_error(priv);
1283                 handled |= CSR_INT_BIT_SW_ERR;
1284         }
1285
1286         /*
1287          * uCode wakes up after power-down sleep.
1288          * Tell device about any new tx or host commands enqueued,
1289          * and about any Rx buffers made available while asleep.
1290          */
1291         if (inta & CSR_INT_BIT_WAKEUP) {
1292                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1293                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1294                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1295                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1296                 priv->isr_stats.wakeup++;
1297                 handled |= CSR_INT_BIT_WAKEUP;
1298         }
1299
1300         /* All uCode command responses, including Tx command responses,
1301          * Rx "responses" (frame-received notification), and other
1302          * notifications from uCode come through here*/
1303         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1304                 iwl_rx_handle(priv);
1305                 priv->isr_stats.rx++;
1306                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1307         }
1308
1309         /* This "Tx" DMA channel is used only for loading uCode */
1310         if (inta & CSR_INT_BIT_FH_TX) {
1311                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1312                 priv->isr_stats.tx++;
1313                 handled |= CSR_INT_BIT_FH_TX;
1314                 /* Wake up uCode load routine, now that load is complete */
1315                 priv->ucode_write_complete = 1;
1316                 wake_up_interruptible(&priv->wait_command_queue);
1317         }
1318
1319         if (inta & ~handled) {
1320                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1321                 priv->isr_stats.unhandled++;
1322         }
1323
1324         if (inta & ~(priv->inta_mask)) {
1325                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1326                          inta & ~priv->inta_mask);
1327                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1328         }
1329
1330         /* Re-enable all interrupts */
1331         /* only Re-enable if diabled by irq */
1332         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1333                 iwl_enable_interrupts(priv);
1334
1335 #ifdef CONFIG_IWLWIFI_DEBUG
1336         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1337                 inta = iwl_read32(priv, CSR_INT);
1338                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1339                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1340                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1341                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1342         }
1343 #endif
1344 }
1345
1346 /* tasklet for iwlagn interrupt */
1347 static void iwl_irq_tasklet(struct iwl_priv *priv)
1348 {
1349         u32 inta = 0;
1350         u32 handled = 0;
1351         unsigned long flags;
1352         u32 i;
1353 #ifdef CONFIG_IWLWIFI_DEBUG
1354         u32 inta_mask;
1355 #endif
1356
1357         spin_lock_irqsave(&priv->lock, flags);
1358
1359         /* Ack/clear/reset pending uCode interrupts.
1360          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1361          */
1362         /* There is a hardware bug in the interrupt mask function that some
1363          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1364          * they are disabled in the CSR_INT_MASK register. Furthermore the
1365          * ICT interrupt handling mechanism has another bug that might cause
1366          * these unmasked interrupts fail to be detected. We workaround the
1367          * hardware bugs here by ACKing all the possible interrupts so that
1368          * interrupt coalescing can still be achieved.
1369          */
1370         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1371
1372         inta = priv->_agn.inta;
1373
1374 #ifdef CONFIG_IWLWIFI_DEBUG
1375         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1376                 /* just for debug */
1377                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1378                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1379                                 inta, inta_mask);
1380         }
1381 #endif
1382
1383         spin_unlock_irqrestore(&priv->lock, flags);
1384
1385         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1386         priv->_agn.inta = 0;
1387
1388         /* Now service all interrupt bits discovered above. */
1389         if (inta & CSR_INT_BIT_HW_ERR) {
1390                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1391
1392                 /* Tell the device to stop sending interrupts */
1393                 iwl_disable_interrupts(priv);
1394
1395                 priv->isr_stats.hw++;
1396                 iwl_irq_handle_error(priv);
1397
1398                 handled |= CSR_INT_BIT_HW_ERR;
1399
1400                 return;
1401         }
1402
1403 #ifdef CONFIG_IWLWIFI_DEBUG
1404         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1405                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1406                 if (inta & CSR_INT_BIT_SCD) {
1407                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1408                                       "the frame/frames.\n");
1409                         priv->isr_stats.sch++;
1410                 }
1411
1412                 /* Alive notification via Rx interrupt will do the real work */
1413                 if (inta & CSR_INT_BIT_ALIVE) {
1414                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1415                         priv->isr_stats.alive++;
1416                 }
1417         }
1418 #endif
1419         /* Safely ignore these bits for debug checks below */
1420         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1421
1422         /* HW RF KILL switch toggled */
1423         if (inta & CSR_INT_BIT_RF_KILL) {
1424                 int hw_rf_kill = 0;
1425                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1426                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1427                         hw_rf_kill = 1;
1428
1429                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1430                                 hw_rf_kill ? "disable radio" : "enable radio");
1431
1432                 priv->isr_stats.rfkill++;
1433
1434                 /* driver only loads ucode once setting the interface up.
1435                  * the driver allows loading the ucode even if the radio
1436                  * is killed. Hence update the killswitch state here. The
1437                  * rfkill handler will care about restarting if needed.
1438                  */
1439                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1440                         if (hw_rf_kill)
1441                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1442                         else
1443                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1444                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1445                 }
1446
1447                 handled |= CSR_INT_BIT_RF_KILL;
1448         }
1449
1450         /* Chip got too hot and stopped itself */
1451         if (inta & CSR_INT_BIT_CT_KILL) {
1452                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1453                 priv->isr_stats.ctkill++;
1454                 handled |= CSR_INT_BIT_CT_KILL;
1455         }
1456
1457         /* Error detected by uCode */
1458         if (inta & CSR_INT_BIT_SW_ERR) {
1459                 IWL_ERR(priv, "Microcode SW error detected. "
1460                         " Restarting 0x%X.\n", inta);
1461                 priv->isr_stats.sw++;
1462                 priv->isr_stats.sw_err = inta;
1463                 iwl_irq_handle_error(priv);
1464                 handled |= CSR_INT_BIT_SW_ERR;
1465         }
1466
1467         /* uCode wakes up after power-down sleep */
1468         if (inta & CSR_INT_BIT_WAKEUP) {
1469                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1470                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1471                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1472                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1473
1474                 priv->isr_stats.wakeup++;
1475
1476                 handled |= CSR_INT_BIT_WAKEUP;
1477         }
1478
1479         /* All uCode command responses, including Tx command responses,
1480          * Rx "responses" (frame-received notification), and other
1481          * notifications from uCode come through here*/
1482         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1483                         CSR_INT_BIT_RX_PERIODIC)) {
1484                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1485                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1486                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1487                         iwl_write32(priv, CSR_FH_INT_STATUS,
1488                                         CSR49_FH_INT_RX_MASK);
1489                 }
1490                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1491                         handled |= CSR_INT_BIT_RX_PERIODIC;
1492                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1493                 }
1494                 /* Sending RX interrupt require many steps to be done in the
1495                  * the device:
1496                  * 1- write interrupt to current index in ICT table.
1497                  * 2- dma RX frame.
1498                  * 3- update RX shared data to indicate last write index.
1499                  * 4- send interrupt.
1500                  * This could lead to RX race, driver could receive RX interrupt
1501                  * but the shared data changes does not reflect this;
1502                  * periodic interrupt will detect any dangling Rx activity.
1503                  */
1504
1505                 /* Disable periodic interrupt; we use it as just a one-shot. */
1506                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1507                             CSR_INT_PERIODIC_DIS);
1508                 iwl_rx_handle(priv);
1509
1510                 /*
1511                  * Enable periodic interrupt in 8 msec only if we received
1512                  * real RX interrupt (instead of just periodic int), to catch
1513                  * any dangling Rx interrupt.  If it was just the periodic
1514                  * interrupt, there was no dangling Rx activity, and no need
1515                  * to extend the periodic interrupt; one-shot is enough.
1516                  */
1517                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1518                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1519                                     CSR_INT_PERIODIC_ENA);
1520
1521                 priv->isr_stats.rx++;
1522         }
1523
1524         /* This "Tx" DMA channel is used only for loading uCode */
1525         if (inta & CSR_INT_BIT_FH_TX) {
1526                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1527                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1528                 priv->isr_stats.tx++;
1529                 handled |= CSR_INT_BIT_FH_TX;
1530                 /* Wake up uCode load routine, now that load is complete */
1531                 priv->ucode_write_complete = 1;
1532                 wake_up_interruptible(&priv->wait_command_queue);
1533         }
1534
1535         if (inta & ~handled) {
1536                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1537                 priv->isr_stats.unhandled++;
1538         }
1539
1540         if (inta & ~(priv->inta_mask)) {
1541                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1542                          inta & ~priv->inta_mask);
1543         }
1544
1545         /* Re-enable all interrupts */
1546         /* only Re-enable if diabled by irq */
1547         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1548                 iwl_enable_interrupts(priv);
1549 }
1550
1551 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1552 #define ACK_CNT_RATIO (50)
1553 #define BA_TIMEOUT_CNT (5)
1554 #define BA_TIMEOUT_MAX (16)
1555
1556 /**
1557  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1558  *
1559  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1560  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1561  * operation state.
1562  */
1563 bool iwl_good_ack_health(struct iwl_priv *priv,
1564                                 struct iwl_rx_packet *pkt)
1565 {
1566         bool rc = true;
1567         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1568         int ba_timeout_delta;
1569
1570         actual_ack_cnt_delta =
1571                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1572                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1573         expected_ack_cnt_delta =
1574                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1575                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1576         ba_timeout_delta =
1577                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1578                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1579         if ((priv->_agn.agg_tids_count > 0) &&
1580             (expected_ack_cnt_delta > 0) &&
1581             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1582                 < ACK_CNT_RATIO) &&
1583             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1584                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1585                                 " expected_ack_cnt = %d\n",
1586                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1587
1588 #ifdef CONFIG_IWLWIFI_DEBUGFS
1589                 /*
1590                  * This is ifdef'ed on DEBUGFS because otherwise the
1591                  * statistics aren't available. If DEBUGFS is set but
1592                  * DEBUG is not, these will just compile out.
1593                  */
1594                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1595                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1596                 IWL_DEBUG_RADIO(priv,
1597                                 "ack_or_ba_timeout_collision delta = %d\n",
1598                                 priv->_agn.delta_statistics.tx.
1599                                 ack_or_ba_timeout_collision);
1600 #endif
1601                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1602                                 ba_timeout_delta);
1603                 if (!actual_ack_cnt_delta &&
1604                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1605                         rc = false;
1606         }
1607         return rc;
1608 }
1609
1610
1611 /*****************************************************************************
1612  *
1613  * sysfs attributes
1614  *
1615  *****************************************************************************/
1616
1617 #ifdef CONFIG_IWLWIFI_DEBUG
1618
1619 /*
1620  * The following adds a new attribute to the sysfs representation
1621  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1622  * used for controlling the debug level.
1623  *
1624  * See the level definitions in iwl for details.
1625  *
1626  * The debug_level being managed using sysfs below is a per device debug
1627  * level that is used instead of the global debug level if it (the per
1628  * device debug level) is set.
1629  */
1630 static ssize_t show_debug_level(struct device *d,
1631                                 struct device_attribute *attr, char *buf)
1632 {
1633         struct iwl_priv *priv = dev_get_drvdata(d);
1634         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1635 }
1636 static ssize_t store_debug_level(struct device *d,
1637                                 struct device_attribute *attr,
1638                                  const char *buf, size_t count)
1639 {
1640         struct iwl_priv *priv = dev_get_drvdata(d);
1641         unsigned long val;
1642         int ret;
1643
1644         ret = strict_strtoul(buf, 0, &val);
1645         if (ret)
1646                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1647         else {
1648                 priv->debug_level = val;
1649                 if (iwl_alloc_traffic_mem(priv))
1650                         IWL_ERR(priv,
1651                                 "Not enough memory to generate traffic log\n");
1652         }
1653         return strnlen(buf, count);
1654 }
1655
1656 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1657                         show_debug_level, store_debug_level);
1658
1659
1660 #endif /* CONFIG_IWLWIFI_DEBUG */
1661
1662
1663 static ssize_t show_temperature(struct device *d,
1664                                 struct device_attribute *attr, char *buf)
1665 {
1666         struct iwl_priv *priv = dev_get_drvdata(d);
1667
1668         if (!iwl_is_alive(priv))
1669                 return -EAGAIN;
1670
1671         return sprintf(buf, "%d\n", priv->temperature);
1672 }
1673
1674 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1675
1676 static ssize_t show_tx_power(struct device *d,
1677                              struct device_attribute *attr, char *buf)
1678 {
1679         struct iwl_priv *priv = dev_get_drvdata(d);
1680
1681         if (!iwl_is_ready_rf(priv))
1682                 return sprintf(buf, "off\n");
1683         else
1684                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1685 }
1686
1687 static ssize_t store_tx_power(struct device *d,
1688                               struct device_attribute *attr,
1689                               const char *buf, size_t count)
1690 {
1691         struct iwl_priv *priv = dev_get_drvdata(d);
1692         unsigned long val;
1693         int ret;
1694
1695         ret = strict_strtoul(buf, 10, &val);
1696         if (ret)
1697                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1698         else {
1699                 ret = iwl_set_tx_power(priv, val, false);
1700                 if (ret)
1701                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1702                                 ret);
1703                 else
1704                         ret = count;
1705         }
1706         return ret;
1707 }
1708
1709 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1710
1711 static struct attribute *iwl_sysfs_entries[] = {
1712         &dev_attr_temperature.attr,
1713         &dev_attr_tx_power.attr,
1714 #ifdef CONFIG_IWLWIFI_DEBUG
1715         &dev_attr_debug_level.attr,
1716 #endif
1717         NULL
1718 };
1719
1720 static struct attribute_group iwl_attribute_group = {
1721         .name = NULL,           /* put in device directory */
1722         .attrs = iwl_sysfs_entries,
1723 };
1724
1725 /******************************************************************************
1726  *
1727  * uCode download functions
1728  *
1729  ******************************************************************************/
1730
1731 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1732 {
1733         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1734         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1735         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1736         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1737         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1738         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1739 }
1740
1741 static void iwl_nic_start(struct iwl_priv *priv)
1742 {
1743         /* Remove all resets to allow NIC to operate */
1744         iwl_write32(priv, CSR_RESET, 0);
1745 }
1746
1747 struct iwlagn_ucode_capabilities {
1748         u32 max_probe_length;
1749         u32 standard_phy_calibration_size;
1750         bool pan;
1751 };
1752
1753 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1754 static int iwl_mac_setup_register(struct iwl_priv *priv,
1755                                   struct iwlagn_ucode_capabilities *capa);
1756
1757 #define UCODE_EXPERIMENTAL_INDEX        100
1758 #define UCODE_EXPERIMENTAL_TAG          "exp"
1759
1760 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1761 {
1762         const char *name_pre = priv->cfg->fw_name_pre;
1763         char tag[8];
1764
1765         if (first) {
1766 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1767                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1768                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1769         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1770 #endif
1771                 priv->fw_index = priv->cfg->ucode_api_max;
1772                 sprintf(tag, "%d", priv->fw_index);
1773         } else {
1774                 priv->fw_index--;
1775                 sprintf(tag, "%d", priv->fw_index);
1776         }
1777
1778         if (priv->fw_index < priv->cfg->ucode_api_min) {
1779                 IWL_ERR(priv, "no suitable firmware found!\n");
1780                 return -ENOENT;
1781         }
1782
1783         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1784
1785         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1786                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1787                                 ? "EXPERIMENTAL " : "",
1788                        priv->firmware_name);
1789
1790         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1791                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1792                                        iwl_ucode_callback);
1793 }
1794
1795 struct iwlagn_firmware_pieces {
1796         const void *inst, *data, *init, *init_data, *boot;
1797         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1798
1799         u32 build;
1800
1801         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1802         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1803 };
1804
1805 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1806                                        const struct firmware *ucode_raw,
1807                                        struct iwlagn_firmware_pieces *pieces)
1808 {
1809         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1810         u32 api_ver, hdr_size;
1811         const u8 *src;
1812
1813         priv->ucode_ver = le32_to_cpu(ucode->ver);
1814         api_ver = IWL_UCODE_API(priv->ucode_ver);
1815
1816         switch (api_ver) {
1817         default:
1818                 /*
1819                  * 4965 doesn't revision the firmware file format
1820                  * along with the API version, it always uses v1
1821                  * file format.
1822                  */
1823                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1824                                 CSR_HW_REV_TYPE_4965) {
1825                         hdr_size = 28;
1826                         if (ucode_raw->size < hdr_size) {
1827                                 IWL_ERR(priv, "File size too small!\n");
1828                                 return -EINVAL;
1829                         }
1830                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1831                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1832                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1833                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1834                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1835                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1836                         src = ucode->u.v2.data;
1837                         break;
1838                 }
1839                 /* fall through for 4965 */
1840         case 0:
1841         case 1:
1842         case 2:
1843                 hdr_size = 24;
1844                 if (ucode_raw->size < hdr_size) {
1845                         IWL_ERR(priv, "File size too small!\n");
1846                         return -EINVAL;
1847                 }
1848                 pieces->build = 0;
1849                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1850                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1851                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1852                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1853                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1854                 src = ucode->u.v1.data;
1855                 break;
1856         }
1857
1858         /* Verify size of file vs. image size info in file's header */
1859         if (ucode_raw->size != hdr_size + pieces->inst_size +
1860                                 pieces->data_size + pieces->init_size +
1861                                 pieces->init_data_size + pieces->boot_size) {
1862
1863                 IWL_ERR(priv,
1864                         "uCode file size %d does not match expected size\n",
1865                         (int)ucode_raw->size);
1866                 return -EINVAL;
1867         }
1868
1869         pieces->inst = src;
1870         src += pieces->inst_size;
1871         pieces->data = src;
1872         src += pieces->data_size;
1873         pieces->init = src;
1874         src += pieces->init_size;
1875         pieces->init_data = src;
1876         src += pieces->init_data_size;
1877         pieces->boot = src;
1878         src += pieces->boot_size;
1879
1880         return 0;
1881 }
1882
1883 static int iwlagn_wanted_ucode_alternative = 1;
1884
1885 static int iwlagn_load_firmware(struct iwl_priv *priv,
1886                                 const struct firmware *ucode_raw,
1887                                 struct iwlagn_firmware_pieces *pieces,
1888                                 struct iwlagn_ucode_capabilities *capa)
1889 {
1890         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1891         struct iwl_ucode_tlv *tlv;
1892         size_t len = ucode_raw->size;
1893         const u8 *data;
1894         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1895         u64 alternatives;
1896         u32 tlv_len;
1897         enum iwl_ucode_tlv_type tlv_type;
1898         const u8 *tlv_data;
1899
1900         if (len < sizeof(*ucode)) {
1901                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1902                 return -EINVAL;
1903         }
1904
1905         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1906                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1907                         le32_to_cpu(ucode->magic));
1908                 return -EINVAL;
1909         }
1910
1911         /*
1912          * Check which alternatives are present, and "downgrade"
1913          * when the chosen alternative is not present, warning
1914          * the user when that happens. Some files may not have
1915          * any alternatives, so don't warn in that case.
1916          */
1917         alternatives = le64_to_cpu(ucode->alternatives);
1918         tmp = wanted_alternative;
1919         if (wanted_alternative > 63)
1920                 wanted_alternative = 63;
1921         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1922                 wanted_alternative--;
1923         if (wanted_alternative && wanted_alternative != tmp)
1924                 IWL_WARN(priv,
1925                          "uCode alternative %d not available, choosing %d\n",
1926                          tmp, wanted_alternative);
1927
1928         priv->ucode_ver = le32_to_cpu(ucode->ver);
1929         pieces->build = le32_to_cpu(ucode->build);
1930         data = ucode->data;
1931
1932         len -= sizeof(*ucode);
1933
1934         while (len >= sizeof(*tlv)) {
1935                 u16 tlv_alt;
1936
1937                 len -= sizeof(*tlv);
1938                 tlv = (void *)data;
1939
1940                 tlv_len = le32_to_cpu(tlv->length);
1941                 tlv_type = le16_to_cpu(tlv->type);
1942                 tlv_alt = le16_to_cpu(tlv->alternative);
1943                 tlv_data = tlv->data;
1944
1945                 if (len < tlv_len) {
1946                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1947                                 len, tlv_len);
1948                         return -EINVAL;
1949                 }
1950                 len -= ALIGN(tlv_len, 4);
1951                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1952
1953                 /*
1954                  * Alternative 0 is always valid.
1955                  *
1956                  * Skip alternative TLVs that are not selected.
1957                  */
1958                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1959                         continue;
1960
1961                 switch (tlv_type) {
1962                 case IWL_UCODE_TLV_INST:
1963                         pieces->inst = tlv_data;
1964                         pieces->inst_size = tlv_len;
1965                         break;
1966                 case IWL_UCODE_TLV_DATA:
1967                         pieces->data = tlv_data;
1968                         pieces->data_size = tlv_len;
1969                         break;
1970                 case IWL_UCODE_TLV_INIT:
1971                         pieces->init = tlv_data;
1972                         pieces->init_size = tlv_len;
1973                         break;
1974                 case IWL_UCODE_TLV_INIT_DATA:
1975                         pieces->init_data = tlv_data;
1976                         pieces->init_data_size = tlv_len;
1977                         break;
1978                 case IWL_UCODE_TLV_BOOT:
1979                         pieces->boot = tlv_data;
1980                         pieces->boot_size = tlv_len;
1981                         break;
1982                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1983                         if (tlv_len != sizeof(u32))
1984                                 goto invalid_tlv_len;
1985                         capa->max_probe_length =
1986                                         le32_to_cpup((__le32 *)tlv_data);
1987                         break;
1988                 case IWL_UCODE_TLV_PAN:
1989                         if (tlv_len)
1990                                 goto invalid_tlv_len;
1991                         capa->pan = true;
1992                         break;
1993                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1994                         if (tlv_len != sizeof(u32))
1995                                 goto invalid_tlv_len;
1996                         pieces->init_evtlog_ptr =
1997                                         le32_to_cpup((__le32 *)tlv_data);
1998                         break;
1999                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
2000                         if (tlv_len != sizeof(u32))
2001                                 goto invalid_tlv_len;
2002                         pieces->init_evtlog_size =
2003                                         le32_to_cpup((__le32 *)tlv_data);
2004                         break;
2005                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
2006                         if (tlv_len != sizeof(u32))
2007                                 goto invalid_tlv_len;
2008                         pieces->init_errlog_ptr =
2009                                         le32_to_cpup((__le32 *)tlv_data);
2010                         break;
2011                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
2012                         if (tlv_len != sizeof(u32))
2013                                 goto invalid_tlv_len;
2014                         pieces->inst_evtlog_ptr =
2015                                         le32_to_cpup((__le32 *)tlv_data);
2016                         break;
2017                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
2018                         if (tlv_len != sizeof(u32))
2019                                 goto invalid_tlv_len;
2020                         pieces->inst_evtlog_size =
2021                                         le32_to_cpup((__le32 *)tlv_data);
2022                         break;
2023                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
2024                         if (tlv_len != sizeof(u32))
2025                                 goto invalid_tlv_len;
2026                         pieces->inst_errlog_ptr =
2027                                         le32_to_cpup((__le32 *)tlv_data);
2028                         break;
2029                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2030                         if (tlv_len)
2031                                 goto invalid_tlv_len;
2032                         priv->enhance_sensitivity_table = true;
2033                         break;
2034                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
2035                         if (tlv_len != sizeof(u32))
2036                                 goto invalid_tlv_len;
2037                         capa->standard_phy_calibration_size =
2038                                         le32_to_cpup((__le32 *)tlv_data);
2039                         break;
2040                 default:
2041                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2042                         break;
2043                 }
2044         }
2045
2046         if (len) {
2047                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2048                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2049                 return -EINVAL;
2050         }
2051
2052         return 0;
2053
2054  invalid_tlv_len:
2055         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2056         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2057
2058         return -EINVAL;
2059 }
2060
2061 /**
2062  * iwl_ucode_callback - callback when firmware was loaded
2063  *
2064  * If loaded successfully, copies the firmware into buffers
2065  * for the card to fetch (via DMA).
2066  */
2067 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2068 {
2069         struct iwl_priv *priv = context;
2070         struct iwl_ucode_header *ucode;
2071         int err;
2072         struct iwlagn_firmware_pieces pieces;
2073         const unsigned int api_max = priv->cfg->ucode_api_max;
2074         const unsigned int api_min = priv->cfg->ucode_api_min;
2075         u32 api_ver;
2076         char buildstr[25];
2077         u32 build;
2078         struct iwlagn_ucode_capabilities ucode_capa = {
2079                 .max_probe_length = 200,
2080                 .standard_phy_calibration_size =
2081                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2082         };
2083
2084         memset(&pieces, 0, sizeof(pieces));
2085
2086         if (!ucode_raw) {
2087                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2088                         IWL_ERR(priv,
2089                                 "request for firmware file '%s' failed.\n",
2090                                 priv->firmware_name);
2091                 goto try_again;
2092         }
2093
2094         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2095                        priv->firmware_name, ucode_raw->size);
2096
2097         /* Make sure that we got at least the API version number */
2098         if (ucode_raw->size < 4) {
2099                 IWL_ERR(priv, "File size way too small!\n");
2100                 goto try_again;
2101         }
2102
2103         /* Data from ucode file:  header followed by uCode images */
2104         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2105
2106         if (ucode->ver)
2107                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2108         else
2109                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2110                                            &ucode_capa);
2111
2112         if (err)
2113                 goto try_again;
2114
2115         api_ver = IWL_UCODE_API(priv->ucode_ver);
2116         build = pieces.build;
2117
2118         /*
2119          * api_ver should match the api version forming part of the
2120          * firmware filename ... but we don't check for that and only rely
2121          * on the API version read from firmware header from here on forward
2122          */
2123         if (api_ver < api_min || api_ver > api_max) {
2124                 IWL_ERR(priv, "Driver unable to support your firmware API. "
2125                           "Driver supports v%u, firmware is v%u.\n",
2126                           api_max, api_ver);
2127                 goto try_again;
2128         }
2129
2130         if (api_ver != api_max)
2131                 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2132                           "got v%u. New firmware can be obtained "
2133                           "from http://www.intellinuxwireless.org.\n",
2134                           api_max, api_ver);
2135
2136         if (build)
2137                 sprintf(buildstr, " build %u%s", build,
2138                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2139                                 ? " (EXP)" : "");
2140         else
2141                 buildstr[0] = '\0';
2142
2143         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2144                  IWL_UCODE_MAJOR(priv->ucode_ver),
2145                  IWL_UCODE_MINOR(priv->ucode_ver),
2146                  IWL_UCODE_API(priv->ucode_ver),
2147                  IWL_UCODE_SERIAL(priv->ucode_ver),
2148                  buildstr);
2149
2150         snprintf(priv->hw->wiphy->fw_version,
2151                  sizeof(priv->hw->wiphy->fw_version),
2152                  "%u.%u.%u.%u%s",
2153                  IWL_UCODE_MAJOR(priv->ucode_ver),
2154                  IWL_UCODE_MINOR(priv->ucode_ver),
2155                  IWL_UCODE_API(priv->ucode_ver),
2156                  IWL_UCODE_SERIAL(priv->ucode_ver),
2157                  buildstr);
2158
2159         /*
2160          * For any of the failures below (before allocating pci memory)
2161          * we will try to load a version with a smaller API -- maybe the
2162          * user just got a corrupted version of the latest API.
2163          */
2164
2165         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2166                        priv->ucode_ver);
2167         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2168                        pieces.inst_size);
2169         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2170                        pieces.data_size);
2171         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2172                        pieces.init_size);
2173         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2174                        pieces.init_data_size);
2175         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2176                        pieces.boot_size);
2177
2178         /* Verify that uCode images will fit in card's SRAM */
2179         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2180                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2181                         pieces.inst_size);
2182                 goto try_again;
2183         }
2184
2185         if (pieces.data_size > priv->hw_params.max_data_size) {
2186                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2187                         pieces.data_size);
2188                 goto try_again;
2189         }
2190
2191         if (pieces.init_size > priv->hw_params.max_inst_size) {
2192                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2193                         pieces.init_size);
2194                 goto try_again;
2195         }
2196
2197         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2198                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2199                         pieces.init_data_size);
2200                 goto try_again;
2201         }
2202
2203         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2204                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2205                         pieces.boot_size);
2206                 goto try_again;
2207         }
2208
2209         /* Allocate ucode buffers for card's bus-master loading ... */
2210
2211         /* Runtime instructions and 2 copies of data:
2212          * 1) unmodified from disk
2213          * 2) backup cache for save/restore during power-downs */
2214         priv->ucode_code.len = pieces.inst_size;
2215         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2216
2217         priv->ucode_data.len = pieces.data_size;
2218         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2219
2220         priv->ucode_data_backup.len = pieces.data_size;
2221         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2222
2223         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2224             !priv->ucode_data_backup.v_addr)
2225                 goto err_pci_alloc;
2226
2227         /* Initialization instructions and data */
2228         if (pieces.init_size && pieces.init_data_size) {
2229                 priv->ucode_init.len = pieces.init_size;
2230                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2231
2232                 priv->ucode_init_data.len = pieces.init_data_size;
2233                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2234
2235                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2236                         goto err_pci_alloc;
2237         }
2238
2239         /* Bootstrap (instructions only, no data) */
2240         if (pieces.boot_size) {
2241                 priv->ucode_boot.len = pieces.boot_size;
2242                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2243
2244                 if (!priv->ucode_boot.v_addr)
2245                         goto err_pci_alloc;
2246         }
2247
2248         /* Now that we can no longer fail, copy information */
2249
2250         /*
2251          * The (size - 16) / 12 formula is based on the information recorded
2252          * for each event, which is of mode 1 (including timestamp) for all
2253          * new microcodes that include this information.
2254          */
2255         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2256         if (pieces.init_evtlog_size)
2257                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2258         else
2259                 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2260         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2261         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2262         if (pieces.inst_evtlog_size)
2263                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2264         else
2265                 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2266         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2267
2268         if (ucode_capa.pan) {
2269                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2270                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2271         } else
2272                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2273
2274         /* Copy images into buffers for card's bus-master reads ... */
2275
2276         /* Runtime instructions (first block of data in file) */
2277         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2278                         pieces.inst_size);
2279         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2280
2281         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2282                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2283
2284         /*
2285          * Runtime data
2286          * NOTE:  Copy into backup buffer will be done in iwl_up()
2287          */
2288         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2289                         pieces.data_size);
2290         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2291         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2292
2293         /* Initialization instructions */
2294         if (pieces.init_size) {
2295                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2296                                 pieces.init_size);
2297                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2298         }
2299
2300         /* Initialization data */
2301         if (pieces.init_data_size) {
2302                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2303                                pieces.init_data_size);
2304                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2305                        pieces.init_data_size);
2306         }
2307
2308         /* Bootstrap instructions */
2309         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2310                         pieces.boot_size);
2311         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2312
2313         /*
2314          * figure out the offset of chain noise reset and gain commands
2315          * base on the size of standard phy calibration commands table size
2316          */
2317         if (ucode_capa.standard_phy_calibration_size >
2318             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2319                 ucode_capa.standard_phy_calibration_size =
2320                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2321
2322         priv->_agn.phy_calib_chain_noise_reset_cmd =
2323                 ucode_capa.standard_phy_calibration_size;
2324         priv->_agn.phy_calib_chain_noise_gain_cmd =
2325                 ucode_capa.standard_phy_calibration_size + 1;
2326
2327         /**************************************************
2328          * This is still part of probe() in a sense...
2329          *
2330          * 9. Setup and register with mac80211 and debugfs
2331          **************************************************/
2332         err = iwl_mac_setup_register(priv, &ucode_capa);
2333         if (err)
2334                 goto out_unbind;
2335
2336         err = iwl_dbgfs_register(priv, DRV_NAME);
2337         if (err)
2338                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2339
2340         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2341                                         &iwl_attribute_group);
2342         if (err) {
2343                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2344                 goto out_unbind;
2345         }
2346
2347         /* We have our copies now, allow OS release its copies */
2348         release_firmware(ucode_raw);
2349         complete(&priv->_agn.firmware_loading_complete);
2350         return;
2351
2352  try_again:
2353         /* try next, if any */
2354         if (iwl_request_firmware(priv, false))
2355                 goto out_unbind;
2356         release_firmware(ucode_raw);
2357         return;
2358
2359  err_pci_alloc:
2360         IWL_ERR(priv, "failed to allocate pci memory\n");
2361         iwl_dealloc_ucode_pci(priv);
2362  out_unbind:
2363         complete(&priv->_agn.firmware_loading_complete);
2364         device_release_driver(&priv->pci_dev->dev);
2365         release_firmware(ucode_raw);
2366 }
2367
2368 static const char *desc_lookup_text[] = {
2369         "OK",
2370         "FAIL",
2371         "BAD_PARAM",
2372         "BAD_CHECKSUM",
2373         "NMI_INTERRUPT_WDG",
2374         "SYSASSERT",
2375         "FATAL_ERROR",
2376         "BAD_COMMAND",
2377         "HW_ERROR_TUNE_LOCK",
2378         "HW_ERROR_TEMPERATURE",
2379         "ILLEGAL_CHAN_FREQ",
2380         "VCC_NOT_STABLE",
2381         "FH_ERROR",
2382         "NMI_INTERRUPT_HOST",
2383         "NMI_INTERRUPT_ACTION_PT",
2384         "NMI_INTERRUPT_UNKNOWN",
2385         "UCODE_VERSION_MISMATCH",
2386         "HW_ERROR_ABS_LOCK",
2387         "HW_ERROR_CAL_LOCK_FAIL",
2388         "NMI_INTERRUPT_INST_ACTION_PT",
2389         "NMI_INTERRUPT_DATA_ACTION_PT",
2390         "NMI_TRM_HW_ER",
2391         "NMI_INTERRUPT_TRM",
2392         "NMI_INTERRUPT_BREAK_POINT"
2393         "DEBUG_0",
2394         "DEBUG_1",
2395         "DEBUG_2",
2396         "DEBUG_3",
2397 };
2398
2399 static struct { char *name; u8 num; } advanced_lookup[] = {
2400         { "NMI_INTERRUPT_WDG", 0x34 },
2401         { "SYSASSERT", 0x35 },
2402         { "UCODE_VERSION_MISMATCH", 0x37 },
2403         { "BAD_COMMAND", 0x38 },
2404         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2405         { "FATAL_ERROR", 0x3D },
2406         { "NMI_TRM_HW_ERR", 0x46 },
2407         { "NMI_INTERRUPT_TRM", 0x4C },
2408         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2409         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2410         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2411         { "NMI_INTERRUPT_HOST", 0x66 },
2412         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2413         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2414         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2415         { "ADVANCED_SYSASSERT", 0 },
2416 };
2417
2418 static const char *desc_lookup(u32 num)
2419 {
2420         int i;
2421         int max = ARRAY_SIZE(desc_lookup_text);
2422
2423         if (num < max)
2424                 return desc_lookup_text[num];
2425
2426         max = ARRAY_SIZE(advanced_lookup) - 1;
2427         for (i = 0; i < max; i++) {
2428                 if (advanced_lookup[i].num == num)
2429                         break;;
2430         }
2431         return advanced_lookup[i].name;
2432 }
2433
2434 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2435 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2436
2437 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2438 {
2439         u32 data2, line;
2440         u32 desc, time, count, base, data1;
2441         u32 blink1, blink2, ilink1, ilink2;
2442         u32 pc, hcmd;
2443
2444         if (priv->ucode_type == UCODE_INIT) {
2445                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2446                 if (!base)
2447                         base = priv->_agn.init_errlog_ptr;
2448         } else {
2449                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2450                 if (!base)
2451                         base = priv->_agn.inst_errlog_ptr;
2452         }
2453
2454         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2455                 IWL_ERR(priv,
2456                         "Not valid error log pointer 0x%08X for %s uCode\n",
2457                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2458                 return;
2459         }
2460
2461         count = iwl_read_targ_mem(priv, base);
2462
2463         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2464                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2465                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2466                         priv->status, count);
2467         }
2468
2469         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2470         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2471         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2472         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2473         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2474         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2475         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2476         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2477         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2478         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2479         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2480
2481         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2482                                       blink1, blink2, ilink1, ilink2);
2483
2484         IWL_ERR(priv, "Desc                                  Time       "
2485                 "data1      data2      line\n");
2486         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2487                 desc_lookup(desc), desc, time, data1, data2, line);
2488         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2489         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2490                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2491 }
2492
2493 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2494
2495 /**
2496  * iwl_print_event_log - Dump error event log to syslog
2497  *
2498  */
2499 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2500                                u32 num_events, u32 mode,
2501                                int pos, char **buf, size_t bufsz)
2502 {
2503         u32 i;
2504         u32 base;       /* SRAM byte address of event log header */
2505         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2506         u32 ptr;        /* SRAM byte address of log data */
2507         u32 ev, time, data; /* event log data */
2508         unsigned long reg_flags;
2509
2510         if (num_events == 0)
2511                 return pos;
2512
2513         if (priv->ucode_type == UCODE_INIT) {
2514                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2515                 if (!base)
2516                         base = priv->_agn.init_evtlog_ptr;
2517         } else {
2518                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2519                 if (!base)
2520                         base = priv->_agn.inst_evtlog_ptr;
2521         }
2522
2523         if (mode == 0)
2524                 event_size = 2 * sizeof(u32);
2525         else
2526                 event_size = 3 * sizeof(u32);
2527
2528         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2529
2530         /* Make sure device is powered up for SRAM reads */
2531         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2532         iwl_grab_nic_access(priv);
2533
2534         /* Set starting address; reads will auto-increment */
2535         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2536         rmb();
2537
2538         /* "time" is actually "data" for mode 0 (no timestamp).
2539         * place event id # at far right for easier visual parsing. */
2540         for (i = 0; i < num_events; i++) {
2541                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2542                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2543                 if (mode == 0) {
2544                         /* data, ev */
2545                         if (bufsz) {
2546                                 pos += scnprintf(*buf + pos, bufsz - pos,
2547                                                 "EVT_LOG:0x%08x:%04u\n",
2548                                                 time, ev);
2549                         } else {
2550                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2551                                         time, ev);
2552                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2553                                         time, ev);
2554                         }
2555                 } else {
2556                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2557                         if (bufsz) {
2558                                 pos += scnprintf(*buf + pos, bufsz - pos,
2559                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2560                                                  time, data, ev);
2561                         } else {
2562                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2563                                         time, data, ev);
2564                                 trace_iwlwifi_dev_ucode_event(priv, time,
2565                                         data, ev);
2566                         }
2567                 }
2568         }
2569
2570         /* Allow device to power down */
2571         iwl_release_nic_access(priv);
2572         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2573         return pos;
2574 }
2575
2576 /**
2577  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2578  */
2579 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2580                                     u32 num_wraps, u32 next_entry,
2581                                     u32 size, u32 mode,
2582                                     int pos, char **buf, size_t bufsz)
2583 {
2584         /*
2585          * display the newest DEFAULT_LOG_ENTRIES entries
2586          * i.e the entries just before the next ont that uCode would fill.
2587          */
2588         if (num_wraps) {
2589                 if (next_entry < size) {
2590                         pos = iwl_print_event_log(priv,
2591                                                 capacity - (size - next_entry),
2592                                                 size - next_entry, mode,
2593                                                 pos, buf, bufsz);
2594                         pos = iwl_print_event_log(priv, 0,
2595                                                   next_entry, mode,
2596                                                   pos, buf, bufsz);
2597                 } else
2598                         pos = iwl_print_event_log(priv, next_entry - size,
2599                                                   size, mode, pos, buf, bufsz);
2600         } else {
2601                 if (next_entry < size) {
2602                         pos = iwl_print_event_log(priv, 0, next_entry,
2603                                                   mode, pos, buf, bufsz);
2604                 } else {
2605                         pos = iwl_print_event_log(priv, next_entry - size,
2606                                                   size, mode, pos, buf, bufsz);
2607                 }
2608         }
2609         return pos;
2610 }
2611
2612 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2613
2614 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2615                             char **buf, bool display)
2616 {
2617         u32 base;       /* SRAM byte address of event log header */
2618         u32 capacity;   /* event log capacity in # entries */
2619         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2620         u32 num_wraps;  /* # times uCode wrapped to top of log */
2621         u32 next_entry; /* index of next entry to be written by uCode */
2622         u32 size;       /* # entries that we'll print */
2623         u32 logsize;
2624         int pos = 0;
2625         size_t bufsz = 0;
2626
2627         if (priv->ucode_type == UCODE_INIT) {
2628                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2629                 logsize = priv->_agn.init_evtlog_size;
2630                 if (!base)
2631                         base = priv->_agn.init_evtlog_ptr;
2632         } else {
2633                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2634                 logsize = priv->_agn.inst_evtlog_size;
2635                 if (!base)
2636                         base = priv->_agn.inst_evtlog_ptr;
2637         }
2638
2639         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2640                 IWL_ERR(priv,
2641                         "Invalid event log pointer 0x%08X for %s uCode\n",
2642                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2643                 return -EINVAL;
2644         }
2645
2646         /* event log header */
2647         capacity = iwl_read_targ_mem(priv, base);
2648         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2649         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2650         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2651
2652         if (capacity > logsize) {
2653                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2654                         capacity, logsize);
2655                 capacity = logsize;
2656         }
2657
2658         if (next_entry > logsize) {
2659                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2660                         next_entry, logsize);
2661                 next_entry = logsize;
2662         }
2663
2664         size = num_wraps ? capacity : next_entry;
2665
2666         /* bail out if nothing in log */
2667         if (size == 0) {
2668                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2669                 return pos;
2670         }
2671
2672         /* enable/disable bt channel announcement */
2673         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2674
2675 #ifdef CONFIG_IWLWIFI_DEBUG
2676         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2677                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2678                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2679 #else
2680         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2681                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2682 #endif
2683         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2684                 size);
2685
2686 #ifdef CONFIG_IWLWIFI_DEBUG
2687         if (display) {
2688                 if (full_log)
2689                         bufsz = capacity * 48;
2690                 else
2691                         bufsz = size * 48;
2692                 *buf = kmalloc(bufsz, GFP_KERNEL);
2693                 if (!*buf)
2694                         return -ENOMEM;
2695         }
2696         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2697                 /*
2698                  * if uCode has wrapped back to top of log,
2699                  * start at the oldest entry,
2700                  * i.e the next one that uCode would fill.
2701                  */
2702                 if (num_wraps)
2703                         pos = iwl_print_event_log(priv, next_entry,
2704                                                 capacity - next_entry, mode,
2705                                                 pos, buf, bufsz);
2706                 /* (then/else) start at top of log */
2707                 pos = iwl_print_event_log(priv, 0,
2708                                           next_entry, mode, pos, buf, bufsz);
2709         } else
2710                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2711                                                 next_entry, size, mode,
2712                                                 pos, buf, bufsz);
2713 #else
2714         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2715                                         next_entry, size, mode,
2716                                         pos, buf, bufsz);
2717 #endif
2718         return pos;
2719 }
2720
2721 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2722 {
2723         struct iwl_ct_kill_config cmd;
2724         struct iwl_ct_kill_throttling_config adv_cmd;
2725         unsigned long flags;
2726         int ret = 0;
2727
2728         spin_lock_irqsave(&priv->lock, flags);
2729         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2730                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2731         spin_unlock_irqrestore(&priv->lock, flags);
2732         priv->thermal_throttle.ct_kill_toggle = false;
2733
2734         if (priv->cfg->support_ct_kill_exit) {
2735                 adv_cmd.critical_temperature_enter =
2736                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2737                 adv_cmd.critical_temperature_exit =
2738                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2739
2740                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2741                                        sizeof(adv_cmd), &adv_cmd);
2742                 if (ret)
2743                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2744                 else
2745                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2746                                         "succeeded, "
2747                                         "critical temperature enter is %d,"
2748                                         "exit is %d\n",
2749                                        priv->hw_params.ct_kill_threshold,
2750                                        priv->hw_params.ct_kill_exit_threshold);
2751         } else {
2752                 cmd.critical_temperature_R =
2753                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2754
2755                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2756                                        sizeof(cmd), &cmd);
2757                 if (ret)
2758                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2759                 else
2760                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2761                                         "succeeded, "
2762                                         "critical temperature is %d\n",
2763                                         priv->hw_params.ct_kill_threshold);
2764         }
2765 }
2766
2767 /**
2768  * iwl_alive_start - called after REPLY_ALIVE notification received
2769  *                   from protocol/runtime uCode (initialization uCode's
2770  *                   Alive gets handled by iwl_init_alive_start()).
2771  */
2772 static void iwl_alive_start(struct iwl_priv *priv)
2773 {
2774         int ret = 0;
2775         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2776
2777         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2778
2779         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2780                 /* We had an error bringing up the hardware, so take it
2781                  * all the way back down so we can try again */
2782                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2783                 goto restart;
2784         }
2785
2786         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2787          * This is a paranoid check, because we would not have gotten the
2788          * "runtime" alive if code weren't properly loaded.  */
2789         if (iwl_verify_ucode(priv)) {
2790                 /* Runtime instruction load was bad;
2791                  * take it all the way back down so we can try again */
2792                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2793                 goto restart;
2794         }
2795
2796         ret = priv->cfg->ops->lib->alive_notify(priv);
2797         if (ret) {
2798                 IWL_WARN(priv,
2799                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2800                 goto restart;
2801         }
2802
2803         /* After the ALIVE response, we can send host commands to the uCode */
2804         set_bit(STATUS_ALIVE, &priv->status);
2805
2806         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2807                 /* Enable timer to monitor the driver queues */
2808                 mod_timer(&priv->monitor_recover,
2809                         jiffies +
2810                         msecs_to_jiffies(priv->cfg->monitor_recover_period));
2811         }
2812
2813         if (iwl_is_rfkill(priv))
2814                 return;
2815
2816         ieee80211_wake_queues(priv->hw);
2817
2818         priv->active_rate = IWL_RATES_MASK;
2819
2820         /* Configure Tx antenna selection based on H/W config */
2821         if (priv->cfg->ops->hcmd->set_tx_ant)
2822                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2823
2824         if (iwl_is_associated_ctx(ctx)) {
2825                 struct iwl_rxon_cmd *active_rxon =
2826                                 (struct iwl_rxon_cmd *)&ctx->active;
2827                 /* apply any changes in staging */
2828                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2829                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2830         } else {
2831                 struct iwl_rxon_context *tmp;
2832                 /* Initialize our rx_config data */
2833                 for_each_context(priv, tmp)
2834                         iwl_connection_init_rx_config(priv, tmp);
2835
2836                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2837                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2838         }
2839
2840         if (!priv->cfg->advanced_bt_coexist) {
2841                 /* Configure Bluetooth device coexistence support */
2842                 priv->cfg->ops->hcmd->send_bt_config(priv);
2843         }
2844
2845         iwl_reset_run_time_calib(priv);
2846
2847         /* Configure the adapter for unassociated operation */
2848         iwlcore_commit_rxon(priv, ctx);
2849
2850         /* At this point, the NIC is initialized and operational */
2851         iwl_rf_kill_ct_config(priv);
2852
2853         iwl_leds_init(priv);
2854
2855         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2856         set_bit(STATUS_READY, &priv->status);
2857         wake_up_interruptible(&priv->wait_command_queue);
2858
2859         iwl_power_update_mode(priv, true);
2860         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2861
2862
2863         return;
2864
2865  restart:
2866         queue_work(priv->workqueue, &priv->restart);
2867 }
2868
2869 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2870
2871 static void __iwl_down(struct iwl_priv *priv)
2872 {
2873         unsigned long flags;
2874         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2875
2876         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2877
2878         if (!exit_pending)
2879                 set_bit(STATUS_EXIT_PENDING, &priv->status);
2880
2881         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2882          * to prevent rearm timer */
2883         if (priv->cfg->ops->lib->recover_from_tx_stall)
2884                 del_timer_sync(&priv->monitor_recover);
2885
2886         iwl_clear_ucode_stations(priv, NULL);
2887         iwl_dealloc_bcast_stations(priv);
2888         iwl_clear_driver_stations(priv);
2889
2890         /* reset BT coex data */
2891         priv->bt_status = 0;
2892         priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2893         priv->bt_sco_active = false;
2894         priv->bt_full_concurrent = false;
2895         priv->bt_ci_compliance = 0;
2896
2897         /* Unblock any waiting calls */
2898         wake_up_interruptible_all(&priv->wait_command_queue);
2899
2900         /* Wipe out the EXIT_PENDING status bit if we are not actually
2901          * exiting the module */
2902         if (!exit_pending)
2903                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2904
2905         /* stop and reset the on-board processor */
2906         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2907
2908         /* tell the device to stop sending interrupts */
2909         spin_lock_irqsave(&priv->lock, flags);
2910         iwl_disable_interrupts(priv);
2911         spin_unlock_irqrestore(&priv->lock, flags);
2912         iwl_synchronize_irq(priv);
2913
2914         if (priv->mac80211_registered)
2915                 ieee80211_stop_queues(priv->hw);
2916
2917         /* If we have not previously called iwl_init() then
2918          * clear all bits but the RF Kill bit and return */
2919         if (!iwl_is_init(priv)) {
2920                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2921                                         STATUS_RF_KILL_HW |
2922                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2923                                         STATUS_GEO_CONFIGURED |
2924                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2925                                         STATUS_EXIT_PENDING;
2926                 goto exit;
2927         }
2928
2929         /* ...otherwise clear out all the status bits but the RF Kill
2930          * bit and continue taking the NIC down. */
2931         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2932                                 STATUS_RF_KILL_HW |
2933                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2934                                 STATUS_GEO_CONFIGURED |
2935                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2936                                 STATUS_FW_ERROR |
2937                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2938                                 STATUS_EXIT_PENDING;
2939
2940         /* device going down, Stop using ICT table */
2941         iwl_disable_ict(priv);
2942
2943         iwlagn_txq_ctx_stop(priv);
2944         iwlagn_rxq_stop(priv);
2945
2946         /* Power-down device's busmaster DMA clocks */
2947         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2948         udelay(5);
2949
2950         /* Make sure (redundant) we've released our request to stay awake */
2951         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2952
2953         /* Stop the device, and put it in low power state */
2954         priv->cfg->ops->lib->apm_ops.stop(priv);
2955
2956  exit:
2957         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2958
2959         if (priv->ibss_beacon)
2960                 dev_kfree_skb(priv->ibss_beacon);
2961         priv->ibss_beacon = NULL;
2962
2963         /* clear out any free frames */
2964         iwl_clear_free_frames(priv);
2965 }
2966
2967 static void iwl_down(struct iwl_priv *priv)
2968 {
2969         mutex_lock(&priv->mutex);
2970         __iwl_down(priv);
2971         mutex_unlock(&priv->mutex);
2972
2973         iwl_cancel_deferred_work(priv);
2974 }
2975
2976 #define HW_READY_TIMEOUT (50)
2977
2978 static int iwl_set_hw_ready(struct iwl_priv *priv)
2979 {
2980         int ret = 0;
2981
2982         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2983                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2984
2985         /* See if we got it */
2986         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2987                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2988                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2989                                 HW_READY_TIMEOUT);
2990         if (ret != -ETIMEDOUT)
2991                 priv->hw_ready = true;
2992         else
2993                 priv->hw_ready = false;
2994
2995         IWL_DEBUG_INFO(priv, "hardware %s\n",
2996                       (priv->hw_ready == 1) ? "ready" : "not ready");
2997         return ret;
2998 }
2999
3000 static int iwl_prepare_card_hw(struct iwl_priv *priv)
3001 {
3002         int ret = 0;
3003
3004         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
3005
3006         ret = iwl_set_hw_ready(priv);
3007         if (priv->hw_ready)
3008                 return ret;
3009
3010         /* If HW is not ready, prepare the conditions to check again */
3011         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3012                         CSR_HW_IF_CONFIG_REG_PREPARE);
3013
3014         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3015                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3016                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3017
3018         /* HW should be ready by now, check again. */
3019         if (ret != -ETIMEDOUT)
3020                 iwl_set_hw_ready(priv);
3021
3022         return ret;
3023 }
3024
3025 #define MAX_HW_RESTARTS 5
3026
3027 static int __iwl_up(struct iwl_priv *priv)
3028 {
3029         struct iwl_rxon_context *ctx;
3030         int i;
3031         int ret;
3032
3033         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3034                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
3035                 return -EIO;
3036         }
3037
3038         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
3039                 IWL_ERR(priv, "ucode not available for device bringup\n");
3040                 return -EIO;
3041         }
3042
3043         for_each_context(priv, ctx) {
3044                 ret = iwl_alloc_bcast_station(priv, ctx, true);
3045                 if (ret) {
3046                         iwl_dealloc_bcast_stations(priv);
3047                         return ret;
3048                 }
3049         }
3050
3051         iwl_prepare_card_hw(priv);
3052
3053         if (!priv->hw_ready) {
3054                 IWL_WARN(priv, "Exit HW not ready\n");
3055                 return -EIO;
3056         }
3057
3058         /* If platform's RF_KILL switch is NOT set to KILL */
3059         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3060                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3061         else
3062                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3063
3064         if (iwl_is_rfkill(priv)) {
3065                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3066
3067                 iwl_enable_interrupts(priv);
3068                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3069                 return 0;
3070         }
3071
3072         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3073
3074         /* must be initialised before iwl_hw_nic_init */
3075         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3076                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3077         else
3078                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3079
3080         ret = iwlagn_hw_nic_init(priv);
3081         if (ret) {
3082                 IWL_ERR(priv, "Unable to init nic\n");
3083                 return ret;
3084         }
3085
3086         /* make sure rfkill handshake bits are cleared */
3087         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3088         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3089                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3090
3091         /* clear (again), then enable host interrupts */
3092         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3093         iwl_enable_interrupts(priv);
3094
3095         /* really make sure rfkill handshake bits are cleared */
3096         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3097         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3098
3099         /* Copy original ucode data image from disk into backup cache.
3100          * This will be used to initialize the on-board processor's
3101          * data SRAM for a clean start when the runtime program first loads. */
3102         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3103                priv->ucode_data.len);
3104
3105         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3106
3107                 /* load bootstrap state machine,
3108                  * load bootstrap program into processor's memory,
3109                  * prepare to load the "initialize" uCode */
3110                 ret = priv->cfg->ops->lib->load_ucode(priv);
3111
3112                 if (ret) {
3113                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3114                                 ret);
3115                         continue;
3116                 }
3117
3118                 /* start card; "initialize" will load runtime ucode */
3119                 iwl_nic_start(priv);
3120
3121                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3122
3123                 return 0;
3124         }
3125
3126         set_bit(STATUS_EXIT_PENDING, &priv->status);
3127         __iwl_down(priv);
3128         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3129
3130         /* tried to restart and config the device for as long as our
3131          * patience could withstand */
3132         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3133         return -EIO;
3134 }
3135
3136
3137 /*****************************************************************************
3138  *
3139  * Workqueue callbacks
3140  *
3141  *****************************************************************************/
3142
3143 static void iwl_bg_init_alive_start(struct work_struct *data)
3144 {
3145         struct iwl_priv *priv =
3146             container_of(data, struct iwl_priv, init_alive_start.work);
3147
3148         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3149                 return;
3150
3151         mutex_lock(&priv->mutex);
3152         priv->cfg->ops->lib->init_alive_start(priv);
3153         mutex_unlock(&priv->mutex);
3154 }
3155
3156 static void iwl_bg_alive_start(struct work_struct *data)
3157 {
3158         struct iwl_priv *priv =
3159             container_of(data, struct iwl_priv, alive_start.work);
3160
3161         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3162                 return;
3163
3164         /* enable dram interrupt */
3165         iwl_reset_ict(priv);
3166
3167         mutex_lock(&priv->mutex);
3168         iwl_alive_start(priv);
3169         mutex_unlock(&priv->mutex);
3170 }
3171
3172 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3173 {
3174         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3175                         run_time_calib_work);
3176
3177         mutex_lock(&priv->mutex);
3178
3179         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3180             test_bit(STATUS_SCANNING, &priv->status)) {
3181                 mutex_unlock(&priv->mutex);
3182                 return;
3183         }
3184
3185         if (priv->start_calib) {
3186                 if (priv->cfg->bt_statistics) {
3187                         iwl_chain_noise_calibration(priv,
3188                                         (void *)&priv->_agn.statistics_bt);
3189                         iwl_sensitivity_calibration(priv,
3190                                         (void *)&priv->_agn.statistics_bt);
3191                 } else {
3192                         iwl_chain_noise_calibration(priv,
3193                                         (void *)&priv->_agn.statistics);
3194                         iwl_sensitivity_calibration(priv,
3195                                         (void *)&priv->_agn.statistics);
3196                 }
3197         }
3198
3199         mutex_unlock(&priv->mutex);
3200 }
3201
3202 static void iwl_bg_restart(struct work_struct *data)
3203 {
3204         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3205
3206         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3207                 return;
3208
3209         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3210                 struct iwl_rxon_context *ctx;
3211                 bool bt_sco, bt_full_concurrent;
3212                 u8 bt_ci_compliance;
3213                 u8 bt_load;
3214                 u8 bt_status;
3215
3216                 mutex_lock(&priv->mutex);
3217                 for_each_context(priv, ctx)
3218                         ctx->vif = NULL;
3219                 priv->is_open = 0;
3220
3221                 /*
3222                  * __iwl_down() will clear the BT status variables,
3223                  * which is correct, but when we restart we really
3224                  * want to keep them so restore them afterwards.
3225                  *
3226                  * The restart process will later pick them up and
3227                  * re-configure the hw when we reconfigure the BT
3228                  * command.
3229                  */
3230                 bt_sco = priv->bt_sco_active;
3231                 bt_full_concurrent = priv->bt_full_concurrent;
3232                 bt_ci_compliance = priv->bt_ci_compliance;
3233                 bt_load = priv->bt_traffic_load;
3234                 bt_status = priv->bt_status;
3235
3236                 __iwl_down(priv);
3237
3238                 priv->bt_sco_active = bt_sco;
3239                 priv->bt_full_concurrent = bt_full_concurrent;
3240                 priv->bt_ci_compliance = bt_ci_compliance;
3241                 priv->bt_traffic_load = bt_load;
3242                 priv->bt_status = bt_status;
3243
3244                 mutex_unlock(&priv->mutex);
3245                 iwl_cancel_deferred_work(priv);
3246                 ieee80211_restart_hw(priv->hw);
3247         } else {
3248                 iwl_down(priv);
3249
3250                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3251                         return;
3252
3253                 mutex_lock(&priv->mutex);
3254                 __iwl_up(priv);
3255                 mutex_unlock(&priv->mutex);
3256         }
3257 }
3258
3259 static void iwl_bg_rx_replenish(struct work_struct *data)
3260 {
3261         struct iwl_priv *priv =
3262             container_of(data, struct iwl_priv, rx_replenish);
3263
3264         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3265                 return;
3266
3267         mutex_lock(&priv->mutex);
3268         iwlagn_rx_replenish(priv);
3269         mutex_unlock(&priv->mutex);
3270 }
3271
3272 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3273
3274 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3275 {
3276         struct iwl_rxon_context *ctx;
3277         struct ieee80211_conf *conf = NULL;
3278         int ret = 0;
3279
3280         if (!vif || !priv->is_open)
3281                 return;
3282
3283         ctx = iwl_rxon_ctx_from_vif(vif);
3284
3285         if (vif->type == NL80211_IFTYPE_AP) {
3286                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3287                 return;
3288         }
3289
3290         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3291                 return;
3292
3293         iwl_scan_cancel_timeout(priv, 200);
3294
3295         conf = ieee80211_get_hw_conf(priv->hw);
3296
3297         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3298         iwlcore_commit_rxon(priv, ctx);
3299
3300         ret = iwl_send_rxon_timing(priv, ctx);
3301         if (ret)
3302                 IWL_WARN(priv, "RXON timing - "
3303                             "Attempting to continue.\n");
3304
3305         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3306
3307         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3308
3309         if (priv->cfg->ops->hcmd->set_rxon_chain)
3310                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3311
3312         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3313
3314         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3315                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3316
3317         if (vif->bss_conf.use_short_preamble)
3318                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3319         else
3320                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3321
3322         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3323                 if (vif->bss_conf.use_short_slot)
3324                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3325                 else
3326                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3327         }
3328
3329         iwlcore_commit_rxon(priv, ctx);
3330
3331         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3332                         vif->bss_conf.aid, ctx->active.bssid_addr);
3333
3334         switch (vif->type) {
3335         case NL80211_IFTYPE_STATION:
3336                 break;
3337         case NL80211_IFTYPE_ADHOC:
3338                 iwl_send_beacon_cmd(priv);
3339                 break;
3340         default:
3341                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3342                           __func__, vif->type);
3343                 break;
3344         }
3345
3346         /* the chain noise calibration will enabled PM upon completion
3347          * If chain noise has already been run, then we need to enable
3348          * power management here */
3349         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3350                 iwl_power_update_mode(priv, false);
3351
3352         /* Enable Rx differential gain and sensitivity calibrations */
3353         iwl_chain_noise_reset(priv);
3354         priv->start_calib = 1;
3355
3356 }
3357
3358 /*****************************************************************************
3359  *
3360  * mac80211 entry point functions
3361  *
3362  *****************************************************************************/
3363
3364 #define UCODE_READY_TIMEOUT     (4 * HZ)
3365
3366 /*
3367  * Not a mac80211 entry point function, but it fits in with all the
3368  * other mac80211 functions grouped here.
3369  */
3370 static int iwl_mac_setup_register(struct iwl_priv *priv,
3371                                   struct iwlagn_ucode_capabilities *capa)
3372 {
3373         int ret;
3374         struct ieee80211_hw *hw = priv->hw;
3375         struct iwl_rxon_context *ctx;
3376
3377         hw->rate_control_algorithm = "iwl-agn-rs";
3378
3379         /* Tell mac80211 our characteristics */
3380         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3381                     IEEE80211_HW_AMPDU_AGGREGATION |
3382                     IEEE80211_HW_NEED_DTIM_PERIOD |
3383                     IEEE80211_HW_SPECTRUM_MGMT;
3384
3385         if (!priv->cfg->broken_powersave)
3386                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3387                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3388
3389         if (priv->cfg->sku & IWL_SKU_N)
3390                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3391                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3392
3393         hw->sta_data_size = sizeof(struct iwl_station_priv);
3394         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3395
3396         for_each_context(priv, ctx) {
3397                 hw->wiphy->interface_modes |= ctx->interface_modes;
3398                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3399         }
3400
3401         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3402                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3403
3404         /*
3405          * For now, disable PS by default because it affects
3406          * RX performance significantly.
3407          */
3408         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3409
3410         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3411         /* we create the 802.11 header and a zero-length SSID element */
3412         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3413
3414         /* Default value; 4 EDCA QOS priorities */
3415         hw->queues = 4;
3416
3417         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3418
3419         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3420                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3421                         &priv->bands[IEEE80211_BAND_2GHZ];
3422         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3423                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3424                         &priv->bands[IEEE80211_BAND_5GHZ];
3425
3426         ret = ieee80211_register_hw(priv->hw);
3427         if (ret) {
3428                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3429                 return ret;
3430         }
3431         priv->mac80211_registered = 1;
3432
3433         return 0;
3434 }
3435
3436
3437 static int iwl_mac_start(struct ieee80211_hw *hw)
3438 {
3439         struct iwl_priv *priv = hw->priv;
3440         int ret;
3441
3442         IWL_DEBUG_MAC80211(priv, "enter\n");
3443
3444         /* we should be verifying the device is ready to be opened */
3445         mutex_lock(&priv->mutex);
3446         ret = __iwl_up(priv);
3447         mutex_unlock(&priv->mutex);
3448
3449         if (ret)
3450                 return ret;
3451
3452         if (iwl_is_rfkill(priv))
3453                 goto out;
3454
3455         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3456
3457         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3458          * mac80211 will not be run successfully. */
3459         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3460                         test_bit(STATUS_READY, &priv->status),
3461                         UCODE_READY_TIMEOUT);
3462         if (!ret) {
3463                 if (!test_bit(STATUS_READY, &priv->status)) {
3464                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3465                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3466                         return -ETIMEDOUT;
3467                 }
3468         }
3469
3470         iwl_led_start(priv);
3471
3472 out:
3473         priv->is_open = 1;
3474         IWL_DEBUG_MAC80211(priv, "leave\n");
3475         return 0;
3476 }
3477
3478 static void iwl_mac_stop(struct ieee80211_hw *hw)
3479 {
3480         struct iwl_priv *priv = hw->priv;
3481
3482         IWL_DEBUG_MAC80211(priv, "enter\n");
3483
3484         if (!priv->is_open)
3485                 return;
3486
3487         priv->is_open = 0;
3488
3489         if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3490                 /* stop mac, cancel any scan request and clear
3491                  * RXON_FILTER_ASSOC_MSK BIT
3492                  */
3493                 mutex_lock(&priv->mutex);
3494                 iwl_scan_cancel_timeout(priv, 100);
3495                 mutex_unlock(&priv->mutex);
3496         }
3497
3498         iwl_down(priv);
3499
3500         flush_workqueue(priv->workqueue);
3501
3502         /* enable interrupts again in order to receive rfkill changes */
3503         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3504         iwl_enable_interrupts(priv);
3505
3506         IWL_DEBUG_MAC80211(priv, "leave\n");
3507 }
3508
3509 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3510 {
3511         struct iwl_priv *priv = hw->priv;
3512
3513         IWL_DEBUG_MACDUMP(priv, "enter\n");
3514
3515         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3516                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3517
3518         if (iwlagn_tx_skb(priv, skb))
3519                 dev_kfree_skb_any(skb);
3520
3521         IWL_DEBUG_MACDUMP(priv, "leave\n");
3522         return NETDEV_TX_OK;
3523 }
3524
3525 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3526 {
3527         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3528         int ret = 0;
3529
3530         lockdep_assert_held(&priv->mutex);
3531
3532         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3533                 return;
3534
3535         /* The following should be done only at AP bring up */
3536         if (!iwl_is_associated_ctx(ctx)) {
3537
3538                 /* RXON - unassoc (to set timing command) */
3539                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3540                 iwlcore_commit_rxon(priv, ctx);
3541
3542                 /* RXON Timing */
3543                 ret = iwl_send_rxon_timing(priv, ctx);
3544                 if (ret)
3545                         IWL_WARN(priv, "RXON timing failed - "
3546                                         "Attempting to continue.\n");
3547
3548                 /* AP has all antennas */
3549                 priv->chain_noise_data.active_chains =
3550                         priv->hw_params.valid_rx_ant;
3551                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3552                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3553                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3554
3555                 ctx->staging.assoc_id = 0;
3556
3557                 if (vif->bss_conf.use_short_preamble)
3558                         ctx->staging.flags |=
3559                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3560                 else
3561                         ctx->staging.flags &=
3562                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3563
3564                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3565                         if (vif->bss_conf.use_short_slot)
3566                                 ctx->staging.flags |=
3567                                         RXON_FLG_SHORT_SLOT_MSK;
3568                         else
3569                                 ctx->staging.flags &=
3570                                         ~RXON_FLG_SHORT_SLOT_MSK;
3571                 }
3572                 /* need to send beacon cmd before committing assoc RXON! */
3573                 iwl_send_beacon_cmd(priv);
3574                 /* restore RXON assoc */
3575                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3576                 iwlcore_commit_rxon(priv, ctx);
3577         }
3578         iwl_send_beacon_cmd(priv);
3579
3580         /* FIXME - we need to add code here to detect a totally new
3581          * configuration, reset the AP, unassoc, rxon timing, assoc,
3582          * clear sta table, add BCAST sta... */
3583 }
3584
3585 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3586                                     struct ieee80211_vif *vif,
3587                                     struct ieee80211_key_conf *keyconf,
3588                                     struct ieee80211_sta *sta,
3589                                     u32 iv32, u16 *phase1key)
3590 {
3591
3592         struct iwl_priv *priv = hw->priv;
3593         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3594
3595         IWL_DEBUG_MAC80211(priv, "enter\n");
3596
3597         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3598                             iv32, phase1key);
3599
3600         IWL_DEBUG_MAC80211(priv, "leave\n");
3601 }
3602
3603 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3604                            struct ieee80211_vif *vif,
3605                            struct ieee80211_sta *sta,
3606                            struct ieee80211_key_conf *key)
3607 {
3608         struct iwl_priv *priv = hw->priv;
3609         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3610         struct iwl_rxon_context *ctx = vif_priv->ctx;
3611         int ret;
3612         u8 sta_id;
3613         bool is_default_wep_key = false;
3614
3615         IWL_DEBUG_MAC80211(priv, "enter\n");
3616
3617         if (priv->cfg->mod_params->sw_crypto) {
3618                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3619                 return -EOPNOTSUPP;
3620         }
3621
3622         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3623         if (sta_id == IWL_INVALID_STATION)
3624                 return -EINVAL;
3625
3626         mutex_lock(&priv->mutex);
3627         iwl_scan_cancel_timeout(priv, 100);
3628
3629         /*
3630          * If we are getting WEP group key and we didn't receive any key mapping
3631          * so far, we are in legacy wep mode (group key only), otherwise we are
3632          * in 1X mode.
3633          * In legacy wep mode, we use another host command to the uCode.
3634          */
3635         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3636              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3637             !sta) {
3638                 if (cmd == SET_KEY)
3639                         is_default_wep_key = !ctx->key_mapping_keys;
3640                 else
3641                         is_default_wep_key =
3642                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3643         }
3644
3645         switch (cmd) {
3646         case SET_KEY:
3647                 if (is_default_wep_key)
3648                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3649                 else
3650                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3651                                                   key, sta_id);
3652
3653                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3654                 break;
3655         case DISABLE_KEY:
3656                 if (is_default_wep_key)
3657                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3658                 else
3659                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3660
3661                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3662                 break;
3663         default:
3664                 ret = -EINVAL;
3665         }
3666
3667         mutex_unlock(&priv->mutex);
3668         IWL_DEBUG_MAC80211(priv, "leave\n");
3669
3670         return ret;
3671 }
3672
3673 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3674                                 struct ieee80211_vif *vif,
3675                                 enum ieee80211_ampdu_mlme_action action,
3676                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3677 {
3678         struct iwl_priv *priv = hw->priv;
3679         int ret = -EINVAL;
3680
3681         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3682                      sta->addr, tid);
3683
3684         if (!(priv->cfg->sku & IWL_SKU_N))
3685                 return -EACCES;
3686
3687         mutex_lock(&priv->mutex);
3688
3689         switch (action) {
3690         case IEEE80211_AMPDU_RX_START:
3691                 IWL_DEBUG_HT(priv, "start Rx\n");
3692                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3693                 break;
3694         case IEEE80211_AMPDU_RX_STOP:
3695                 IWL_DEBUG_HT(priv, "stop Rx\n");
3696                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3697                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3698                         ret = 0;
3699                 break;
3700         case IEEE80211_AMPDU_TX_START:
3701                 IWL_DEBUG_HT(priv, "start Tx\n");
3702                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3703                 if (ret == 0) {
3704                         priv->_agn.agg_tids_count++;
3705                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3706                                      priv->_agn.agg_tids_count);
3707                 }
3708                 break;
3709         case IEEE80211_AMPDU_TX_STOP:
3710                 IWL_DEBUG_HT(priv, "stop Tx\n");
3711                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3712                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3713                         priv->_agn.agg_tids_count--;
3714                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3715                                      priv->_agn.agg_tids_count);
3716                 }
3717                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3718                         ret = 0;
3719                 if (priv->cfg->use_rts_for_aggregation) {
3720                         struct iwl_station_priv *sta_priv =
3721                                 (void *) sta->drv_priv;
3722                         /*
3723                          * switch off RTS/CTS if it was previously enabled
3724                          */
3725
3726                         sta_priv->lq_sta.lq.general_params.flags &=
3727                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3728                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3729                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3730                 }
3731                 break;
3732         case IEEE80211_AMPDU_TX_OPERATIONAL:
3733                 if (priv->cfg->use_rts_for_aggregation) {
3734                         struct iwl_station_priv *sta_priv =
3735                                 (void *) sta->drv_priv;
3736
3737                         /*
3738                          * switch to RTS/CTS if it is the prefer protection
3739                          * method for HT traffic
3740                          */
3741
3742                         sta_priv->lq_sta.lq.general_params.flags |=
3743                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3744                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3745                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3746                 }
3747                 ret = 0;
3748                 break;
3749         }
3750         mutex_unlock(&priv->mutex);
3751
3752         return ret;
3753 }
3754
3755 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3756                                struct ieee80211_vif *vif,
3757                                enum sta_notify_cmd cmd,
3758                                struct ieee80211_sta *sta)
3759 {
3760         struct iwl_priv *priv = hw->priv;
3761         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3762         int sta_id;
3763
3764         switch (cmd) {
3765         case STA_NOTIFY_SLEEP:
3766                 WARN_ON(!sta_priv->client);
3767                 sta_priv->asleep = true;
3768                 if (atomic_read(&sta_priv->pending_frames) > 0)
3769                         ieee80211_sta_block_awake(hw, sta, true);
3770                 break;
3771         case STA_NOTIFY_AWAKE:
3772                 WARN_ON(!sta_priv->client);
3773                 if (!sta_priv->asleep)
3774                         break;
3775                 sta_priv->asleep = false;
3776                 sta_id = iwl_sta_id(sta);
3777                 if (sta_id != IWL_INVALID_STATION)
3778                         iwl_sta_modify_ps_wake(priv, sta_id);
3779                 break;
3780         default:
3781                 break;
3782         }
3783 }
3784
3785 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3786                               struct ieee80211_vif *vif,
3787                               struct ieee80211_sta *sta)
3788 {
3789         struct iwl_priv *priv = hw->priv;
3790         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3791         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3792         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3793         int ret;
3794         u8 sta_id;
3795
3796         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3797                         sta->addr);
3798         mutex_lock(&priv->mutex);
3799         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3800                         sta->addr);
3801         sta_priv->common.sta_id = IWL_INVALID_STATION;
3802
3803         atomic_set(&sta_priv->pending_frames, 0);
3804         if (vif->type == NL80211_IFTYPE_AP)
3805                 sta_priv->client = true;
3806
3807         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3808                                      is_ap, sta, &sta_id);
3809         if (ret) {
3810                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3811                         sta->addr, ret);
3812                 /* Should we return success if return code is EEXIST ? */
3813                 mutex_unlock(&priv->mutex);
3814                 return ret;
3815         }
3816
3817         sta_priv->common.sta_id = sta_id;
3818
3819         /* Initialize rate scaling */
3820         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3821                        sta->addr);
3822         iwl_rs_rate_init(priv, sta, sta_id);
3823         mutex_unlock(&priv->mutex);
3824
3825         return 0;
3826 }
3827
3828 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3829                                    struct ieee80211_channel_switch *ch_switch)
3830 {
3831         struct iwl_priv *priv = hw->priv;
3832         const struct iwl_channel_info *ch_info;
3833         struct ieee80211_conf *conf = &hw->conf;
3834         struct ieee80211_channel *channel = ch_switch->channel;
3835         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3836         /*
3837          * MULTI-FIXME
3838          * When we add support for multiple interfaces, we need to
3839          * revisit this. The channel switch command in the device
3840          * only affects the BSS context, but what does that really
3841          * mean? And what if we get a CSA on the second interface?
3842          * This needs a lot of work.
3843          */
3844         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3845         u16 ch;
3846         unsigned long flags = 0;
3847
3848         IWL_DEBUG_MAC80211(priv, "enter\n");
3849
3850         if (iwl_is_rfkill(priv))
3851                 goto out_exit;
3852
3853         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3854             test_bit(STATUS_SCANNING, &priv->status))
3855                 goto out_exit;
3856
3857         if (!iwl_is_associated_ctx(ctx))
3858                 goto out_exit;
3859
3860         /* channel switch in progress */
3861         if (priv->switch_rxon.switch_in_progress == true)
3862                 goto out_exit;
3863
3864         mutex_lock(&priv->mutex);
3865         if (priv->cfg->ops->lib->set_channel_switch) {
3866
3867                 ch = channel->hw_value;
3868                 if (le16_to_cpu(ctx->active.channel) != ch) {
3869                         ch_info = iwl_get_channel_info(priv,
3870                                                        channel->band,
3871                                                        ch);
3872                         if (!is_channel_valid(ch_info)) {
3873                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3874                                 goto out;
3875                         }
3876                         spin_lock_irqsave(&priv->lock, flags);
3877
3878                         priv->current_ht_config.smps = conf->smps_mode;
3879
3880                         /* Configure HT40 channels */
3881                         ctx->ht.enabled = conf_is_ht(conf);
3882                         if (ctx->ht.enabled) {
3883                                 if (conf_is_ht40_minus(conf)) {
3884                                         ctx->ht.extension_chan_offset =
3885                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3886                                         ctx->ht.is_40mhz = true;
3887                                 } else if (conf_is_ht40_plus(conf)) {
3888                                         ctx->ht.extension_chan_offset =
3889                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3890                                         ctx->ht.is_40mhz = true;
3891                                 } else {
3892                                         ctx->ht.extension_chan_offset =
3893                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3894                                         ctx->ht.is_40mhz = false;
3895                                 }
3896                         } else
3897                                 ctx->ht.is_40mhz = false;
3898
3899                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3900                                 ctx->staging.flags = 0;
3901
3902                         iwl_set_rxon_channel(priv, channel, ctx);
3903                         iwl_set_rxon_ht(priv, ht_conf);
3904                         iwl_set_flags_for_band(priv, ctx, channel->band,
3905                                                ctx->vif);
3906                         spin_unlock_irqrestore(&priv->lock, flags);
3907
3908                         iwl_set_rate(priv);
3909                         /*
3910                          * at this point, staging_rxon has the
3911                          * configuration for channel switch
3912                          */
3913                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3914                                                                     ch_switch))
3915                                 priv->switch_rxon.switch_in_progress = false;
3916                 }
3917         }
3918 out:
3919         mutex_unlock(&priv->mutex);
3920 out_exit:
3921         if (!priv->switch_rxon.switch_in_progress)
3922                 ieee80211_chswitch_done(ctx->vif, false);
3923         IWL_DEBUG_MAC80211(priv, "leave\n");
3924 }
3925
3926 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3927                                     unsigned int changed_flags,
3928                                     unsigned int *total_flags,
3929                                     u64 multicast)
3930 {
3931         struct iwl_priv *priv = hw->priv;
3932         __le32 filter_or = 0, filter_nand = 0;
3933         struct iwl_rxon_context *ctx;
3934
3935 #define CHK(test, flag) do { \
3936         if (*total_flags & (test))              \
3937                 filter_or |= (flag);            \
3938         else                                    \
3939                 filter_nand |= (flag);          \
3940         } while (0)
3941
3942         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3943                         changed_flags, *total_flags);
3944
3945         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3946         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3947         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3948
3949 #undef CHK
3950
3951         mutex_lock(&priv->mutex);
3952
3953         for_each_context(priv, ctx) {
3954                 ctx->staging.filter_flags &= ~filter_nand;
3955                 ctx->staging.filter_flags |= filter_or;
3956                 iwlcore_commit_rxon(priv, ctx);
3957         }
3958
3959         mutex_unlock(&priv->mutex);
3960
3961         /*
3962          * Receiving all multicast frames is always enabled by the
3963          * default flags setup in iwl_connection_init_rx_config()
3964          * since we currently do not support programming multicast
3965          * filters into the device.
3966          */
3967         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3968                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3969 }
3970
3971 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3972 {
3973         struct iwl_priv *priv = hw->priv;
3974
3975         mutex_lock(&priv->mutex);
3976         IWL_DEBUG_MAC80211(priv, "enter\n");
3977
3978         /* do not support "flush" */
3979         if (!priv->cfg->ops->lib->txfifo_flush)
3980                 goto done;
3981
3982         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3983                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3984                 goto done;
3985         }
3986         if (iwl_is_rfkill(priv)) {
3987                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3988                 goto done;
3989         }
3990
3991         /*
3992          * mac80211 will not push any more frames for transmit
3993          * until the flush is completed
3994          */
3995         if (drop) {
3996                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3997                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3998                         IWL_ERR(priv, "flush request fail\n");
3999                         goto done;
4000                 }
4001         }
4002         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4003         iwlagn_wait_tx_queue_empty(priv);
4004 done:
4005         mutex_unlock(&priv->mutex);
4006         IWL_DEBUG_MAC80211(priv, "leave\n");
4007 }
4008
4009 /*****************************************************************************
4010  *
4011  * driver setup and teardown
4012  *
4013  *****************************************************************************/
4014
4015 static void iwl_setup_deferred_work(struct iwl_priv *priv)
4016 {
4017         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
4018
4019         init_waitqueue_head(&priv->wait_command_queue);
4020
4021         INIT_WORK(&priv->restart, iwl_bg_restart);
4022         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
4023         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
4024         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4025         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4026         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
4027         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4028         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4029         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4030
4031         iwl_setup_scan_deferred_work(priv);
4032
4033         if (priv->cfg->ops->lib->setup_deferred_work)
4034                 priv->cfg->ops->lib->setup_deferred_work(priv);
4035
4036         init_timer(&priv->statistics_periodic);
4037         priv->statistics_periodic.data = (unsigned long)priv;
4038         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
4039
4040         init_timer(&priv->ucode_trace);
4041         priv->ucode_trace.data = (unsigned long)priv;
4042         priv->ucode_trace.function = iwl_bg_ucode_trace;
4043
4044         if (priv->cfg->ops->lib->recover_from_tx_stall) {
4045                 init_timer(&priv->monitor_recover);
4046                 priv->monitor_recover.data = (unsigned long)priv;
4047                 priv->monitor_recover.function =
4048                         priv->cfg->ops->lib->recover_from_tx_stall;
4049         }
4050
4051         if (!priv->cfg->use_isr_legacy)
4052                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4053                         iwl_irq_tasklet, (unsigned long)priv);
4054         else
4055                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4056                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4057 }
4058
4059 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4060 {
4061         if (priv->cfg->ops->lib->cancel_deferred_work)
4062                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4063
4064         cancel_delayed_work_sync(&priv->init_alive_start);
4065         cancel_delayed_work(&priv->scan_check);
4066         cancel_work_sync(&priv->start_internal_scan);
4067         cancel_delayed_work(&priv->alive_start);
4068         cancel_work_sync(&priv->run_time_calib_work);
4069         cancel_work_sync(&priv->beacon_update);
4070         cancel_work_sync(&priv->bt_full_concurrency);
4071         cancel_work_sync(&priv->bt_runtime_config);
4072         del_timer_sync(&priv->statistics_periodic);
4073         del_timer_sync(&priv->ucode_trace);
4074 }
4075
4076 static void iwl_init_hw_rates(struct iwl_priv *priv,
4077                               struct ieee80211_rate *rates)
4078 {
4079         int i;
4080
4081         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4082                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4083                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4084                 rates[i].hw_value_short = i;
4085                 rates[i].flags = 0;
4086                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4087                         /*
4088                          * If CCK != 1M then set short preamble rate flag.
4089                          */
4090                         rates[i].flags |=
4091                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4092                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4093                 }
4094         }
4095 }
4096
4097 static int iwl_init_drv(struct iwl_priv *priv)
4098 {
4099         int ret;
4100
4101         priv->ibss_beacon = NULL;
4102
4103         spin_lock_init(&priv->sta_lock);
4104         spin_lock_init(&priv->hcmd_lock);
4105
4106         INIT_LIST_HEAD(&priv->free_frames);
4107
4108         mutex_init(&priv->mutex);
4109         mutex_init(&priv->sync_cmd_mutex);
4110
4111         priv->ieee_channels = NULL;
4112         priv->ieee_rates = NULL;
4113         priv->band = IEEE80211_BAND_2GHZ;
4114
4115         priv->iw_mode = NL80211_IFTYPE_STATION;
4116         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4117         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4118         priv->_agn.agg_tids_count = 0;
4119
4120         /* initialize force reset */
4121         priv->force_reset[IWL_RF_RESET].reset_duration =
4122                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4123         priv->force_reset[IWL_FW_RESET].reset_duration =
4124                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4125
4126         /* Choose which receivers/antennas to use */
4127         if (priv->cfg->ops->hcmd->set_rxon_chain)
4128                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4129                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4130
4131         iwl_init_scan_params(priv);
4132
4133         /* init bt coex */
4134         if (priv->cfg->advanced_bt_coexist) {
4135                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4136                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4137                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4138                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4139                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4140                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4141                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4142         }
4143
4144         /* Set the tx_power_user_lmt to the lowest power level
4145          * this value will get overwritten by channel max power avg
4146          * from eeprom */
4147         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4148
4149         ret = iwl_init_channel_map(priv);
4150         if (ret) {
4151                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4152                 goto err;
4153         }
4154
4155         ret = iwlcore_init_geos(priv);
4156         if (ret) {
4157                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4158                 goto err_free_channel_map;
4159         }
4160         iwl_init_hw_rates(priv, priv->ieee_rates);
4161
4162         return 0;
4163
4164 err_free_channel_map:
4165         iwl_free_channel_map(priv);
4166 err:
4167         return ret;
4168 }
4169
4170 static void iwl_uninit_drv(struct iwl_priv *priv)
4171 {
4172         iwl_calib_free_results(priv);
4173         iwlcore_free_geos(priv);
4174         iwl_free_channel_map(priv);
4175         kfree(priv->scan_cmd);
4176 }
4177
4178 static struct ieee80211_ops iwl_hw_ops = {
4179         .tx = iwl_mac_tx,
4180         .start = iwl_mac_start,
4181         .stop = iwl_mac_stop,
4182         .add_interface = iwl_mac_add_interface,
4183         .remove_interface = iwl_mac_remove_interface,
4184         .config = iwl_mac_config,
4185         .configure_filter = iwlagn_configure_filter,
4186         .set_key = iwl_mac_set_key,
4187         .update_tkip_key = iwl_mac_update_tkip_key,
4188         .conf_tx = iwl_mac_conf_tx,
4189         .reset_tsf = iwl_mac_reset_tsf,
4190         .bss_info_changed = iwl_bss_info_changed,
4191         .ampdu_action = iwl_mac_ampdu_action,
4192         .hw_scan = iwl_mac_hw_scan,
4193         .sta_notify = iwl_mac_sta_notify,
4194         .sta_add = iwlagn_mac_sta_add,
4195         .sta_remove = iwl_mac_sta_remove,
4196         .channel_switch = iwl_mac_channel_switch,
4197         .flush = iwl_mac_flush,
4198         .tx_last_beacon = iwl_mac_tx_last_beacon,
4199 };
4200
4201 static void iwl_hw_detect(struct iwl_priv *priv)
4202 {
4203         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4204         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4205         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4206         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4207 }
4208
4209 static int iwl_set_hw_params(struct iwl_priv *priv)
4210 {
4211         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4212         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4213         if (priv->cfg->mod_params->amsdu_size_8K)
4214                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4215         else
4216                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4217
4218         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4219
4220         if (priv->cfg->mod_params->disable_11n)
4221                 priv->cfg->sku &= ~IWL_SKU_N;
4222
4223         /* Device-specific setup */
4224         return priv->cfg->ops->lib->set_hw_params(priv);
4225 }
4226
4227 static const u8 iwlagn_bss_ac_to_fifo[] = {
4228         IWL_TX_FIFO_VO,
4229         IWL_TX_FIFO_VI,
4230         IWL_TX_FIFO_BE,
4231         IWL_TX_FIFO_BK,
4232 };
4233
4234 static const u8 iwlagn_bss_ac_to_queue[] = {
4235         0, 1, 2, 3,
4236 };
4237
4238 static const u8 iwlagn_pan_ac_to_fifo[] = {
4239         IWL_TX_FIFO_VO_IPAN,
4240         IWL_TX_FIFO_VI_IPAN,
4241         IWL_TX_FIFO_BE_IPAN,
4242         IWL_TX_FIFO_BK_IPAN,
4243 };
4244
4245 static const u8 iwlagn_pan_ac_to_queue[] = {
4246         7, 6, 5, 4,
4247 };
4248
4249 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4250 {
4251         int err = 0, i;
4252         struct iwl_priv *priv;
4253         struct ieee80211_hw *hw;
4254         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4255         unsigned long flags;
4256         u16 pci_cmd, num_mac;
4257
4258         /************************
4259          * 1. Allocating HW data
4260          ************************/
4261
4262         /* Disabling hardware scan means that mac80211 will perform scans
4263          * "the hard way", rather than using device's scan. */
4264         if (cfg->mod_params->disable_hw_scan) {
4265                 if (iwl_debug_level & IWL_DL_INFO)
4266                         dev_printk(KERN_DEBUG, &(pdev->dev),
4267                                    "Disabling hw_scan\n");
4268                 iwl_hw_ops.hw_scan = NULL;
4269         }
4270
4271         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4272         if (!hw) {
4273                 err = -ENOMEM;
4274                 goto out;
4275         }
4276         priv = hw->priv;
4277         /* At this point both hw and priv are allocated. */
4278
4279         /*
4280          * The default context is always valid,
4281          * more may be discovered when firmware
4282          * is loaded.
4283          */
4284         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4285
4286         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4287                 priv->contexts[i].ctxid = i;
4288
4289         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4290         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4291         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4292         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4293         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4294         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4295         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4296         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4297         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4298                 BIT(NL80211_IFTYPE_ADHOC);
4299         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4300                 BIT(NL80211_IFTYPE_STATION);
4301         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4302         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4303         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4304
4305         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4306         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4307         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4308         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4309         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4310         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4311         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4312         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4313         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4314         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4315         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4316         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4317                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4318         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4319         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4320         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4321
4322         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4323
4324         SET_IEEE80211_DEV(hw, &pdev->dev);
4325
4326         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4327         priv->cfg = cfg;
4328         priv->pci_dev = pdev;
4329         priv->inta_mask = CSR_INI_SET_MASK;
4330
4331         /* is antenna coupling more than 35dB ? */
4332         priv->bt_ant_couple_ok =
4333                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4334                 true : false;
4335
4336         /* enable/disable bt channel announcement */
4337         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4338
4339         if (iwl_alloc_traffic_mem(priv))
4340                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4341
4342         /**************************
4343          * 2. Initializing PCI bus
4344          **************************/
4345         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4346                                 PCIE_LINK_STATE_CLKPM);
4347
4348         if (pci_enable_device(pdev)) {
4349                 err = -ENODEV;
4350                 goto out_ieee80211_free_hw;
4351         }
4352
4353         pci_set_master(pdev);
4354
4355         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4356         if (!err)
4357                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4358         if (err) {
4359                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4360                 if (!err)
4361                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4362                 /* both attempts failed: */
4363                 if (err) {
4364                         IWL_WARN(priv, "No suitable DMA available.\n");
4365                         goto out_pci_disable_device;
4366                 }
4367         }
4368
4369         err = pci_request_regions(pdev, DRV_NAME);
4370         if (err)
4371                 goto out_pci_disable_device;
4372
4373         pci_set_drvdata(pdev, priv);
4374
4375
4376         /***********************
4377          * 3. Read REV register
4378          ***********************/
4379         priv->hw_base = pci_iomap(pdev, 0, 0);
4380         if (!priv->hw_base) {
4381                 err = -ENODEV;
4382                 goto out_pci_release_regions;
4383         }
4384
4385         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4386                 (unsigned long long) pci_resource_len(pdev, 0));
4387         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4388
4389         /* these spin locks will be used in apm_ops.init and EEPROM access
4390          * we should init now
4391          */
4392         spin_lock_init(&priv->reg_lock);
4393         spin_lock_init(&priv->lock);
4394
4395         /*
4396          * stop and reset the on-board processor just in case it is in a
4397          * strange state ... like being left stranded by a primary kernel
4398          * and this is now the kdump kernel trying to start up
4399          */
4400         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4401
4402         iwl_hw_detect(priv);
4403         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4404                 priv->cfg->name, priv->hw_rev);
4405
4406         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4407          * PCI Tx retries from interfering with C3 CPU state */
4408         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4409
4410         iwl_prepare_card_hw(priv);
4411         if (!priv->hw_ready) {
4412                 IWL_WARN(priv, "Failed, HW not ready\n");
4413                 goto out_iounmap;
4414         }
4415
4416         /*****************
4417          * 4. Read EEPROM
4418          *****************/
4419         /* Read the EEPROM */
4420         err = iwl_eeprom_init(priv);
4421         if (err) {
4422                 IWL_ERR(priv, "Unable to init EEPROM\n");
4423                 goto out_iounmap;
4424         }
4425         err = iwl_eeprom_check_version(priv);
4426         if (err)
4427                 goto out_free_eeprom;
4428
4429         /* extract MAC Address */
4430         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4431         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4432         priv->hw->wiphy->addresses = priv->addresses;
4433         priv->hw->wiphy->n_addresses = 1;
4434         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4435         if (num_mac > 1) {
4436                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4437                        ETH_ALEN);
4438                 priv->addresses[1].addr[5]++;
4439                 priv->hw->wiphy->n_addresses++;
4440         }
4441
4442         /************************
4443          * 5. Setup HW constants
4444          ************************/
4445         if (iwl_set_hw_params(priv)) {
4446                 IWL_ERR(priv, "failed to set hw parameters\n");
4447                 goto out_free_eeprom;
4448         }
4449
4450         /*******************
4451          * 6. Setup priv
4452          *******************/
4453
4454         err = iwl_init_drv(priv);
4455         if (err)
4456                 goto out_free_eeprom;
4457         /* At this point both hw and priv are initialized. */
4458
4459         /********************
4460          * 7. Setup services
4461          ********************/
4462         spin_lock_irqsave(&priv->lock, flags);
4463         iwl_disable_interrupts(priv);
4464         spin_unlock_irqrestore(&priv->lock, flags);
4465
4466         pci_enable_msi(priv->pci_dev);
4467
4468         iwl_alloc_isr_ict(priv);
4469         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4470                           IRQF_SHARED, DRV_NAME, priv);
4471         if (err) {
4472                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4473                 goto out_disable_msi;
4474         }
4475
4476         iwl_setup_deferred_work(priv);
4477         iwl_setup_rx_handlers(priv);
4478
4479         /*********************************************
4480          * 8. Enable interrupts and read RFKILL state
4481          *********************************************/
4482
4483         /* enable interrupts if needed: hw bug w/a */
4484         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4485         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4486                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4487                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4488         }
4489
4490         iwl_enable_interrupts(priv);
4491
4492         /* If platform's RF_KILL switch is NOT set to KILL */
4493         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4494                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4495         else
4496                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4497
4498         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4499                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4500
4501         iwl_power_initialize(priv);
4502         iwl_tt_initialize(priv);
4503
4504         init_completion(&priv->_agn.firmware_loading_complete);
4505
4506         err = iwl_request_firmware(priv, true);
4507         if (err)
4508                 goto out_destroy_workqueue;
4509
4510         return 0;
4511
4512  out_destroy_workqueue:
4513         destroy_workqueue(priv->workqueue);
4514         priv->workqueue = NULL;
4515         free_irq(priv->pci_dev->irq, priv);
4516         iwl_free_isr_ict(priv);
4517  out_disable_msi:
4518         pci_disable_msi(priv->pci_dev);
4519         iwl_uninit_drv(priv);
4520  out_free_eeprom:
4521         iwl_eeprom_free(priv);
4522  out_iounmap:
4523         pci_iounmap(pdev, priv->hw_base);
4524  out_pci_release_regions:
4525         pci_set_drvdata(pdev, NULL);
4526         pci_release_regions(pdev);
4527  out_pci_disable_device:
4528         pci_disable_device(pdev);
4529  out_ieee80211_free_hw:
4530         iwl_free_traffic_mem(priv);
4531         ieee80211_free_hw(priv->hw);
4532  out:
4533         return err;
4534 }
4535
4536 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4537 {
4538         struct iwl_priv *priv = pci_get_drvdata(pdev);
4539         unsigned long flags;
4540
4541         if (!priv)
4542                 return;
4543
4544         wait_for_completion(&priv->_agn.firmware_loading_complete);
4545
4546         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4547
4548         iwl_dbgfs_unregister(priv);
4549         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4550
4551         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4552          * to be called and iwl_down since we are removing the device
4553          * we need to set STATUS_EXIT_PENDING bit.
4554          */
4555         set_bit(STATUS_EXIT_PENDING, &priv->status);
4556         if (priv->mac80211_registered) {
4557                 ieee80211_unregister_hw(priv->hw);
4558                 priv->mac80211_registered = 0;
4559         } else {
4560                 iwl_down(priv);
4561         }
4562
4563         /*
4564          * Make sure device is reset to low power before unloading driver.
4565          * This may be redundant with iwl_down(), but there are paths to
4566          * run iwl_down() without calling apm_ops.stop(), and there are
4567          * paths to avoid running iwl_down() at all before leaving driver.
4568          * This (inexpensive) call *makes sure* device is reset.
4569          */
4570         priv->cfg->ops->lib->apm_ops.stop(priv);
4571
4572         iwl_tt_exit(priv);
4573
4574         /* make sure we flush any pending irq or
4575          * tasklet for the driver
4576          */
4577         spin_lock_irqsave(&priv->lock, flags);
4578         iwl_disable_interrupts(priv);
4579         spin_unlock_irqrestore(&priv->lock, flags);
4580
4581         iwl_synchronize_irq(priv);
4582
4583         iwl_dealloc_ucode_pci(priv);
4584
4585         if (priv->rxq.bd)
4586                 iwlagn_rx_queue_free(priv, &priv->rxq);
4587         iwlagn_hw_txq_ctx_free(priv);
4588
4589         iwl_eeprom_free(priv);
4590
4591
4592         /*netif_stop_queue(dev); */
4593         flush_workqueue(priv->workqueue);
4594
4595         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4596          * priv->workqueue... so we can't take down the workqueue
4597          * until now... */
4598         destroy_workqueue(priv->workqueue);
4599         priv->workqueue = NULL;
4600         iwl_free_traffic_mem(priv);
4601
4602         free_irq(priv->pci_dev->irq, priv);
4603         pci_disable_msi(priv->pci_dev);
4604         pci_iounmap(pdev, priv->hw_base);
4605         pci_release_regions(pdev);
4606         pci_disable_device(pdev);
4607         pci_set_drvdata(pdev, NULL);
4608
4609         iwl_uninit_drv(priv);
4610
4611         iwl_free_isr_ict(priv);
4612
4613         if (priv->ibss_beacon)
4614                 dev_kfree_skb(priv->ibss_beacon);
4615
4616         ieee80211_free_hw(priv->hw);
4617 }
4618
4619
4620 /*****************************************************************************
4621  *
4622  * driver and module entry point
4623  *
4624  *****************************************************************************/
4625
4626 /* Hardware specific file defines the PCI IDs table for that hardware module */
4627 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4628 #ifdef CONFIG_IWL4965
4629         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4630         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4631 #endif /* CONFIG_IWL4965 */
4632 #ifdef CONFIG_IWL5000
4633 /* 5100 Series WiFi */
4634         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4635         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4636         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4637         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4638         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4639         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4640         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4641         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4642         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4643         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4644         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4645         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4646         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4647         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4648         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4649         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4650         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4651         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4652         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4653         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4654         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4655         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4656         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4657         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4658
4659 /* 5300 Series WiFi */
4660         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4661         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4662         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4663         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4664         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4665         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4666         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4667         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4668         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4669         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4670         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4671         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4672
4673 /* 5350 Series WiFi/WiMax */
4674         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4675         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4676         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4677
4678 /* 5150 Series Wifi/WiMax */
4679         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4680         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4681         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4682         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4683         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4684         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4685
4686         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4687         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4688         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4689         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4690
4691 /* 6x00 Series */
4692         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4693         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4694         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4695         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4696         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4697         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4698         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4699         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4700         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4701         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4702
4703 /* 6x00 Series Gen2a */
4704         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4705         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4706         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4707         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4708         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4709         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4710         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4711         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4712         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4713         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4714         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4715         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4716         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4717         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4718
4719 /* 6x00 Series Gen2b */
4720         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4721         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4722         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4723         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4724         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4725         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4726         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4727         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4728         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4729         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4730         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4731         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4732         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4733         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4734         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4735         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4736         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4737         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4738         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4739         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4740         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4741         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4742         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4743         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4744         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4745         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4746         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4747         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4748
4749 /* 6x50 WiFi/WiMax Series */
4750         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4751         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4752         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4753         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4754         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4755         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4756
4757 /* 6x50 WiFi/WiMax Series Gen2 */
4758         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4759         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4760         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4761         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4762         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4763         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4764
4765 /* 1000 Series WiFi */
4766         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4767         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4768         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4769         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4770         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4771         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4772         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4773         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4774         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4775         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4776         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4777         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4778 #endif /* CONFIG_IWL5000 */
4779
4780         {0}
4781 };
4782 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4783
4784 static struct pci_driver iwl_driver = {
4785         .name = DRV_NAME,
4786         .id_table = iwl_hw_card_ids,
4787         .probe = iwl_pci_probe,
4788         .remove = __devexit_p(iwl_pci_remove),
4789 #ifdef CONFIG_PM
4790         .suspend = iwl_pci_suspend,
4791         .resume = iwl_pci_resume,
4792 #endif
4793 };
4794
4795 static int __init iwl_init(void)
4796 {
4797
4798         int ret;
4799         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4800         pr_info(DRV_COPYRIGHT "\n");
4801
4802         ret = iwlagn_rate_control_register();
4803         if (ret) {
4804                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4805                 return ret;
4806         }
4807
4808         ret = pci_register_driver(&iwl_driver);
4809         if (ret) {
4810                 pr_err("Unable to initialize PCI module\n");
4811                 goto error_register;
4812         }
4813
4814         return ret;
4815
4816 error_register:
4817         iwlagn_rate_control_unregister();
4818         return ret;
4819 }
4820
4821 static void __exit iwl_exit(void)
4822 {
4823         pci_unregister_driver(&iwl_driver);
4824         iwlagn_rate_control_unregister();
4825 }
4826
4827 module_exit(iwl_exit);
4828 module_init(iwl_init);
4829
4830 #ifdef CONFIG_IWLWIFI_DEBUG
4831 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4832 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4833 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4834 MODULE_PARM_DESC(debug, "debug output mask");
4835 #endif
4836
4837 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4838 MODULE_PARM_DESC(swcrypto50,
4839                  "using crypto in software (default 0 [hardware]) (deprecated)");
4840 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4841 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4842 module_param_named(queues_num50,
4843                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4844 MODULE_PARM_DESC(queues_num50,
4845                  "number of hw queues in 50xx series (deprecated)");
4846 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4847 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4848 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4849 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4850 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4851 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4852 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4853                    int, S_IRUGO);
4854 MODULE_PARM_DESC(amsdu_size_8K50,
4855                  "enable 8K amsdu size in 50XX series (deprecated)");
4856 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4857                    int, S_IRUGO);
4858 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4859 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4860 MODULE_PARM_DESC(fw_restart50,
4861                  "restart firmware in case of error (deprecated)");
4862 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4863 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4864 module_param_named(
4865         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4866 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4867
4868 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4869                    S_IRUGO);
4870 MODULE_PARM_DESC(ucode_alternative,
4871                  "specify ucode alternative to use from ucode file");
4872
4873 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4874 MODULE_PARM_DESC(antenna_coupling,
4875                  "specify antenna coupling in dB (defualt: 0 dB)");
4876
4877 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4878 MODULE_PARM_DESC(bt_ch_announce,
4879                  "Enable BT channel announcement mode (default: enable)");