drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 static void iwl_bg_beacon_update(struct work_struct *work)
 428 {
 429         struct iwl_priv *priv =
 430                 container_of(work, struct iwl_priv, beacon_update);
 431         struct sk_buff *beacon;
 432
 433         mutex_lock(&priv->mutex);
 434         if (!priv->beacon_ctx) {
 435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 436                 goto out;
 437         }
 438
 439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 440                 /*
 441                  * The ucode will send beacon notifications even in
 442                  * IBSS mode, but we don't want to process them. But
 443                  * we need to defer the type check to here due to
 444                  * requiring locking around the beacon_ctx access.
 445                  */
 446                 goto out;
 447         }
 448
 449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 451         if (!beacon) {
 452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 453                 goto out;
 454         }
 455
 456         /* new beacon skb is allocated every time; dispose previous.*/
 457         dev_kfree_skb(priv->beacon_skb);
 458
 459         priv->beacon_skb = beacon;
 460
 461         iwlagn_send_beacon_cmd(priv);
 462  out:
 463         mutex_unlock(&priv->mutex);
 464 }
 465
 466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 467 {
 468         struct iwl_priv *priv =
 469                 container_of(work, struct iwl_priv, bt_runtime_config);
 470
 471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 472                 return;
 473
 474         /* dont send host command if rf-kill is on */
 475         if (!iwl_is_ready_rf(priv))
 476                 return;
 477         priv->cfg->ops->hcmd->send_bt_config(priv);
 478 }
 479
 480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 481 {
 482         struct iwl_priv *priv =
 483                 container_of(work, struct iwl_priv, bt_full_concurrency);
 484         struct iwl_rxon_context *ctx;
 485
 486         mutex_lock(&priv->mutex);
 487
 488         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 489                 goto out;
 490
 491         /* dont send host command if rf-kill is on */
 492         if (!iwl_is_ready_rf(priv))
 493                 goto out;
 494
 495         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 496                        priv->bt_full_concurrent ?
 497                        "full concurrency" : "3-wire");
 498
 499         /*
 500          * LQ & RXON updated cmds must be sent before BT Config cmd
 501          * to avoid 3-wire collisions
 502          */
 503         for_each_context(priv, ctx) {
 504                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 505                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 506                 iwlcore_commit_rxon(priv, ctx);
 507         }
 508
 509         priv->cfg->ops->hcmd->send_bt_config(priv);
 510 out:
 511         mutex_unlock(&priv->mutex);
 512 }
 513
 514 /**
 515  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 516  *
 517  * This callback is provided in order to send a statistics request.
 518  *
 519  * This timer function is continually reset to execute within
 520  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 521  * was received.  We need to ensure we receive the statistics in order
 522  * to update the temperature used for calibrating the TXPOWER.
 523  */
 524 static void iwl_bg_statistics_periodic(unsigned long data)
 525 {
 526         struct iwl_priv *priv = (struct iwl_priv *)data;
 527
 528         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 529                 return;
 530
 531         /* dont send host command if rf-kill is on */
 532         if (!iwl_is_ready_rf(priv))
 533                 return;
 534
 535         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 536 }
 537
 538
 539 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 540                                         u32 start_idx, u32 num_events,
 541                                         u32 mode)
 542 {
 543         u32 i;
 544         u32 ptr;        /* SRAM byte address of log data */
 545         u32 ev, time, data; /* event log data */
 546         unsigned long reg_flags;
 547
 548         if (mode == 0)
 549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 550         else
 551                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 552
 553         /* Make sure device is powered up for SRAM reads */
 554         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 555         if (iwl_grab_nic_access(priv)) {
 556                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 557                 return;
 558         }
 559
 560         /* Set starting address; reads will auto-increment */
 561         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 562         rmb();
 563
 564         /*
 565          * "time" is actually "data" for mode 0 (no timestamp).
 566          * place event id # at far right for easier visual parsing.
 567          */
 568         for (i = 0; i < num_events; i++) {
 569                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 570                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 571                 if (mode == 0) {
 572                         trace_iwlwifi_dev_ucode_cont_event(priv,
 573                                                         0, time, ev);
 574                 } else {
 575                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 576                         trace_iwlwifi_dev_ucode_cont_event(priv,
 577                                                 time, data, ev);
 578                 }
 579         }
 580         /* Allow device to power down */
 581         iwl_release_nic_access(priv);
 582         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 583 }
 584
 585 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 586 {
 587         u32 capacity;   /* event log capacity in # entries */
 588         u32 base;       /* SRAM byte address of event log header */
 589         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 590         u32 num_wraps;  /* # times uCode wrapped to top of log */
 591         u32 next_entry; /* index of next entry to be written by uCode */
 592
 593         if (priv->ucode_type == UCODE_INIT)
 594                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 595         else
 596                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 597         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 598                 capacity = iwl_read_targ_mem(priv, base);
 599                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 600                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 601                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 602         } else
 603                 return;
 604
 605         if (num_wraps == priv->event_log.num_wraps) {
 606                 iwl_print_cont_event_trace(priv,
 607                                        base, priv->event_log.next_entry,
 608                                        next_entry - priv->event_log.next_entry,
 609                                        mode);
 610                 priv->event_log.non_wraps_count++;
 611         } else {
 612                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 613                         priv->event_log.wraps_more_count++;
 614                 else
 615                         priv->event_log.wraps_once_count++;
 616                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 617                                 num_wraps - priv->event_log.num_wraps,
 618                                 next_entry, priv->event_log.next_entry);
 619                 if (next_entry < priv->event_log.next_entry) {
 620                         iwl_print_cont_event_trace(priv, base,
 621                                priv->event_log.next_entry,
 622                                capacity - priv->event_log.next_entry,
 623                                mode);
 624
 625                         iwl_print_cont_event_trace(priv, base, 0,
 626                                 next_entry, mode);
 627                 } else {
 628                         iwl_print_cont_event_trace(priv, base,
 629                                next_entry, capacity - next_entry,
 630                                mode);
 631
 632                         iwl_print_cont_event_trace(priv, base, 0,
 633                                 next_entry, mode);
 634                 }
 635         }
 636         priv->event_log.num_wraps = num_wraps;
 637         priv->event_log.next_entry = next_entry;
 638 }
 639
 640 /**
 641  * iwl_bg_ucode_trace - Timer callback to log ucode event
 642  *
 643  * The timer is continually set to execute every
 644  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 645  * this function is to perform continuous uCode event logging operation
 646  * if enabled
 647  */
 648 static void iwl_bg_ucode_trace(unsigned long data)
 649 {
 650         struct iwl_priv *priv = (struct iwl_priv *)data;
 651
 652         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 653                 return;
 654
 655         if (priv->event_log.ucode_trace) {
 656                 iwl_continuous_event_trace(priv);
 657                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 658                 mod_timer(&priv->ucode_trace,
 659                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 660         }
 661 }
 662
 663 static void iwl_bg_tx_flush(struct work_struct *work)
 664 {
 665         struct iwl_priv *priv =
 666                 container_of(work, struct iwl_priv, tx_flush);
 667
 668         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 669                 return;
 670
 671         /* do nothing if rf-kill is on */
 672         if (!iwl_is_ready_rf(priv))
 673                 return;
 674
 675         if (priv->cfg->ops->lib->txfifo_flush) {
 676                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 677                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 678         }
 679 }
 680
 681 /**
 682  * iwl_rx_handle - Main entry function for receiving responses from uCode
 683  *
 684  * Uses the priv->rx_handlers callback function array to invoke
 685  * the appropriate handlers, including command responses,
 686  * frame-received notifications, and other notifications.
 687  */
 688 static void iwl_rx_handle(struct iwl_priv *priv)
 689 {
 690         struct iwl_rx_mem_buffer *rxb;
 691         struct iwl_rx_packet *pkt;
 692         struct iwl_rx_queue *rxq = &priv->rxq;
 693         u32 r, i;
 694         int reclaim;
 695         unsigned long flags;
 696         u8 fill_rx = 0;
 697         u32 count = 8;
 698         int total_empty;
 699
 700         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 701          * buffer that the driver may process (last buffer filled by ucode). */
 702         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 703         i = rxq->read;
 704
 705         /* Rx interrupt, but nothing sent from uCode */
 706         if (i == r)
 707                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 708
 709         /* calculate total frames need to be restock after handling RX */
 710         total_empty = r - rxq->write_actual;
 711         if (total_empty < 0)
 712                 total_empty += RX_QUEUE_SIZE;
 713
 714         if (total_empty > (RX_QUEUE_SIZE / 2))
 715                 fill_rx = 1;
 716
 717         while (i != r) {
 718                 int len;
 719
 720                 rxb = rxq->queue[i];
 721
 722                 /* If an RXB doesn't have a Rx queue slot associated with it,
 723                  * then a bug has been introduced in the queue refilling
 724                  * routines -- catch it here */
 725                 BUG_ON(rxb == NULL);
 726
 727                 rxq->queue[i] = NULL;
 728
 729                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 730                                PAGE_SIZE << priv->hw_params.rx_page_order,
 731                                PCI_DMA_FROMDEVICE);
 732                 pkt = rxb_addr(rxb);
 733
 734                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 735                 len += sizeof(u32); /* account for status word */
 736                 trace_iwlwifi_dev_rx(priv, pkt, len);
 737
 738                 /* Reclaim a command buffer only if this packet is a response
 739                  *   to a (driver-originated) command.
 740                  * If the packet (e.g. Rx frame) originated from uCode,
 741                  *   there is no command buffer to reclaim.
 742                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 743                  *   but apparently a few don't get set; catch them here. */
 744                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 745                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 746                         (pkt->hdr.cmd != REPLY_RX) &&
 747                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 748                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 749                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 750                         (pkt->hdr.cmd != REPLY_TX);
 751
 752                 /*
 753                  * Do the notification wait before RX handlers so
 754                  * even if the RX handler consumes the RXB we have
 755                  * access to it in the notification wait entry.
 756                  */
 757                 if (!list_empty(&priv->_agn.notif_waits)) {
 758                         struct iwl_notification_wait *w;
 759
 760                         spin_lock(&priv->_agn.notif_wait_lock);
 761                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 762                                 if (w->cmd == pkt->hdr.cmd) {
 763                                         w->triggered = true;
 764                                         if (w->fn)
 765                                                 w->fn(priv, pkt);
 766                                 }
 767                         }
 768                         spin_unlock(&priv->_agn.notif_wait_lock);
 769
 770                         wake_up_all(&priv->_agn.notif_waitq);
 771                 }
 772
 773                 /* Based on type of command response or notification,
 774                  *   handle those that need handling via function in
 775                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 776                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 777                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 778                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 779                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 780                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 781                 } else {
 782                         /* No handling needed */
 783                         IWL_DEBUG_RX(priv,
 784                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 785                                 r, i, get_cmd_string(pkt->hdr.cmd),
 786                                 pkt->hdr.cmd);
 787                 }
 788
 789                 /*
 790                  * XXX: After here, we should always check rxb->page
 791                  * against NULL before touching it or its virtual
 792                  * memory (pkt). Because some rx_handler might have
 793                  * already taken or freed the pages.
 794                  */
 795
 796                 if (reclaim) {
 797                         /* Invoke any callbacks, transfer the buffer to caller,
 798                          * and fire off the (possibly) blocking iwl_send_cmd()
 799                          * as we reclaim the driver command queue */
 800                         if (rxb->page)
 801                                 iwl_tx_cmd_complete(priv, rxb);
 802                         else
 803                                 IWL_WARN(priv, "Claim null rxb?\n");
 804                 }
 805
 806                 /* Reuse the page if possible. For notification packets and
 807                  * SKBs that fail to Rx correctly, add them back into the
 808                  * rx_free list for reuse later. */
 809                 spin_lock_irqsave(&rxq->lock, flags);
 810                 if (rxb->page != NULL) {
 811                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 812                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 813                                 PCI_DMA_FROMDEVICE);
 814                         list_add_tail(&rxb->list, &rxq->rx_free);
 815                         rxq->free_count++;
 816                 } else
 817                         list_add_tail(&rxb->list, &rxq->rx_used);
 818
 819                 spin_unlock_irqrestore(&rxq->lock, flags);
 820
 821                 i = (i + 1) & RX_QUEUE_MASK;
 822                 /* If there are a lot of unused frames,
 823                  * restock the Rx queue so ucode wont assert. */
 824                 if (fill_rx) {
 825                         count++;
 826                         if (count >= 8) {
 827                                 rxq->read = i;
 828                                 iwlagn_rx_replenish_now(priv);
 829                                 count = 0;
 830                         }
 831                 }
 832         }
 833
 834         /* Backtrack one entry */
 835         rxq->read = i;
 836         if (fill_rx)
 837                 iwlagn_rx_replenish_now(priv);
 838         else
 839                 iwlagn_rx_queue_restock(priv);
 840 }
 841
 842 /* call this function to flush any scheduled tasklet */
 843 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
 844 {
 845         /* wait to make sure we flush pending tasklet*/
 846         synchronize_irq(priv->pci_dev->irq);
 847         tasklet_kill(&priv->irq_tasklet);
 848 }
 849
 850 /* tasklet for iwlagn interrupt */
 851 static void iwl_irq_tasklet(struct iwl_priv *priv)
 852 {
 853         u32 inta = 0;
 854         u32 handled = 0;
 855         unsigned long flags;
 856         u32 i;
 857 #ifdef CONFIG_IWLWIFI_DEBUG
 858         u32 inta_mask;
 859 #endif
 860
 861         spin_lock_irqsave(&priv->lock, flags);
 862
 863         /* Ack/clear/reset pending uCode interrupts.
 864          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 865          */
 866         /* There is a hardware bug in the interrupt mask function that some
 867          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 868          * they are disabled in the CSR_INT_MASK register. Furthermore the
 869          * ICT interrupt handling mechanism has another bug that might cause
 870          * these unmasked interrupts fail to be detected. We workaround the
 871          * hardware bugs here by ACKing all the possible interrupts so that
 872          * interrupt coalescing can still be achieved.
 873          */
 874         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
 875
 876         inta = priv->_agn.inta;
 877
 878 #ifdef CONFIG_IWLWIFI_DEBUG
 879         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
 880                 /* just for debug */
 881                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
 882                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
 883                                 inta, inta_mask);
 884         }
 885 #endif
 886
 887         spin_unlock_irqrestore(&priv->lock, flags);
 888
 889         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
 890         priv->_agn.inta = 0;
 891
 892         /* Now service all interrupt bits discovered above. */
 893         if (inta & CSR_INT_BIT_HW_ERR) {
 894                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
 895
 896                 /* Tell the device to stop sending interrupts */
 897                 iwl_disable_interrupts(priv);
 898
 899                 priv->isr_stats.hw++;
 900                 iwl_irq_handle_error(priv);
 901
 902                 handled |= CSR_INT_BIT_HW_ERR;
 903
 904                 return;
 905         }
 906
 907 #ifdef CONFIG_IWLWIFI_DEBUG
 908         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
 909                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 910                 if (inta & CSR_INT_BIT_SCD) {
 911                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
 912                                       "the frame/frames.\n");
 913                         priv->isr_stats.sch++;
 914                 }
 915
 916                 /* Alive notification via Rx interrupt will do the real work */
 917                 if (inta & CSR_INT_BIT_ALIVE) {
 918                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
 919                         priv->isr_stats.alive++;
 920                 }
 921         }
 922 #endif
 923         /* Safely ignore these bits for debug checks below */
 924         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 925
 926         /* HW RF KILL switch toggled */
 927         if (inta & CSR_INT_BIT_RF_KILL) {
 928                 int hw_rf_kill = 0;
 929                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
 930                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 931                         hw_rf_kill = 1;
 932
 933                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
 934                                 hw_rf_kill ? "disable radio" : "enable radio");
 935
 936                 priv->isr_stats.rfkill++;
 937
 938                 /* driver only loads ucode once setting the interface up.
 939                  * the driver allows loading the ucode even if the radio
 940                  * is killed. Hence update the killswitch state here. The
 941                  * rfkill handler will care about restarting if needed.
 942                  */
 943                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
 944                         if (hw_rf_kill)
 945                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 946                         else
 947                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 948                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
 949                 }
 950
 951                 handled |= CSR_INT_BIT_RF_KILL;
 952         }
 953
 954         /* Chip got too hot and stopped itself */
 955         if (inta & CSR_INT_BIT_CT_KILL) {
 956                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
 957                 priv->isr_stats.ctkill++;
 958                 handled |= CSR_INT_BIT_CT_KILL;
 959         }
 960
 961         /* Error detected by uCode */
 962         if (inta & CSR_INT_BIT_SW_ERR) {
 963                 IWL_ERR(priv, "Microcode SW error detected. "
 964                         " Restarting 0x%X.\n", inta);
 965                 priv->isr_stats.sw++;
 966                 iwl_irq_handle_error(priv);
 967                 handled |= CSR_INT_BIT_SW_ERR;
 968         }
 969
 970         /* uCode wakes up after power-down sleep */
 971         if (inta & CSR_INT_BIT_WAKEUP) {
 972                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
 973                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
 974                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
 975                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
 976
 977                 priv->isr_stats.wakeup++;
 978
 979                 handled |= CSR_INT_BIT_WAKEUP;
 980         }
 981
 982         /* All uCode command responses, including Tx command responses,
 983          * Rx "responses" (frame-received notification), and other
 984          * notifications from uCode come through here*/
 985         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 986                         CSR_INT_BIT_RX_PERIODIC)) {
 987                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
 988                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 989                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 990                         iwl_write32(priv, CSR_FH_INT_STATUS,
 991                                         CSR_FH_INT_RX_MASK);
 992                 }
 993                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 994                         handled |= CSR_INT_BIT_RX_PERIODIC;
 995                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 996                 }
 997                 /* Sending RX interrupt require many steps to be done in the
 998                  * the device:
 999                  * 1- write interrupt to current index in ICT table.
1000                  * 2- dma RX frame.
1001                  * 3- update RX shared data to indicate last write index.
1002                  * 4- send interrupt.
1003                  * This could lead to RX race, driver could receive RX interrupt
1004                  * but the shared data changes does not reflect this;
1005                  * periodic interrupt will detect any dangling Rx activity.
1006                  */
1007
1008                 /* Disable periodic interrupt; we use it as just a one-shot. */
1009                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1010                             CSR_INT_PERIODIC_DIS);
1011                 iwl_rx_handle(priv);
1012
1013                 /*
1014                  * Enable periodic interrupt in 8 msec only if we received
1015                  * real RX interrupt (instead of just periodic int), to catch
1016                  * any dangling Rx interrupt.  If it was just the periodic
1017                  * interrupt, there was no dangling Rx activity, and no need
1018                  * to extend the periodic interrupt; one-shot is enough.
1019                  */
1020                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1021                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1022                                     CSR_INT_PERIODIC_ENA);
1023
1024                 priv->isr_stats.rx++;
1025         }
1026
1027         /* This "Tx" DMA channel is used only for loading uCode */
1028         if (inta & CSR_INT_BIT_FH_TX) {
1029                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1030                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1031                 priv->isr_stats.tx++;
1032                 handled |= CSR_INT_BIT_FH_TX;
1033                 /* Wake up uCode load routine, now that load is complete */
1034                 priv->ucode_write_complete = 1;
1035                 wake_up_interruptible(&priv->wait_command_queue);
1036         }
1037
1038         if (inta & ~handled) {
1039                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1040                 priv->isr_stats.unhandled++;
1041         }
1042
1043         if (inta & ~(priv->inta_mask)) {
1044                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1045                          inta & ~priv->inta_mask);
1046         }
1047
1048         /* Re-enable all interrupts */
1049         /* only Re-enable if disabled by irq */
1050         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1051                 iwl_enable_interrupts(priv);
1052         /* Re-enable RF_KILL if it occurred */
1053         else if (handled & CSR_INT_BIT_RF_KILL)
1054                 iwl_enable_rfkill_int(priv);
1055 }
1056
1057 /*****************************************************************************
1058  *
1059  * sysfs attributes
1060  *
1061  *****************************************************************************/
1062
1063 #ifdef CONFIG_IWLWIFI_DEBUG
1064
1065 /*
1066  * The following adds a new attribute to the sysfs representation
1067  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1068  * used for controlling the debug level.
1069  *
1070  * See the level definitions in iwl for details.
1071  *
1072  * The debug_level being managed using sysfs below is a per device debug
1073  * level that is used instead of the global debug level if it (the per
1074  * device debug level) is set.
1075  */
1076 static ssize_t show_debug_level(struct device *d,
1077                                 struct device_attribute *attr, char *buf)
1078 {
1079         struct iwl_priv *priv = dev_get_drvdata(d);
1080         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1081 }
1082 static ssize_t store_debug_level(struct device *d,
1083                                 struct device_attribute *attr,
1084                                  const char *buf, size_t count)
1085 {
1086         struct iwl_priv *priv = dev_get_drvdata(d);
1087         unsigned long val;
1088         int ret;
1089
1090         ret = strict_strtoul(buf, 0, &val);
1091         if (ret)
1092                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1093         else {
1094                 priv->debug_level = val;
1095                 if (iwl_alloc_traffic_mem(priv))
1096                         IWL_ERR(priv,
1097                                 "Not enough memory to generate traffic log\n");
1098         }
1099         return strnlen(buf, count);
1100 }
1101
1102 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1103                         show_debug_level, store_debug_level);
1104
1105
1106 #endif /* CONFIG_IWLWIFI_DEBUG */
1107
1108
1109 static ssize_t show_temperature(struct device *d,
1110                                 struct device_attribute *attr, char *buf)
1111 {
1112         struct iwl_priv *priv = dev_get_drvdata(d);
1113
1114         if (!iwl_is_alive(priv))
1115                 return -EAGAIN;
1116
1117         return sprintf(buf, "%d\n", priv->temperature);
1118 }
1119
1120 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1121
1122 static ssize_t show_tx_power(struct device *d,
1123                              struct device_attribute *attr, char *buf)
1124 {
1125         struct iwl_priv *priv = dev_get_drvdata(d);
1126
1127         if (!iwl_is_ready_rf(priv))
1128                 return sprintf(buf, "off\n");
1129         else
1130                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1131 }
1132
1133 static ssize_t store_tx_power(struct device *d,
1134                               struct device_attribute *attr,
1135                               const char *buf, size_t count)
1136 {
1137         struct iwl_priv *priv = dev_get_drvdata(d);
1138         unsigned long val;
1139         int ret;
1140
1141         ret = strict_strtoul(buf, 10, &val);
1142         if (ret)
1143                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1144         else {
1145                 ret = iwl_set_tx_power(priv, val, false);
1146                 if (ret)
1147                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1148                                 ret);
1149                 else
1150                         ret = count;
1151         }
1152         return ret;
1153 }
1154
1155 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1156
1157 static struct attribute *iwl_sysfs_entries[] = {
1158         &dev_attr_temperature.attr,
1159         &dev_attr_tx_power.attr,
1160 #ifdef CONFIG_IWLWIFI_DEBUG
1161         &dev_attr_debug_level.attr,
1162 #endif
1163         NULL
1164 };
1165
1166 static struct attribute_group iwl_attribute_group = {
1167         .name = NULL,           /* put in device directory */
1168         .attrs = iwl_sysfs_entries,
1169 };
1170
1171 /******************************************************************************
1172  *
1173  * uCode download functions
1174  *
1175  ******************************************************************************/
1176
1177 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1178 {
1179         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1180         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1181         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1182         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1183 }
1184
1185 static void iwl_nic_start(struct iwl_priv *priv)
1186 {
1187         /* Remove all resets to allow NIC to operate */
1188         iwl_write32(priv, CSR_RESET, 0);
1189 }
1190
1191 struct iwlagn_ucode_capabilities {
1192         u32 max_probe_length;
1193         u32 standard_phy_calibration_size;
1194         bool pan;
1195 };
1196
1197 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1198 static int iwl_mac_setup_register(struct iwl_priv *priv,
1199                                   struct iwlagn_ucode_capabilities *capa);
1200
1201 #define UCODE_EXPERIMENTAL_INDEX        100
1202 #define UCODE_EXPERIMENTAL_TAG          "exp"
1203
1204 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1205 {
1206         const char *name_pre = priv->cfg->fw_name_pre;
1207         char tag[8];
1208
1209         if (first) {
1210 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1211                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1212                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1213         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1214 #endif
1215                 priv->fw_index = priv->cfg->ucode_api_max;
1216                 sprintf(tag, "%d", priv->fw_index);
1217         } else {
1218                 priv->fw_index--;
1219                 sprintf(tag, "%d", priv->fw_index);
1220         }
1221
1222         if (priv->fw_index < priv->cfg->ucode_api_min) {
1223                 IWL_ERR(priv, "no suitable firmware found!\n");
1224                 return -ENOENT;
1225         }
1226
1227         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1228
1229         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1230                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1231                                 ? "EXPERIMENTAL " : "",
1232                        priv->firmware_name);
1233
1234         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1235                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1236                                        iwl_ucode_callback);
1237 }
1238
1239 struct iwlagn_firmware_pieces {
1240         const void *inst, *data, *init, *init_data;
1241         size_t inst_size, data_size, init_size, init_data_size;
1242
1243         u32 build;
1244
1245         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1246         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1247 };
1248
1249 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1250                                        const struct firmware *ucode_raw,
1251                                        struct iwlagn_firmware_pieces *pieces)
1252 {
1253         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1254         u32 api_ver, hdr_size;
1255         const u8 *src;
1256
1257         priv->ucode_ver = le32_to_cpu(ucode->ver);
1258         api_ver = IWL_UCODE_API(priv->ucode_ver);
1259
1260         switch (api_ver) {
1261         default:
1262                 hdr_size = 28;
1263                 if (ucode_raw->size < hdr_size) {
1264                         IWL_ERR(priv, "File size too small!\n");
1265                         return -EINVAL;
1266                 }
1267                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1268                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1269                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1270                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1271                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1272                 src = ucode->u.v2.data;
1273                 break;
1274         case 0:
1275         case 1:
1276         case 2:
1277                 hdr_size = 24;
1278                 if (ucode_raw->size < hdr_size) {
1279                         IWL_ERR(priv, "File size too small!\n");
1280                         return -EINVAL;
1281                 }
1282                 pieces->build = 0;
1283                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1284                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1285                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1286                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1287                 src = ucode->u.v1.data;
1288                 break;
1289         }
1290
1291         /* Verify size of file vs. image size info in file's header */
1292         if (ucode_raw->size != hdr_size + pieces->inst_size +
1293                                 pieces->data_size + pieces->init_size +
1294                                 pieces->init_data_size) {
1295
1296                 IWL_ERR(priv,
1297                         "uCode file size %d does not match expected size\n",
1298                         (int)ucode_raw->size);
1299                 return -EINVAL;
1300         }
1301
1302         pieces->inst = src;
1303         src += pieces->inst_size;
1304         pieces->data = src;
1305         src += pieces->data_size;
1306         pieces->init = src;
1307         src += pieces->init_size;
1308         pieces->init_data = src;
1309         src += pieces->init_data_size;
1310
1311         return 0;
1312 }
1313
1314 static int iwlagn_wanted_ucode_alternative = 1;
1315
1316 static int iwlagn_load_firmware(struct iwl_priv *priv,
1317                                 const struct firmware *ucode_raw,
1318                                 struct iwlagn_firmware_pieces *pieces,
1319                                 struct iwlagn_ucode_capabilities *capa)
1320 {
1321         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1322         struct iwl_ucode_tlv *tlv;
1323         size_t len = ucode_raw->size;
1324         const u8 *data;
1325         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1326         u64 alternatives;
1327         u32 tlv_len;
1328         enum iwl_ucode_tlv_type tlv_type;
1329         const u8 *tlv_data;
1330
1331         if (len < sizeof(*ucode)) {
1332                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1333                 return -EINVAL;
1334         }
1335
1336         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1337                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1338                         le32_to_cpu(ucode->magic));
1339                 return -EINVAL;
1340         }
1341
1342         /*
1343          * Check which alternatives are present, and "downgrade"
1344          * when the chosen alternative is not present, warning
1345          * the user when that happens. Some files may not have
1346          * any alternatives, so don't warn in that case.
1347          */
1348         alternatives = le64_to_cpu(ucode->alternatives);
1349         tmp = wanted_alternative;
1350         if (wanted_alternative > 63)
1351                 wanted_alternative = 63;
1352         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1353                 wanted_alternative--;
1354         if (wanted_alternative && wanted_alternative != tmp)
1355                 IWL_WARN(priv,
1356                          "uCode alternative %d not available, choosing %d\n",
1357                          tmp, wanted_alternative);
1358
1359         priv->ucode_ver = le32_to_cpu(ucode->ver);
1360         pieces->build = le32_to_cpu(ucode->build);
1361         data = ucode->data;
1362
1363         len -= sizeof(*ucode);
1364
1365         while (len >= sizeof(*tlv)) {
1366                 u16 tlv_alt;
1367
1368                 len -= sizeof(*tlv);
1369                 tlv = (void *)data;
1370
1371                 tlv_len = le32_to_cpu(tlv->length);
1372                 tlv_type = le16_to_cpu(tlv->type);
1373                 tlv_alt = le16_to_cpu(tlv->alternative);
1374                 tlv_data = tlv->data;
1375
1376                 if (len < tlv_len) {
1377                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1378                                 len, tlv_len);
1379                         return -EINVAL;
1380                 }
1381                 len -= ALIGN(tlv_len, 4);
1382                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1383
1384                 /*
1385                  * Alternative 0 is always valid.
1386                  *
1387                  * Skip alternative TLVs that are not selected.
1388                  */
1389                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1390                         continue;
1391
1392                 switch (tlv_type) {
1393                 case IWL_UCODE_TLV_INST:
1394                         pieces->inst = tlv_data;
1395                         pieces->inst_size = tlv_len;
1396                         break;
1397                 case IWL_UCODE_TLV_DATA:
1398                         pieces->data = tlv_data;
1399                         pieces->data_size = tlv_len;
1400                         break;
1401                 case IWL_UCODE_TLV_INIT:
1402                         pieces->init = tlv_data;
1403                         pieces->init_size = tlv_len;
1404                         break;
1405                 case IWL_UCODE_TLV_INIT_DATA:
1406                         pieces->init_data = tlv_data;
1407                         pieces->init_data_size = tlv_len;
1408                         break;
1409                 case IWL_UCODE_TLV_BOOT:
1410                         IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1411                         break;
1412                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1413                         if (tlv_len != sizeof(u32))
1414                                 goto invalid_tlv_len;
1415                         capa->max_probe_length =
1416                                         le32_to_cpup((__le32 *)tlv_data);
1417                         break;
1418                 case IWL_UCODE_TLV_PAN:
1419                         if (tlv_len)
1420                                 goto invalid_tlv_len;
1421                         capa->pan = true;
1422                         break;
1423                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1424                         if (tlv_len != sizeof(u32))
1425                                 goto invalid_tlv_len;
1426                         pieces->init_evtlog_ptr =
1427                                         le32_to_cpup((__le32 *)tlv_data);
1428                         break;
1429                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1430                         if (tlv_len != sizeof(u32))
1431                                 goto invalid_tlv_len;
1432                         pieces->init_evtlog_size =
1433                                         le32_to_cpup((__le32 *)tlv_data);
1434                         break;
1435                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1436                         if (tlv_len != sizeof(u32))
1437                                 goto invalid_tlv_len;
1438                         pieces->init_errlog_ptr =
1439                                         le32_to_cpup((__le32 *)tlv_data);
1440                         break;
1441                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1442                         if (tlv_len != sizeof(u32))
1443                                 goto invalid_tlv_len;
1444                         pieces->inst_evtlog_ptr =
1445                                         le32_to_cpup((__le32 *)tlv_data);
1446                         break;
1447                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1448                         if (tlv_len != sizeof(u32))
1449                                 goto invalid_tlv_len;
1450                         pieces->inst_evtlog_size =
1451                                         le32_to_cpup((__le32 *)tlv_data);
1452                         break;
1453                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1454                         if (tlv_len != sizeof(u32))
1455                                 goto invalid_tlv_len;
1456                         pieces->inst_errlog_ptr =
1457                                         le32_to_cpup((__le32 *)tlv_data);
1458                         break;
1459                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1460                         if (tlv_len)
1461                                 goto invalid_tlv_len;
1462                         priv->enhance_sensitivity_table = true;
1463                         break;
1464                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1465                         if (tlv_len != sizeof(u32))
1466                                 goto invalid_tlv_len;
1467                         capa->standard_phy_calibration_size =
1468                                         le32_to_cpup((__le32 *)tlv_data);
1469                         break;
1470                 default:
1471                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1472                         break;
1473                 }
1474         }
1475
1476         if (len) {
1477                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1478                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1479                 return -EINVAL;
1480         }
1481
1482         return 0;
1483
1484  invalid_tlv_len:
1485         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1486         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1487
1488         return -EINVAL;
1489 }
1490
1491 /**
1492  * iwl_ucode_callback - callback when firmware was loaded
1493  *
1494  * If loaded successfully, copies the firmware into buffers
1495  * for the card to fetch (via DMA).
1496  */
1497 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1498 {
1499         struct iwl_priv *priv = context;
1500         struct iwl_ucode_header *ucode;
1501         int err;
1502         struct iwlagn_firmware_pieces pieces;
1503         const unsigned int api_max = priv->cfg->ucode_api_max;
1504         const unsigned int api_min = priv->cfg->ucode_api_min;
1505         u32 api_ver;
1506         char buildstr[25];
1507         u32 build;
1508         struct iwlagn_ucode_capabilities ucode_capa = {
1509                 .max_probe_length = 200,
1510                 .standard_phy_calibration_size =
1511                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1512         };
1513
1514         memset(&pieces, 0, sizeof(pieces));
1515
1516         if (!ucode_raw) {
1517                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1518                         IWL_ERR(priv,
1519                                 "request for firmware file '%s' failed.\n",
1520                                 priv->firmware_name);
1521                 goto try_again;
1522         }
1523
1524         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1525                        priv->firmware_name, ucode_raw->size);
1526
1527         /* Make sure that we got at least the API version number */
1528         if (ucode_raw->size < 4) {
1529                 IWL_ERR(priv, "File size way too small!\n");
1530                 goto try_again;
1531         }
1532
1533         /* Data from ucode file:  header followed by uCode images */
1534         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1535
1536         if (ucode->ver)
1537                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1538         else
1539                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1540                                            &ucode_capa);
1541
1542         if (err)
1543                 goto try_again;
1544
1545         api_ver = IWL_UCODE_API(priv->ucode_ver);
1546         build = pieces.build;
1547
1548         /*
1549          * api_ver should match the api version forming part of the
1550          * firmware filename ... but we don't check for that and only rely
1551          * on the API version read from firmware header from here on forward
1552          */
1553         /* no api version check required for experimental uCode */
1554         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1555                 if (api_ver < api_min || api_ver > api_max) {
1556                         IWL_ERR(priv,
1557                                 "Driver unable to support your firmware API. "
1558                                 "Driver supports v%u, firmware is v%u.\n",
1559                                 api_max, api_ver);
1560                         goto try_again;
1561                 }
1562
1563                 if (api_ver != api_max)
1564                         IWL_ERR(priv,
1565                                 "Firmware has old API version. Expected v%u, "
1566                                 "got v%u. New firmware can be obtained "
1567                                 "from http://www.intellinuxwireless.org.\n",
1568                                 api_max, api_ver);
1569         }
1570
1571         if (build)
1572                 sprintf(buildstr, " build %u%s", build,
1573                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1574                                 ? " (EXP)" : "");
1575         else
1576                 buildstr[0] = '\0';
1577
1578         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1579                  IWL_UCODE_MAJOR(priv->ucode_ver),
1580                  IWL_UCODE_MINOR(priv->ucode_ver),
1581                  IWL_UCODE_API(priv->ucode_ver),
1582                  IWL_UCODE_SERIAL(priv->ucode_ver),
1583                  buildstr);
1584
1585         snprintf(priv->hw->wiphy->fw_version,
1586                  sizeof(priv->hw->wiphy->fw_version),
1587                  "%u.%u.%u.%u%s",
1588                  IWL_UCODE_MAJOR(priv->ucode_ver),
1589                  IWL_UCODE_MINOR(priv->ucode_ver),
1590                  IWL_UCODE_API(priv->ucode_ver),
1591                  IWL_UCODE_SERIAL(priv->ucode_ver),
1592                  buildstr);
1593
1594         /*
1595          * For any of the failures below (before allocating pci memory)
1596          * we will try to load a version with a smaller API -- maybe the
1597          * user just got a corrupted version of the latest API.
1598          */
1599
1600         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1601                        priv->ucode_ver);
1602         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1603                        pieces.inst_size);
1604         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1605                        pieces.data_size);
1606         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1607                        pieces.init_size);
1608         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1609                        pieces.init_data_size);
1610
1611         /* Verify that uCode images will fit in card's SRAM */
1612         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1613                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1614                         pieces.inst_size);
1615                 goto try_again;
1616         }
1617
1618         if (pieces.data_size > priv->hw_params.max_data_size) {
1619                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1620                         pieces.data_size);
1621                 goto try_again;
1622         }
1623
1624         if (pieces.init_size > priv->hw_params.max_inst_size) {
1625                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1626                         pieces.init_size);
1627                 goto try_again;
1628         }
1629
1630         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1631                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1632                         pieces.init_data_size);
1633                 goto try_again;
1634         }
1635
1636         /* Allocate ucode buffers for card's bus-master loading ... */
1637
1638         /* Runtime instructions and 2 copies of data:
1639          * 1) unmodified from disk
1640          * 2) backup cache for save/restore during power-downs */
1641         priv->ucode_code.len = pieces.inst_size;
1642         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1643
1644         priv->ucode_data.len = pieces.data_size;
1645         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1646
1647         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1648                 goto err_pci_alloc;
1649
1650         /* Initialization instructions and data */
1651         if (pieces.init_size && pieces.init_data_size) {
1652                 priv->ucode_init.len = pieces.init_size;
1653                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1654
1655                 priv->ucode_init_data.len = pieces.init_data_size;
1656                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1657
1658                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1659                         goto err_pci_alloc;
1660         }
1661
1662         /* Now that we can no longer fail, copy information */
1663
1664         /*
1665          * The (size - 16) / 12 formula is based on the information recorded
1666          * for each event, which is of mode 1 (including timestamp) for all
1667          * new microcodes that include this information.
1668          */
1669         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1670         if (pieces.init_evtlog_size)
1671                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1672         else
1673                 priv->_agn.init_evtlog_size =
1674                         priv->cfg->base_params->max_event_log_size;
1675         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1676         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1677         if (pieces.inst_evtlog_size)
1678                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1679         else
1680                 priv->_agn.inst_evtlog_size =
1681                         priv->cfg->base_params->max_event_log_size;
1682         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1683
1684         if (ucode_capa.pan) {
1685                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1686                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1687         } else
1688                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1689
1690         /* Copy images into buffers for card's bus-master reads ... */
1691
1692         /* Runtime instructions (first block of data in file) */
1693         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1694                         pieces.inst_size);
1695         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1696
1697         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1698                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1699
1700         /*
1701          * Runtime data
1702          * NOTE:  Copy into backup buffer will be done in iwl_up()
1703          */
1704         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1705                         pieces.data_size);
1706         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1707
1708         /* Initialization instructions */
1709         if (pieces.init_size) {
1710                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1711                                 pieces.init_size);
1712                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1713         }
1714
1715         /* Initialization data */
1716         if (pieces.init_data_size) {
1717                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1718                                pieces.init_data_size);
1719                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1720                        pieces.init_data_size);
1721         }
1722
1723         /*
1724          * figure out the offset of chain noise reset and gain commands
1725          * base on the size of standard phy calibration commands table size
1726          */
1727         if (ucode_capa.standard_phy_calibration_size >
1728             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1729                 ucode_capa.standard_phy_calibration_size =
1730                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1731
1732         priv->_agn.phy_calib_chain_noise_reset_cmd =
1733                 ucode_capa.standard_phy_calibration_size;
1734         priv->_agn.phy_calib_chain_noise_gain_cmd =
1735                 ucode_capa.standard_phy_calibration_size + 1;
1736
1737         /**************************************************
1738          * This is still part of probe() in a sense...
1739          *
1740          * 9. Setup and register with mac80211 and debugfs
1741          **************************************************/
1742         err = iwl_mac_setup_register(priv, &ucode_capa);
1743         if (err)
1744                 goto out_unbind;
1745
1746         err = iwl_dbgfs_register(priv, DRV_NAME);
1747         if (err)
1748                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1749
1750         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1751                                         &iwl_attribute_group);
1752         if (err) {
1753                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1754                 goto out_unbind;
1755         }
1756
1757         /* We have our copies now, allow OS release its copies */
1758         release_firmware(ucode_raw);
1759         complete(&priv->_agn.firmware_loading_complete);
1760         return;
1761
1762  try_again:
1763         /* try next, if any */
1764         if (iwl_request_firmware(priv, false))
1765                 goto out_unbind;
1766         release_firmware(ucode_raw);
1767         return;
1768
1769  err_pci_alloc:
1770         IWL_ERR(priv, "failed to allocate pci memory\n");
1771         iwl_dealloc_ucode_pci(priv);
1772  out_unbind:
1773         complete(&priv->_agn.firmware_loading_complete);
1774         device_release_driver(&priv->pci_dev->dev);
1775         release_firmware(ucode_raw);
1776 }
1777
1778 static const char *desc_lookup_text[] = {
1779         "OK",
1780         "FAIL",
1781         "BAD_PARAM",
1782         "BAD_CHECKSUM",
1783         "NMI_INTERRUPT_WDG",
1784         "SYSASSERT",
1785         "FATAL_ERROR",
1786         "BAD_COMMAND",
1787         "HW_ERROR_TUNE_LOCK",
1788         "HW_ERROR_TEMPERATURE",
1789         "ILLEGAL_CHAN_FREQ",
1790         "VCC_NOT_STABLE",
1791         "FH_ERROR",
1792         "NMI_INTERRUPT_HOST",
1793         "NMI_INTERRUPT_ACTION_PT",
1794         "NMI_INTERRUPT_UNKNOWN",
1795         "UCODE_VERSION_MISMATCH",
1796         "HW_ERROR_ABS_LOCK",
1797         "HW_ERROR_CAL_LOCK_FAIL",
1798         "NMI_INTERRUPT_INST_ACTION_PT",
1799         "NMI_INTERRUPT_DATA_ACTION_PT",
1800         "NMI_TRM_HW_ER",
1801         "NMI_INTERRUPT_TRM",
1802         "NMI_INTERRUPT_BREAK_POINT"
1803         "DEBUG_0",
1804         "DEBUG_1",
1805         "DEBUG_2",
1806         "DEBUG_3",
1807 };
1808
1809 static struct { char *name; u8 num; } advanced_lookup[] = {
1810         { "NMI_INTERRUPT_WDG", 0x34 },
1811         { "SYSASSERT", 0x35 },
1812         { "UCODE_VERSION_MISMATCH", 0x37 },
1813         { "BAD_COMMAND", 0x38 },
1814         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1815         { "FATAL_ERROR", 0x3D },
1816         { "NMI_TRM_HW_ERR", 0x46 },
1817         { "NMI_INTERRUPT_TRM", 0x4C },
1818         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1819         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1820         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1821         { "NMI_INTERRUPT_HOST", 0x66 },
1822         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1823         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1824         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1825         { "ADVANCED_SYSASSERT", 0 },
1826 };
1827
1828 static const char *desc_lookup(u32 num)
1829 {
1830         int i;
1831         int max = ARRAY_SIZE(desc_lookup_text);
1832
1833         if (num < max)
1834                 return desc_lookup_text[num];
1835
1836         max = ARRAY_SIZE(advanced_lookup) - 1;
1837         for (i = 0; i < max; i++) {
1838                 if (advanced_lookup[i].num == num)
1839                         break;;
1840         }
1841         return advanced_lookup[i].name;
1842 }
1843
1844 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1845 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1846
1847 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1848 {
1849         u32 data2, line;
1850         u32 desc, time, count, base, data1;
1851         u32 blink1, blink2, ilink1, ilink2;
1852         u32 pc, hcmd;
1853
1854         if (priv->ucode_type == UCODE_INIT) {
1855                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1856                 if (!base)
1857                         base = priv->_agn.init_errlog_ptr;
1858         } else {
1859                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1860                 if (!base)
1861                         base = priv->_agn.inst_errlog_ptr;
1862         }
1863
1864         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1865                 IWL_ERR(priv,
1866                         "Not valid error log pointer 0x%08X for %s uCode\n",
1867                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1868                 return;
1869         }
1870
1871         count = iwl_read_targ_mem(priv, base);
1872
1873         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1874                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1875                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1876                         priv->status, count);
1877         }
1878
1879         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1880         priv->isr_stats.err_code = desc;
1881         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1882         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1883         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1884         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1885         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1886         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1887         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1888         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1889         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1890         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1891
1892         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1893                                       blink1, blink2, ilink1, ilink2);
1894
1895         IWL_ERR(priv, "Desc                                  Time       "
1896                 "data1      data2      line\n");
1897         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1898                 desc_lookup(desc), desc, time, data1, data2, line);
1899         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1900         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1901                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1902 }
1903
1904 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1905
1906 /**
1907  * iwl_print_event_log - Dump error event log to syslog
1908  *
1909  */
1910 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1911                                u32 num_events, u32 mode,
1912                                int pos, char **buf, size_t bufsz)
1913 {
1914         u32 i;
1915         u32 base;       /* SRAM byte address of event log header */
1916         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1917         u32 ptr;        /* SRAM byte address of log data */
1918         u32 ev, time, data; /* event log data */
1919         unsigned long reg_flags;
1920
1921         if (num_events == 0)
1922                 return pos;
1923
1924         if (priv->ucode_type == UCODE_INIT) {
1925                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1926                 if (!base)
1927                         base = priv->_agn.init_evtlog_ptr;
1928         } else {
1929                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1930                 if (!base)
1931                         base = priv->_agn.inst_evtlog_ptr;
1932         }
1933
1934         if (mode == 0)
1935                 event_size = 2 * sizeof(u32);
1936         else
1937                 event_size = 3 * sizeof(u32);
1938
1939         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1940
1941         /* Make sure device is powered up for SRAM reads */
1942         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1943         iwl_grab_nic_access(priv);
1944
1945         /* Set starting address; reads will auto-increment */
1946         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1947         rmb();
1948
1949         /* "time" is actually "data" for mode 0 (no timestamp).
1950         * place event id # at far right for easier visual parsing. */
1951         for (i = 0; i < num_events; i++) {
1952                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1953                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1954                 if (mode == 0) {
1955                         /* data, ev */
1956                         if (bufsz) {
1957                                 pos += scnprintf(*buf + pos, bufsz - pos,
1958                                                 "EVT_LOG:0x%08x:%04u\n",
1959                                                 time, ev);
1960                         } else {
1961                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1962                                         time, ev);
1963                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1964                                         time, ev);
1965                         }
1966                 } else {
1967                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1968                         if (bufsz) {
1969                                 pos += scnprintf(*buf + pos, bufsz - pos,
1970                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
1971                                                  time, data, ev);
1972                         } else {
1973                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1974                                         time, data, ev);
1975                                 trace_iwlwifi_dev_ucode_event(priv, time,
1976                                         data, ev);
1977                         }
1978                 }
1979         }
1980
1981         /* Allow device to power down */
1982         iwl_release_nic_access(priv);
1983         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1984         return pos;
1985 }
1986
1987 /**
1988  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1989  */
1990 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1991                                     u32 num_wraps, u32 next_entry,
1992                                     u32 size, u32 mode,
1993                                     int pos, char **buf, size_t bufsz)
1994 {
1995         /*
1996          * display the newest DEFAULT_LOG_ENTRIES entries
1997          * i.e the entries just before the next ont that uCode would fill.
1998          */
1999         if (num_wraps) {
2000                 if (next_entry < size) {
2001                         pos = iwl_print_event_log(priv,
2002                                                 capacity - (size - next_entry),
2003                                                 size - next_entry, mode,
2004                                                 pos, buf, bufsz);
2005                         pos = iwl_print_event_log(priv, 0,
2006                                                   next_entry, mode,
2007                                                   pos, buf, bufsz);
2008                 } else
2009                         pos = iwl_print_event_log(priv, next_entry - size,
2010                                                   size, mode, pos, buf, bufsz);
2011         } else {
2012                 if (next_entry < size) {
2013                         pos = iwl_print_event_log(priv, 0, next_entry,
2014                                                   mode, pos, buf, bufsz);
2015                 } else {
2016                         pos = iwl_print_event_log(priv, next_entry - size,
2017                                                   size, mode, pos, buf, bufsz);
2018                 }
2019         }
2020         return pos;
2021 }
2022
2023 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2024
2025 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2026                             char **buf, bool display)
2027 {
2028         u32 base;       /* SRAM byte address of event log header */
2029         u32 capacity;   /* event log capacity in # entries */
2030         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2031         u32 num_wraps;  /* # times uCode wrapped to top of log */
2032         u32 next_entry; /* index of next entry to be written by uCode */
2033         u32 size;       /* # entries that we'll print */
2034         u32 logsize;
2035         int pos = 0;
2036         size_t bufsz = 0;
2037
2038         if (priv->ucode_type == UCODE_INIT) {
2039                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2040                 logsize = priv->_agn.init_evtlog_size;
2041                 if (!base)
2042                         base = priv->_agn.init_evtlog_ptr;
2043         } else {
2044                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2045                 logsize = priv->_agn.inst_evtlog_size;
2046                 if (!base)
2047                         base = priv->_agn.inst_evtlog_ptr;
2048         }
2049
2050         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2051                 IWL_ERR(priv,
2052                         "Invalid event log pointer 0x%08X for %s uCode\n",
2053                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2054                 return -EINVAL;
2055         }
2056
2057         /* event log header */
2058         capacity = iwl_read_targ_mem(priv, base);
2059         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2060         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2061         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2062
2063         if (capacity > logsize) {
2064                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2065                         capacity, logsize);
2066                 capacity = logsize;
2067         }
2068
2069         if (next_entry > logsize) {
2070                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2071                         next_entry, logsize);
2072                 next_entry = logsize;
2073         }
2074
2075         size = num_wraps ? capacity : next_entry;
2076
2077         /* bail out if nothing in log */
2078         if (size == 0) {
2079                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2080                 return pos;
2081         }
2082
2083         /* enable/disable bt channel inhibition */
2084         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2085
2086 #ifdef CONFIG_IWLWIFI_DEBUG
2087         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2088                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2089                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2090 #else
2091         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2092                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2093 #endif
2094         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2095                 size);
2096
2097 #ifdef CONFIG_IWLWIFI_DEBUG
2098         if (display) {
2099                 if (full_log)
2100                         bufsz = capacity * 48;
2101                 else
2102                         bufsz = size * 48;
2103                 *buf = kmalloc(bufsz, GFP_KERNEL);
2104                 if (!*buf)
2105                         return -ENOMEM;
2106         }
2107         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2108                 /*
2109                  * if uCode has wrapped back to top of log,
2110                  * start at the oldest entry,
2111                  * i.e the next one that uCode would fill.
2112                  */
2113                 if (num_wraps)
2114                         pos = iwl_print_event_log(priv, next_entry,
2115                                                 capacity - next_entry, mode,
2116                                                 pos, buf, bufsz);
2117                 /* (then/else) start at top of log */
2118                 pos = iwl_print_event_log(priv, 0,
2119                                           next_entry, mode, pos, buf, bufsz);
2120         } else
2121                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2122                                                 next_entry, size, mode,
2123                                                 pos, buf, bufsz);
2124 #else
2125         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2126                                         next_entry, size, mode,
2127                                         pos, buf, bufsz);
2128 #endif
2129         return pos;
2130 }
2131
2132 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2133 {
2134         struct iwl_ct_kill_config cmd;
2135         struct iwl_ct_kill_throttling_config adv_cmd;
2136         unsigned long flags;
2137         int ret = 0;
2138
2139         spin_lock_irqsave(&priv->lock, flags);
2140         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2141                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2142         spin_unlock_irqrestore(&priv->lock, flags);
2143         priv->thermal_throttle.ct_kill_toggle = false;
2144
2145         if (priv->cfg->base_params->support_ct_kill_exit) {
2146                 adv_cmd.critical_temperature_enter =
2147                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2148                 adv_cmd.critical_temperature_exit =
2149                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2150
2151                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2152                                        sizeof(adv_cmd), &adv_cmd);
2153                 if (ret)
2154                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2155                 else
2156                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2157                                         "succeeded, "
2158                                         "critical temperature enter is %d,"
2159                                         "exit is %d\n",
2160                                        priv->hw_params.ct_kill_threshold,
2161                                        priv->hw_params.ct_kill_exit_threshold);
2162         } else {
2163                 cmd.critical_temperature_R =
2164                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2165
2166                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2167                                        sizeof(cmd), &cmd);
2168                 if (ret)
2169                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2170                 else
2171                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2172                                         "succeeded, "
2173                                         "critical temperature is %d\n",
2174                                         priv->hw_params.ct_kill_threshold);
2175         }
2176 }
2177
2178 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2179 {
2180         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2181         struct iwl_host_cmd cmd = {
2182                 .id = CALIBRATION_CFG_CMD,
2183                 .len = sizeof(struct iwl_calib_cfg_cmd),
2184                 .data = &calib_cfg_cmd,
2185         };
2186
2187         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2188         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2189         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2190
2191         return iwl_send_cmd(priv, &cmd);
2192 }
2193
2194
2195 /**
2196  * iwl_alive_start - called after REPLY_ALIVE notification received
2197  *                   from protocol/runtime uCode (initialization uCode's
2198  *                   Alive gets handled by iwl_init_alive_start()).
2199  */
2200 static void iwl_alive_start(struct iwl_priv *priv)
2201 {
2202         int ret = 0;
2203         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2204
2205         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2206
2207         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2208          * This is a paranoid check, because we would not have gotten the
2209          * "runtime" alive if code weren't properly loaded.  */
2210         if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2211                 /* Runtime instruction load was bad;
2212                  * take it all the way back down so we can try again */
2213                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2214                 goto restart;
2215         }
2216
2217         ret = iwlagn_alive_notify(priv);
2218         if (ret) {
2219                 IWL_WARN(priv,
2220                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2221                 goto restart;
2222         }
2223
2224
2225         /* After the ALIVE response, we can send host commands to the uCode */
2226         set_bit(STATUS_ALIVE, &priv->status);
2227
2228         /* Enable watchdog to monitor the driver tx queues */
2229         iwl_setup_watchdog(priv);
2230
2231         if (iwl_is_rfkill(priv))
2232                 return;
2233
2234         /* download priority table before any calibration request */
2235         if (priv->cfg->bt_params &&
2236             priv->cfg->bt_params->advanced_bt_coexist) {
2237                 /* Configure Bluetooth device coexistence support */
2238                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2239                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2240                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2241                 priv->cfg->ops->hcmd->send_bt_config(priv);
2242                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2243                 iwlagn_send_prio_tbl(priv);
2244
2245                 /* FIXME: w/a to force change uCode BT state machine */
2246                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2247                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2248                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2249                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2250         }
2251         if (priv->hw_params.calib_rt_cfg)
2252                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2253
2254         ieee80211_wake_queues(priv->hw);
2255
2256         priv->active_rate = IWL_RATES_MASK;
2257
2258         /* Configure Tx antenna selection based on H/W config */
2259         if (priv->cfg->ops->hcmd->set_tx_ant)
2260                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2261
2262         if (iwl_is_associated_ctx(ctx)) {
2263                 struct iwl_rxon_cmd *active_rxon =
2264                                 (struct iwl_rxon_cmd *)&ctx->active;
2265                 /* apply any changes in staging */
2266                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2267                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2268         } else {
2269                 struct iwl_rxon_context *tmp;
2270                 /* Initialize our rx_config data */
2271                 for_each_context(priv, tmp)
2272                         iwl_connection_init_rx_config(priv, tmp);
2273
2274                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2275                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2276         }
2277
2278         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2279             !priv->cfg->bt_params->advanced_bt_coexist)) {
2280                 /*
2281                  * default is 2-wire BT coexexistence support
2282                  */
2283                 priv->cfg->ops->hcmd->send_bt_config(priv);
2284         }
2285
2286         iwl_reset_run_time_calib(priv);
2287
2288         set_bit(STATUS_READY, &priv->status);
2289
2290         /* Configure the adapter for unassociated operation */
2291         iwlcore_commit_rxon(priv, ctx);
2292
2293         /* At this point, the NIC is initialized and operational */
2294         iwl_rf_kill_ct_config(priv);
2295
2296         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2297         wake_up_interruptible(&priv->wait_command_queue);
2298
2299         iwl_power_update_mode(priv, true);
2300         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2301
2302
2303         return;
2304
2305  restart:
2306         queue_work(priv->workqueue, &priv->restart);
2307 }
2308
2309 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2310
2311 static void __iwl_down(struct iwl_priv *priv)
2312 {
2313         unsigned long flags;
2314         int exit_pending;
2315
2316         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2317
2318         iwl_scan_cancel_timeout(priv, 200);
2319
2320         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2321
2322         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2323          * to prevent rearm timer */
2324         del_timer_sync(&priv->watchdog);
2325
2326         iwl_clear_ucode_stations(priv, NULL);
2327         iwl_dealloc_bcast_stations(priv);
2328         iwl_clear_driver_stations(priv);
2329
2330         /* reset BT coex data */
2331         priv->bt_status = 0;
2332         if (priv->cfg->bt_params)
2333                 priv->bt_traffic_load =
2334                          priv->cfg->bt_params->bt_init_traffic_load;
2335         else
2336                 priv->bt_traffic_load = 0;
2337         priv->bt_full_concurrent = false;
2338         priv->bt_ci_compliance = 0;
2339
2340         /* Wipe out the EXIT_PENDING status bit if we are not actually
2341          * exiting the module */
2342         if (!exit_pending)
2343                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2344
2345         /* stop and reset the on-board processor */
2346         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2347
2348         /* tell the device to stop sending interrupts */
2349         spin_lock_irqsave(&priv->lock, flags);
2350         iwl_disable_interrupts(priv);
2351         spin_unlock_irqrestore(&priv->lock, flags);
2352         iwl_synchronize_irq(priv);
2353
2354         if (priv->mac80211_registered)
2355                 ieee80211_stop_queues(priv->hw);
2356
2357         /* If we have not previously called iwl_init() then
2358          * clear all bits but the RF Kill bit and return */
2359         if (!iwl_is_init(priv)) {
2360                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2361                                         STATUS_RF_KILL_HW |
2362                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2363                                         STATUS_GEO_CONFIGURED |
2364                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2365                                         STATUS_EXIT_PENDING;
2366                 goto exit;
2367         }
2368
2369         /* ...otherwise clear out all the status bits but the RF Kill
2370          * bit and continue taking the NIC down. */
2371         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2372                                 STATUS_RF_KILL_HW |
2373                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2374                                 STATUS_GEO_CONFIGURED |
2375                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2376                                 STATUS_FW_ERROR |
2377                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2378                                 STATUS_EXIT_PENDING;
2379
2380         /* device going down, Stop using ICT table */
2381         if (priv->cfg->ops->lib->isr_ops.disable)
2382                 priv->cfg->ops->lib->isr_ops.disable(priv);
2383
2384         iwlagn_txq_ctx_stop(priv);
2385         iwlagn_rxq_stop(priv);
2386
2387         /* Power-down device's busmaster DMA clocks */
2388         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2389         udelay(5);
2390
2391         /* Make sure (redundant) we've released our request to stay awake */
2392         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2393
2394         /* Stop the device, and put it in low power state */
2395         iwl_apm_stop(priv);
2396
2397  exit:
2398         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2399
2400         dev_kfree_skb(priv->beacon_skb);
2401         priv->beacon_skb = NULL;
2402
2403         /* clear out any free frames */
2404         iwl_clear_free_frames(priv);
2405 }
2406
2407 static void iwl_down(struct iwl_priv *priv)
2408 {
2409         mutex_lock(&priv->mutex);
2410         __iwl_down(priv);
2411         mutex_unlock(&priv->mutex);
2412
2413         iwl_cancel_deferred_work(priv);
2414 }
2415
2416 #define HW_READY_TIMEOUT (50)
2417
2418 static int iwl_set_hw_ready(struct iwl_priv *priv)
2419 {
2420         int ret = 0;
2421
2422         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2423                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2424
2425         /* See if we got it */
2426         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2427                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2428                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2429                                 HW_READY_TIMEOUT);
2430         if (ret != -ETIMEDOUT)
2431                 priv->hw_ready = true;
2432         else
2433                 priv->hw_ready = false;
2434
2435         IWL_DEBUG_INFO(priv, "hardware %s\n",
2436                       (priv->hw_ready == 1) ? "ready" : "not ready");
2437         return ret;
2438 }
2439
2440 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2441 {
2442         int ret = 0;
2443
2444         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2445
2446         ret = iwl_set_hw_ready(priv);
2447         if (priv->hw_ready)
2448                 return ret;
2449
2450         /* If HW is not ready, prepare the conditions to check again */
2451         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2452                         CSR_HW_IF_CONFIG_REG_PREPARE);
2453
2454         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2455                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2456                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2457
2458         /* HW should be ready by now, check again. */
2459         if (ret != -ETIMEDOUT)
2460                 iwl_set_hw_ready(priv);
2461
2462         return ret;
2463 }
2464
2465 #define MAX_HW_RESTARTS 5
2466
2467 static int __iwl_up(struct iwl_priv *priv)
2468 {
2469         struct iwl_rxon_context *ctx;
2470         int i;
2471         int ret;
2472
2473         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2474                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2475                 return -EIO;
2476         }
2477
2478         for_each_context(priv, ctx) {
2479                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2480                 if (ret) {
2481                         iwl_dealloc_bcast_stations(priv);
2482                         return ret;
2483                 }
2484         }
2485
2486         iwl_prepare_card_hw(priv);
2487
2488         if (!priv->hw_ready) {
2489                 IWL_WARN(priv, "Exit HW not ready\n");
2490                 return -EIO;
2491         }
2492
2493         /* If platform's RF_KILL switch is NOT set to KILL */
2494         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2495                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2496         else
2497                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2498
2499         if (iwl_is_rfkill(priv)) {
2500                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2501
2502                 iwl_enable_interrupts(priv);
2503                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2504                 return 0;
2505         }
2506
2507         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2508
2509         /* must be initialised before iwl_hw_nic_init */
2510         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2511                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2512         else
2513                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2514
2515         ret = iwlagn_hw_nic_init(priv);
2516         if (ret) {
2517                 IWL_ERR(priv, "Unable to init nic\n");
2518                 return ret;
2519         }
2520
2521         /* make sure rfkill handshake bits are cleared */
2522         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2523         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2524                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2525
2526         /* clear (again), then enable host interrupts */
2527         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2528         iwl_enable_interrupts(priv);
2529
2530         /* really make sure rfkill handshake bits are cleared */
2531         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2532         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2533
2534         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2535
2536                 /* load bootstrap state machine,
2537                  * load bootstrap program into processor's memory,
2538                  * prepare to load the "initialize" uCode */
2539                 ret = iwlagn_load_ucode(priv);
2540
2541                 if (ret) {
2542                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2543                                 ret);
2544                         continue;
2545                 }
2546
2547                 /* start card; "initialize" will load runtime ucode */
2548                 iwl_nic_start(priv);
2549
2550                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2551
2552                 return 0;
2553         }
2554
2555         set_bit(STATUS_EXIT_PENDING, &priv->status);
2556         __iwl_down(priv);
2557         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2558
2559         /* tried to restart and config the device for as long as our
2560          * patience could withstand */
2561         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2562         return -EIO;
2563 }
2564
2565
2566 /*****************************************************************************
2567  *
2568  * Workqueue callbacks
2569  *
2570  *****************************************************************************/
2571
2572 static void iwl_bg_init_alive_start(struct work_struct *data)
2573 {
2574         struct iwl_priv *priv =
2575             container_of(data, struct iwl_priv, init_alive_start.work);
2576
2577         mutex_lock(&priv->mutex);
2578
2579         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2580                 mutex_unlock(&priv->mutex);
2581                 return;
2582         }
2583
2584         iwlagn_init_alive_start(priv);
2585         mutex_unlock(&priv->mutex);
2586 }
2587
2588 static void iwl_bg_alive_start(struct work_struct *data)
2589 {
2590         struct iwl_priv *priv =
2591             container_of(data, struct iwl_priv, alive_start.work);
2592
2593         mutex_lock(&priv->mutex);
2594         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2595                 goto unlock;
2596
2597         /* enable dram interrupt */
2598         if (priv->cfg->ops->lib->isr_ops.reset)
2599                 priv->cfg->ops->lib->isr_ops.reset(priv);
2600
2601         iwl_alive_start(priv);
2602 unlock:
2603         mutex_unlock(&priv->mutex);
2604 }
2605
2606 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2607 {
2608         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2609                         run_time_calib_work);
2610
2611         mutex_lock(&priv->mutex);
2612
2613         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2614             test_bit(STATUS_SCANNING, &priv->status)) {
2615                 mutex_unlock(&priv->mutex);
2616                 return;
2617         }
2618
2619         if (priv->start_calib) {
2620                 if (iwl_bt_statistics(priv)) {
2621                         iwl_chain_noise_calibration(priv,
2622                                         (void *)&priv->_agn.statistics_bt);
2623                         iwl_sensitivity_calibration(priv,
2624                                         (void *)&priv->_agn.statistics_bt);
2625                 } else {
2626                         iwl_chain_noise_calibration(priv,
2627                                         (void *)&priv->_agn.statistics);
2628                         iwl_sensitivity_calibration(priv,
2629                                         (void *)&priv->_agn.statistics);
2630                 }
2631         }
2632
2633         mutex_unlock(&priv->mutex);
2634 }
2635
2636 static void iwl_bg_restart(struct work_struct *data)
2637 {
2638         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2639
2640         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2641                 return;
2642
2643         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2644                 struct iwl_rxon_context *ctx;
2645                 bool bt_full_concurrent;
2646                 u8 bt_ci_compliance;
2647                 u8 bt_load;
2648                 u8 bt_status;
2649
2650                 mutex_lock(&priv->mutex);
2651                 for_each_context(priv, ctx)
2652                         ctx->vif = NULL;
2653                 priv->is_open = 0;
2654
2655                 /*
2656                  * __iwl_down() will clear the BT status variables,
2657                  * which is correct, but when we restart we really
2658                  * want to keep them so restore them afterwards.
2659                  *
2660                  * The restart process will later pick them up and
2661                  * re-configure the hw when we reconfigure the BT
2662                  * command.
2663                  */
2664                 bt_full_concurrent = priv->bt_full_concurrent;
2665                 bt_ci_compliance = priv->bt_ci_compliance;
2666                 bt_load = priv->bt_traffic_load;
2667                 bt_status = priv->bt_status;
2668
2669                 __iwl_down(priv);
2670
2671                 priv->bt_full_concurrent = bt_full_concurrent;
2672                 priv->bt_ci_compliance = bt_ci_compliance;
2673                 priv->bt_traffic_load = bt_load;
2674                 priv->bt_status = bt_status;
2675
2676                 mutex_unlock(&priv->mutex);
2677                 iwl_cancel_deferred_work(priv);
2678                 ieee80211_restart_hw(priv->hw);
2679         } else {
2680                 iwl_down(priv);
2681
2682                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2683                         return;
2684
2685                 mutex_lock(&priv->mutex);
2686                 __iwl_up(priv);
2687                 mutex_unlock(&priv->mutex);
2688         }
2689 }
2690
2691 static void iwl_bg_rx_replenish(struct work_struct *data)
2692 {
2693         struct iwl_priv *priv =
2694             container_of(data, struct iwl_priv, rx_replenish);
2695
2696         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2697                 return;
2698
2699         mutex_lock(&priv->mutex);
2700         iwlagn_rx_replenish(priv);
2701         mutex_unlock(&priv->mutex);
2702 }
2703
2704 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2705                                  struct ieee80211_channel *chan,
2706                                  enum nl80211_channel_type channel_type,
2707                                  unsigned int wait)
2708 {
2709         struct iwl_priv *priv = hw->priv;
2710         int ret;
2711
2712         /* Not supported if we don't have PAN */
2713         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2714                 ret = -EOPNOTSUPP;
2715                 goto free;
2716         }
2717
2718         /* Not supported on pre-P2P firmware */
2719         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2720                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2721                 ret = -EOPNOTSUPP;
2722                 goto free;
2723         }
2724
2725         mutex_lock(&priv->mutex);
2726
2727         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2728                 /*
2729                  * If the PAN context is free, use the normal
2730                  * way of doing remain-on-channel offload + TX.
2731                  */
2732                 ret = 1;
2733                 goto out;
2734         }
2735
2736         /* TODO: queue up if scanning? */
2737         if (test_bit(STATUS_SCANNING, &priv->status) ||
2738             priv->_agn.offchan_tx_skb) {
2739                 ret = -EBUSY;
2740                 goto out;
2741         }
2742
2743         /*
2744          * max_scan_ie_len doesn't include the blank SSID or the header,
2745          * so need to add that again here.
2746          */
2747         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2748                 ret = -ENOBUFS;
2749                 goto out;
2750         }
2751
2752         priv->_agn.offchan_tx_skb = skb;
2753         priv->_agn.offchan_tx_timeout = wait;
2754         priv->_agn.offchan_tx_chan = chan;
2755
2756         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2757                                 IWL_SCAN_OFFCH_TX, chan->band);
2758         if (ret)
2759                 priv->_agn.offchan_tx_skb = NULL;
2760  out:
2761         mutex_unlock(&priv->mutex);
2762  free:
2763         if (ret < 0)
2764                 kfree_skb(skb);
2765
2766         return ret;
2767 }
2768
2769 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2770 {
2771         struct iwl_priv *priv = hw->priv;
2772         int ret;
2773
2774         mutex_lock(&priv->mutex);
2775
2776         if (!priv->_agn.offchan_tx_skb) {
2777                 ret = -EINVAL;
2778                 goto unlock;
2779         }
2780
2781         priv->_agn.offchan_tx_skb = NULL;
2782
2783         ret = iwl_scan_cancel_timeout(priv, 200);
2784         if (ret)
2785                 ret = -EIO;
2786 unlock:
2787         mutex_unlock(&priv->mutex);
2788
2789         return ret;
2790 }
2791
2792 /*****************************************************************************
2793  *
2794  * mac80211 entry point functions
2795  *
2796  *****************************************************************************/
2797
2798 #define UCODE_READY_TIMEOUT     (4 * HZ)
2799
2800 /*
2801  * Not a mac80211 entry point function, but it fits in with all the
2802  * other mac80211 functions grouped here.
2803  */
2804 static int iwl_mac_setup_register(struct iwl_priv *priv,
2805                                   struct iwlagn_ucode_capabilities *capa)
2806 {
2807         int ret;
2808         struct ieee80211_hw *hw = priv->hw;
2809         struct iwl_rxon_context *ctx;
2810
2811         hw->rate_control_algorithm = "iwl-agn-rs";
2812
2813         /* Tell mac80211 our characteristics */
2814         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2815                     IEEE80211_HW_AMPDU_AGGREGATION |
2816                     IEEE80211_HW_NEED_DTIM_PERIOD |
2817                     IEEE80211_HW_SPECTRUM_MGMT |
2818                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2819
2820         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2821
2822         if (!priv->cfg->base_params->broken_powersave)
2823                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2824                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2825
2826         if (priv->cfg->sku & IWL_SKU_N)
2827                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2828                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2829
2830         hw->sta_data_size = sizeof(struct iwl_station_priv);
2831         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2832
2833         for_each_context(priv, ctx) {
2834                 hw->wiphy->interface_modes |= ctx->interface_modes;
2835                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2836         }
2837
2838         hw->wiphy->max_remain_on_channel_duration = 1000;
2839
2840         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2841                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2842                             WIPHY_FLAG_IBSS_RSN;
2843
2844         /*
2845          * For now, disable PS by default because it affects
2846          * RX performance significantly.
2847          */
2848         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2849
2850         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2851         /* we create the 802.11 header and a zero-length SSID element */
2852         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2853
2854         /* Default value; 4 EDCA QOS priorities */
2855         hw->queues = 4;
2856
2857         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2858
2859         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2860                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2861                         &priv->bands[IEEE80211_BAND_2GHZ];
2862         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2863                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2864                         &priv->bands[IEEE80211_BAND_5GHZ];
2865
2866         iwl_leds_init(priv);
2867
2868         ret = ieee80211_register_hw(priv->hw);
2869         if (ret) {
2870                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2871                 return ret;
2872         }
2873         priv->mac80211_registered = 1;
2874
2875         return 0;
2876 }
2877
2878
2879 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2880 {
2881         struct iwl_priv *priv = hw->priv;
2882         int ret;
2883
2884         IWL_DEBUG_MAC80211(priv, "enter\n");
2885
2886         /* we should be verifying the device is ready to be opened */
2887         mutex_lock(&priv->mutex);
2888         ret = __iwl_up(priv);
2889         mutex_unlock(&priv->mutex);
2890
2891         if (ret)
2892                 return ret;
2893
2894         if (iwl_is_rfkill(priv))
2895                 goto out;
2896
2897         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2898
2899         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2900          * mac80211 will not be run successfully. */
2901         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2902                         test_bit(STATUS_READY, &priv->status),
2903                         UCODE_READY_TIMEOUT);
2904         if (!ret) {
2905                 if (!test_bit(STATUS_READY, &priv->status)) {
2906                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2907                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2908                         return -ETIMEDOUT;
2909                 }
2910         }
2911
2912         iwlagn_led_enable(priv);
2913
2914 out:
2915         priv->is_open = 1;
2916         IWL_DEBUG_MAC80211(priv, "leave\n");
2917         return 0;
2918 }
2919
2920 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2921 {
2922         struct iwl_priv *priv = hw->priv;
2923
2924         IWL_DEBUG_MAC80211(priv, "enter\n");
2925
2926         if (!priv->is_open)
2927                 return;
2928
2929         priv->is_open = 0;
2930
2931         iwl_down(priv);
2932
2933         flush_workqueue(priv->workqueue);
2934
2935         /* User space software may expect getting rfkill changes
2936          * even if interface is down */
2937         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2938         iwl_enable_rfkill_int(priv);
2939
2940         IWL_DEBUG_MAC80211(priv, "leave\n");
2941 }
2942
2943 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2944 {
2945         struct iwl_priv *priv = hw->priv;
2946
2947         IWL_DEBUG_MACDUMP(priv, "enter\n");
2948
2949         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2950                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2951
2952         if (iwlagn_tx_skb(priv, skb))
2953                 dev_kfree_skb_any(skb);
2954
2955         IWL_DEBUG_MACDUMP(priv, "leave\n");
2956 }
2957
2958 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2959                                        struct ieee80211_vif *vif,
2960                                        struct ieee80211_key_conf *keyconf,
2961                                        struct ieee80211_sta *sta,
2962                                        u32 iv32, u16 *phase1key)
2963 {
2964         struct iwl_priv *priv = hw->priv;
2965         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2966
2967         IWL_DEBUG_MAC80211(priv, "enter\n");
2968
2969         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2970                             iv32, phase1key);
2971
2972         IWL_DEBUG_MAC80211(priv, "leave\n");
2973 }
2974
2975 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2976                               struct ieee80211_vif *vif,
2977                               struct ieee80211_sta *sta,
2978                               struct ieee80211_key_conf *key)
2979 {
2980         struct iwl_priv *priv = hw->priv;
2981         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2982         struct iwl_rxon_context *ctx = vif_priv->ctx;
2983         int ret;
2984         u8 sta_id;
2985         bool is_default_wep_key = false;
2986
2987         IWL_DEBUG_MAC80211(priv, "enter\n");
2988
2989         if (priv->cfg->mod_params->sw_crypto) {
2990                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2991                 return -EOPNOTSUPP;
2992         }
2993
2994         /*
2995          * To support IBSS RSN, don't program group keys in IBSS, the
2996          * hardware will then not attempt to decrypt the frames.
2997          */
2998         if (vif->type == NL80211_IFTYPE_ADHOC &&
2999             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3000                 return -EOPNOTSUPP;
3001
3002         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3003         if (sta_id == IWL_INVALID_STATION)
3004                 return -EINVAL;
3005
3006         mutex_lock(&priv->mutex);
3007         iwl_scan_cancel_timeout(priv, 100);
3008
3009         /*
3010          * If we are getting WEP group key and we didn't receive any key mapping
3011          * so far, we are in legacy wep mode (group key only), otherwise we are
3012          * in 1X mode.
3013          * In legacy wep mode, we use another host command to the uCode.
3014          */
3015         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3016              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3017             !sta) {
3018                 if (cmd == SET_KEY)
3019                         is_default_wep_key = !ctx->key_mapping_keys;
3020                 else
3021                         is_default_wep_key =
3022                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3023         }
3024
3025         switch (cmd) {
3026         case SET_KEY:
3027                 if (is_default_wep_key)
3028                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3029                 else
3030                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3031                                                   key, sta_id);
3032
3033                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3034                 break;
3035         case DISABLE_KEY:
3036                 if (is_default_wep_key)
3037                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3038                 else
3039                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3040
3041                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3042                 break;
3043         default:
3044                 ret = -EINVAL;
3045         }
3046
3047         mutex_unlock(&priv->mutex);
3048         IWL_DEBUG_MAC80211(priv, "leave\n");
3049
3050         return ret;
3051 }
3052
3053 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3054                                    struct ieee80211_vif *vif,
3055                                    enum ieee80211_ampdu_mlme_action action,
3056                                    struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3057                                    u8 buf_size)
3058 {
3059         struct iwl_priv *priv = hw->priv;
3060         int ret = -EINVAL;
3061         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3062
3063         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3064                      sta->addr, tid);
3065
3066         if (!(priv->cfg->sku & IWL_SKU_N))
3067                 return -EACCES;
3068
3069         mutex_lock(&priv->mutex);
3070
3071         switch (action) {
3072         case IEEE80211_AMPDU_RX_START:
3073                 IWL_DEBUG_HT(priv, "start Rx\n");
3074                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3075                 break;
3076         case IEEE80211_AMPDU_RX_STOP:
3077                 IWL_DEBUG_HT(priv, "stop Rx\n");
3078                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3079                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3080                         ret = 0;
3081                 break;
3082         case IEEE80211_AMPDU_TX_START:
3083                 IWL_DEBUG_HT(priv, "start Tx\n");
3084                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3085                 if (ret == 0) {
3086                         priv->_agn.agg_tids_count++;
3087                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3088                                      priv->_agn.agg_tids_count);
3089                 }
3090                 break;
3091         case IEEE80211_AMPDU_TX_STOP:
3092                 IWL_DEBUG_HT(priv, "stop Tx\n");
3093                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3094                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3095                         priv->_agn.agg_tids_count--;
3096                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3097                                      priv->_agn.agg_tids_count);
3098                 }
3099                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3100                         ret = 0;
3101                 if (priv->cfg->ht_params &&
3102                     priv->cfg->ht_params->use_rts_for_aggregation) {
3103                         struct iwl_station_priv *sta_priv =
3104                                 (void *) sta->drv_priv;
3105                         /*
3106                          * switch off RTS/CTS if it was previously enabled
3107                          */
3108
3109                         sta_priv->lq_sta.lq.general_params.flags &=
3110                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3111                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3112                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3113                 }
3114                 break;
3115         case IEEE80211_AMPDU_TX_OPERATIONAL:
3116                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3117
3118                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3119
3120                 /*
3121                  * If the limit is 0, then it wasn't initialised yet,
3122                  * use the default. We can do that since we take the
3123                  * minimum below, and we don't want to go above our
3124                  * default due to hardware restrictions.
3125                  */
3126                 if (sta_priv->max_agg_bufsize == 0)
3127                         sta_priv->max_agg_bufsize =
3128                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3129
3130                 /*
3131                  * Even though in theory the peer could have different
3132                  * aggregation reorder buffer sizes for different sessions,
3133                  * our ucode doesn't allow for that and has a global limit
3134                  * for each station. Therefore, use the minimum of all the
3135                  * aggregation sessions and our default value.
3136                  */
3137                 sta_priv->max_agg_bufsize =
3138                         min(sta_priv->max_agg_bufsize, buf_size);
3139
3140                 if (priv->cfg->ht_params &&
3141                     priv->cfg->ht_params->use_rts_for_aggregation) {
3142                         /*
3143                          * switch to RTS/CTS if it is the prefer protection
3144                          * method for HT traffic
3145                          */
3146
3147                         sta_priv->lq_sta.lq.general_params.flags |=
3148                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3149                 }
3150
3151                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3152                         sta_priv->max_agg_bufsize;
3153
3154                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3155                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3156                 ret = 0;
3157                 break;
3158         }
3159         mutex_unlock(&priv->mutex);
3160
3161         return ret;
3162 }
3163
3164 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3165                               struct ieee80211_vif *vif,
3166                               struct ieee80211_sta *sta)
3167 {
3168         struct iwl_priv *priv = hw->priv;
3169         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3170         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3171         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3172         int ret;
3173         u8 sta_id;
3174
3175         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3176                         sta->addr);
3177         mutex_lock(&priv->mutex);
3178         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3179                         sta->addr);
3180         sta_priv->common.sta_id = IWL_INVALID_STATION;
3181
3182         atomic_set(&sta_priv->pending_frames, 0);
3183         if (vif->type == NL80211_IFTYPE_AP)
3184                 sta_priv->client = true;
3185
3186         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3187                                      is_ap, sta, &sta_id);
3188         if (ret) {
3189                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3190                         sta->addr, ret);
3191                 /* Should we return success if return code is EEXIST ? */
3192                 mutex_unlock(&priv->mutex);
3193                 return ret;
3194         }
3195
3196         sta_priv->common.sta_id = sta_id;
3197
3198         /* Initialize rate scaling */
3199         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3200                        sta->addr);
3201         iwl_rs_rate_init(priv, sta, sta_id);
3202         mutex_unlock(&priv->mutex);
3203
3204         return 0;
3205 }
3206
3207 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3208                                 struct ieee80211_channel_switch *ch_switch)
3209 {
3210         struct iwl_priv *priv = hw->priv;
3211         const struct iwl_channel_info *ch_info;
3212         struct ieee80211_conf *conf = &hw->conf;
3213         struct ieee80211_channel *channel = ch_switch->channel;
3214         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3215         /*
3216          * MULTI-FIXME
3217          * When we add support for multiple interfaces, we need to
3218          * revisit this. The channel switch command in the device
3219          * only affects the BSS context, but what does that really
3220          * mean? And what if we get a CSA on the second interface?
3221          * This needs a lot of work.
3222          */
3223         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3224         u16 ch;
3225         unsigned long flags = 0;
3226
3227         IWL_DEBUG_MAC80211(priv, "enter\n");
3228
3229         mutex_lock(&priv->mutex);
3230
3231         if (iwl_is_rfkill(priv))
3232                 goto out;
3233
3234         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3235             test_bit(STATUS_SCANNING, &priv->status))
3236                 goto out;
3237
3238         if (!iwl_is_associated_ctx(ctx))
3239                 goto out;
3240
3241         /* channel switch in progress */
3242         if (priv->switch_rxon.switch_in_progress == true)
3243                 goto out;
3244
3245         if (priv->cfg->ops->lib->set_channel_switch) {
3246
3247                 ch = channel->hw_value;
3248                 if (le16_to_cpu(ctx->active.channel) != ch) {
3249                         ch_info = iwl_get_channel_info(priv,
3250                                                        channel->band,
3251                                                        ch);
3252                         if (!is_channel_valid(ch_info)) {
3253                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3254                                 goto out;
3255                         }
3256                         spin_lock_irqsave(&priv->lock, flags);
3257
3258                         priv->current_ht_config.smps = conf->smps_mode;
3259
3260                         /* Configure HT40 channels */
3261                         ctx->ht.enabled = conf_is_ht(conf);
3262                         if (ctx->ht.enabled) {
3263                                 if (conf_is_ht40_minus(conf)) {
3264                                         ctx->ht.extension_chan_offset =
3265                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3266                                         ctx->ht.is_40mhz = true;
3267                                 } else if (conf_is_ht40_plus(conf)) {
3268                                         ctx->ht.extension_chan_offset =
3269                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3270                                         ctx->ht.is_40mhz = true;
3271                                 } else {
3272                                         ctx->ht.extension_chan_offset =
3273                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3274                                         ctx->ht.is_40mhz = false;
3275                                 }
3276                         } else
3277                                 ctx->ht.is_40mhz = false;
3278
3279                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3280                                 ctx->staging.flags = 0;
3281
3282                         iwl_set_rxon_channel(priv, channel, ctx);
3283                         iwl_set_rxon_ht(priv, ht_conf);
3284                         iwl_set_flags_for_band(priv, ctx, channel->band,
3285                                                ctx->vif);
3286                         spin_unlock_irqrestore(&priv->lock, flags);
3287
3288                         iwl_set_rate(priv);
3289                         /*
3290                          * at this point, staging_rxon has the
3291                          * configuration for channel switch
3292                          */
3293                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3294                                                                     ch_switch))
3295                                 priv->switch_rxon.switch_in_progress = false;
3296                 }
3297         }
3298 out:
3299         mutex_unlock(&priv->mutex);
3300         if (!priv->switch_rxon.switch_in_progress)
3301                 ieee80211_chswitch_done(ctx->vif, false);
3302         IWL_DEBUG_MAC80211(priv, "leave\n");
3303 }
3304
3305 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3306                                     unsigned int changed_flags,
3307                                     unsigned int *total_flags,
3308                                     u64 multicast)
3309 {
3310         struct iwl_priv *priv = hw->priv;
3311         __le32 filter_or = 0, filter_nand = 0;
3312         struct iwl_rxon_context *ctx;
3313
3314 #define CHK(test, flag) do { \
3315         if (*total_flags & (test))              \
3316                 filter_or |= (flag);            \
3317         else                                    \
3318                 filter_nand |= (flag);          \
3319         } while (0)
3320
3321         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3322                         changed_flags, *total_flags);
3323
3324         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3325         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3326         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3327         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3328
3329 #undef CHK
3330
3331         mutex_lock(&priv->mutex);
3332
3333         for_each_context(priv, ctx) {
3334                 ctx->staging.filter_flags &= ~filter_nand;
3335                 ctx->staging.filter_flags |= filter_or;
3336
3337                 /*
3338                  * Not committing directly because hardware can perform a scan,
3339                  * but we'll eventually commit the filter flags change anyway.
3340                  */
3341         }
3342
3343         mutex_unlock(&priv->mutex);
3344
3345         /*
3346          * Receiving all multicast frames is always enabled by the
3347          * default flags setup in iwl_connection_init_rx_config()
3348          * since we currently do not support programming multicast
3349          * filters into the device.
3350          */
3351         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3352                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3353 }
3354
3355 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3356 {
3357         struct iwl_priv *priv = hw->priv;
3358
3359         mutex_lock(&priv->mutex);
3360         IWL_DEBUG_MAC80211(priv, "enter\n");
3361
3362         /* do not support "flush" */
3363         if (!priv->cfg->ops->lib->txfifo_flush)
3364                 goto done;
3365
3366         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3367                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3368                 goto done;
3369         }
3370         if (iwl_is_rfkill(priv)) {
3371                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3372                 goto done;
3373         }
3374
3375         /*
3376          * mac80211 will not push any more frames for transmit
3377          * until the flush is completed
3378          */
3379         if (drop) {
3380                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3381                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3382                         IWL_ERR(priv, "flush request fail\n");
3383                         goto done;
3384                 }
3385         }
3386         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3387         iwlagn_wait_tx_queue_empty(priv);
3388 done:
3389         mutex_unlock(&priv->mutex);
3390         IWL_DEBUG_MAC80211(priv, "leave\n");
3391 }
3392
3393 static void iwlagn_disable_roc(struct iwl_priv *priv)
3394 {
3395         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3396         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3397
3398         lockdep_assert_held(&priv->mutex);
3399
3400         if (!ctx->is_active)
3401                 return;
3402
3403         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3404         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3405         iwl_set_rxon_channel(priv, chan, ctx);
3406         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3407
3408         priv->_agn.hw_roc_channel = NULL;
3409
3410         iwlcore_commit_rxon(priv, ctx);
3411
3412         ctx->is_active = false;
3413 }
3414
3415 static void iwlagn_bg_roc_done(struct work_struct *work)
3416 {
3417         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3418                                              _agn.hw_roc_work.work);
3419
3420         mutex_lock(&priv->mutex);
3421         ieee80211_remain_on_channel_expired(priv->hw);
3422         iwlagn_disable_roc(priv);
3423         mutex_unlock(&priv->mutex);
3424 }
3425
3426 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3427                                      struct ieee80211_channel *channel,
3428                                      enum nl80211_channel_type channel_type,
3429                                      int duration)
3430 {
3431         struct iwl_priv *priv = hw->priv;
3432         int err = 0;
3433
3434         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3435                 return -EOPNOTSUPP;
3436
3437         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3438                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3439                 return -EOPNOTSUPP;
3440
3441         mutex_lock(&priv->mutex);
3442
3443         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3444             test_bit(STATUS_SCAN_HW, &priv->status)) {
3445                 err = -EBUSY;
3446                 goto out;
3447         }
3448
3449         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3450         priv->_agn.hw_roc_channel = channel;
3451         priv->_agn.hw_roc_chantype = channel_type;
3452         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3453         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3454         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3455                            msecs_to_jiffies(duration + 20));
3456
3457         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3458         ieee80211_ready_on_channel(priv->hw);
3459
3460  out:
3461         mutex_unlock(&priv->mutex);
3462
3463         return err;
3464 }
3465
3466 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3467 {
3468         struct iwl_priv *priv = hw->priv;
3469
3470         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3471                 return -EOPNOTSUPP;
3472
3473         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3474
3475         mutex_lock(&priv->mutex);
3476         iwlagn_disable_roc(priv);
3477         mutex_unlock(&priv->mutex);
3478
3479         return 0;
3480 }
3481
3482 /*****************************************************************************
3483  *
3484  * driver setup and teardown
3485  *
3486  *****************************************************************************/
3487
3488 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3489 {
3490         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3491
3492         init_waitqueue_head(&priv->wait_command_queue);
3493
3494         INIT_WORK(&priv->restart, iwl_bg_restart);
3495         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3496         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3497         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3498         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3499         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3500         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3501         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3502         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3503         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3504
3505         iwl_setup_scan_deferred_work(priv);
3506
3507         if (priv->cfg->ops->lib->setup_deferred_work)
3508                 priv->cfg->ops->lib->setup_deferred_work(priv);
3509
3510         init_timer(&priv->statistics_periodic);
3511         priv->statistics_periodic.data = (unsigned long)priv;
3512         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3513
3514         init_timer(&priv->ucode_trace);
3515         priv->ucode_trace.data = (unsigned long)priv;
3516         priv->ucode_trace.function = iwl_bg_ucode_trace;
3517
3518         init_timer(&priv->watchdog);
3519         priv->watchdog.data = (unsigned long)priv;
3520         priv->watchdog.function = iwl_bg_watchdog;
3521
3522         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3523                 iwl_irq_tasklet, (unsigned long)priv);
3524 }
3525
3526 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3527 {
3528         if (priv->cfg->ops->lib->cancel_deferred_work)
3529                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3530
3531         cancel_delayed_work_sync(&priv->init_alive_start);
3532         cancel_delayed_work(&priv->alive_start);
3533         cancel_work_sync(&priv->run_time_calib_work);
3534         cancel_work_sync(&priv->beacon_update);
3535
3536         iwl_cancel_scan_deferred_work(priv);
3537
3538         cancel_work_sync(&priv->bt_full_concurrency);
3539         cancel_work_sync(&priv->bt_runtime_config);
3540
3541         del_timer_sync(&priv->statistics_periodic);
3542         del_timer_sync(&priv->ucode_trace);
3543 }
3544
3545 static void iwl_init_hw_rates(struct iwl_priv *priv,
3546                               struct ieee80211_rate *rates)
3547 {
3548         int i;
3549
3550         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3551                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3552                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3553                 rates[i].hw_value_short = i;
3554                 rates[i].flags = 0;
3555                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3556                         /*
3557                          * If CCK != 1M then set short preamble rate flag.
3558                          */
3559                         rates[i].flags |=
3560                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3561                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3562                 }
3563         }
3564 }
3565
3566 static int iwl_init_drv(struct iwl_priv *priv)
3567 {
3568         int ret;
3569
3570         spin_lock_init(&priv->sta_lock);
3571         spin_lock_init(&priv->hcmd_lock);
3572
3573         INIT_LIST_HEAD(&priv->free_frames);
3574
3575         mutex_init(&priv->mutex);
3576
3577         priv->ieee_channels = NULL;
3578         priv->ieee_rates = NULL;
3579         priv->band = IEEE80211_BAND_2GHZ;
3580
3581         priv->iw_mode = NL80211_IFTYPE_STATION;
3582         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3583         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3584         priv->_agn.agg_tids_count = 0;
3585
3586         /* initialize force reset */
3587         priv->force_reset[IWL_RF_RESET].reset_duration =
3588                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3589         priv->force_reset[IWL_FW_RESET].reset_duration =
3590                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3591
3592         priv->rx_statistics_jiffies = jiffies;
3593
3594         /* Choose which receivers/antennas to use */
3595         if (priv->cfg->ops->hcmd->set_rxon_chain)
3596                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3597                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3598
3599         iwl_init_scan_params(priv);
3600
3601         /* init bt coex */
3602         if (priv->cfg->bt_params &&
3603             priv->cfg->bt_params->advanced_bt_coexist) {
3604                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3605                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3606                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3607                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3608                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3609                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3610         }
3611
3612         /* Set the tx_power_user_lmt to the lowest power level
3613          * this value will get overwritten by channel max power avg
3614          * from eeprom */
3615         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3616         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3617
3618         ret = iwl_init_channel_map(priv);
3619         if (ret) {
3620                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3621                 goto err;
3622         }
3623
3624         ret = iwlcore_init_geos(priv);
3625         if (ret) {
3626                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3627                 goto err_free_channel_map;
3628         }
3629         iwl_init_hw_rates(priv, priv->ieee_rates);
3630
3631         return 0;
3632
3633 err_free_channel_map:
3634         iwl_free_channel_map(priv);
3635 err:
3636         return ret;
3637 }
3638
3639 static void iwl_uninit_drv(struct iwl_priv *priv)
3640 {
3641         iwl_calib_free_results(priv);
3642         iwlcore_free_geos(priv);
3643         iwl_free_channel_map(priv);
3644         kfree(priv->scan_cmd);
3645 }
3646
3647 struct ieee80211_ops iwlagn_hw_ops = {
3648         .tx = iwlagn_mac_tx,
3649         .start = iwlagn_mac_start,
3650         .stop = iwlagn_mac_stop,
3651         .add_interface = iwl_mac_add_interface,
3652         .remove_interface = iwl_mac_remove_interface,
3653         .change_interface = iwl_mac_change_interface,
3654         .config = iwlagn_mac_config,
3655         .configure_filter = iwlagn_configure_filter,
3656         .set_key = iwlagn_mac_set_key,
3657         .update_tkip_key = iwlagn_mac_update_tkip_key,
3658         .conf_tx = iwl_mac_conf_tx,
3659         .bss_info_changed = iwlagn_bss_info_changed,
3660         .ampdu_action = iwlagn_mac_ampdu_action,
3661         .hw_scan = iwl_mac_hw_scan,
3662         .sta_notify = iwlagn_mac_sta_notify,
3663         .sta_add = iwlagn_mac_sta_add,
3664         .sta_remove = iwl_mac_sta_remove,
3665         .channel_switch = iwlagn_mac_channel_switch,
3666         .flush = iwlagn_mac_flush,
3667         .tx_last_beacon = iwl_mac_tx_last_beacon,
3668         .remain_on_channel = iwl_mac_remain_on_channel,
3669         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3670         .offchannel_tx = iwl_mac_offchannel_tx,
3671         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3672 };
3673
3674 static void iwl_hw_detect(struct iwl_priv *priv)
3675 {
3676         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3677         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3678         priv->rev_id = priv->pci_dev->revision;
3679         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3680 }
3681
3682 static int iwl_set_hw_params(struct iwl_priv *priv)
3683 {
3684         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3685         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3686         if (priv->cfg->mod_params->amsdu_size_8K)
3687                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3688         else
3689                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3690
3691         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3692
3693         if (priv->cfg->mod_params->disable_11n)
3694                 priv->cfg->sku &= ~IWL_SKU_N;
3695
3696         /* Device-specific setup */
3697         return priv->cfg->ops->lib->set_hw_params(priv);
3698 }
3699
3700 static const u8 iwlagn_bss_ac_to_fifo[] = {
3701         IWL_TX_FIFO_VO,
3702         IWL_TX_FIFO_VI,
3703         IWL_TX_FIFO_BE,
3704         IWL_TX_FIFO_BK,
3705 };
3706
3707 static const u8 iwlagn_bss_ac_to_queue[] = {
3708         0, 1, 2, 3,
3709 };
3710
3711 static const u8 iwlagn_pan_ac_to_fifo[] = {
3712         IWL_TX_FIFO_VO_IPAN,
3713         IWL_TX_FIFO_VI_IPAN,
3714         IWL_TX_FIFO_BE_IPAN,
3715         IWL_TX_FIFO_BK_IPAN,
3716 };
3717
3718 static const u8 iwlagn_pan_ac_to_queue[] = {
3719         7, 6, 5, 4,
3720 };
3721
3722 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3723 {
3724         int err = 0, i;
3725         struct iwl_priv *priv;
3726         struct ieee80211_hw *hw;
3727         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3728         unsigned long flags;
3729         u16 pci_cmd, num_mac;
3730
3731         /************************
3732          * 1. Allocating HW data
3733          ************************/
3734
3735         hw = iwl_alloc_all(cfg);
3736         if (!hw) {
3737                 err = -ENOMEM;
3738                 goto out;
3739         }
3740         priv = hw->priv;
3741         /* At this point both hw and priv are allocated. */
3742
3743         /*
3744          * The default context is always valid,
3745          * more may be discovered when firmware
3746          * is loaded.
3747          */
3748         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3749
3750         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3751                 priv->contexts[i].ctxid = i;
3752
3753         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3754         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3755         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3756         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3757         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3758         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3759         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3760         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3761         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3762         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3763         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3764                 BIT(NL80211_IFTYPE_ADHOC);
3765         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3766                 BIT(NL80211_IFTYPE_STATION);
3767         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3768         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3769         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3770         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3771
3772         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3773         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3774         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3775         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3776         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3777         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3778         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3779         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3780         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3781         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3782         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3783         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3784                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3785 #ifdef CONFIG_IWL_P2P
3786         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3787                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3788 #endif
3789         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3790         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3791         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3792
3793         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3794
3795         SET_IEEE80211_DEV(hw, &pdev->dev);
3796
3797         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3798         priv->cfg = cfg;
3799         priv->pci_dev = pdev;
3800         priv->inta_mask = CSR_INI_SET_MASK;
3801
3802         /* is antenna coupling more than 35dB ? */
3803         priv->bt_ant_couple_ok =
3804                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3805                 true : false;
3806
3807         /* enable/disable bt channel inhibition */
3808         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3809         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3810                        (priv->bt_ch_announce) ? "On" : "Off");
3811
3812         if (iwl_alloc_traffic_mem(priv))
3813                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3814
3815         /**************************
3816          * 2. Initializing PCI bus
3817          **************************/
3818         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3819                                 PCIE_LINK_STATE_CLKPM);
3820
3821         if (pci_enable_device(pdev)) {
3822                 err = -ENODEV;
3823                 goto out_ieee80211_free_hw;
3824         }
3825
3826         pci_set_master(pdev);
3827
3828         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3829         if (!err)
3830                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3831         if (err) {
3832                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3833                 if (!err)
3834                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3835                 /* both attempts failed: */
3836                 if (err) {
3837                         IWL_WARN(priv, "No suitable DMA available.\n");
3838                         goto out_pci_disable_device;
3839                 }
3840         }
3841
3842         err = pci_request_regions(pdev, DRV_NAME);
3843         if (err)
3844                 goto out_pci_disable_device;
3845
3846         pci_set_drvdata(pdev, priv);
3847
3848
3849         /***********************
3850          * 3. Read REV register
3851          ***********************/
3852         priv->hw_base = pci_iomap(pdev, 0, 0);
3853         if (!priv->hw_base) {
3854                 err = -ENODEV;
3855                 goto out_pci_release_regions;
3856         }
3857
3858         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3859                 (unsigned long long) pci_resource_len(pdev, 0));
3860         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3861
3862         /* these spin locks will be used in apm_ops.init and EEPROM access
3863          * we should init now
3864          */
3865         spin_lock_init(&priv->reg_lock);
3866         spin_lock_init(&priv->lock);
3867
3868         /*
3869          * stop and reset the on-board processor just in case it is in a
3870          * strange state ... like being left stranded by a primary kernel
3871          * and this is now the kdump kernel trying to start up
3872          */
3873         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3874
3875         iwl_hw_detect(priv);
3876         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3877                 priv->cfg->name, priv->hw_rev);
3878
3879         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3880          * PCI Tx retries from interfering with C3 CPU state */
3881         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3882
3883         iwl_prepare_card_hw(priv);
3884         if (!priv->hw_ready) {
3885                 IWL_WARN(priv, "Failed, HW not ready\n");
3886                 goto out_iounmap;
3887         }
3888
3889         /*****************
3890          * 4. Read EEPROM
3891          *****************/
3892         /* Read the EEPROM */
3893         err = iwl_eeprom_init(priv);
3894         if (err) {
3895                 IWL_ERR(priv, "Unable to init EEPROM\n");
3896                 goto out_iounmap;
3897         }
3898         err = iwl_eeprom_check_version(priv);
3899         if (err)
3900                 goto out_free_eeprom;
3901
3902         err = iwl_eeprom_check_sku(priv);
3903         if (err)
3904                 goto out_free_eeprom;
3905
3906         /* extract MAC Address */
3907         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3908         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3909         priv->hw->wiphy->addresses = priv->addresses;
3910         priv->hw->wiphy->n_addresses = 1;
3911         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3912         if (num_mac > 1) {
3913                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3914                        ETH_ALEN);
3915                 priv->addresses[1].addr[5]++;
3916                 priv->hw->wiphy->n_addresses++;
3917         }
3918
3919         /************************
3920          * 5. Setup HW constants
3921          ************************/
3922         if (iwl_set_hw_params(priv)) {
3923                 IWL_ERR(priv, "failed to set hw parameters\n");
3924                 goto out_free_eeprom;
3925         }
3926
3927         /*******************
3928          * 6. Setup priv
3929          *******************/
3930
3931         err = iwl_init_drv(priv);
3932         if (err)
3933                 goto out_free_eeprom;
3934         /* At this point both hw and priv are initialized. */
3935
3936         /********************
3937          * 7. Setup services
3938          ********************/
3939         spin_lock_irqsave(&priv->lock, flags);
3940         iwl_disable_interrupts(priv);
3941         spin_unlock_irqrestore(&priv->lock, flags);
3942
3943         pci_enable_msi(priv->pci_dev);
3944
3945         if (priv->cfg->ops->lib->isr_ops.alloc)
3946                 priv->cfg->ops->lib->isr_ops.alloc(priv);
3947
3948         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
3949                           IRQF_SHARED, DRV_NAME, priv);
3950         if (err) {
3951                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3952                 goto out_disable_msi;
3953         }
3954
3955         iwl_setup_deferred_work(priv);
3956         iwl_setup_rx_handlers(priv);
3957
3958         /*********************************************
3959          * 8. Enable interrupts and read RFKILL state
3960          *********************************************/
3961
3962         /* enable rfkill interrupt: hw bug w/a */
3963         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3964         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3965                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3966                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3967         }
3968
3969         iwl_enable_rfkill_int(priv);
3970
3971         /* If platform's RF_KILL switch is NOT set to KILL */
3972         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3973                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3974         else
3975                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3976
3977         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3978                 test_bit(STATUS_RF_KILL_HW, &priv->status));
3979
3980         iwl_power_initialize(priv);
3981         iwl_tt_initialize(priv);
3982
3983         init_completion(&priv->_agn.firmware_loading_complete);
3984
3985         err = iwl_request_firmware(priv, true);
3986         if (err)
3987                 goto out_destroy_workqueue;
3988
3989         return 0;
3990
3991  out_destroy_workqueue:
3992         destroy_workqueue(priv->workqueue);
3993         priv->workqueue = NULL;
3994         free_irq(priv->pci_dev->irq, priv);
3995         if (priv->cfg->ops->lib->isr_ops.free)
3996                 priv->cfg->ops->lib->isr_ops.free(priv);
3997  out_disable_msi:
3998         pci_disable_msi(priv->pci_dev);
3999         iwl_uninit_drv(priv);
4000  out_free_eeprom:
4001         iwl_eeprom_free(priv);
4002  out_iounmap:
4003         pci_iounmap(pdev, priv->hw_base);
4004  out_pci_release_regions:
4005         pci_set_drvdata(pdev, NULL);
4006         pci_release_regions(pdev);
4007  out_pci_disable_device:
4008         pci_disable_device(pdev);
4009  out_ieee80211_free_hw:
4010         iwl_free_traffic_mem(priv);
4011         ieee80211_free_hw(priv->hw);
4012  out:
4013         return err;
4014 }
4015
4016 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4017 {
4018         struct iwl_priv *priv = pci_get_drvdata(pdev);
4019         unsigned long flags;
4020
4021         if (!priv)
4022                 return;
4023
4024         wait_for_completion(&priv->_agn.firmware_loading_complete);
4025
4026         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4027
4028         iwl_dbgfs_unregister(priv);
4029         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4030
4031         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4032          * to be called and iwl_down since we are removing the device
4033          * we need to set STATUS_EXIT_PENDING bit.
4034          */
4035         set_bit(STATUS_EXIT_PENDING, &priv->status);
4036
4037         iwl_leds_exit(priv);
4038
4039         if (priv->mac80211_registered) {
4040                 ieee80211_unregister_hw(priv->hw);
4041                 priv->mac80211_registered = 0;
4042         } else {
4043                 iwl_down(priv);
4044         }
4045
4046         /*
4047          * Make sure device is reset to low power before unloading driver.
4048          * This may be redundant with iwl_down(), but there are paths to
4049          * run iwl_down() without calling apm_ops.stop(), and there are
4050          * paths to avoid running iwl_down() at all before leaving driver.
4051          * This (inexpensive) call *makes sure* device is reset.
4052          */
4053         iwl_apm_stop(priv);
4054
4055         iwl_tt_exit(priv);
4056
4057         /* make sure we flush any pending irq or
4058          * tasklet for the driver
4059          */
4060         spin_lock_irqsave(&priv->lock, flags);
4061         iwl_disable_interrupts(priv);
4062         spin_unlock_irqrestore(&priv->lock, flags);
4063
4064         iwl_synchronize_irq(priv);
4065
4066         iwl_dealloc_ucode_pci(priv);
4067
4068         if (priv->rxq.bd)
4069                 iwlagn_rx_queue_free(priv, &priv->rxq);
4070         iwlagn_hw_txq_ctx_free(priv);
4071
4072         iwl_eeprom_free(priv);
4073
4074
4075         /*netif_stop_queue(dev); */
4076         flush_workqueue(priv->workqueue);
4077
4078         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4079          * priv->workqueue... so we can't take down the workqueue
4080          * until now... */
4081         destroy_workqueue(priv->workqueue);
4082         priv->workqueue = NULL;
4083         iwl_free_traffic_mem(priv);
4084
4085         free_irq(priv->pci_dev->irq, priv);
4086         pci_disable_msi(priv->pci_dev);
4087         pci_iounmap(pdev, priv->hw_base);
4088         pci_release_regions(pdev);
4089         pci_disable_device(pdev);
4090         pci_set_drvdata(pdev, NULL);
4091
4092         iwl_uninit_drv(priv);
4093
4094         if (priv->cfg->ops->lib->isr_ops.free)
4095                 priv->cfg->ops->lib->isr_ops.free(priv);
4096
4097         dev_kfree_skb(priv->beacon_skb);
4098
4099         ieee80211_free_hw(priv->hw);
4100 }
4101
4102
4103 /*****************************************************************************
4104  *
4105  * driver and module entry point
4106  *
4107  *****************************************************************************/
4108
4109 /* Hardware specific file defines the PCI IDs table for that hardware module */
4110 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4111         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4112         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4113         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4114         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4115         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4116         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4117         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4118         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4119         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4120         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4121         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4122         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4123         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4124         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4125         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4126         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4127         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4128         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4129         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4130         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4131         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4132         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4133         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4134         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4135
4136 /* 5300 Series WiFi */
4137         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4138         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4139         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4140         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4141         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4142         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4143         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4144         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4145         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4146         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4147         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4148         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4149
4150 /* 5350 Series WiFi/WiMax */
4151         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4152         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4153         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4154
4155 /* 5150 Series Wifi/WiMax */
4156         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4157         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4158         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4159         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4160         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4161         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4162
4163         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4164         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4165         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4166         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4167
4168 /* 6x00 Series */
4169         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4170         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4171         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4172         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4173         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4174         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4175         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4176         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4177         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4178         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4179
4180 /* 6x05 Series */
4181         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4182         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4183         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4184         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4185         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4186         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4187         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4188
4189 /* 6x30 Series */
4190         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4191         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4192         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4193         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4194         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4195         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4196         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4197         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4198         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4199         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4200         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4201         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4202         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4203         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4204         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4205         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4206
4207 /* 6x50 WiFi/WiMax Series */
4208         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4209         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4210         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4211         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4212         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4213         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4214
4215 /* 6150 WiFi/WiMax Series */
4216         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4217         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4218         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4219         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4220         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4221         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4222
4223 /* 1000 Series WiFi */
4224         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4225         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4226         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4227         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4228         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4229         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4230         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4231         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4232         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4233         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4234         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4235         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4236
4237 /* 100 Series WiFi */
4238         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4239         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4240         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4241         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4242         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4243         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4244
4245 /* 130 Series WiFi */
4246         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4247         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4248         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4249         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4250         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4251         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4252
4253 /* 2x00 Series */
4254         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4255         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4256         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4257         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4258         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4259         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4260
4261 /* 2x30 Series */
4262         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4263         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4264         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4265         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4266         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4267         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4268
4269 /* 6x35 Series */
4270         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4271         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4272         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4273         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4274         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4275         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4276         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4277         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4278         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4279
4280 /* 200 Series */
4281         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4282         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4283         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4284         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4285         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4286         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4287
4288 /* 230 Series */
4289         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4290         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4291         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4292         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4293         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4294         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4295
4296         {0}
4297 };
4298 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4299
4300 static struct pci_driver iwl_driver = {
4301         .name = DRV_NAME,
4302         .id_table = iwl_hw_card_ids,
4303         .probe = iwl_pci_probe,
4304         .remove = __devexit_p(iwl_pci_remove),
4305         .driver.pm = IWL_PM_OPS,
4306 };
4307
4308 static int __init iwl_init(void)
4309 {
4310
4311         int ret;
4312         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4313         pr_info(DRV_COPYRIGHT "\n");
4314
4315         ret = iwlagn_rate_control_register();
4316         if (ret) {
4317                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4318                 return ret;
4319         }
4320
4321         ret = pci_register_driver(&iwl_driver);
4322         if (ret) {
4323                 pr_err("Unable to initialize PCI module\n");
4324                 goto error_register;
4325         }
4326
4327         return ret;
4328
4329 error_register:
4330         iwlagn_rate_control_unregister();
4331         return ret;
4332 }
4333
4334 static void __exit iwl_exit(void)
4335 {
4336         pci_unregister_driver(&iwl_driver);
4337         iwlagn_rate_control_unregister();
4338 }
4339
4340 module_exit(iwl_exit);
4341 module_init(iwl_init);
4342
4343 #ifdef CONFIG_IWLWIFI_DEBUG
4344 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4345 MODULE_PARM_DESC(debug, "debug output mask");
4346 #endif
4347
4348 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4349 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4350 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4351 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4352 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4353 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4354 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4355                    int, S_IRUGO);
4356 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4357 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4358 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4359
4360 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4361                    S_IRUGO);
4362 MODULE_PARM_DESC(ucode_alternative,
4363                  "specify ucode alternative to use from ucode file");
4364
4365 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4366 MODULE_PARM_DESC(antenna_coupling,
4367                  "specify antenna coupling in dB (defualt: 0 dB)");
4368
4369 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4370 MODULE_PARM_DESC(bt_ch_inhibition,
4371                  "Disable BT channel inhibition (default: enable)");
4372
4373 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4374 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4375
4376 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4377 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");