drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89 MODULE_ALIAS("iwl4965");
  90
  91 static int iwlagn_ant_coupling;
  92 static bool iwlagn_bt_ch_announce = 1;
  93
  94 void iwl_update_chain_flags(struct iwl_priv *priv)
  95 {
  96         struct iwl_rxon_context *ctx;
  97
  98         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  99                 for_each_context(priv, ctx) {
 100                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 101                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 102                                 iwlcore_commit_rxon(priv, ctx);
 103                 }
 104         }
 105 }
 106
 107 static void iwl_clear_free_frames(struct iwl_priv *priv)
 108 {
 109         struct list_head *element;
 110
 111         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 112                        priv->frames_count);
 113
 114         while (!list_empty(&priv->free_frames)) {
 115                 element = priv->free_frames.next;
 116                 list_del(element);
 117                 kfree(list_entry(element, struct iwl_frame, list));
 118                 priv->frames_count--;
 119         }
 120
 121         if (priv->frames_count) {
 122                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 123                             priv->frames_count);
 124                 priv->frames_count = 0;
 125         }
 126 }
 127
 128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 129 {
 130         struct iwl_frame *frame;
 131         struct list_head *element;
 132         if (list_empty(&priv->free_frames)) {
 133                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 134                 if (!frame) {
 135                         IWL_ERR(priv, "Could not allocate frame!\n");
 136                         return NULL;
 137                 }
 138
 139                 priv->frames_count++;
 140                 return frame;
 141         }
 142
 143         element = priv->free_frames.next;
 144         list_del(element);
 145         return list_entry(element, struct iwl_frame, list);
 146 }
 147
 148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 149 {
 150         memset(frame, 0, sizeof(*frame));
 151         list_add(&frame->list, &priv->free_frames);
 152 }
 153
 154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 155                                  struct ieee80211_hdr *hdr,
 156                                  int left)
 157 {
 158         lockdep_assert_held(&priv->mutex);
 159
 160         if (!priv->beacon_skb)
 161                 return 0;
 162
 163         if (priv->beacon_skb->len > left)
 164                 return 0;
 165
 166         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 167
 168         return priv->beacon_skb->len;
 169 }
 170
 171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 173                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 174                                u8 *beacon, u32 frame_size)
 175 {
 176         u16 tim_idx;
 177         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 178
 179         /*
 180          * The index is relative to frame start but we start looking at the
 181          * variable-length part of the beacon.
 182          */
 183         tim_idx = mgmt->u.beacon.variable - beacon;
 184
 185         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 186         while ((tim_idx < (frame_size - 2)) &&
 187                         (beacon[tim_idx] != WLAN_EID_TIM))
 188                 tim_idx += beacon[tim_idx+1] + 2;
 189
 190         /* If TIM field was found, set variables */
 191         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 192                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 193                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 194         } else
 195                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 196 }
 197
 198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 199                                        struct iwl_frame *frame)
 200 {
 201         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 202         u32 frame_size;
 203         u32 rate_flags;
 204         u32 rate;
 205         /*
 206          * We have to set up the TX command, the TX Beacon command, and the
 207          * beacon contents.
 208          */
 209
 210         lockdep_assert_held(&priv->mutex);
 211
 212         if (!priv->beacon_ctx) {
 213                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 214                 return 0;
 215         }
 216
 217         /* Initialize memory */
 218         tx_beacon_cmd = &frame->u.beacon;
 219         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 220
 221         /* Set up TX beacon contents */
 222         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 223                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 224         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 225                 return 0;
 226         if (!frame_size)
 227                 return 0;
 228
 229         /* Set up TX command fields */
 230         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 231         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 232         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 233         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 234                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 235
 236         /* Set up TX beacon command fields */
 237         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 238                            frame_size);
 239
 240         /* Set up packet rate and flags */
 241         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 242         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 243                                               priv->hw_params.valid_tx_ant);
 244         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 245         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 246                 rate_flags |= RATE_MCS_CCK_MSK;
 247         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 248                         rate_flags);
 249
 250         return sizeof(*tx_beacon_cmd) + frame_size;
 251 }
 252
 253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 254 {
 255         struct iwl_frame *frame;
 256         unsigned int frame_size;
 257         int rc;
 258
 259         frame = iwl_get_free_frame(priv);
 260         if (!frame) {
 261                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 262                           "command.\n");
 263                 return -ENOMEM;
 264         }
 265
 266         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 267         if (!frame_size) {
 268                 IWL_ERR(priv, "Error configuring the beacon command\n");
 269                 iwl_free_frame(priv, frame);
 270                 return -EINVAL;
 271         }
 272
 273         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 274                               &frame->u.cmd[0]);
 275
 276         iwl_free_frame(priv, frame);
 277
 278         return rc;
 279 }
 280
 281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 282 {
 283         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 284
 285         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 286         if (sizeof(dma_addr_t) > sizeof(u32))
 287                 addr |=
 288                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 289
 290         return addr;
 291 }
 292
 293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 294 {
 295         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 296
 297         return le16_to_cpu(tb->hi_n_len) >> 4;
 298 }
 299
 300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 301                                   dma_addr_t addr, u16 len)
 302 {
 303         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 304         u16 hi_n_len = len << 4;
 305
 306         put_unaligned_le32(addr, &tb->lo);
 307         if (sizeof(dma_addr_t) > sizeof(u32))
 308                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 309
 310         tb->hi_n_len = cpu_to_le16(hi_n_len);
 311
 312         tfd->num_tbs = idx + 1;
 313 }
 314
 315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 316 {
 317         return tfd->num_tbs & 0x1f;
 318 }
 319
 320 /**
 321  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 322  * @priv - driver private data
 323  * @txq - tx queue
 324  *
 325  * Does NOT advance any TFD circular buffer read/write indexes
 326  * Does NOT free the TFD itself (which is within circular buffer)
 327  */
 328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 329 {
 330         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 331         struct iwl_tfd *tfd;
 332         struct pci_dev *dev = priv->pci_dev;
 333         int index = txq->q.read_ptr;
 334         int i;
 335         int num_tbs;
 336
 337         tfd = &tfd_tmp[index];
 338
 339         /* Sanity check on number of chunks */
 340         num_tbs = iwl_tfd_get_num_tbs(tfd);
 341
 342         if (num_tbs >= IWL_NUM_OF_TBS) {
 343                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 344                 /* @todo issue fatal error, it is quite serious situation */
 345                 return;
 346         }
 347
 348         /* Unmap tx_cmd */
 349         if (num_tbs)
 350                 pci_unmap_single(dev,
 351                                 dma_unmap_addr(&txq->meta[index], mapping),
 352                                 dma_unmap_len(&txq->meta[index], len),
 353                                 PCI_DMA_BIDIRECTIONAL);
 354
 355         /* Unmap chunks, if any. */
 356         for (i = 1; i < num_tbs; i++)
 357                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 358                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 359
 360         /* free SKB */
 361         if (txq->txb) {
 362                 struct sk_buff *skb;
 363
 364                 skb = txq->txb[txq->q.read_ptr].skb;
 365
 366                 /* can be called from irqs-disabled context */
 367                 if (skb) {
 368                         dev_kfree_skb_any(skb);
 369                         txq->txb[txq->q.read_ptr].skb = NULL;
 370                 }
 371         }
 372 }
 373
 374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 375                                  struct iwl_tx_queue *txq,
 376                                  dma_addr_t addr, u16 len,
 377                                  u8 reset, u8 pad)
 378 {
 379         struct iwl_queue *q;
 380         struct iwl_tfd *tfd, *tfd_tmp;
 381         u32 num_tbs;
 382
 383         q = &txq->q;
 384         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 385         tfd = &tfd_tmp[q->write_ptr];
 386
 387         if (reset)
 388                 memset(tfd, 0, sizeof(*tfd));
 389
 390         num_tbs = iwl_tfd_get_num_tbs(tfd);
 391
 392         /* Each TFD can point to a maximum 20 Tx buffers */
 393         if (num_tbs >= IWL_NUM_OF_TBS) {
 394                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 395                           IWL_NUM_OF_TBS);
 396                 return -EINVAL;
 397         }
 398
 399         BUG_ON(addr & ~DMA_BIT_MASK(36));
 400         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 401                 IWL_ERR(priv, "Unaligned address = %llx\n",
 402                           (unsigned long long)addr);
 403
 404         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 411  * given Tx queue, and enable the DMA channel used for that queue.
 412  *
 413  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 414  * channels supported in hardware.
 415  */
 416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 417                          struct iwl_tx_queue *txq)
 418 {
 419         int txq_id = txq->q.id;
 420
 421         /* Circular buffer (TFD queue in DRAM) physical base address */
 422         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 423                              txq->q.dma_addr >> 8);
 424
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  *
 430  * Generic RX handler implementations
 431  *
 432  ******************************************************************************/
 433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 434                                 struct iwl_rx_mem_buffer *rxb)
 435 {
 436         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 437         struct iwl_alive_resp *palive;
 438         struct delayed_work *pwork;
 439
 440         palive = &pkt->u.alive_frame;
 441
 442         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 443                        "0x%01X 0x%01X\n",
 444                        palive->is_valid, palive->ver_type,
 445                        palive->ver_subtype);
 446
 447         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 448                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 449                 memcpy(&priv->card_alive_init,
 450                        &pkt->u.alive_frame,
 451                        sizeof(struct iwl_init_alive_resp));
 452                 pwork = &priv->init_alive_start;
 453         } else {
 454                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 455                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 456                        sizeof(struct iwl_alive_resp));
 457                 pwork = &priv->alive_start;
 458         }
 459
 460         /* We delay the ALIVE response by 5ms to
 461          * give the HW RF Kill time to activate... */
 462         if (palive->is_valid == UCODE_VALID_OK)
 463                 queue_delayed_work(priv->workqueue, pwork,
 464                                    msecs_to_jiffies(5));
 465         else {
 466                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 467                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 468                         "init" : "runtime");
 469                 queue_work(priv->workqueue, &priv->restart);
 470         }
 471 }
 472
 473 static void iwl_bg_beacon_update(struct work_struct *work)
 474 {
 475         struct iwl_priv *priv =
 476                 container_of(work, struct iwl_priv, beacon_update);
 477         struct sk_buff *beacon;
 478
 479         mutex_lock(&priv->mutex);
 480         if (!priv->beacon_ctx) {
 481                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 482                 goto out;
 483         }
 484
 485         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 486                 /*
 487                  * The ucode will send beacon notifications even in
 488                  * IBSS mode, but we don't want to process them. But
 489                  * we need to defer the type check to here due to
 490                  * requiring locking around the beacon_ctx access.
 491                  */
 492                 goto out;
 493         }
 494
 495         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 496         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 497         if (!beacon) {
 498                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 499                 goto out;
 500         }
 501
 502         /* new beacon skb is allocated every time; dispose previous.*/
 503         dev_kfree_skb(priv->beacon_skb);
 504
 505         priv->beacon_skb = beacon;
 506
 507         iwlagn_send_beacon_cmd(priv);
 508  out:
 509         mutex_unlock(&priv->mutex);
 510 }
 511
 512 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 513 {
 514         struct iwl_priv *priv =
 515                 container_of(work, struct iwl_priv, bt_runtime_config);
 516
 517         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 518                 return;
 519
 520         /* dont send host command if rf-kill is on */
 521         if (!iwl_is_ready_rf(priv))
 522                 return;
 523         priv->cfg->ops->hcmd->send_bt_config(priv);
 524 }
 525
 526 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 527 {
 528         struct iwl_priv *priv =
 529                 container_of(work, struct iwl_priv, bt_full_concurrency);
 530         struct iwl_rxon_context *ctx;
 531
 532         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 533                 return;
 534
 535         /* dont send host command if rf-kill is on */
 536         if (!iwl_is_ready_rf(priv))
 537                 return;
 538
 539         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 540                        priv->bt_full_concurrent ?
 541                        "full concurrency" : "3-wire");
 542
 543         /*
 544          * LQ & RXON updated cmds must be sent before BT Config cmd
 545          * to avoid 3-wire collisions
 546          */
 547         mutex_lock(&priv->mutex);
 548         for_each_context(priv, ctx) {
 549                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 550                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 551                 iwlcore_commit_rxon(priv, ctx);
 552         }
 553         mutex_unlock(&priv->mutex);
 554
 555         priv->cfg->ops->hcmd->send_bt_config(priv);
 556 }
 557
 558 /**
 559  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 560  *
 561  * This callback is provided in order to send a statistics request.
 562  *
 563  * This timer function is continually reset to execute within
 564  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 565  * was received.  We need to ensure we receive the statistics in order
 566  * to update the temperature used for calibrating the TXPOWER.
 567  */
 568 static void iwl_bg_statistics_periodic(unsigned long data)
 569 {
 570         struct iwl_priv *priv = (struct iwl_priv *)data;
 571
 572         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 573                 return;
 574
 575         /* dont send host command if rf-kill is on */
 576         if (!iwl_is_ready_rf(priv))
 577                 return;
 578
 579         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 580 }
 581
 582
 583 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 584                                         u32 start_idx, u32 num_events,
 585                                         u32 mode)
 586 {
 587         u32 i;
 588         u32 ptr;        /* SRAM byte address of log data */
 589         u32 ev, time, data; /* event log data */
 590         unsigned long reg_flags;
 591
 592         if (mode == 0)
 593                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 594         else
 595                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 596
 597         /* Make sure device is powered up for SRAM reads */
 598         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 599         if (iwl_grab_nic_access(priv)) {
 600                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 601                 return;
 602         }
 603
 604         /* Set starting address; reads will auto-increment */
 605         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 606         rmb();
 607
 608         /*
 609          * "time" is actually "data" for mode 0 (no timestamp).
 610          * place event id # at far right for easier visual parsing.
 611          */
 612         for (i = 0; i < num_events; i++) {
 613                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 614                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 615                 if (mode == 0) {
 616                         trace_iwlwifi_dev_ucode_cont_event(priv,
 617                                                         0, time, ev);
 618                 } else {
 619                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 620                         trace_iwlwifi_dev_ucode_cont_event(priv,
 621                                                 time, data, ev);
 622                 }
 623         }
 624         /* Allow device to power down */
 625         iwl_release_nic_access(priv);
 626         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 627 }
 628
 629 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 630 {
 631         u32 capacity;   /* event log capacity in # entries */
 632         u32 base;       /* SRAM byte address of event log header */
 633         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 634         u32 num_wraps;  /* # times uCode wrapped to top of log */
 635         u32 next_entry; /* index of next entry to be written by uCode */
 636
 637         if (priv->ucode_type == UCODE_INIT)
 638                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 639         else
 640                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 641         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 642                 capacity = iwl_read_targ_mem(priv, base);
 643                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 644                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 645                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 646         } else
 647                 return;
 648
 649         if (num_wraps == priv->event_log.num_wraps) {
 650                 iwl_print_cont_event_trace(priv,
 651                                        base, priv->event_log.next_entry,
 652                                        next_entry - priv->event_log.next_entry,
 653                                        mode);
 654                 priv->event_log.non_wraps_count++;
 655         } else {
 656                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 657                         priv->event_log.wraps_more_count++;
 658                 else
 659                         priv->event_log.wraps_once_count++;
 660                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 661                                 num_wraps - priv->event_log.num_wraps,
 662                                 next_entry, priv->event_log.next_entry);
 663                 if (next_entry < priv->event_log.next_entry) {
 664                         iwl_print_cont_event_trace(priv, base,
 665                                priv->event_log.next_entry,
 666                                capacity - priv->event_log.next_entry,
 667                                mode);
 668
 669                         iwl_print_cont_event_trace(priv, base, 0,
 670                                 next_entry, mode);
 671                 } else {
 672                         iwl_print_cont_event_trace(priv, base,
 673                                next_entry, capacity - next_entry,
 674                                mode);
 675
 676                         iwl_print_cont_event_trace(priv, base, 0,
 677                                 next_entry, mode);
 678                 }
 679         }
 680         priv->event_log.num_wraps = num_wraps;
 681         priv->event_log.next_entry = next_entry;
 682 }
 683
 684 /**
 685  * iwl_bg_ucode_trace - Timer callback to log ucode event
 686  *
 687  * The timer is continually set to execute every
 688  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 689  * this function is to perform continuous uCode event logging operation
 690  * if enabled
 691  */
 692 static void iwl_bg_ucode_trace(unsigned long data)
 693 {
 694         struct iwl_priv *priv = (struct iwl_priv *)data;
 695
 696         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 697                 return;
 698
 699         if (priv->event_log.ucode_trace) {
 700                 iwl_continuous_event_trace(priv);
 701                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 702                 mod_timer(&priv->ucode_trace,
 703                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 704         }
 705 }
 706
 707 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 708                                    struct iwl_rx_mem_buffer *rxb)
 709 {
 710         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 711         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 712 #ifdef CONFIG_IWLWIFI_DEBUG
 713         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 714         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 715
 716         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 717                 "tsf:0x%.8x%.8x rate:%d\n",
 718                 status & TX_STATUS_MSK,
 719                 beacon->beacon_notify_hdr.failure_frame,
 720                 le32_to_cpu(beacon->ibss_mgr_status),
 721                 le32_to_cpu(beacon->high_tsf),
 722                 le32_to_cpu(beacon->low_tsf), rate);
 723 #endif
 724
 725         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 726
 727         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 728                 queue_work(priv->workqueue, &priv->beacon_update);
 729 }
 730
 731 /* Handle notification from uCode that card's power state is changing
 732  * due to software, hardware, or critical temperature RFKILL */
 733 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 734                                     struct iwl_rx_mem_buffer *rxb)
 735 {
 736         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 737         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 738         unsigned long status = priv->status;
 739
 740         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 741                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 742                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 743                           (flags & CT_CARD_DISABLED) ?
 744                           "Reached" : "Not reached");
 745
 746         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 747                      CT_CARD_DISABLED)) {
 748
 749                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 750                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 751
 752                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 753                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 754
 755                 if (!(flags & RXON_CARD_DISABLED)) {
 756                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 757                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 758                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 759                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 760                 }
 761                 if (flags & CT_CARD_DISABLED)
 762                         iwl_tt_enter_ct_kill(priv);
 763         }
 764         if (!(flags & CT_CARD_DISABLED))
 765                 iwl_tt_exit_ct_kill(priv);
 766
 767         if (flags & HW_CARD_DISABLED)
 768                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 769         else
 770                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 771
 772
 773         if (!(flags & RXON_CARD_DISABLED))
 774                 iwl_scan_cancel(priv);
 775
 776         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 777              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 778                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 779                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 780         else
 781                 wake_up_interruptible(&priv->wait_command_queue);
 782 }
 783
 784 static void iwl_bg_tx_flush(struct work_struct *work)
 785 {
 786         struct iwl_priv *priv =
 787                 container_of(work, struct iwl_priv, tx_flush);
 788
 789         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 790                 return;
 791
 792         /* do nothing if rf-kill is on */
 793         if (!iwl_is_ready_rf(priv))
 794                 return;
 795
 796         if (priv->cfg->ops->lib->txfifo_flush) {
 797                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 798                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 799         }
 800 }
 801
 802 /**
 803  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 804  *
 805  * Setup the RX handlers for each of the reply types sent from the uCode
 806  * to the host.
 807  *
 808  * This function chains into the hardware specific files for them to setup
 809  * any hardware specific handlers as well.
 810  */
 811 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 812 {
 813         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 814         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 815         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 816         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 817                         iwl_rx_spectrum_measure_notif;
 818         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 819         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 820             iwl_rx_pm_debug_statistics_notif;
 821         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 822
 823         /*
 824          * The same handler is used for both the REPLY to a discrete
 825          * statistics request from the host as well as for the periodic
 826          * statistics notifications (after received beacons) from the uCode.
 827          */
 828         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 829         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 830
 831         iwl_setup_rx_scan_handlers(priv);
 832
 833         /* status change handler */
 834         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 835
 836         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 837             iwl_rx_missed_beacon_notif;
 838         /* Rx handlers */
 839         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 840         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 841         /* block ack */
 842         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 843         /* Set up hardware specific Rx handlers */
 844         priv->cfg->ops->lib->rx_handler_setup(priv);
 845 }
 846
 847 /**
 848  * iwl_rx_handle - Main entry function for receiving responses from uCode
 849  *
 850  * Uses the priv->rx_handlers callback function array to invoke
 851  * the appropriate handlers, including command responses,
 852  * frame-received notifications, and other notifications.
 853  */
 854 static void iwl_rx_handle(struct iwl_priv *priv)
 855 {
 856         struct iwl_rx_mem_buffer *rxb;
 857         struct iwl_rx_packet *pkt;
 858         struct iwl_rx_queue *rxq = &priv->rxq;
 859         u32 r, i;
 860         int reclaim;
 861         unsigned long flags;
 862         u8 fill_rx = 0;
 863         u32 count = 8;
 864         int total_empty;
 865
 866         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 867          * buffer that the driver may process (last buffer filled by ucode). */
 868         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 869         i = rxq->read;
 870
 871         /* Rx interrupt, but nothing sent from uCode */
 872         if (i == r)
 873                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 874
 875         /* calculate total frames need to be restock after handling RX */
 876         total_empty = r - rxq->write_actual;
 877         if (total_empty < 0)
 878                 total_empty += RX_QUEUE_SIZE;
 879
 880         if (total_empty > (RX_QUEUE_SIZE / 2))
 881                 fill_rx = 1;
 882
 883         while (i != r) {
 884                 int len;
 885
 886                 rxb = rxq->queue[i];
 887
 888                 /* If an RXB doesn't have a Rx queue slot associated with it,
 889                  * then a bug has been introduced in the queue refilling
 890                  * routines -- catch it here */
 891                 BUG_ON(rxb == NULL);
 892
 893                 rxq->queue[i] = NULL;
 894
 895                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 896                                PAGE_SIZE << priv->hw_params.rx_page_order,
 897                                PCI_DMA_FROMDEVICE);
 898                 pkt = rxb_addr(rxb);
 899
 900                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 901                 len += sizeof(u32); /* account for status word */
 902                 trace_iwlwifi_dev_rx(priv, pkt, len);
 903
 904                 /* Reclaim a command buffer only if this packet is a response
 905                  *   to a (driver-originated) command.
 906                  * If the packet (e.g. Rx frame) originated from uCode,
 907                  *   there is no command buffer to reclaim.
 908                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 909                  *   but apparently a few don't get set; catch them here. */
 910                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 911                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 912                         (pkt->hdr.cmd != REPLY_RX) &&
 913                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 914                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 915                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 916                         (pkt->hdr.cmd != REPLY_TX);
 917
 918                 /*
 919                  * Do the notification wait before RX handlers so
 920                  * even if the RX handler consumes the RXB we have
 921                  * access to it in the notification wait entry.
 922                  */
 923                 if (!list_empty(&priv->_agn.notif_waits)) {
 924                         struct iwl_notification_wait *w;
 925
 926                         spin_lock(&priv->_agn.notif_wait_lock);
 927                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 928                                 if (w->cmd == pkt->hdr.cmd) {
 929                                         w->triggered = true;
 930                                         if (w->fn)
 931                                                 w->fn(priv, pkt);
 932                                 }
 933                         }
 934                         spin_unlock(&priv->_agn.notif_wait_lock);
 935
 936                         wake_up_all(&priv->_agn.notif_waitq);
 937                 }
 938
 939                 /* Based on type of command response or notification,
 940                  *   handle those that need handling via function in
 941                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 942                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 943                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 944                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 945                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 946                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 947                 } else {
 948                         /* No handling needed */
 949                         IWL_DEBUG_RX(priv,
 950                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 951                                 r, i, get_cmd_string(pkt->hdr.cmd),
 952                                 pkt->hdr.cmd);
 953                 }
 954
 955                 /*
 956                  * XXX: After here, we should always check rxb->page
 957                  * against NULL before touching it or its virtual
 958                  * memory (pkt). Because some rx_handler might have
 959                  * already taken or freed the pages.
 960                  */
 961
 962                 if (reclaim) {
 963                         /* Invoke any callbacks, transfer the buffer to caller,
 964                          * and fire off the (possibly) blocking iwl_send_cmd()
 965                          * as we reclaim the driver command queue */
 966                         if (rxb->page)
 967                                 iwl_tx_cmd_complete(priv, rxb);
 968                         else
 969                                 IWL_WARN(priv, "Claim null rxb?\n");
 970                 }
 971
 972                 /* Reuse the page if possible. For notification packets and
 973                  * SKBs that fail to Rx correctly, add them back into the
 974                  * rx_free list for reuse later. */
 975                 spin_lock_irqsave(&rxq->lock, flags);
 976                 if (rxb->page != NULL) {
 977                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 978                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 979                                 PCI_DMA_FROMDEVICE);
 980                         list_add_tail(&rxb->list, &rxq->rx_free);
 981                         rxq->free_count++;
 982                 } else
 983                         list_add_tail(&rxb->list, &rxq->rx_used);
 984
 985                 spin_unlock_irqrestore(&rxq->lock, flags);
 986
 987                 i = (i + 1) & RX_QUEUE_MASK;
 988                 /* If there are a lot of unused frames,
 989                  * restock the Rx queue so ucode wont assert. */
 990                 if (fill_rx) {
 991                         count++;
 992                         if (count >= 8) {
 993                                 rxq->read = i;
 994                                 iwlagn_rx_replenish_now(priv);
 995                                 count = 0;
 996                         }
 997                 }
 998         }
 999
1000         /* Backtrack one entry */
1001         rxq->read = i;
1002         if (fill_rx)
1003                 iwlagn_rx_replenish_now(priv);
1004         else
1005                 iwlagn_rx_queue_restock(priv);
1006 }
1007
1008 /* call this function to flush any scheduled tasklet */
1009 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1010 {
1011         /* wait to make sure we flush pending tasklet*/
1012         synchronize_irq(priv->pci_dev->irq);
1013         tasklet_kill(&priv->irq_tasklet);
1014 }
1015
1016 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1017 {
1018         u32 inta, handled = 0;
1019         u32 inta_fh;
1020         unsigned long flags;
1021         u32 i;
1022 #ifdef CONFIG_IWLWIFI_DEBUG
1023         u32 inta_mask;
1024 #endif
1025
1026         spin_lock_irqsave(&priv->lock, flags);
1027
1028         /* Ack/clear/reset pending uCode interrupts.
1029          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1030          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1031         inta = iwl_read32(priv, CSR_INT);
1032         iwl_write32(priv, CSR_INT, inta);
1033
1034         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1035          * Any new interrupts that happen after this, either while we're
1036          * in this tasklet, or later, will show up in next ISR/tasklet. */
1037         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1038         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1039
1040 #ifdef CONFIG_IWLWIFI_DEBUG
1041         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1042                 /* just for debug */
1043                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1044                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1045                               inta, inta_mask, inta_fh);
1046         }
1047 #endif
1048
1049         spin_unlock_irqrestore(&priv->lock, flags);
1050
1051         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1052          * atomic, make sure that inta covers all the interrupts that
1053          * we've discovered, even if FH interrupt came in just after
1054          * reading CSR_INT. */
1055         if (inta_fh & CSR49_FH_INT_RX_MASK)
1056                 inta |= CSR_INT_BIT_FH_RX;
1057         if (inta_fh & CSR49_FH_INT_TX_MASK)
1058                 inta |= CSR_INT_BIT_FH_TX;
1059
1060         /* Now service all interrupt bits discovered above. */
1061         if (inta & CSR_INT_BIT_HW_ERR) {
1062                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1063
1064                 /* Tell the device to stop sending interrupts */
1065                 iwl_disable_interrupts(priv);
1066
1067                 priv->isr_stats.hw++;
1068                 iwl_irq_handle_error(priv);
1069
1070                 handled |= CSR_INT_BIT_HW_ERR;
1071
1072                 return;
1073         }
1074
1075 #ifdef CONFIG_IWLWIFI_DEBUG
1076         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1077                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1078                 if (inta & CSR_INT_BIT_SCD) {
1079                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1080                                       "the frame/frames.\n");
1081                         priv->isr_stats.sch++;
1082                 }
1083
1084                 /* Alive notification via Rx interrupt will do the real work */
1085                 if (inta & CSR_INT_BIT_ALIVE) {
1086                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1087                         priv->isr_stats.alive++;
1088                 }
1089         }
1090 #endif
1091         /* Safely ignore these bits for debug checks below */
1092         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1093
1094         /* HW RF KILL switch toggled */
1095         if (inta & CSR_INT_BIT_RF_KILL) {
1096                 int hw_rf_kill = 0;
1097                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1098                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1099                         hw_rf_kill = 1;
1100
1101                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1102                                 hw_rf_kill ? "disable radio" : "enable radio");
1103
1104                 priv->isr_stats.rfkill++;
1105
1106                 /* driver only loads ucode once setting the interface up.
1107                  * the driver allows loading the ucode even if the radio
1108                  * is killed. Hence update the killswitch state here. The
1109                  * rfkill handler will care about restarting if needed.
1110                  */
1111                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1112                         if (hw_rf_kill)
1113                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1114                         else
1115                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1116                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1117                 }
1118
1119                 handled |= CSR_INT_BIT_RF_KILL;
1120         }
1121
1122         /* Chip got too hot and stopped itself */
1123         if (inta & CSR_INT_BIT_CT_KILL) {
1124                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1125                 priv->isr_stats.ctkill++;
1126                 handled |= CSR_INT_BIT_CT_KILL;
1127         }
1128
1129         /* Error detected by uCode */
1130         if (inta & CSR_INT_BIT_SW_ERR) {
1131                 IWL_ERR(priv, "Microcode SW error detected. "
1132                         " Restarting 0x%X.\n", inta);
1133                 priv->isr_stats.sw++;
1134                 iwl_irq_handle_error(priv);
1135                 handled |= CSR_INT_BIT_SW_ERR;
1136         }
1137
1138         /*
1139          * uCode wakes up after power-down sleep.
1140          * Tell device about any new tx or host commands enqueued,
1141          * and about any Rx buffers made available while asleep.
1142          */
1143         if (inta & CSR_INT_BIT_WAKEUP) {
1144                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1145                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1146                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1147                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1148                 priv->isr_stats.wakeup++;
1149                 handled |= CSR_INT_BIT_WAKEUP;
1150         }
1151
1152         /* All uCode command responses, including Tx command responses,
1153          * Rx "responses" (frame-received notification), and other
1154          * notifications from uCode come through here*/
1155         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1156                 iwl_rx_handle(priv);
1157                 priv->isr_stats.rx++;
1158                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1159         }
1160
1161         /* This "Tx" DMA channel is used only for loading uCode */
1162         if (inta & CSR_INT_BIT_FH_TX) {
1163                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1164                 priv->isr_stats.tx++;
1165                 handled |= CSR_INT_BIT_FH_TX;
1166                 /* Wake up uCode load routine, now that load is complete */
1167                 priv->ucode_write_complete = 1;
1168                 wake_up_interruptible(&priv->wait_command_queue);
1169         }
1170
1171         if (inta & ~handled) {
1172                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1173                 priv->isr_stats.unhandled++;
1174         }
1175
1176         if (inta & ~(priv->inta_mask)) {
1177                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1178                          inta & ~priv->inta_mask);
1179                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1180         }
1181
1182         /* Re-enable all interrupts */
1183         /* only Re-enable if disabled by irq */
1184         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1185                 iwl_enable_interrupts(priv);
1186         /* Re-enable RF_KILL if it occurred */
1187         else if (handled & CSR_INT_BIT_RF_KILL)
1188                 iwl_enable_rfkill_int(priv);
1189
1190 #ifdef CONFIG_IWLWIFI_DEBUG
1191         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1192                 inta = iwl_read32(priv, CSR_INT);
1193                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1194                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1195                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1196                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1197         }
1198 #endif
1199 }
1200
1201 /* tasklet for iwlagn interrupt */
1202 static void iwl_irq_tasklet(struct iwl_priv *priv)
1203 {
1204         u32 inta = 0;
1205         u32 handled = 0;
1206         unsigned long flags;
1207         u32 i;
1208 #ifdef CONFIG_IWLWIFI_DEBUG
1209         u32 inta_mask;
1210 #endif
1211
1212         spin_lock_irqsave(&priv->lock, flags);
1213
1214         /* Ack/clear/reset pending uCode interrupts.
1215          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1216          */
1217         /* There is a hardware bug in the interrupt mask function that some
1218          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1219          * they are disabled in the CSR_INT_MASK register. Furthermore the
1220          * ICT interrupt handling mechanism has another bug that might cause
1221          * these unmasked interrupts fail to be detected. We workaround the
1222          * hardware bugs here by ACKing all the possible interrupts so that
1223          * interrupt coalescing can still be achieved.
1224          */
1225         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1226
1227         inta = priv->_agn.inta;
1228
1229 #ifdef CONFIG_IWLWIFI_DEBUG
1230         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1231                 /* just for debug */
1232                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1233                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1234                                 inta, inta_mask);
1235         }
1236 #endif
1237
1238         spin_unlock_irqrestore(&priv->lock, flags);
1239
1240         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1241         priv->_agn.inta = 0;
1242
1243         /* Now service all interrupt bits discovered above. */
1244         if (inta & CSR_INT_BIT_HW_ERR) {
1245                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1246
1247                 /* Tell the device to stop sending interrupts */
1248                 iwl_disable_interrupts(priv);
1249
1250                 priv->isr_stats.hw++;
1251                 iwl_irq_handle_error(priv);
1252
1253                 handled |= CSR_INT_BIT_HW_ERR;
1254
1255                 return;
1256         }
1257
1258 #ifdef CONFIG_IWLWIFI_DEBUG
1259         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1260                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1261                 if (inta & CSR_INT_BIT_SCD) {
1262                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1263                                       "the frame/frames.\n");
1264                         priv->isr_stats.sch++;
1265                 }
1266
1267                 /* Alive notification via Rx interrupt will do the real work */
1268                 if (inta & CSR_INT_BIT_ALIVE) {
1269                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1270                         priv->isr_stats.alive++;
1271                 }
1272         }
1273 #endif
1274         /* Safely ignore these bits for debug checks below */
1275         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1276
1277         /* HW RF KILL switch toggled */
1278         if (inta & CSR_INT_BIT_RF_KILL) {
1279                 int hw_rf_kill = 0;
1280                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1281                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1282                         hw_rf_kill = 1;
1283
1284                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1285                                 hw_rf_kill ? "disable radio" : "enable radio");
1286
1287                 priv->isr_stats.rfkill++;
1288
1289                 /* driver only loads ucode once setting the interface up.
1290                  * the driver allows loading the ucode even if the radio
1291                  * is killed. Hence update the killswitch state here. The
1292                  * rfkill handler will care about restarting if needed.
1293                  */
1294                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1295                         if (hw_rf_kill)
1296                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1297                         else
1298                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1299                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1300                 }
1301
1302                 handled |= CSR_INT_BIT_RF_KILL;
1303         }
1304
1305         /* Chip got too hot and stopped itself */
1306         if (inta & CSR_INT_BIT_CT_KILL) {
1307                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1308                 priv->isr_stats.ctkill++;
1309                 handled |= CSR_INT_BIT_CT_KILL;
1310         }
1311
1312         /* Error detected by uCode */
1313         if (inta & CSR_INT_BIT_SW_ERR) {
1314                 IWL_ERR(priv, "Microcode SW error detected. "
1315                         " Restarting 0x%X.\n", inta);
1316                 priv->isr_stats.sw++;
1317                 iwl_irq_handle_error(priv);
1318                 handled |= CSR_INT_BIT_SW_ERR;
1319         }
1320
1321         /* uCode wakes up after power-down sleep */
1322         if (inta & CSR_INT_BIT_WAKEUP) {
1323                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1324                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1325                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1326                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1327
1328                 priv->isr_stats.wakeup++;
1329
1330                 handled |= CSR_INT_BIT_WAKEUP;
1331         }
1332
1333         /* All uCode command responses, including Tx command responses,
1334          * Rx "responses" (frame-received notification), and other
1335          * notifications from uCode come through here*/
1336         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1337                         CSR_INT_BIT_RX_PERIODIC)) {
1338                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1339                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1340                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1341                         iwl_write32(priv, CSR_FH_INT_STATUS,
1342                                         CSR49_FH_INT_RX_MASK);
1343                 }
1344                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1345                         handled |= CSR_INT_BIT_RX_PERIODIC;
1346                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1347                 }
1348                 /* Sending RX interrupt require many steps to be done in the
1349                  * the device:
1350                  * 1- write interrupt to current index in ICT table.
1351                  * 2- dma RX frame.
1352                  * 3- update RX shared data to indicate last write index.
1353                  * 4- send interrupt.
1354                  * This could lead to RX race, driver could receive RX interrupt
1355                  * but the shared data changes does not reflect this;
1356                  * periodic interrupt will detect any dangling Rx activity.
1357                  */
1358
1359                 /* Disable periodic interrupt; we use it as just a one-shot. */
1360                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1361                             CSR_INT_PERIODIC_DIS);
1362                 iwl_rx_handle(priv);
1363
1364                 /*
1365                  * Enable periodic interrupt in 8 msec only if we received
1366                  * real RX interrupt (instead of just periodic int), to catch
1367                  * any dangling Rx interrupt.  If it was just the periodic
1368                  * interrupt, there was no dangling Rx activity, and no need
1369                  * to extend the periodic interrupt; one-shot is enough.
1370                  */
1371                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1372                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1373                                     CSR_INT_PERIODIC_ENA);
1374
1375                 priv->isr_stats.rx++;
1376         }
1377
1378         /* This "Tx" DMA channel is used only for loading uCode */
1379         if (inta & CSR_INT_BIT_FH_TX) {
1380                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1381                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1382                 priv->isr_stats.tx++;
1383                 handled |= CSR_INT_BIT_FH_TX;
1384                 /* Wake up uCode load routine, now that load is complete */
1385                 priv->ucode_write_complete = 1;
1386                 wake_up_interruptible(&priv->wait_command_queue);
1387         }
1388
1389         if (inta & ~handled) {
1390                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1391                 priv->isr_stats.unhandled++;
1392         }
1393
1394         if (inta & ~(priv->inta_mask)) {
1395                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1396                          inta & ~priv->inta_mask);
1397         }
1398
1399         /* Re-enable all interrupts */
1400         /* only Re-enable if disabled by irq */
1401         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1402                 iwl_enable_interrupts(priv);
1403         /* Re-enable RF_KILL if it occurred */
1404         else if (handled & CSR_INT_BIT_RF_KILL)
1405                 iwl_enable_rfkill_int(priv);
1406 }
1407
1408 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1409 #define ACK_CNT_RATIO (50)
1410 #define BA_TIMEOUT_CNT (5)
1411 #define BA_TIMEOUT_MAX (16)
1412
1413 /**
1414  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1415  *
1416  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1417  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1418  * operation state.
1419  */
1420 bool iwl_good_ack_health(struct iwl_priv *priv,
1421                                 struct iwl_rx_packet *pkt)
1422 {
1423         bool rc = true;
1424         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1425         int ba_timeout_delta;
1426
1427         actual_ack_cnt_delta =
1428                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1429                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1430         expected_ack_cnt_delta =
1431                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1432                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1433         ba_timeout_delta =
1434                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1435                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1436         if ((priv->_agn.agg_tids_count > 0) &&
1437             (expected_ack_cnt_delta > 0) &&
1438             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1439                 < ACK_CNT_RATIO) &&
1440             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1441                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1442                                 " expected_ack_cnt = %d\n",
1443                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1444
1445 #ifdef CONFIG_IWLWIFI_DEBUGFS
1446                 /*
1447                  * This is ifdef'ed on DEBUGFS because otherwise the
1448                  * statistics aren't available. If DEBUGFS is set but
1449                  * DEBUG is not, these will just compile out.
1450                  */
1451                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1452                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1453                 IWL_DEBUG_RADIO(priv,
1454                                 "ack_or_ba_timeout_collision delta = %d\n",
1455                                 priv->_agn.delta_statistics.tx.
1456                                 ack_or_ba_timeout_collision);
1457 #endif
1458                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1459                                 ba_timeout_delta);
1460                 if (!actual_ack_cnt_delta &&
1461                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1462                         rc = false;
1463         }
1464         return rc;
1465 }
1466
1467
1468 /*****************************************************************************
1469  *
1470  * sysfs attributes
1471  *
1472  *****************************************************************************/
1473
1474 #ifdef CONFIG_IWLWIFI_DEBUG
1475
1476 /*
1477  * The following adds a new attribute to the sysfs representation
1478  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1479  * used for controlling the debug level.
1480  *
1481  * See the level definitions in iwl for details.
1482  *
1483  * The debug_level being managed using sysfs below is a per device debug
1484  * level that is used instead of the global debug level if it (the per
1485  * device debug level) is set.
1486  */
1487 static ssize_t show_debug_level(struct device *d,
1488                                 struct device_attribute *attr, char *buf)
1489 {
1490         struct iwl_priv *priv = dev_get_drvdata(d);
1491         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1492 }
1493 static ssize_t store_debug_level(struct device *d,
1494                                 struct device_attribute *attr,
1495                                  const char *buf, size_t count)
1496 {
1497         struct iwl_priv *priv = dev_get_drvdata(d);
1498         unsigned long val;
1499         int ret;
1500
1501         ret = strict_strtoul(buf, 0, &val);
1502         if (ret)
1503                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1504         else {
1505                 priv->debug_level = val;
1506                 if (iwl_alloc_traffic_mem(priv))
1507                         IWL_ERR(priv,
1508                                 "Not enough memory to generate traffic log\n");
1509         }
1510         return strnlen(buf, count);
1511 }
1512
1513 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1514                         show_debug_level, store_debug_level);
1515
1516
1517 #endif /* CONFIG_IWLWIFI_DEBUG */
1518
1519
1520 static ssize_t show_temperature(struct device *d,
1521                                 struct device_attribute *attr, char *buf)
1522 {
1523         struct iwl_priv *priv = dev_get_drvdata(d);
1524
1525         if (!iwl_is_alive(priv))
1526                 return -EAGAIN;
1527
1528         return sprintf(buf, "%d\n", priv->temperature);
1529 }
1530
1531 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1532
1533 static ssize_t show_tx_power(struct device *d,
1534                              struct device_attribute *attr, char *buf)
1535 {
1536         struct iwl_priv *priv = dev_get_drvdata(d);
1537
1538         if (!iwl_is_ready_rf(priv))
1539                 return sprintf(buf, "off\n");
1540         else
1541                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1542 }
1543
1544 static ssize_t store_tx_power(struct device *d,
1545                               struct device_attribute *attr,
1546                               const char *buf, size_t count)
1547 {
1548         struct iwl_priv *priv = dev_get_drvdata(d);
1549         unsigned long val;
1550         int ret;
1551
1552         ret = strict_strtoul(buf, 10, &val);
1553         if (ret)
1554                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1555         else {
1556                 ret = iwl_set_tx_power(priv, val, false);
1557                 if (ret)
1558                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1559                                 ret);
1560                 else
1561                         ret = count;
1562         }
1563         return ret;
1564 }
1565
1566 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1567
1568 static struct attribute *iwl_sysfs_entries[] = {
1569         &dev_attr_temperature.attr,
1570         &dev_attr_tx_power.attr,
1571 #ifdef CONFIG_IWLWIFI_DEBUG
1572         &dev_attr_debug_level.attr,
1573 #endif
1574         NULL
1575 };
1576
1577 static struct attribute_group iwl_attribute_group = {
1578         .name = NULL,           /* put in device directory */
1579         .attrs = iwl_sysfs_entries,
1580 };
1581
1582 /******************************************************************************
1583  *
1584  * uCode download functions
1585  *
1586  ******************************************************************************/
1587
1588 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1589 {
1590         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1591         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1592         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1593         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1594         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1595         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1596 }
1597
1598 static void iwl_nic_start(struct iwl_priv *priv)
1599 {
1600         /* Remove all resets to allow NIC to operate */
1601         iwl_write32(priv, CSR_RESET, 0);
1602 }
1603
1604 struct iwlagn_ucode_capabilities {
1605         u32 max_probe_length;
1606         u32 standard_phy_calibration_size;
1607         bool pan;
1608 };
1609
1610 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1611 static int iwl_mac_setup_register(struct iwl_priv *priv,
1612                                   struct iwlagn_ucode_capabilities *capa);
1613
1614 #define UCODE_EXPERIMENTAL_INDEX        100
1615 #define UCODE_EXPERIMENTAL_TAG          "exp"
1616
1617 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1618 {
1619         const char *name_pre = priv->cfg->fw_name_pre;
1620         char tag[8];
1621
1622         if (first) {
1623 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1624                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1625                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1626         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1627 #endif
1628                 priv->fw_index = priv->cfg->ucode_api_max;
1629                 sprintf(tag, "%d", priv->fw_index);
1630         } else {
1631                 priv->fw_index--;
1632                 sprintf(tag, "%d", priv->fw_index);
1633         }
1634
1635         if (priv->fw_index < priv->cfg->ucode_api_min) {
1636                 IWL_ERR(priv, "no suitable firmware found!\n");
1637                 return -ENOENT;
1638         }
1639
1640         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1641
1642         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1643                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1644                                 ? "EXPERIMENTAL " : "",
1645                        priv->firmware_name);
1646
1647         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1648                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1649                                        iwl_ucode_callback);
1650 }
1651
1652 struct iwlagn_firmware_pieces {
1653         const void *inst, *data, *init, *init_data, *boot;
1654         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1655
1656         u32 build;
1657
1658         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1659         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1660 };
1661
1662 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1663                                        const struct firmware *ucode_raw,
1664                                        struct iwlagn_firmware_pieces *pieces)
1665 {
1666         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1667         u32 api_ver, hdr_size;
1668         const u8 *src;
1669
1670         priv->ucode_ver = le32_to_cpu(ucode->ver);
1671         api_ver = IWL_UCODE_API(priv->ucode_ver);
1672
1673         switch (api_ver) {
1674         default:
1675                 /*
1676                  * 4965 doesn't revision the firmware file format
1677                  * along with the API version, it always uses v1
1678                  * file format.
1679                  */
1680                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1681                                 CSR_HW_REV_TYPE_4965) {
1682                         hdr_size = 28;
1683                         if (ucode_raw->size < hdr_size) {
1684                                 IWL_ERR(priv, "File size too small!\n");
1685                                 return -EINVAL;
1686                         }
1687                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1688                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1689                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1690                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1691                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1692                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1693                         src = ucode->u.v2.data;
1694                         break;
1695                 }
1696                 /* fall through for 4965 */
1697         case 0:
1698         case 1:
1699         case 2:
1700                 hdr_size = 24;
1701                 if (ucode_raw->size < hdr_size) {
1702                         IWL_ERR(priv, "File size too small!\n");
1703                         return -EINVAL;
1704                 }
1705                 pieces->build = 0;
1706                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1707                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1708                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1709                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1710                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1711                 src = ucode->u.v1.data;
1712                 break;
1713         }
1714
1715         /* Verify size of file vs. image size info in file's header */
1716         if (ucode_raw->size != hdr_size + pieces->inst_size +
1717                                 pieces->data_size + pieces->init_size +
1718                                 pieces->init_data_size + pieces->boot_size) {
1719
1720                 IWL_ERR(priv,
1721                         "uCode file size %d does not match expected size\n",
1722                         (int)ucode_raw->size);
1723                 return -EINVAL;
1724         }
1725
1726         pieces->inst = src;
1727         src += pieces->inst_size;
1728         pieces->data = src;
1729         src += pieces->data_size;
1730         pieces->init = src;
1731         src += pieces->init_size;
1732         pieces->init_data = src;
1733         src += pieces->init_data_size;
1734         pieces->boot = src;
1735         src += pieces->boot_size;
1736
1737         return 0;
1738 }
1739
1740 static int iwlagn_wanted_ucode_alternative = 1;
1741
1742 static int iwlagn_load_firmware(struct iwl_priv *priv,
1743                                 const struct firmware *ucode_raw,
1744                                 struct iwlagn_firmware_pieces *pieces,
1745                                 struct iwlagn_ucode_capabilities *capa)
1746 {
1747         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1748         struct iwl_ucode_tlv *tlv;
1749         size_t len = ucode_raw->size;
1750         const u8 *data;
1751         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1752         u64 alternatives;
1753         u32 tlv_len;
1754         enum iwl_ucode_tlv_type tlv_type;
1755         const u8 *tlv_data;
1756
1757         if (len < sizeof(*ucode)) {
1758                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1759                 return -EINVAL;
1760         }
1761
1762         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1763                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1764                         le32_to_cpu(ucode->magic));
1765                 return -EINVAL;
1766         }
1767
1768         /*
1769          * Check which alternatives are present, and "downgrade"
1770          * when the chosen alternative is not present, warning
1771          * the user when that happens. Some files may not have
1772          * any alternatives, so don't warn in that case.
1773          */
1774         alternatives = le64_to_cpu(ucode->alternatives);
1775         tmp = wanted_alternative;
1776         if (wanted_alternative > 63)
1777                 wanted_alternative = 63;
1778         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1779                 wanted_alternative--;
1780         if (wanted_alternative && wanted_alternative != tmp)
1781                 IWL_WARN(priv,
1782                          "uCode alternative %d not available, choosing %d\n",
1783                          tmp, wanted_alternative);
1784
1785         priv->ucode_ver = le32_to_cpu(ucode->ver);
1786         pieces->build = le32_to_cpu(ucode->build);
1787         data = ucode->data;
1788
1789         len -= sizeof(*ucode);
1790
1791         while (len >= sizeof(*tlv)) {
1792                 u16 tlv_alt;
1793
1794                 len -= sizeof(*tlv);
1795                 tlv = (void *)data;
1796
1797                 tlv_len = le32_to_cpu(tlv->length);
1798                 tlv_type = le16_to_cpu(tlv->type);
1799                 tlv_alt = le16_to_cpu(tlv->alternative);
1800                 tlv_data = tlv->data;
1801
1802                 if (len < tlv_len) {
1803                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1804                                 len, tlv_len);
1805                         return -EINVAL;
1806                 }
1807                 len -= ALIGN(tlv_len, 4);
1808                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1809
1810                 /*
1811                  * Alternative 0 is always valid.
1812                  *
1813                  * Skip alternative TLVs that are not selected.
1814                  */
1815                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1816                         continue;
1817
1818                 switch (tlv_type) {
1819                 case IWL_UCODE_TLV_INST:
1820                         pieces->inst = tlv_data;
1821                         pieces->inst_size = tlv_len;
1822                         break;
1823                 case IWL_UCODE_TLV_DATA:
1824                         pieces->data = tlv_data;
1825                         pieces->data_size = tlv_len;
1826                         break;
1827                 case IWL_UCODE_TLV_INIT:
1828                         pieces->init = tlv_data;
1829                         pieces->init_size = tlv_len;
1830                         break;
1831                 case IWL_UCODE_TLV_INIT_DATA:
1832                         pieces->init_data = tlv_data;
1833                         pieces->init_data_size = tlv_len;
1834                         break;
1835                 case IWL_UCODE_TLV_BOOT:
1836                         pieces->boot = tlv_data;
1837                         pieces->boot_size = tlv_len;
1838                         break;
1839                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1840                         if (tlv_len != sizeof(u32))
1841                                 goto invalid_tlv_len;
1842                         capa->max_probe_length =
1843                                         le32_to_cpup((__le32 *)tlv_data);
1844                         break;
1845                 case IWL_UCODE_TLV_PAN:
1846                         if (tlv_len)
1847                                 goto invalid_tlv_len;
1848                         capa->pan = true;
1849                         break;
1850                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1851                         if (tlv_len != sizeof(u32))
1852                                 goto invalid_tlv_len;
1853                         pieces->init_evtlog_ptr =
1854                                         le32_to_cpup((__le32 *)tlv_data);
1855                         break;
1856                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1857                         if (tlv_len != sizeof(u32))
1858                                 goto invalid_tlv_len;
1859                         pieces->init_evtlog_size =
1860                                         le32_to_cpup((__le32 *)tlv_data);
1861                         break;
1862                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1863                         if (tlv_len != sizeof(u32))
1864                                 goto invalid_tlv_len;
1865                         pieces->init_errlog_ptr =
1866                                         le32_to_cpup((__le32 *)tlv_data);
1867                         break;
1868                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1869                         if (tlv_len != sizeof(u32))
1870                                 goto invalid_tlv_len;
1871                         pieces->inst_evtlog_ptr =
1872                                         le32_to_cpup((__le32 *)tlv_data);
1873                         break;
1874                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1875                         if (tlv_len != sizeof(u32))
1876                                 goto invalid_tlv_len;
1877                         pieces->inst_evtlog_size =
1878                                         le32_to_cpup((__le32 *)tlv_data);
1879                         break;
1880                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1881                         if (tlv_len != sizeof(u32))
1882                                 goto invalid_tlv_len;
1883                         pieces->inst_errlog_ptr =
1884                                         le32_to_cpup((__le32 *)tlv_data);
1885                         break;
1886                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1887                         if (tlv_len)
1888                                 goto invalid_tlv_len;
1889                         priv->enhance_sensitivity_table = true;
1890                         break;
1891                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1892                         if (tlv_len != sizeof(u32))
1893                                 goto invalid_tlv_len;
1894                         capa->standard_phy_calibration_size =
1895                                         le32_to_cpup((__le32 *)tlv_data);
1896                         break;
1897                 default:
1898                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1899                         break;
1900                 }
1901         }
1902
1903         if (len) {
1904                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1905                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1906                 return -EINVAL;
1907         }
1908
1909         return 0;
1910
1911  invalid_tlv_len:
1912         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1913         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1914
1915         return -EINVAL;
1916 }
1917
1918 /**
1919  * iwl_ucode_callback - callback when firmware was loaded
1920  *
1921  * If loaded successfully, copies the firmware into buffers
1922  * for the card to fetch (via DMA).
1923  */
1924 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1925 {
1926         struct iwl_priv *priv = context;
1927         struct iwl_ucode_header *ucode;
1928         int err;
1929         struct iwlagn_firmware_pieces pieces;
1930         const unsigned int api_max = priv->cfg->ucode_api_max;
1931         const unsigned int api_min = priv->cfg->ucode_api_min;
1932         u32 api_ver;
1933         char buildstr[25];
1934         u32 build;
1935         struct iwlagn_ucode_capabilities ucode_capa = {
1936                 .max_probe_length = 200,
1937                 .standard_phy_calibration_size =
1938                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1939         };
1940
1941         memset(&pieces, 0, sizeof(pieces));
1942
1943         if (!ucode_raw) {
1944                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1945                         IWL_ERR(priv,
1946                                 "request for firmware file '%s' failed.\n",
1947                                 priv->firmware_name);
1948                 goto try_again;
1949         }
1950
1951         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1952                        priv->firmware_name, ucode_raw->size);
1953
1954         /* Make sure that we got at least the API version number */
1955         if (ucode_raw->size < 4) {
1956                 IWL_ERR(priv, "File size way too small!\n");
1957                 goto try_again;
1958         }
1959
1960         /* Data from ucode file:  header followed by uCode images */
1961         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1962
1963         if (ucode->ver)
1964                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1965         else
1966                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1967                                            &ucode_capa);
1968
1969         if (err)
1970                 goto try_again;
1971
1972         api_ver = IWL_UCODE_API(priv->ucode_ver);
1973         build = pieces.build;
1974
1975         /*
1976          * api_ver should match the api version forming part of the
1977          * firmware filename ... but we don't check for that and only rely
1978          * on the API version read from firmware header from here on forward
1979          */
1980         /* no api version check required for experimental uCode */
1981         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1982                 if (api_ver < api_min || api_ver > api_max) {
1983                         IWL_ERR(priv,
1984                                 "Driver unable to support your firmware API. "
1985                                 "Driver supports v%u, firmware is v%u.\n",
1986                                 api_max, api_ver);
1987                         goto try_again;
1988                 }
1989
1990                 if (api_ver != api_max)
1991                         IWL_ERR(priv,
1992                                 "Firmware has old API version. Expected v%u, "
1993                                 "got v%u. New firmware can be obtained "
1994                                 "from http://www.intellinuxwireless.org.\n",
1995                                 api_max, api_ver);
1996         }
1997
1998         if (build)
1999                 sprintf(buildstr, " build %u%s", build,
2000                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2001                                 ? " (EXP)" : "");
2002         else
2003                 buildstr[0] = '\0';
2004
2005         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2006                  IWL_UCODE_MAJOR(priv->ucode_ver),
2007                  IWL_UCODE_MINOR(priv->ucode_ver),
2008                  IWL_UCODE_API(priv->ucode_ver),
2009                  IWL_UCODE_SERIAL(priv->ucode_ver),
2010                  buildstr);
2011
2012         snprintf(priv->hw->wiphy->fw_version,
2013                  sizeof(priv->hw->wiphy->fw_version),
2014                  "%u.%u.%u.%u%s",
2015                  IWL_UCODE_MAJOR(priv->ucode_ver),
2016                  IWL_UCODE_MINOR(priv->ucode_ver),
2017                  IWL_UCODE_API(priv->ucode_ver),
2018                  IWL_UCODE_SERIAL(priv->ucode_ver),
2019                  buildstr);
2020
2021         /*
2022          * For any of the failures below (before allocating pci memory)
2023          * we will try to load a version with a smaller API -- maybe the
2024          * user just got a corrupted version of the latest API.
2025          */
2026
2027         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2028                        priv->ucode_ver);
2029         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2030                        pieces.inst_size);
2031         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2032                        pieces.data_size);
2033         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2034                        pieces.init_size);
2035         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2036                        pieces.init_data_size);
2037         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2038                        pieces.boot_size);
2039
2040         /* Verify that uCode images will fit in card's SRAM */
2041         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2042                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2043                         pieces.inst_size);
2044                 goto try_again;
2045         }
2046
2047         if (pieces.data_size > priv->hw_params.max_data_size) {
2048                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2049                         pieces.data_size);
2050                 goto try_again;
2051         }
2052
2053         if (pieces.init_size > priv->hw_params.max_inst_size) {
2054                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2055                         pieces.init_size);
2056                 goto try_again;
2057         }
2058
2059         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2060                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2061                         pieces.init_data_size);
2062                 goto try_again;
2063         }
2064
2065         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2066                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2067                         pieces.boot_size);
2068                 goto try_again;
2069         }
2070
2071         /* Allocate ucode buffers for card's bus-master loading ... */
2072
2073         /* Runtime instructions and 2 copies of data:
2074          * 1) unmodified from disk
2075          * 2) backup cache for save/restore during power-downs */
2076         priv->ucode_code.len = pieces.inst_size;
2077         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2078
2079         priv->ucode_data.len = pieces.data_size;
2080         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2081
2082         priv->ucode_data_backup.len = pieces.data_size;
2083         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2084
2085         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2086             !priv->ucode_data_backup.v_addr)
2087                 goto err_pci_alloc;
2088
2089         /* Initialization instructions and data */
2090         if (pieces.init_size && pieces.init_data_size) {
2091                 priv->ucode_init.len = pieces.init_size;
2092                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2093
2094                 priv->ucode_init_data.len = pieces.init_data_size;
2095                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2096
2097                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2098                         goto err_pci_alloc;
2099         }
2100
2101         /* Bootstrap (instructions only, no data) */
2102         if (pieces.boot_size) {
2103                 priv->ucode_boot.len = pieces.boot_size;
2104                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2105
2106                 if (!priv->ucode_boot.v_addr)
2107                         goto err_pci_alloc;
2108         }
2109
2110         /* Now that we can no longer fail, copy information */
2111
2112         /*
2113          * The (size - 16) / 12 formula is based on the information recorded
2114          * for each event, which is of mode 1 (including timestamp) for all
2115          * new microcodes that include this information.
2116          */
2117         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2118         if (pieces.init_evtlog_size)
2119                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2120         else
2121                 priv->_agn.init_evtlog_size =
2122                         priv->cfg->base_params->max_event_log_size;
2123         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2124         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2125         if (pieces.inst_evtlog_size)
2126                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2127         else
2128                 priv->_agn.inst_evtlog_size =
2129                         priv->cfg->base_params->max_event_log_size;
2130         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2131
2132         if (ucode_capa.pan) {
2133                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2134                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2135         } else
2136                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2137
2138         /* Copy images into buffers for card's bus-master reads ... */
2139
2140         /* Runtime instructions (first block of data in file) */
2141         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2142                         pieces.inst_size);
2143         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2144
2145         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2146                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2147
2148         /*
2149          * Runtime data
2150          * NOTE:  Copy into backup buffer will be done in iwl_up()
2151          */
2152         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2153                         pieces.data_size);
2154         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2155         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2156
2157         /* Initialization instructions */
2158         if (pieces.init_size) {
2159                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2160                                 pieces.init_size);
2161                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2162         }
2163
2164         /* Initialization data */
2165         if (pieces.init_data_size) {
2166                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2167                                pieces.init_data_size);
2168                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2169                        pieces.init_data_size);
2170         }
2171
2172         /* Bootstrap instructions */
2173         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2174                         pieces.boot_size);
2175         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2176
2177         /*
2178          * figure out the offset of chain noise reset and gain commands
2179          * base on the size of standard phy calibration commands table size
2180          */
2181         if (ucode_capa.standard_phy_calibration_size >
2182             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2183                 ucode_capa.standard_phy_calibration_size =
2184                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2185
2186         priv->_agn.phy_calib_chain_noise_reset_cmd =
2187                 ucode_capa.standard_phy_calibration_size;
2188         priv->_agn.phy_calib_chain_noise_gain_cmd =
2189                 ucode_capa.standard_phy_calibration_size + 1;
2190
2191         /**************************************************
2192          * This is still part of probe() in a sense...
2193          *
2194          * 9. Setup and register with mac80211 and debugfs
2195          **************************************************/
2196         err = iwl_mac_setup_register(priv, &ucode_capa);
2197         if (err)
2198                 goto out_unbind;
2199
2200         err = iwl_dbgfs_register(priv, DRV_NAME);
2201         if (err)
2202                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2203
2204         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2205                                         &iwl_attribute_group);
2206         if (err) {
2207                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2208                 goto out_unbind;
2209         }
2210
2211         /* We have our copies now, allow OS release its copies */
2212         release_firmware(ucode_raw);
2213         complete(&priv->_agn.firmware_loading_complete);
2214         return;
2215
2216  try_again:
2217         /* try next, if any */
2218         if (iwl_request_firmware(priv, false))
2219                 goto out_unbind;
2220         release_firmware(ucode_raw);
2221         return;
2222
2223  err_pci_alloc:
2224         IWL_ERR(priv, "failed to allocate pci memory\n");
2225         iwl_dealloc_ucode_pci(priv);
2226  out_unbind:
2227         complete(&priv->_agn.firmware_loading_complete);
2228         device_release_driver(&priv->pci_dev->dev);
2229         release_firmware(ucode_raw);
2230 }
2231
2232 static const char *desc_lookup_text[] = {
2233         "OK",
2234         "FAIL",
2235         "BAD_PARAM",
2236         "BAD_CHECKSUM",
2237         "NMI_INTERRUPT_WDG",
2238         "SYSASSERT",
2239         "FATAL_ERROR",
2240         "BAD_COMMAND",
2241         "HW_ERROR_TUNE_LOCK",
2242         "HW_ERROR_TEMPERATURE",
2243         "ILLEGAL_CHAN_FREQ",
2244         "VCC_NOT_STABLE",
2245         "FH_ERROR",
2246         "NMI_INTERRUPT_HOST",
2247         "NMI_INTERRUPT_ACTION_PT",
2248         "NMI_INTERRUPT_UNKNOWN",
2249         "UCODE_VERSION_MISMATCH",
2250         "HW_ERROR_ABS_LOCK",
2251         "HW_ERROR_CAL_LOCK_FAIL",
2252         "NMI_INTERRUPT_INST_ACTION_PT",
2253         "NMI_INTERRUPT_DATA_ACTION_PT",
2254         "NMI_TRM_HW_ER",
2255         "NMI_INTERRUPT_TRM",
2256         "NMI_INTERRUPT_BREAK_POINT"
2257         "DEBUG_0",
2258         "DEBUG_1",
2259         "DEBUG_2",
2260         "DEBUG_3",
2261 };
2262
2263 static struct { char *name; u8 num; } advanced_lookup[] = {
2264         { "NMI_INTERRUPT_WDG", 0x34 },
2265         { "SYSASSERT", 0x35 },
2266         { "UCODE_VERSION_MISMATCH", 0x37 },
2267         { "BAD_COMMAND", 0x38 },
2268         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2269         { "FATAL_ERROR", 0x3D },
2270         { "NMI_TRM_HW_ERR", 0x46 },
2271         { "NMI_INTERRUPT_TRM", 0x4C },
2272         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2273         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2274         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2275         { "NMI_INTERRUPT_HOST", 0x66 },
2276         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2277         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2278         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2279         { "ADVANCED_SYSASSERT", 0 },
2280 };
2281
2282 static const char *desc_lookup(u32 num)
2283 {
2284         int i;
2285         int max = ARRAY_SIZE(desc_lookup_text);
2286
2287         if (num < max)
2288                 return desc_lookup_text[num];
2289
2290         max = ARRAY_SIZE(advanced_lookup) - 1;
2291         for (i = 0; i < max; i++) {
2292                 if (advanced_lookup[i].num == num)
2293                         break;;
2294         }
2295         return advanced_lookup[i].name;
2296 }
2297
2298 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2299 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2300
2301 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2302 {
2303         u32 data2, line;
2304         u32 desc, time, count, base, data1;
2305         u32 blink1, blink2, ilink1, ilink2;
2306         u32 pc, hcmd;
2307
2308         if (priv->ucode_type == UCODE_INIT) {
2309                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2310                 if (!base)
2311                         base = priv->_agn.init_errlog_ptr;
2312         } else {
2313                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2314                 if (!base)
2315                         base = priv->_agn.inst_errlog_ptr;
2316         }
2317
2318         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2319                 IWL_ERR(priv,
2320                         "Not valid error log pointer 0x%08X for %s uCode\n",
2321                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2322                 return;
2323         }
2324
2325         count = iwl_read_targ_mem(priv, base);
2326
2327         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2328                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2329                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2330                         priv->status, count);
2331         }
2332
2333         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2334         priv->isr_stats.err_code = desc;
2335         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2336         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2337         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2338         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2339         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2340         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2341         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2342         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2343         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2344         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2345
2346         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2347                                       blink1, blink2, ilink1, ilink2);
2348
2349         IWL_ERR(priv, "Desc                                  Time       "
2350                 "data1      data2      line\n");
2351         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2352                 desc_lookup(desc), desc, time, data1, data2, line);
2353         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2354         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2355                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2356 }
2357
2358 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2359
2360 /**
2361  * iwl_print_event_log - Dump error event log to syslog
2362  *
2363  */
2364 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2365                                u32 num_events, u32 mode,
2366                                int pos, char **buf, size_t bufsz)
2367 {
2368         u32 i;
2369         u32 base;       /* SRAM byte address of event log header */
2370         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2371         u32 ptr;        /* SRAM byte address of log data */
2372         u32 ev, time, data; /* event log data */
2373         unsigned long reg_flags;
2374
2375         if (num_events == 0)
2376                 return pos;
2377
2378         if (priv->ucode_type == UCODE_INIT) {
2379                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2380                 if (!base)
2381                         base = priv->_agn.init_evtlog_ptr;
2382         } else {
2383                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2384                 if (!base)
2385                         base = priv->_agn.inst_evtlog_ptr;
2386         }
2387
2388         if (mode == 0)
2389                 event_size = 2 * sizeof(u32);
2390         else
2391                 event_size = 3 * sizeof(u32);
2392
2393         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2394
2395         /* Make sure device is powered up for SRAM reads */
2396         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2397         iwl_grab_nic_access(priv);
2398
2399         /* Set starting address; reads will auto-increment */
2400         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2401         rmb();
2402
2403         /* "time" is actually "data" for mode 0 (no timestamp).
2404         * place event id # at far right for easier visual parsing. */
2405         for (i = 0; i < num_events; i++) {
2406                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2407                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2408                 if (mode == 0) {
2409                         /* data, ev */
2410                         if (bufsz) {
2411                                 pos += scnprintf(*buf + pos, bufsz - pos,
2412                                                 "EVT_LOG:0x%08x:%04u\n",
2413                                                 time, ev);
2414                         } else {
2415                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2416                                         time, ev);
2417                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2418                                         time, ev);
2419                         }
2420                 } else {
2421                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2422                         if (bufsz) {
2423                                 pos += scnprintf(*buf + pos, bufsz - pos,
2424                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2425                                                  time, data, ev);
2426                         } else {
2427                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2428                                         time, data, ev);
2429                                 trace_iwlwifi_dev_ucode_event(priv, time,
2430                                         data, ev);
2431                         }
2432                 }
2433         }
2434
2435         /* Allow device to power down */
2436         iwl_release_nic_access(priv);
2437         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2438         return pos;
2439 }
2440
2441 /**
2442  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2443  */
2444 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2445                                     u32 num_wraps, u32 next_entry,
2446                                     u32 size, u32 mode,
2447                                     int pos, char **buf, size_t bufsz)
2448 {
2449         /*
2450          * display the newest DEFAULT_LOG_ENTRIES entries
2451          * i.e the entries just before the next ont that uCode would fill.
2452          */
2453         if (num_wraps) {
2454                 if (next_entry < size) {
2455                         pos = iwl_print_event_log(priv,
2456                                                 capacity - (size - next_entry),
2457                                                 size - next_entry, mode,
2458                                                 pos, buf, bufsz);
2459                         pos = iwl_print_event_log(priv, 0,
2460                                                   next_entry, mode,
2461                                                   pos, buf, bufsz);
2462                 } else
2463                         pos = iwl_print_event_log(priv, next_entry - size,
2464                                                   size, mode, pos, buf, bufsz);
2465         } else {
2466                 if (next_entry < size) {
2467                         pos = iwl_print_event_log(priv, 0, next_entry,
2468                                                   mode, pos, buf, bufsz);
2469                 } else {
2470                         pos = iwl_print_event_log(priv, next_entry - size,
2471                                                   size, mode, pos, buf, bufsz);
2472                 }
2473         }
2474         return pos;
2475 }
2476
2477 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2478
2479 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2480                             char **buf, bool display)
2481 {
2482         u32 base;       /* SRAM byte address of event log header */
2483         u32 capacity;   /* event log capacity in # entries */
2484         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2485         u32 num_wraps;  /* # times uCode wrapped to top of log */
2486         u32 next_entry; /* index of next entry to be written by uCode */
2487         u32 size;       /* # entries that we'll print */
2488         u32 logsize;
2489         int pos = 0;
2490         size_t bufsz = 0;
2491
2492         if (priv->ucode_type == UCODE_INIT) {
2493                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2494                 logsize = priv->_agn.init_evtlog_size;
2495                 if (!base)
2496                         base = priv->_agn.init_evtlog_ptr;
2497         } else {
2498                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2499                 logsize = priv->_agn.inst_evtlog_size;
2500                 if (!base)
2501                         base = priv->_agn.inst_evtlog_ptr;
2502         }
2503
2504         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2505                 IWL_ERR(priv,
2506                         "Invalid event log pointer 0x%08X for %s uCode\n",
2507                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2508                 return -EINVAL;
2509         }
2510
2511         /* event log header */
2512         capacity = iwl_read_targ_mem(priv, base);
2513         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2514         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2515         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2516
2517         if (capacity > logsize) {
2518                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2519                         capacity, logsize);
2520                 capacity = logsize;
2521         }
2522
2523         if (next_entry > logsize) {
2524                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2525                         next_entry, logsize);
2526                 next_entry = logsize;
2527         }
2528
2529         size = num_wraps ? capacity : next_entry;
2530
2531         /* bail out if nothing in log */
2532         if (size == 0) {
2533                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2534                 return pos;
2535         }
2536
2537         /* enable/disable bt channel inhibition */
2538         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2539
2540 #ifdef CONFIG_IWLWIFI_DEBUG
2541         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2542                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2543                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2544 #else
2545         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2546                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2547 #endif
2548         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2549                 size);
2550
2551 #ifdef CONFIG_IWLWIFI_DEBUG
2552         if (display) {
2553                 if (full_log)
2554                         bufsz = capacity * 48;
2555                 else
2556                         bufsz = size * 48;
2557                 *buf = kmalloc(bufsz, GFP_KERNEL);
2558                 if (!*buf)
2559                         return -ENOMEM;
2560         }
2561         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2562                 /*
2563                  * if uCode has wrapped back to top of log,
2564                  * start at the oldest entry,
2565                  * i.e the next one that uCode would fill.
2566                  */
2567                 if (num_wraps)
2568                         pos = iwl_print_event_log(priv, next_entry,
2569                                                 capacity - next_entry, mode,
2570                                                 pos, buf, bufsz);
2571                 /* (then/else) start at top of log */
2572                 pos = iwl_print_event_log(priv, 0,
2573                                           next_entry, mode, pos, buf, bufsz);
2574         } else
2575                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2576                                                 next_entry, size, mode,
2577                                                 pos, buf, bufsz);
2578 #else
2579         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2580                                         next_entry, size, mode,
2581                                         pos, buf, bufsz);
2582 #endif
2583         return pos;
2584 }
2585
2586 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2587 {
2588         struct iwl_ct_kill_config cmd;
2589         struct iwl_ct_kill_throttling_config adv_cmd;
2590         unsigned long flags;
2591         int ret = 0;
2592
2593         spin_lock_irqsave(&priv->lock, flags);
2594         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2595                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2596         spin_unlock_irqrestore(&priv->lock, flags);
2597         priv->thermal_throttle.ct_kill_toggle = false;
2598
2599         if (priv->cfg->base_params->support_ct_kill_exit) {
2600                 adv_cmd.critical_temperature_enter =
2601                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2602                 adv_cmd.critical_temperature_exit =
2603                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2604
2605                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2606                                        sizeof(adv_cmd), &adv_cmd);
2607                 if (ret)
2608                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2609                 else
2610                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2611                                         "succeeded, "
2612                                         "critical temperature enter is %d,"
2613                                         "exit is %d\n",
2614                                        priv->hw_params.ct_kill_threshold,
2615                                        priv->hw_params.ct_kill_exit_threshold);
2616         } else {
2617                 cmd.critical_temperature_R =
2618                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2619
2620                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2621                                        sizeof(cmd), &cmd);
2622                 if (ret)
2623                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2624                 else
2625                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2626                                         "succeeded, "
2627                                         "critical temperature is %d\n",
2628                                         priv->hw_params.ct_kill_threshold);
2629         }
2630 }
2631
2632 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2633 {
2634         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2635         struct iwl_host_cmd cmd = {
2636                 .id = CALIBRATION_CFG_CMD,
2637                 .len = sizeof(struct iwl_calib_cfg_cmd),
2638                 .data = &calib_cfg_cmd,
2639         };
2640
2641         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2642         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2643         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2644
2645         return iwl_send_cmd(priv, &cmd);
2646 }
2647
2648
2649 /**
2650  * iwl_alive_start - called after REPLY_ALIVE notification received
2651  *                   from protocol/runtime uCode (initialization uCode's
2652  *                   Alive gets handled by iwl_init_alive_start()).
2653  */
2654 static void iwl_alive_start(struct iwl_priv *priv)
2655 {
2656         int ret = 0;
2657         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2658
2659         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2660
2661         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2662          * This is a paranoid check, because we would not have gotten the
2663          * "runtime" alive if code weren't properly loaded.  */
2664         if (iwl_verify_ucode(priv)) {
2665                 /* Runtime instruction load was bad;
2666                  * take it all the way back down so we can try again */
2667                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2668                 goto restart;
2669         }
2670
2671         ret = priv->cfg->ops->lib->alive_notify(priv);
2672         if (ret) {
2673                 IWL_WARN(priv,
2674                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2675                 goto restart;
2676         }
2677
2678
2679         /* After the ALIVE response, we can send host commands to the uCode */
2680         set_bit(STATUS_ALIVE, &priv->status);
2681
2682         /* Enable watchdog to monitor the driver tx queues */
2683         iwl_setup_watchdog(priv);
2684
2685         if (iwl_is_rfkill(priv))
2686                 return;
2687
2688         /* download priority table before any calibration request */
2689         if (priv->cfg->bt_params &&
2690             priv->cfg->bt_params->advanced_bt_coexist) {
2691                 /* Configure Bluetooth device coexistence support */
2692                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2693                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2694                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2695                 priv->cfg->ops->hcmd->send_bt_config(priv);
2696                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2697                 iwlagn_send_prio_tbl(priv);
2698
2699                 /* FIXME: w/a to force change uCode BT state machine */
2700                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2701                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2702                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2703                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2704         }
2705         if (priv->hw_params.calib_rt_cfg)
2706                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2707
2708         ieee80211_wake_queues(priv->hw);
2709
2710         priv->active_rate = IWL_RATES_MASK;
2711
2712         /* Configure Tx antenna selection based on H/W config */
2713         if (priv->cfg->ops->hcmd->set_tx_ant)
2714                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2715
2716         if (iwl_is_associated_ctx(ctx)) {
2717                 struct iwl_rxon_cmd *active_rxon =
2718                                 (struct iwl_rxon_cmd *)&ctx->active;
2719                 /* apply any changes in staging */
2720                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2721                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2722         } else {
2723                 struct iwl_rxon_context *tmp;
2724                 /* Initialize our rx_config data */
2725                 for_each_context(priv, tmp)
2726                         iwl_connection_init_rx_config(priv, tmp);
2727
2728                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2729                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2730         }
2731
2732         if (priv->cfg->bt_params &&
2733             !priv->cfg->bt_params->advanced_bt_coexist) {
2734                 /* Configure Bluetooth device coexistence support */
2735                 priv->cfg->ops->hcmd->send_bt_config(priv);
2736         }
2737
2738         iwl_reset_run_time_calib(priv);
2739
2740         set_bit(STATUS_READY, &priv->status);
2741
2742         /* Configure the adapter for unassociated operation */
2743         iwlcore_commit_rxon(priv, ctx);
2744
2745         /* At this point, the NIC is initialized and operational */
2746         iwl_rf_kill_ct_config(priv);
2747
2748         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2749         wake_up_interruptible(&priv->wait_command_queue);
2750
2751         iwl_power_update_mode(priv, true);
2752         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2753
2754
2755         return;
2756
2757  restart:
2758         queue_work(priv->workqueue, &priv->restart);
2759 }
2760
2761 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2762
2763 static void __iwl_down(struct iwl_priv *priv)
2764 {
2765         unsigned long flags;
2766         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2767
2768         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2769
2770         iwl_scan_cancel_timeout(priv, 200);
2771
2772         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2773
2774         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2775          * to prevent rearm timer */
2776         del_timer_sync(&priv->watchdog);
2777
2778         iwl_clear_ucode_stations(priv, NULL);
2779         iwl_dealloc_bcast_stations(priv);
2780         iwl_clear_driver_stations(priv);
2781
2782         /* reset BT coex data */
2783         priv->bt_status = 0;
2784         if (priv->cfg->bt_params)
2785                 priv->bt_traffic_load =
2786                          priv->cfg->bt_params->bt_init_traffic_load;
2787         else
2788                 priv->bt_traffic_load = 0;
2789         priv->bt_full_concurrent = false;
2790         priv->bt_ci_compliance = 0;
2791
2792         /* Unblock any waiting calls */
2793         wake_up_interruptible_all(&priv->wait_command_queue);
2794
2795         /* Wipe out the EXIT_PENDING status bit if we are not actually
2796          * exiting the module */
2797         if (!exit_pending)
2798                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2799
2800         /* stop and reset the on-board processor */
2801         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2802
2803         /* tell the device to stop sending interrupts */
2804         spin_lock_irqsave(&priv->lock, flags);
2805         iwl_disable_interrupts(priv);
2806         spin_unlock_irqrestore(&priv->lock, flags);
2807         iwl_synchronize_irq(priv);
2808
2809         if (priv->mac80211_registered)
2810                 ieee80211_stop_queues(priv->hw);
2811
2812         /* If we have not previously called iwl_init() then
2813          * clear all bits but the RF Kill bit and return */
2814         if (!iwl_is_init(priv)) {
2815                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2816                                         STATUS_RF_KILL_HW |
2817                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2818                                         STATUS_GEO_CONFIGURED |
2819                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2820                                         STATUS_EXIT_PENDING;
2821                 goto exit;
2822         }
2823
2824         /* ...otherwise clear out all the status bits but the RF Kill
2825          * bit and continue taking the NIC down. */
2826         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2827                                 STATUS_RF_KILL_HW |
2828                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2829                                 STATUS_GEO_CONFIGURED |
2830                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2831                                 STATUS_FW_ERROR |
2832                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2833                                 STATUS_EXIT_PENDING;
2834
2835         /* device going down, Stop using ICT table */
2836         if (priv->cfg->ops->lib->isr_ops.disable)
2837                 priv->cfg->ops->lib->isr_ops.disable(priv);
2838
2839         iwlagn_txq_ctx_stop(priv);
2840         iwlagn_rxq_stop(priv);
2841
2842         /* Power-down device's busmaster DMA clocks */
2843         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2844         udelay(5);
2845
2846         /* Make sure (redundant) we've released our request to stay awake */
2847         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2848
2849         /* Stop the device, and put it in low power state */
2850         iwl_apm_stop(priv);
2851
2852  exit:
2853         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2854
2855         dev_kfree_skb(priv->beacon_skb);
2856         priv->beacon_skb = NULL;
2857
2858         /* clear out any free frames */
2859         iwl_clear_free_frames(priv);
2860 }
2861
2862 static void iwl_down(struct iwl_priv *priv)
2863 {
2864         mutex_lock(&priv->mutex);
2865         __iwl_down(priv);
2866         mutex_unlock(&priv->mutex);
2867
2868         iwl_cancel_deferred_work(priv);
2869 }
2870
2871 #define HW_READY_TIMEOUT (50)
2872
2873 static int iwl_set_hw_ready(struct iwl_priv *priv)
2874 {
2875         int ret = 0;
2876
2877         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2878                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2879
2880         /* See if we got it */
2881         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2882                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2883                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2884                                 HW_READY_TIMEOUT);
2885         if (ret != -ETIMEDOUT)
2886                 priv->hw_ready = true;
2887         else
2888                 priv->hw_ready = false;
2889
2890         IWL_DEBUG_INFO(priv, "hardware %s\n",
2891                       (priv->hw_ready == 1) ? "ready" : "not ready");
2892         return ret;
2893 }
2894
2895 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2896 {
2897         int ret = 0;
2898
2899         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2900
2901         ret = iwl_set_hw_ready(priv);
2902         if (priv->hw_ready)
2903                 return ret;
2904
2905         /* If HW is not ready, prepare the conditions to check again */
2906         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2907                         CSR_HW_IF_CONFIG_REG_PREPARE);
2908
2909         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2910                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2911                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2912
2913         /* HW should be ready by now, check again. */
2914         if (ret != -ETIMEDOUT)
2915                 iwl_set_hw_ready(priv);
2916
2917         return ret;
2918 }
2919
2920 #define MAX_HW_RESTARTS 5
2921
2922 static int __iwl_up(struct iwl_priv *priv)
2923 {
2924         struct iwl_rxon_context *ctx;
2925         int i;
2926         int ret;
2927
2928         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2929                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2930                 return -EIO;
2931         }
2932
2933         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2934                 IWL_ERR(priv, "ucode not available for device bringup\n");
2935                 return -EIO;
2936         }
2937
2938         for_each_context(priv, ctx) {
2939                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2940                 if (ret) {
2941                         iwl_dealloc_bcast_stations(priv);
2942                         return ret;
2943                 }
2944         }
2945
2946         iwl_prepare_card_hw(priv);
2947
2948         if (!priv->hw_ready) {
2949                 IWL_WARN(priv, "Exit HW not ready\n");
2950                 return -EIO;
2951         }
2952
2953         /* If platform's RF_KILL switch is NOT set to KILL */
2954         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2955                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2956         else
2957                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2958
2959         if (iwl_is_rfkill(priv)) {
2960                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2961
2962                 iwl_enable_interrupts(priv);
2963                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2964                 return 0;
2965         }
2966
2967         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2968
2969         /* must be initialised before iwl_hw_nic_init */
2970         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2971                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2972         else
2973                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2974
2975         ret = iwlagn_hw_nic_init(priv);
2976         if (ret) {
2977                 IWL_ERR(priv, "Unable to init nic\n");
2978                 return ret;
2979         }
2980
2981         /* make sure rfkill handshake bits are cleared */
2982         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2983         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2984                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2985
2986         /* clear (again), then enable host interrupts */
2987         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2988         iwl_enable_interrupts(priv);
2989
2990         /* really make sure rfkill handshake bits are cleared */
2991         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2992         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2993
2994         /* Copy original ucode data image from disk into backup cache.
2995          * This will be used to initialize the on-board processor's
2996          * data SRAM for a clean start when the runtime program first loads. */
2997         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2998                priv->ucode_data.len);
2999
3000         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3001
3002                 /* load bootstrap state machine,
3003                  * load bootstrap program into processor's memory,
3004                  * prepare to load the "initialize" uCode */
3005                 ret = priv->cfg->ops->lib->load_ucode(priv);
3006
3007                 if (ret) {
3008                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3009                                 ret);
3010                         continue;
3011                 }
3012
3013                 /* start card; "initialize" will load runtime ucode */
3014                 iwl_nic_start(priv);
3015
3016                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3017
3018                 return 0;
3019         }
3020
3021         set_bit(STATUS_EXIT_PENDING, &priv->status);
3022         __iwl_down(priv);
3023         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3024
3025         /* tried to restart and config the device for as long as our
3026          * patience could withstand */
3027         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3028         return -EIO;
3029 }
3030
3031
3032 /*****************************************************************************
3033  *
3034  * Workqueue callbacks
3035  *
3036  *****************************************************************************/
3037
3038 static void iwl_bg_init_alive_start(struct work_struct *data)
3039 {
3040         struct iwl_priv *priv =
3041             container_of(data, struct iwl_priv, init_alive_start.work);
3042
3043         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3044                 return;
3045
3046         mutex_lock(&priv->mutex);
3047         priv->cfg->ops->lib->init_alive_start(priv);
3048         mutex_unlock(&priv->mutex);
3049 }
3050
3051 static void iwl_bg_alive_start(struct work_struct *data)
3052 {
3053         struct iwl_priv *priv =
3054             container_of(data, struct iwl_priv, alive_start.work);
3055
3056         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3057                 return;
3058
3059         /* enable dram interrupt */
3060         if (priv->cfg->ops->lib->isr_ops.reset)
3061                 priv->cfg->ops->lib->isr_ops.reset(priv);
3062
3063         mutex_lock(&priv->mutex);
3064         iwl_alive_start(priv);
3065         mutex_unlock(&priv->mutex);
3066 }
3067
3068 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3069 {
3070         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3071                         run_time_calib_work);
3072
3073         mutex_lock(&priv->mutex);
3074
3075         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3076             test_bit(STATUS_SCANNING, &priv->status)) {
3077                 mutex_unlock(&priv->mutex);
3078                 return;
3079         }
3080
3081         if (priv->start_calib) {
3082                 if (iwl_bt_statistics(priv)) {
3083                         iwl_chain_noise_calibration(priv,
3084                                         (void *)&priv->_agn.statistics_bt);
3085                         iwl_sensitivity_calibration(priv,
3086                                         (void *)&priv->_agn.statistics_bt);
3087                 } else {
3088                         iwl_chain_noise_calibration(priv,
3089                                         (void *)&priv->_agn.statistics);
3090                         iwl_sensitivity_calibration(priv,
3091                                         (void *)&priv->_agn.statistics);
3092                 }
3093         }
3094
3095         mutex_unlock(&priv->mutex);
3096 }
3097
3098 static void iwl_bg_restart(struct work_struct *data)
3099 {
3100         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3101
3102         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3103                 return;
3104
3105         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3106                 struct iwl_rxon_context *ctx;
3107                 bool bt_full_concurrent;
3108                 u8 bt_ci_compliance;
3109                 u8 bt_load;
3110                 u8 bt_status;
3111
3112                 mutex_lock(&priv->mutex);
3113                 for_each_context(priv, ctx)
3114                         ctx->vif = NULL;
3115                 priv->is_open = 0;
3116
3117                 /*
3118                  * __iwl_down() will clear the BT status variables,
3119                  * which is correct, but when we restart we really
3120                  * want to keep them so restore them afterwards.
3121                  *
3122                  * The restart process will later pick them up and
3123                  * re-configure the hw when we reconfigure the BT
3124                  * command.
3125                  */
3126                 bt_full_concurrent = priv->bt_full_concurrent;
3127                 bt_ci_compliance = priv->bt_ci_compliance;
3128                 bt_load = priv->bt_traffic_load;
3129                 bt_status = priv->bt_status;
3130
3131                 __iwl_down(priv);
3132
3133                 priv->bt_full_concurrent = bt_full_concurrent;
3134                 priv->bt_ci_compliance = bt_ci_compliance;
3135                 priv->bt_traffic_load = bt_load;
3136                 priv->bt_status = bt_status;
3137
3138                 mutex_unlock(&priv->mutex);
3139                 iwl_cancel_deferred_work(priv);
3140                 ieee80211_restart_hw(priv->hw);
3141         } else {
3142                 iwl_down(priv);
3143
3144                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3145                         return;
3146
3147                 mutex_lock(&priv->mutex);
3148                 __iwl_up(priv);
3149                 mutex_unlock(&priv->mutex);
3150         }
3151 }
3152
3153 static void iwl_bg_rx_replenish(struct work_struct *data)
3154 {
3155         struct iwl_priv *priv =
3156             container_of(data, struct iwl_priv, rx_replenish);
3157
3158         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3159                 return;
3160
3161         mutex_lock(&priv->mutex);
3162         iwlagn_rx_replenish(priv);
3163         mutex_unlock(&priv->mutex);
3164 }
3165
3166 /*****************************************************************************
3167  *
3168  * mac80211 entry point functions
3169  *
3170  *****************************************************************************/
3171
3172 #define UCODE_READY_TIMEOUT     (4 * HZ)
3173
3174 /*
3175  * Not a mac80211 entry point function, but it fits in with all the
3176  * other mac80211 functions grouped here.
3177  */
3178 static int iwl_mac_setup_register(struct iwl_priv *priv,
3179                                   struct iwlagn_ucode_capabilities *capa)
3180 {
3181         int ret;
3182         struct ieee80211_hw *hw = priv->hw;
3183         struct iwl_rxon_context *ctx;
3184
3185         hw->rate_control_algorithm = "iwl-agn-rs";
3186
3187         /* Tell mac80211 our characteristics */
3188         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3189                     IEEE80211_HW_AMPDU_AGGREGATION |
3190                     IEEE80211_HW_NEED_DTIM_PERIOD |
3191                     IEEE80211_HW_SPECTRUM_MGMT |
3192                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3193
3194         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3195
3196         if (!priv->cfg->base_params->broken_powersave)
3197                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3198                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3199
3200         if (priv->cfg->sku & IWL_SKU_N)
3201                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3202                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3203
3204         hw->sta_data_size = sizeof(struct iwl_station_priv);
3205         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3206
3207         for_each_context(priv, ctx) {
3208                 hw->wiphy->interface_modes |= ctx->interface_modes;
3209                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3210         }
3211
3212         hw->wiphy->max_remain_on_channel_duration = 1000;
3213
3214         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3215                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3216                             WIPHY_FLAG_IBSS_RSN;
3217
3218         /*
3219          * For now, disable PS by default because it affects
3220          * RX performance significantly.
3221          */
3222         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3223
3224         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3225         /* we create the 802.11 header and a zero-length SSID element */
3226         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3227
3228         /* Default value; 4 EDCA QOS priorities */
3229         hw->queues = 4;
3230
3231         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3232
3233         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3234                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3235                         &priv->bands[IEEE80211_BAND_2GHZ];
3236         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3237                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3238                         &priv->bands[IEEE80211_BAND_5GHZ];
3239
3240         iwl_leds_init(priv);
3241
3242         ret = ieee80211_register_hw(priv->hw);
3243         if (ret) {
3244                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3245                 return ret;
3246         }
3247         priv->mac80211_registered = 1;
3248
3249         return 0;
3250 }
3251
3252
3253 int iwlagn_mac_start(struct ieee80211_hw *hw)
3254 {
3255         struct iwl_priv *priv = hw->priv;
3256         int ret;
3257
3258         IWL_DEBUG_MAC80211(priv, "enter\n");
3259
3260         /* we should be verifying the device is ready to be opened */
3261         mutex_lock(&priv->mutex);
3262         ret = __iwl_up(priv);
3263         mutex_unlock(&priv->mutex);
3264
3265         if (ret)
3266                 return ret;
3267
3268         if (iwl_is_rfkill(priv))
3269                 goto out;
3270
3271         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3272
3273         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3274          * mac80211 will not be run successfully. */
3275         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3276                         test_bit(STATUS_READY, &priv->status),
3277                         UCODE_READY_TIMEOUT);
3278         if (!ret) {
3279                 if (!test_bit(STATUS_READY, &priv->status)) {
3280                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3281                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3282                         return -ETIMEDOUT;
3283                 }
3284         }
3285
3286         iwlagn_led_enable(priv);
3287
3288 out:
3289         priv->is_open = 1;
3290         IWL_DEBUG_MAC80211(priv, "leave\n");
3291         return 0;
3292 }
3293
3294 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3295 {
3296         struct iwl_priv *priv = hw->priv;
3297
3298         IWL_DEBUG_MAC80211(priv, "enter\n");
3299
3300         if (!priv->is_open)
3301                 return;
3302
3303         priv->is_open = 0;
3304
3305         iwl_down(priv);
3306
3307         flush_workqueue(priv->workqueue);
3308
3309         /* User space software may expect getting rfkill changes
3310          * even if interface is down */
3311         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3312         iwl_enable_rfkill_int(priv);
3313
3314         IWL_DEBUG_MAC80211(priv, "leave\n");
3315 }
3316
3317 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3318 {
3319         struct iwl_priv *priv = hw->priv;
3320
3321         IWL_DEBUG_MACDUMP(priv, "enter\n");
3322
3323         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3324                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3325
3326         if (iwlagn_tx_skb(priv, skb))
3327                 dev_kfree_skb_any(skb);
3328
3329         IWL_DEBUG_MACDUMP(priv, "leave\n");
3330         return NETDEV_TX_OK;
3331 }
3332
3333 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3334                                 struct ieee80211_vif *vif,
3335                                 struct ieee80211_key_conf *keyconf,
3336                                 struct ieee80211_sta *sta,
3337                                 u32 iv32, u16 *phase1key)
3338 {
3339         struct iwl_priv *priv = hw->priv;
3340         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3341
3342         IWL_DEBUG_MAC80211(priv, "enter\n");
3343
3344         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3345                             iv32, phase1key);
3346
3347         IWL_DEBUG_MAC80211(priv, "leave\n");
3348 }
3349
3350 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3351                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3352                        struct ieee80211_key_conf *key)
3353 {
3354         struct iwl_priv *priv = hw->priv;
3355         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3356         struct iwl_rxon_context *ctx = vif_priv->ctx;
3357         int ret;
3358         u8 sta_id;
3359         bool is_default_wep_key = false;
3360
3361         IWL_DEBUG_MAC80211(priv, "enter\n");
3362
3363         if (priv->cfg->mod_params->sw_crypto) {
3364                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3365                 return -EOPNOTSUPP;
3366         }
3367
3368         /*
3369          * To support IBSS RSN, don't program group keys in IBSS, the
3370          * hardware will then not attempt to decrypt the frames.
3371          */
3372         if (vif->type == NL80211_IFTYPE_ADHOC &&
3373             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3374                 return -EOPNOTSUPP;
3375
3376         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3377         if (sta_id == IWL_INVALID_STATION)
3378                 return -EINVAL;
3379
3380         mutex_lock(&priv->mutex);
3381         iwl_scan_cancel_timeout(priv, 100);
3382
3383         /*
3384          * If we are getting WEP group key and we didn't receive any key mapping
3385          * so far, we are in legacy wep mode (group key only), otherwise we are
3386          * in 1X mode.
3387          * In legacy wep mode, we use another host command to the uCode.
3388          */
3389         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3390              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3391             !sta) {
3392                 if (cmd == SET_KEY)
3393                         is_default_wep_key = !ctx->key_mapping_keys;
3394                 else
3395                         is_default_wep_key =
3396                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3397         }
3398
3399         switch (cmd) {
3400         case SET_KEY:
3401                 if (is_default_wep_key)
3402                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3403                 else
3404                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3405                                                   key, sta_id);
3406
3407                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3408                 break;
3409         case DISABLE_KEY:
3410                 if (is_default_wep_key)
3411                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3412                 else
3413                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3414
3415                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3416                 break;
3417         default:
3418                 ret = -EINVAL;
3419         }
3420
3421         mutex_unlock(&priv->mutex);
3422         IWL_DEBUG_MAC80211(priv, "leave\n");
3423
3424         return ret;
3425 }
3426
3427 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3428                             struct ieee80211_vif *vif,
3429                             enum ieee80211_ampdu_mlme_action action,
3430                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3431                             u8 buf_size)
3432 {
3433         struct iwl_priv *priv = hw->priv;
3434         int ret = -EINVAL;
3435         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3436
3437         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3438                      sta->addr, tid);
3439
3440         if (!(priv->cfg->sku & IWL_SKU_N))
3441                 return -EACCES;
3442
3443         mutex_lock(&priv->mutex);
3444
3445         switch (action) {
3446         case IEEE80211_AMPDU_RX_START:
3447                 IWL_DEBUG_HT(priv, "start Rx\n");
3448                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3449                 break;
3450         case IEEE80211_AMPDU_RX_STOP:
3451                 IWL_DEBUG_HT(priv, "stop Rx\n");
3452                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3453                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3454                         ret = 0;
3455                 break;
3456         case IEEE80211_AMPDU_TX_START:
3457                 IWL_DEBUG_HT(priv, "start Tx\n");
3458                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3459                 if (ret == 0) {
3460                         priv->_agn.agg_tids_count++;
3461                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3462                                      priv->_agn.agg_tids_count);
3463                 }
3464                 break;
3465         case IEEE80211_AMPDU_TX_STOP:
3466                 IWL_DEBUG_HT(priv, "stop Tx\n");
3467                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3468                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3469                         priv->_agn.agg_tids_count--;
3470                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3471                                      priv->_agn.agg_tids_count);
3472                 }
3473                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3474                         ret = 0;
3475                 if (priv->cfg->ht_params &&
3476                     priv->cfg->ht_params->use_rts_for_aggregation) {
3477                         struct iwl_station_priv *sta_priv =
3478                                 (void *) sta->drv_priv;
3479                         /*
3480                          * switch off RTS/CTS if it was previously enabled
3481                          */
3482
3483                         sta_priv->lq_sta.lq.general_params.flags &=
3484                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3485                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3486                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3487                 }
3488                 break;
3489         case IEEE80211_AMPDU_TX_OPERATIONAL:
3490                 /*
3491                  * If the limit is 0, then it wasn't initialised yet,
3492                  * use the default. We can do that since we take the
3493                  * minimum below, and we don't want to go above our
3494                  * default due to hardware restrictions.
3495                  */
3496                 if (sta_priv->max_agg_bufsize == 0)
3497                         sta_priv->max_agg_bufsize =
3498                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3499
3500                 /*
3501                  * Even though in theory the peer could have different
3502                  * aggregation reorder buffer sizes for different sessions,
3503                  * our ucode doesn't allow for that and has a global limit
3504                  * for each station. Therefore, use the minimum of all the
3505                  * aggregation sessions and our default value.
3506                  */
3507                 sta_priv->max_agg_bufsize =
3508                         min(sta_priv->max_agg_bufsize, buf_size);
3509
3510                 if (priv->cfg->ht_params &&
3511                     priv->cfg->ht_params->use_rts_for_aggregation) {
3512                         /*
3513                          * switch to RTS/CTS if it is the prefer protection
3514                          * method for HT traffic
3515                          */
3516
3517                         sta_priv->lq_sta.lq.general_params.flags |=
3518                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3519                 }
3520
3521                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3522                         sta_priv->max_agg_bufsize;
3523
3524                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3525                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3526                 ret = 0;
3527                 break;
3528         }
3529         mutex_unlock(&priv->mutex);
3530
3531         return ret;
3532 }
3533
3534 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3535                        struct ieee80211_vif *vif,
3536                        struct ieee80211_sta *sta)
3537 {
3538         struct iwl_priv *priv = hw->priv;
3539         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3540         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3541         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3542         int ret;
3543         u8 sta_id;
3544
3545         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3546                         sta->addr);
3547         mutex_lock(&priv->mutex);
3548         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3549                         sta->addr);
3550         sta_priv->common.sta_id = IWL_INVALID_STATION;
3551
3552         atomic_set(&sta_priv->pending_frames, 0);
3553         if (vif->type == NL80211_IFTYPE_AP)
3554                 sta_priv->client = true;
3555
3556         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3557                                      is_ap, sta, &sta_id);
3558         if (ret) {
3559                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3560                         sta->addr, ret);
3561                 /* Should we return success if return code is EEXIST ? */
3562                 mutex_unlock(&priv->mutex);
3563                 return ret;
3564         }
3565
3566         sta_priv->common.sta_id = sta_id;
3567
3568         /* Initialize rate scaling */
3569         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3570                        sta->addr);
3571         iwl_rs_rate_init(priv, sta, sta_id);
3572         mutex_unlock(&priv->mutex);
3573
3574         return 0;
3575 }
3576
3577 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3578                                struct ieee80211_channel_switch *ch_switch)
3579 {
3580         struct iwl_priv *priv = hw->priv;
3581         const struct iwl_channel_info *ch_info;
3582         struct ieee80211_conf *conf = &hw->conf;
3583         struct ieee80211_channel *channel = ch_switch->channel;
3584         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3585         /*
3586          * MULTI-FIXME
3587          * When we add support for multiple interfaces, we need to
3588          * revisit this. The channel switch command in the device
3589          * only affects the BSS context, but what does that really
3590          * mean? And what if we get a CSA on the second interface?
3591          * This needs a lot of work.
3592          */
3593         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3594         u16 ch;
3595         unsigned long flags = 0;
3596
3597         IWL_DEBUG_MAC80211(priv, "enter\n");
3598
3599         if (iwl_is_rfkill(priv))
3600                 goto out_exit;
3601
3602         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3603             test_bit(STATUS_SCANNING, &priv->status))
3604                 goto out_exit;
3605
3606         if (!iwl_is_associated_ctx(ctx))
3607                 goto out_exit;
3608
3609         /* channel switch in progress */
3610         if (priv->switch_rxon.switch_in_progress == true)
3611                 goto out_exit;
3612
3613         mutex_lock(&priv->mutex);
3614         if (priv->cfg->ops->lib->set_channel_switch) {
3615
3616                 ch = channel->hw_value;
3617                 if (le16_to_cpu(ctx->active.channel) != ch) {
3618                         ch_info = iwl_get_channel_info(priv,
3619                                                        channel->band,
3620                                                        ch);
3621                         if (!is_channel_valid(ch_info)) {
3622                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3623                                 goto out;
3624                         }
3625                         spin_lock_irqsave(&priv->lock, flags);
3626
3627                         priv->current_ht_config.smps = conf->smps_mode;
3628
3629                         /* Configure HT40 channels */
3630                         ctx->ht.enabled = conf_is_ht(conf);
3631                         if (ctx->ht.enabled) {
3632                                 if (conf_is_ht40_minus(conf)) {
3633                                         ctx->ht.extension_chan_offset =
3634                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3635                                         ctx->ht.is_40mhz = true;
3636                                 } else if (conf_is_ht40_plus(conf)) {
3637                                         ctx->ht.extension_chan_offset =
3638                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3639                                         ctx->ht.is_40mhz = true;
3640                                 } else {
3641                                         ctx->ht.extension_chan_offset =
3642                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3643                                         ctx->ht.is_40mhz = false;
3644                                 }
3645                         } else
3646                                 ctx->ht.is_40mhz = false;
3647
3648                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3649                                 ctx->staging.flags = 0;
3650
3651                         iwl_set_rxon_channel(priv, channel, ctx);
3652                         iwl_set_rxon_ht(priv, ht_conf);
3653                         iwl_set_flags_for_band(priv, ctx, channel->band,
3654                                                ctx->vif);
3655                         spin_unlock_irqrestore(&priv->lock, flags);
3656
3657                         iwl_set_rate(priv);
3658                         /*
3659                          * at this point, staging_rxon has the
3660                          * configuration for channel switch
3661                          */
3662                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3663                                                                     ch_switch))
3664                                 priv->switch_rxon.switch_in_progress = false;
3665                 }
3666         }
3667 out:
3668         mutex_unlock(&priv->mutex);
3669 out_exit:
3670         if (!priv->switch_rxon.switch_in_progress)
3671                 ieee80211_chswitch_done(ctx->vif, false);
3672         IWL_DEBUG_MAC80211(priv, "leave\n");
3673 }
3674
3675 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3676                              unsigned int changed_flags,
3677                              unsigned int *total_flags,
3678                              u64 multicast)
3679 {
3680         struct iwl_priv *priv = hw->priv;
3681         __le32 filter_or = 0, filter_nand = 0;
3682         struct iwl_rxon_context *ctx;
3683
3684 #define CHK(test, flag) do { \
3685         if (*total_flags & (test))              \
3686                 filter_or |= (flag);            \
3687         else                                    \
3688                 filter_nand |= (flag);          \
3689         } while (0)
3690
3691         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3692                         changed_flags, *total_flags);
3693
3694         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3695         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3696         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3697         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3698
3699 #undef CHK
3700
3701         mutex_lock(&priv->mutex);
3702
3703         for_each_context(priv, ctx) {
3704                 ctx->staging.filter_flags &= ~filter_nand;
3705                 ctx->staging.filter_flags |= filter_or;
3706
3707                 /*
3708                  * Not committing directly because hardware can perform a scan,
3709                  * but we'll eventually commit the filter flags change anyway.
3710                  */
3711         }
3712
3713         mutex_unlock(&priv->mutex);
3714
3715         /*
3716          * Receiving all multicast frames is always enabled by the
3717          * default flags setup in iwl_connection_init_rx_config()
3718          * since we currently do not support programming multicast
3719          * filters into the device.
3720          */
3721         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3722                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3723 }
3724
3725 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3726 {
3727         struct iwl_priv *priv = hw->priv;
3728
3729         mutex_lock(&priv->mutex);
3730         IWL_DEBUG_MAC80211(priv, "enter\n");
3731
3732         /* do not support "flush" */
3733         if (!priv->cfg->ops->lib->txfifo_flush)
3734                 goto done;
3735
3736         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3737                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3738                 goto done;
3739         }
3740         if (iwl_is_rfkill(priv)) {
3741                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3742                 goto done;
3743         }
3744
3745         /*
3746          * mac80211 will not push any more frames for transmit
3747          * until the flush is completed
3748          */
3749         if (drop) {
3750                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3751                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3752                         IWL_ERR(priv, "flush request fail\n");
3753                         goto done;
3754                 }
3755         }
3756         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3757         iwlagn_wait_tx_queue_empty(priv);
3758 done:
3759         mutex_unlock(&priv->mutex);
3760         IWL_DEBUG_MAC80211(priv, "leave\n");
3761 }
3762
3763 static void iwlagn_disable_roc(struct iwl_priv *priv)
3764 {
3765         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3766         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3767
3768         lockdep_assert_held(&priv->mutex);
3769
3770         if (!ctx->is_active)
3771                 return;
3772
3773         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3774         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3775         iwl_set_rxon_channel(priv, chan, ctx);
3776         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3777
3778         priv->_agn.hw_roc_channel = NULL;
3779
3780         iwlcore_commit_rxon(priv, ctx);
3781
3782         ctx->is_active = false;
3783 }
3784
3785 static void iwlagn_bg_roc_done(struct work_struct *work)
3786 {
3787         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3788                                              _agn.hw_roc_work.work);
3789
3790         mutex_lock(&priv->mutex);
3791         ieee80211_remain_on_channel_expired(priv->hw);
3792         iwlagn_disable_roc(priv);
3793         mutex_unlock(&priv->mutex);
3794 }
3795
3796 #ifdef CONFIG_IWL5000
3797 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3798                                      struct ieee80211_channel *channel,
3799                                      enum nl80211_channel_type channel_type,
3800                                      int duration)
3801 {
3802         struct iwl_priv *priv = hw->priv;
3803         int err = 0;
3804
3805         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3806                 return -EOPNOTSUPP;
3807
3808         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3809                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3810                 return -EOPNOTSUPP;
3811
3812         mutex_lock(&priv->mutex);
3813
3814         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3815             test_bit(STATUS_SCAN_HW, &priv->status)) {
3816                 err = -EBUSY;
3817                 goto out;
3818         }
3819
3820         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3821         priv->_agn.hw_roc_channel = channel;
3822         priv->_agn.hw_roc_chantype = channel_type;
3823         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3824         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3825         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3826                            msecs_to_jiffies(duration + 20));
3827
3828         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3829         ieee80211_ready_on_channel(priv->hw);
3830
3831  out:
3832         mutex_unlock(&priv->mutex);
3833
3834         return err;
3835 }
3836
3837 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3838 {
3839         struct iwl_priv *priv = hw->priv;
3840
3841         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3842                 return -EOPNOTSUPP;
3843
3844         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3845
3846         mutex_lock(&priv->mutex);
3847         iwlagn_disable_roc(priv);
3848         mutex_unlock(&priv->mutex);
3849
3850         return 0;
3851 }
3852 #endif
3853
3854 /*****************************************************************************
3855  *
3856  * driver setup and teardown
3857  *
3858  *****************************************************************************/
3859
3860 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3861 {
3862         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3863
3864         init_waitqueue_head(&priv->wait_command_queue);
3865
3866         INIT_WORK(&priv->restart, iwl_bg_restart);
3867         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3868         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3869         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3870         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3871         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3872         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3873         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3874         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3875         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3876
3877         iwl_setup_scan_deferred_work(priv);
3878
3879         if (priv->cfg->ops->lib->setup_deferred_work)
3880                 priv->cfg->ops->lib->setup_deferred_work(priv);
3881
3882         init_timer(&priv->statistics_periodic);
3883         priv->statistics_periodic.data = (unsigned long)priv;
3884         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3885
3886         init_timer(&priv->ucode_trace);
3887         priv->ucode_trace.data = (unsigned long)priv;
3888         priv->ucode_trace.function = iwl_bg_ucode_trace;
3889
3890         init_timer(&priv->watchdog);
3891         priv->watchdog.data = (unsigned long)priv;
3892         priv->watchdog.function = iwl_bg_watchdog;
3893
3894         if (!priv->cfg->base_params->use_isr_legacy)
3895                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3896                         iwl_irq_tasklet, (unsigned long)priv);
3897         else
3898                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3899                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3900 }
3901
3902 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3903 {
3904         if (priv->cfg->ops->lib->cancel_deferred_work)
3905                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3906
3907         cancel_delayed_work_sync(&priv->init_alive_start);
3908         cancel_delayed_work(&priv->alive_start);
3909         cancel_work_sync(&priv->run_time_calib_work);
3910         cancel_work_sync(&priv->beacon_update);
3911
3912         iwl_cancel_scan_deferred_work(priv);
3913
3914         cancel_work_sync(&priv->bt_full_concurrency);
3915         cancel_work_sync(&priv->bt_runtime_config);
3916
3917         del_timer_sync(&priv->statistics_periodic);
3918         del_timer_sync(&priv->ucode_trace);
3919 }
3920
3921 static void iwl_init_hw_rates(struct iwl_priv *priv,
3922                               struct ieee80211_rate *rates)
3923 {
3924         int i;
3925
3926         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3927                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3928                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3929                 rates[i].hw_value_short = i;
3930                 rates[i].flags = 0;
3931                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3932                         /*
3933                          * If CCK != 1M then set short preamble rate flag.
3934                          */
3935                         rates[i].flags |=
3936                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3937                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3938                 }
3939         }
3940 }
3941
3942 static int iwl_init_drv(struct iwl_priv *priv)
3943 {
3944         int ret;
3945
3946         spin_lock_init(&priv->sta_lock);
3947         spin_lock_init(&priv->hcmd_lock);
3948
3949         INIT_LIST_HEAD(&priv->free_frames);
3950
3951         mutex_init(&priv->mutex);
3952         mutex_init(&priv->sync_cmd_mutex);
3953
3954         priv->ieee_channels = NULL;
3955         priv->ieee_rates = NULL;
3956         priv->band = IEEE80211_BAND_2GHZ;
3957
3958         priv->iw_mode = NL80211_IFTYPE_STATION;
3959         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3960         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3961         priv->_agn.agg_tids_count = 0;
3962
3963         /* initialize force reset */
3964         priv->force_reset[IWL_RF_RESET].reset_duration =
3965                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3966         priv->force_reset[IWL_FW_RESET].reset_duration =
3967                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3968
3969         /* Choose which receivers/antennas to use */
3970         if (priv->cfg->ops->hcmd->set_rxon_chain)
3971                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3972                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3973
3974         iwl_init_scan_params(priv);
3975
3976         /* init bt coex */
3977         if (priv->cfg->bt_params &&
3978             priv->cfg->bt_params->advanced_bt_coexist) {
3979                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3980                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3981                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3982                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3983                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3984                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3985         }
3986
3987         /* Set the tx_power_user_lmt to the lowest power level
3988          * this value will get overwritten by channel max power avg
3989          * from eeprom */
3990         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3991         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3992
3993         ret = iwl_init_channel_map(priv);
3994         if (ret) {
3995                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3996                 goto err;
3997         }
3998
3999         ret = iwlcore_init_geos(priv);
4000         if (ret) {
4001                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4002                 goto err_free_channel_map;
4003         }
4004         iwl_init_hw_rates(priv, priv->ieee_rates);
4005
4006         return 0;
4007
4008 err_free_channel_map:
4009         iwl_free_channel_map(priv);
4010 err:
4011         return ret;
4012 }
4013
4014 static void iwl_uninit_drv(struct iwl_priv *priv)
4015 {
4016         iwl_calib_free_results(priv);
4017         iwlcore_free_geos(priv);
4018         iwl_free_channel_map(priv);
4019         kfree(priv->scan_cmd);
4020 }
4021
4022 #ifdef CONFIG_IWL5000
4023 struct ieee80211_ops iwlagn_hw_ops = {
4024         .tx = iwlagn_mac_tx,
4025         .start = iwlagn_mac_start,
4026         .stop = iwlagn_mac_stop,
4027         .add_interface = iwl_mac_add_interface,
4028         .remove_interface = iwl_mac_remove_interface,
4029         .change_interface = iwl_mac_change_interface,
4030         .config = iwlagn_mac_config,
4031         .configure_filter = iwlagn_configure_filter,
4032         .set_key = iwlagn_mac_set_key,
4033         .update_tkip_key = iwlagn_mac_update_tkip_key,
4034         .conf_tx = iwl_mac_conf_tx,
4035         .bss_info_changed = iwlagn_bss_info_changed,
4036         .ampdu_action = iwlagn_mac_ampdu_action,
4037         .hw_scan = iwl_mac_hw_scan,
4038         .sta_notify = iwlagn_mac_sta_notify,
4039         .sta_add = iwlagn_mac_sta_add,
4040         .sta_remove = iwl_mac_sta_remove,
4041         .channel_switch = iwlagn_mac_channel_switch,
4042         .flush = iwlagn_mac_flush,
4043         .tx_last_beacon = iwl_mac_tx_last_beacon,
4044         .remain_on_channel = iwl_mac_remain_on_channel,
4045         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4046 };
4047 #endif
4048
4049 static void iwl_hw_detect(struct iwl_priv *priv)
4050 {
4051         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4052         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4053         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4054         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4055 }
4056
4057 static int iwl_set_hw_params(struct iwl_priv *priv)
4058 {
4059         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4060         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4061         if (priv->cfg->mod_params->amsdu_size_8K)
4062                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4063         else
4064                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4065
4066         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4067
4068         if (priv->cfg->mod_params->disable_11n)
4069                 priv->cfg->sku &= ~IWL_SKU_N;
4070
4071         /* Device-specific setup */
4072         return priv->cfg->ops->lib->set_hw_params(priv);
4073 }
4074
4075 static const u8 iwlagn_bss_ac_to_fifo[] = {
4076         IWL_TX_FIFO_VO,
4077         IWL_TX_FIFO_VI,
4078         IWL_TX_FIFO_BE,
4079         IWL_TX_FIFO_BK,
4080 };
4081
4082 static const u8 iwlagn_bss_ac_to_queue[] = {
4083         0, 1, 2, 3,
4084 };
4085
4086 static const u8 iwlagn_pan_ac_to_fifo[] = {
4087         IWL_TX_FIFO_VO_IPAN,
4088         IWL_TX_FIFO_VI_IPAN,
4089         IWL_TX_FIFO_BE_IPAN,
4090         IWL_TX_FIFO_BK_IPAN,
4091 };
4092
4093 static const u8 iwlagn_pan_ac_to_queue[] = {
4094         7, 6, 5, 4,
4095 };
4096
4097 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4098 {
4099         int err = 0, i;
4100         struct iwl_priv *priv;
4101         struct ieee80211_hw *hw;
4102         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4103         unsigned long flags;
4104         u16 pci_cmd, num_mac;
4105
4106         /************************
4107          * 1. Allocating HW data
4108          ************************/
4109
4110         /* Disabling hardware scan means that mac80211 will perform scans
4111          * "the hard way", rather than using device's scan. */
4112         if (cfg->mod_params->disable_hw_scan) {
4113                 dev_printk(KERN_DEBUG, &(pdev->dev),
4114                         "sw scan support is deprecated\n");
4115 #ifdef CONFIG_IWL5000
4116                 iwlagn_hw_ops.hw_scan = NULL;
4117 #endif
4118 #ifdef CONFIG_IWL4965
4119                 iwl4965_hw_ops.hw_scan = NULL;
4120 #endif
4121         }
4122
4123         hw = iwl_alloc_all(cfg);
4124         if (!hw) {
4125                 err = -ENOMEM;
4126                 goto out;
4127         }
4128         priv = hw->priv;
4129         /* At this point both hw and priv are allocated. */
4130
4131         /*
4132          * The default context is always valid,
4133          * more may be discovered when firmware
4134          * is loaded.
4135          */
4136         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4137
4138         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4139                 priv->contexts[i].ctxid = i;
4140
4141         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4142         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4143         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4144         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4145         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4146         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4147         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4148         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4149         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4150         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4151         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4152                 BIT(NL80211_IFTYPE_ADHOC);
4153         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4154                 BIT(NL80211_IFTYPE_STATION);
4155         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4156         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4157         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4158         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4159
4160         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4161         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4162         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4163         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4164         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4165         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4166         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4167         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4168         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4169         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4170         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4171         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4172                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4173 #ifdef CONFIG_IWL_P2P
4174         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4175                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4176 #endif
4177         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4178         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4179         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4180
4181         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4182
4183         SET_IEEE80211_DEV(hw, &pdev->dev);
4184
4185         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4186         priv->cfg = cfg;
4187         priv->pci_dev = pdev;
4188         priv->inta_mask = CSR_INI_SET_MASK;
4189
4190         /* is antenna coupling more than 35dB ? */
4191         priv->bt_ant_couple_ok =
4192                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4193                 true : false;
4194
4195         /* enable/disable bt channel inhibition */
4196         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4197         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4198                        (priv->bt_ch_announce) ? "On" : "Off");
4199
4200         if (iwl_alloc_traffic_mem(priv))
4201                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4202
4203         /**************************
4204          * 2. Initializing PCI bus
4205          **************************/
4206         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4207                                 PCIE_LINK_STATE_CLKPM);
4208
4209         if (pci_enable_device(pdev)) {
4210                 err = -ENODEV;
4211                 goto out_ieee80211_free_hw;
4212         }
4213
4214         pci_set_master(pdev);
4215
4216         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4217         if (!err)
4218                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4219         if (err) {
4220                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4221                 if (!err)
4222                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4223                 /* both attempts failed: */
4224                 if (err) {
4225                         IWL_WARN(priv, "No suitable DMA available.\n");
4226                         goto out_pci_disable_device;
4227                 }
4228         }
4229
4230         err = pci_request_regions(pdev, DRV_NAME);
4231         if (err)
4232                 goto out_pci_disable_device;
4233
4234         pci_set_drvdata(pdev, priv);
4235
4236
4237         /***********************
4238          * 3. Read REV register
4239          ***********************/
4240         priv->hw_base = pci_iomap(pdev, 0, 0);
4241         if (!priv->hw_base) {
4242                 err = -ENODEV;
4243                 goto out_pci_release_regions;
4244         }
4245
4246         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4247                 (unsigned long long) pci_resource_len(pdev, 0));
4248         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4249
4250         /* these spin locks will be used in apm_ops.init and EEPROM access
4251          * we should init now
4252          */
4253         spin_lock_init(&priv->reg_lock);
4254         spin_lock_init(&priv->lock);
4255
4256         /*
4257          * stop and reset the on-board processor just in case it is in a
4258          * strange state ... like being left stranded by a primary kernel
4259          * and this is now the kdump kernel trying to start up
4260          */
4261         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4262
4263         iwl_hw_detect(priv);
4264         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4265                 priv->cfg->name, priv->hw_rev);
4266
4267         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4268          * PCI Tx retries from interfering with C3 CPU state */
4269         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4270
4271         iwl_prepare_card_hw(priv);
4272         if (!priv->hw_ready) {
4273                 IWL_WARN(priv, "Failed, HW not ready\n");
4274                 goto out_iounmap;
4275         }
4276
4277         /*****************
4278          * 4. Read EEPROM
4279          *****************/
4280         /* Read the EEPROM */
4281         err = iwl_eeprom_init(priv);
4282         if (err) {
4283                 IWL_ERR(priv, "Unable to init EEPROM\n");
4284                 goto out_iounmap;
4285         }
4286         err = iwl_eeprom_check_version(priv);
4287         if (err)
4288                 goto out_free_eeprom;
4289
4290         err = iwl_eeprom_check_sku(priv);
4291         if (err)
4292                 goto out_free_eeprom;
4293
4294         /* extract MAC Address */
4295         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4296         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4297         priv->hw->wiphy->addresses = priv->addresses;
4298         priv->hw->wiphy->n_addresses = 1;
4299         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4300         if (num_mac > 1) {
4301                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4302                        ETH_ALEN);
4303                 priv->addresses[1].addr[5]++;
4304                 priv->hw->wiphy->n_addresses++;
4305         }
4306
4307         /************************
4308          * 5. Setup HW constants
4309          ************************/
4310         if (iwl_set_hw_params(priv)) {
4311                 IWL_ERR(priv, "failed to set hw parameters\n");
4312                 goto out_free_eeprom;
4313         }
4314
4315         /*******************
4316          * 6. Setup priv
4317          *******************/
4318
4319         err = iwl_init_drv(priv);
4320         if (err)
4321                 goto out_free_eeprom;
4322         /* At this point both hw and priv are initialized. */
4323
4324         /********************
4325          * 7. Setup services
4326          ********************/
4327         spin_lock_irqsave(&priv->lock, flags);
4328         iwl_disable_interrupts(priv);
4329         spin_unlock_irqrestore(&priv->lock, flags);
4330
4331         pci_enable_msi(priv->pci_dev);
4332
4333         if (priv->cfg->ops->lib->isr_ops.alloc)
4334                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4335
4336         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4337                           IRQF_SHARED, DRV_NAME, priv);
4338         if (err) {
4339                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4340                 goto out_disable_msi;
4341         }
4342
4343         iwl_setup_deferred_work(priv);
4344         iwl_setup_rx_handlers(priv);
4345
4346         /*********************************************
4347          * 8. Enable interrupts and read RFKILL state
4348          *********************************************/
4349
4350         /* enable rfkill interrupt: hw bug w/a */
4351         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4352         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4353                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4354                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4355         }
4356
4357         iwl_enable_rfkill_int(priv);
4358
4359         /* If platform's RF_KILL switch is NOT set to KILL */
4360         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4361                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4362         else
4363                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4364
4365         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4366                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4367
4368         iwl_power_initialize(priv);
4369         iwl_tt_initialize(priv);
4370
4371         init_completion(&priv->_agn.firmware_loading_complete);
4372
4373         err = iwl_request_firmware(priv, true);
4374         if (err)
4375                 goto out_destroy_workqueue;
4376
4377         return 0;
4378
4379  out_destroy_workqueue:
4380         destroy_workqueue(priv->workqueue);
4381         priv->workqueue = NULL;
4382         free_irq(priv->pci_dev->irq, priv);
4383         if (priv->cfg->ops->lib->isr_ops.free)
4384                 priv->cfg->ops->lib->isr_ops.free(priv);
4385  out_disable_msi:
4386         pci_disable_msi(priv->pci_dev);
4387         iwl_uninit_drv(priv);
4388  out_free_eeprom:
4389         iwl_eeprom_free(priv);
4390  out_iounmap:
4391         pci_iounmap(pdev, priv->hw_base);
4392  out_pci_release_regions:
4393         pci_set_drvdata(pdev, NULL);
4394         pci_release_regions(pdev);
4395  out_pci_disable_device:
4396         pci_disable_device(pdev);
4397  out_ieee80211_free_hw:
4398         iwl_free_traffic_mem(priv);
4399         ieee80211_free_hw(priv->hw);
4400  out:
4401         return err;
4402 }
4403
4404 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4405 {
4406         struct iwl_priv *priv = pci_get_drvdata(pdev);
4407         unsigned long flags;
4408
4409         if (!priv)
4410                 return;
4411
4412         wait_for_completion(&priv->_agn.firmware_loading_complete);
4413
4414         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4415
4416         iwl_dbgfs_unregister(priv);
4417         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4418
4419         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4420          * to be called and iwl_down since we are removing the device
4421          * we need to set STATUS_EXIT_PENDING bit.
4422          */
4423         set_bit(STATUS_EXIT_PENDING, &priv->status);
4424
4425         iwl_leds_exit(priv);
4426
4427         if (priv->mac80211_registered) {
4428                 ieee80211_unregister_hw(priv->hw);
4429                 priv->mac80211_registered = 0;
4430         } else {
4431                 iwl_down(priv);
4432         }
4433
4434         /*
4435          * Make sure device is reset to low power before unloading driver.
4436          * This may be redundant with iwl_down(), but there are paths to
4437          * run iwl_down() without calling apm_ops.stop(), and there are
4438          * paths to avoid running iwl_down() at all before leaving driver.
4439          * This (inexpensive) call *makes sure* device is reset.
4440          */
4441         iwl_apm_stop(priv);
4442
4443         iwl_tt_exit(priv);
4444
4445         /* make sure we flush any pending irq or
4446          * tasklet for the driver
4447          */
4448         spin_lock_irqsave(&priv->lock, flags);
4449         iwl_disable_interrupts(priv);
4450         spin_unlock_irqrestore(&priv->lock, flags);
4451
4452         iwl_synchronize_irq(priv);
4453
4454         iwl_dealloc_ucode_pci(priv);
4455
4456         if (priv->rxq.bd)
4457                 iwlagn_rx_queue_free(priv, &priv->rxq);
4458         iwlagn_hw_txq_ctx_free(priv);
4459
4460         iwl_eeprom_free(priv);
4461
4462
4463         /*netif_stop_queue(dev); */
4464         flush_workqueue(priv->workqueue);
4465
4466         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4467          * priv->workqueue... so we can't take down the workqueue
4468          * until now... */
4469         destroy_workqueue(priv->workqueue);
4470         priv->workqueue = NULL;
4471         iwl_free_traffic_mem(priv);
4472
4473         free_irq(priv->pci_dev->irq, priv);
4474         pci_disable_msi(priv->pci_dev);
4475         pci_iounmap(pdev, priv->hw_base);
4476         pci_release_regions(pdev);
4477         pci_disable_device(pdev);
4478         pci_set_drvdata(pdev, NULL);
4479
4480         iwl_uninit_drv(priv);
4481
4482         if (priv->cfg->ops->lib->isr_ops.free)
4483                 priv->cfg->ops->lib->isr_ops.free(priv);
4484
4485         dev_kfree_skb(priv->beacon_skb);
4486
4487         ieee80211_free_hw(priv->hw);
4488 }
4489
4490
4491 /*****************************************************************************
4492  *
4493  * driver and module entry point
4494  *
4495  *****************************************************************************/
4496
4497 /* Hardware specific file defines the PCI IDs table for that hardware module */
4498 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4499 #ifdef CONFIG_IWL4965
4500         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4501         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4502 #endif /* CONFIG_IWL4965 */
4503 #ifdef CONFIG_IWL5000
4504 /* 5100 Series WiFi */
4505         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4506         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4507         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4508         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4509         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4510         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4511         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4512         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4513         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4514         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4515         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4516         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4517         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4518         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4519         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4520         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4521         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4522         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4523         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4524         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4525         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4526         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4527         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4528         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4529
4530 /* 5300 Series WiFi */
4531         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4532         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4533         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4534         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4535         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4536         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4537         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4538         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4539         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4540         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4541         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4542         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4543
4544 /* 5350 Series WiFi/WiMax */
4545         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4546         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4547         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4548
4549 /* 5150 Series Wifi/WiMax */
4550         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4551         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4552         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4553         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4554         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4555         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4556
4557         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4558         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4559         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4560         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4561
4562 /* 6x00 Series */
4563         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4564         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4565         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4566         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4567         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4568         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4569         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4570         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4571         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4572         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4573
4574 /* 6x05 Series */
4575         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4576         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4577         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4578         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4579         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4580         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4581         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4582
4583 /* 6x30 Series */
4584         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4585         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4586         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4587         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4588         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4589         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4590         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4591         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4592         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4593         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4594         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4595         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4596         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4597         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4598         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4599         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4600
4601 /* 6x50 WiFi/WiMax Series */
4602         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4603         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4604         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4605         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4606         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4607         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4608
4609 /* 6150 WiFi/WiMax Series */
4610         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4611         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4612         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4613         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4614         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4615         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4616
4617 /* 1000 Series WiFi */
4618         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4621         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4622         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4623         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4624         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4625         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4626         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4627         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4628         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4629         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4630
4631 /* 100 Series WiFi */
4632         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4633         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4634         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4635         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4636         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4637         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4638
4639 /* 130 Series WiFi */
4640         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4641         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4642         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4643         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4644         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4645         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4646
4647 /* 2x00 Series */
4648         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4649         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4650         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4651         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4652         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4653         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4654
4655 /* 2x30 Series */
4656         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4657         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4658         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4659         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4660         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4661         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4662
4663 /* 6x35 Series */
4664         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4665         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4666         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4667         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4668         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4669         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4670         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4671         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4672         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4673
4674 /* 200 Series */
4675         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4676         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4677         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4678         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4679         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4680         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4681
4682 /* 230 Series */
4683         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4684         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4685         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4686         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4687         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4688         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4689
4690 #endif /* CONFIG_IWL5000 */
4691
4692         {0}
4693 };
4694 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4695
4696 static struct pci_driver iwl_driver = {
4697         .name = DRV_NAME,
4698         .id_table = iwl_hw_card_ids,
4699         .probe = iwl_pci_probe,
4700         .remove = __devexit_p(iwl_pci_remove),
4701         .driver.pm = IWL_PM_OPS,
4702 };
4703
4704 static int __init iwl_init(void)
4705 {
4706
4707         int ret;
4708         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4709         pr_info(DRV_COPYRIGHT "\n");
4710
4711         ret = iwlagn_rate_control_register();
4712         if (ret) {
4713                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4714                 return ret;
4715         }
4716
4717         ret = pci_register_driver(&iwl_driver);
4718         if (ret) {
4719                 pr_err("Unable to initialize PCI module\n");
4720                 goto error_register;
4721         }
4722
4723         return ret;
4724
4725 error_register:
4726         iwlagn_rate_control_unregister();
4727         return ret;
4728 }
4729
4730 static void __exit iwl_exit(void)
4731 {
4732         pci_unregister_driver(&iwl_driver);
4733         iwlagn_rate_control_unregister();
4734 }
4735
4736 module_exit(iwl_exit);
4737 module_init(iwl_init);
4738
4739 #ifdef CONFIG_IWLWIFI_DEBUG
4740 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4741 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4742 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4743 MODULE_PARM_DESC(debug, "debug output mask");
4744 #endif
4745
4746 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4747 MODULE_PARM_DESC(swcrypto50,
4748                  "using crypto in software (default 0 [hardware]) (deprecated)");
4749 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4750 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4751 module_param_named(queues_num50,
4752                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4753 MODULE_PARM_DESC(queues_num50,
4754                  "number of hw queues in 50xx series (deprecated)");
4755 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4756 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4757 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4758 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4759 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4760 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4761 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4762                    int, S_IRUGO);
4763 MODULE_PARM_DESC(amsdu_size_8K50,
4764                  "enable 8K amsdu size in 50XX series (deprecated)");
4765 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4766                    int, S_IRUGO);
4767 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4768 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4769 MODULE_PARM_DESC(fw_restart50,
4770                  "restart firmware in case of error (deprecated)");
4771 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4772 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4773 module_param_named(
4774         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4775 MODULE_PARM_DESC(disable_hw_scan,
4776                  "disable hardware scanning (default 0) (deprecated)");
4777
4778 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4779                    S_IRUGO);
4780 MODULE_PARM_DESC(ucode_alternative,
4781                  "specify ucode alternative to use from ucode file");
4782
4783 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4784 MODULE_PARM_DESC(antenna_coupling,
4785                  "specify antenna coupling in dB (defualt: 0 dB)");
4786
4787 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4788 MODULE_PARM_DESC(bt_ch_inhibition,
4789                  "Disable BT channel inhibition (default: enable)");