drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88 MODULE_ALIAS("iwl4965");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 /**
  94  * iwlagn_commit_rxon - commit staging_rxon to hardware
  95  *
  96  * The RXON command in staging_rxon is committed to the hardware and
  97  * the active_rxon structure is updated with the new data.  This
  98  * function correctly transitions out of the RXON_ASSOC_MSK state if
  99  * a HW tune is required based on the RXON structure changes.
 100  */
 101 int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 102 {
 103         /* cast away the const for active_rxon in this function */
 104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
 105         int ret;
 106         bool new_assoc =
 107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
 108         bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
 109
 110         if (!iwl_is_alive(priv))
 111                 return -EBUSY;
 112
 113         if (!ctx->is_active)
 114                 return 0;
 115
 116         /* always get timestamp with Rx frame */
 117         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
 118
 119         ret = iwl_check_rxon_cmd(priv, ctx);
 120         if (ret) {
 121                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
 122                 return -EINVAL;
 123         }
 124
 125         /*
 126          * receive commit_rxon request
 127          * abort any previous channel switch if still in process
 128          */
 129         if (priv->switch_rxon.switch_in_progress &&
 130             (priv->switch_rxon.channel != ctx->staging.channel)) {
 131                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
 132                       le16_to_cpu(priv->switch_rxon.channel));
 133                 iwl_chswitch_done(priv, false);
 134         }
 135
 136         /* If we don't need to send a full RXON, we can use
 137          * iwl_rxon_assoc_cmd which is used to reconfigure filter
 138          * and other flags for the current radio configuration. */
 139         if (!iwl_full_rxon_required(priv, ctx)) {
 140                 ret = iwl_send_rxon_assoc(priv, ctx);
 141                 if (ret) {
 142                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
 143                         return ret;
 144                 }
 145
 146                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 147                 iwl_print_rx_config_cmd(priv, ctx);
 148                 return 0;
 149         }
 150
 151         /* If we are currently associated and the new config requires
 152          * an RXON_ASSOC and the new config wants the associated mask enabled,
 153          * we must clear the associated from the active configuration
 154          * before we apply the new config */
 155         if (iwl_is_associated_ctx(ctx) && new_assoc) {
 156                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
 157                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 158
 159                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 160                                        sizeof(struct iwl_rxon_cmd),
 161                                        active_rxon);
 162
 163                 /* If the mask clearing failed then we set
 164                  * active_rxon back to what it was previously */
 165                 if (ret) {
 166                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
 167                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
 168                         return ret;
 169                 }
 170                 iwl_clear_ucode_stations(priv, ctx);
 171                 iwl_restore_stations(priv, ctx);
 172                 ret = iwl_restore_default_wep_keys(priv, ctx);
 173                 if (ret) {
 174                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 175                         return ret;
 176                 }
 177         }
 178
 179         IWL_DEBUG_INFO(priv, "Sending RXON\n"
 180                        "* with%s RXON_FILTER_ASSOC_MSK\n"
 181                        "* channel = %d\n"
 182                        "* bssid = %pM\n",
 183                        (new_assoc ? "" : "out"),
 184                        le16_to_cpu(ctx->staging.channel),
 185                        ctx->staging.bssid_addr);
 186
 187         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
 188
 189         if (!old_assoc) {
 190                 /*
 191                  * First of all, before setting associated, we need to
 192                  * send RXON timing so the device knows about the DTIM
 193                  * period and other timing values
 194                  */
 195                 ret = iwl_send_rxon_timing(priv, ctx);
 196                 if (ret) {
 197                         IWL_ERR(priv, "Error setting RXON timing!\n");
 198                         return ret;
 199                 }
 200         }
 201
 202         if (priv->cfg->ops->hcmd->set_pan_params) {
 203                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         /* Apply the new configuration
 209          * RXON unassoc clears the station table in uCode so restoration of
 210          * stations is needed after it (the RXON command) completes
 211          */
 212         if (!new_assoc) {
 213                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 214                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 215                 if (ret) {
 216                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 217                         return ret;
 218                 }
 219                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
 220                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 221                 iwl_clear_ucode_stations(priv, ctx);
 222                 iwl_restore_stations(priv, ctx);
 223                 ret = iwl_restore_default_wep_keys(priv, ctx);
 224                 if (ret) {
 225                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
 226                         return ret;
 227                 }
 228         }
 229         if (new_assoc) {
 230                 priv->start_calib = 0;
 231                 /* Apply the new configuration
 232                  * RXON assoc doesn't clear the station table in uCode,
 233                  */
 234                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
 235                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
 236                 if (ret) {
 237                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
 238                         return ret;
 239                 }
 240                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
 241         }
 242         iwl_print_rx_config_cmd(priv, ctx);
 243
 244         iwl_init_sensitivity(priv);
 245
 246         /* If we issue a new RXON command which required a tune then we must
 247          * send a new TXPOWER command or we won't be able to Tx any frames */
 248         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
 249         if (ret) {
 250                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
 251                 return ret;
 252         }
 253
 254         return 0;
 255 }
 256
 257 void iwl_update_chain_flags(struct iwl_priv *priv)
 258 {
 259         struct iwl_rxon_context *ctx;
 260
 261         if (priv->cfg->ops->hcmd->set_rxon_chain) {
 262                 for_each_context(priv, ctx) {
 263                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 264                         iwlcore_commit_rxon(priv, ctx);
 265                 }
 266         }
 267 }
 268
 269 static void iwl_clear_free_frames(struct iwl_priv *priv)
 270 {
 271         struct list_head *element;
 272
 273         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 274                        priv->frames_count);
 275
 276         while (!list_empty(&priv->free_frames)) {
 277                 element = priv->free_frames.next;
 278                 list_del(element);
 279                 kfree(list_entry(element, struct iwl_frame, list));
 280                 priv->frames_count--;
 281         }
 282
 283         if (priv->frames_count) {
 284                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 285                             priv->frames_count);
 286                 priv->frames_count = 0;
 287         }
 288 }
 289
 290 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 291 {
 292         struct iwl_frame *frame;
 293         struct list_head *element;
 294         if (list_empty(&priv->free_frames)) {
 295                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 296                 if (!frame) {
 297                         IWL_ERR(priv, "Could not allocate frame!\n");
 298                         return NULL;
 299                 }
 300
 301                 priv->frames_count++;
 302                 return frame;
 303         }
 304
 305         element = priv->free_frames.next;
 306         list_del(element);
 307         return list_entry(element, struct iwl_frame, list);
 308 }
 309
 310 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 311 {
 312         memset(frame, 0, sizeof(*frame));
 313         list_add(&frame->list, &priv->free_frames);
 314 }
 315
 316 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 317                                  struct ieee80211_hdr *hdr,
 318                                  int left)
 319 {
 320         lockdep_assert_held(&priv->mutex);
 321
 322         if (!priv->beacon_skb)
 323                 return 0;
 324
 325         if (priv->beacon_skb->len > left)
 326                 return 0;
 327
 328         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 329
 330         return priv->beacon_skb->len;
 331 }
 332
 333 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 334 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 335                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 336                                u8 *beacon, u32 frame_size)
 337 {
 338         u16 tim_idx;
 339         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 340
 341         /*
 342          * The index is relative to frame start but we start looking at the
 343          * variable-length part of the beacon.
 344          */
 345         tim_idx = mgmt->u.beacon.variable - beacon;
 346
 347         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 348         while ((tim_idx < (frame_size - 2)) &&
 349                         (beacon[tim_idx] != WLAN_EID_TIM))
 350                 tim_idx += beacon[tim_idx+1] + 2;
 351
 352         /* If TIM field was found, set variables */
 353         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 354                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 355                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 356         } else
 357                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 358 }
 359
 360 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 361                                        struct iwl_frame *frame)
 362 {
 363         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 364         u32 frame_size;
 365         u32 rate_flags;
 366         u32 rate;
 367         /*
 368          * We have to set up the TX command, the TX Beacon command, and the
 369          * beacon contents.
 370          */
 371
 372         lockdep_assert_held(&priv->mutex);
 373
 374         if (!priv->beacon_ctx) {
 375                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 376                 return 0;
 377         }
 378
 379         /* Initialize memory */
 380         tx_beacon_cmd = &frame->u.beacon;
 381         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 382
 383         /* Set up TX beacon contents */
 384         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 385                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 386         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 387                 return 0;
 388
 389         /* Set up TX command fields */
 390         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 391         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 392         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 393         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 394                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 395
 396         /* Set up TX beacon command fields */
 397         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 398                            frame_size);
 399
 400         /* Set up packet rate and flags */
 401         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 402         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 403                                               priv->hw_params.valid_tx_ant);
 404         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 405         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 406                 rate_flags |= RATE_MCS_CCK_MSK;
 407         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 408                         rate_flags);
 409
 410         return sizeof(*tx_beacon_cmd) + frame_size;
 411 }
 412 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
 413 {
 414         struct iwl_frame *frame;
 415         unsigned int frame_size;
 416         int rc;
 417
 418         frame = iwl_get_free_frame(priv);
 419         if (!frame) {
 420                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 421                           "command.\n");
 422                 return -ENOMEM;
 423         }
 424
 425         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 426         if (!frame_size) {
 427                 IWL_ERR(priv, "Error configuring the beacon command\n");
 428                 iwl_free_frame(priv, frame);
 429                 return -EINVAL;
 430         }
 431
 432         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 433                               &frame->u.cmd[0]);
 434
 435         iwl_free_frame(priv, frame);
 436
 437         return rc;
 438 }
 439
 440 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 441 {
 442         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 443
 444         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 445         if (sizeof(dma_addr_t) > sizeof(u32))
 446                 addr |=
 447                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 448
 449         return addr;
 450 }
 451
 452 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 453 {
 454         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 455
 456         return le16_to_cpu(tb->hi_n_len) >> 4;
 457 }
 458
 459 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 460                                   dma_addr_t addr, u16 len)
 461 {
 462         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 463         u16 hi_n_len = len << 4;
 464
 465         put_unaligned_le32(addr, &tb->lo);
 466         if (sizeof(dma_addr_t) > sizeof(u32))
 467                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 468
 469         tb->hi_n_len = cpu_to_le16(hi_n_len);
 470
 471         tfd->num_tbs = idx + 1;
 472 }
 473
 474 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 475 {
 476         return tfd->num_tbs & 0x1f;
 477 }
 478
 479 /**
 480  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 481  * @priv - driver private data
 482  * @txq - tx queue
 483  *
 484  * Does NOT advance any TFD circular buffer read/write indexes
 485  * Does NOT free the TFD itself (which is within circular buffer)
 486  */
 487 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 488 {
 489         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 490         struct iwl_tfd *tfd;
 491         struct pci_dev *dev = priv->pci_dev;
 492         int index = txq->q.read_ptr;
 493         int i;
 494         int num_tbs;
 495
 496         tfd = &tfd_tmp[index];
 497
 498         /* Sanity check on number of chunks */
 499         num_tbs = iwl_tfd_get_num_tbs(tfd);
 500
 501         if (num_tbs >= IWL_NUM_OF_TBS) {
 502                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 503                 /* @todo issue fatal error, it is quite serious situation */
 504                 return;
 505         }
 506
 507         /* Unmap tx_cmd */
 508         if (num_tbs)
 509                 pci_unmap_single(dev,
 510                                 dma_unmap_addr(&txq->meta[index], mapping),
 511                                 dma_unmap_len(&txq->meta[index], len),
 512                                 PCI_DMA_BIDIRECTIONAL);
 513
 514         /* Unmap chunks, if any. */
 515         for (i = 1; i < num_tbs; i++)
 516                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 517                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 518
 519         /* free SKB */
 520         if (txq->txb) {
 521                 struct sk_buff *skb;
 522
 523                 skb = txq->txb[txq->q.read_ptr].skb;
 524
 525                 /* can be called from irqs-disabled context */
 526                 if (skb) {
 527                         dev_kfree_skb_any(skb);
 528                         txq->txb[txq->q.read_ptr].skb = NULL;
 529                 }
 530         }
 531 }
 532
 533 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 534                                  struct iwl_tx_queue *txq,
 535                                  dma_addr_t addr, u16 len,
 536                                  u8 reset, u8 pad)
 537 {
 538         struct iwl_queue *q;
 539         struct iwl_tfd *tfd, *tfd_tmp;
 540         u32 num_tbs;
 541
 542         q = &txq->q;
 543         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 544         tfd = &tfd_tmp[q->write_ptr];
 545
 546         if (reset)
 547                 memset(tfd, 0, sizeof(*tfd));
 548
 549         num_tbs = iwl_tfd_get_num_tbs(tfd);
 550
 551         /* Each TFD can point to a maximum 20 Tx buffers */
 552         if (num_tbs >= IWL_NUM_OF_TBS) {
 553                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 554                           IWL_NUM_OF_TBS);
 555                 return -EINVAL;
 556         }
 557
 558         BUG_ON(addr & ~DMA_BIT_MASK(36));
 559         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 560                 IWL_ERR(priv, "Unaligned address = %llx\n",
 561                           (unsigned long long)addr);
 562
 563         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 564
 565         return 0;
 566 }
 567
 568 /*
 569  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 570  * given Tx queue, and enable the DMA channel used for that queue.
 571  *
 572  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 573  * channels supported in hardware.
 574  */
 575 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 576                          struct iwl_tx_queue *txq)
 577 {
 578         int txq_id = txq->q.id;
 579
 580         /* Circular buffer (TFD queue in DRAM) physical base address */
 581         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 582                              txq->q.dma_addr >> 8);
 583
 584         return 0;
 585 }
 586
 587 /******************************************************************************
 588  *
 589  * Generic RX handler implementations
 590  *
 591  ******************************************************************************/
 592 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 593                                 struct iwl_rx_mem_buffer *rxb)
 594 {
 595         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 596         struct iwl_alive_resp *palive;
 597         struct delayed_work *pwork;
 598
 599         palive = &pkt->u.alive_frame;
 600
 601         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 602                        "0x%01X 0x%01X\n",
 603                        palive->is_valid, palive->ver_type,
 604                        palive->ver_subtype);
 605
 606         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 607                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 608                 memcpy(&priv->card_alive_init,
 609                        &pkt->u.alive_frame,
 610                        sizeof(struct iwl_init_alive_resp));
 611                 pwork = &priv->init_alive_start;
 612         } else {
 613                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 614                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 615                        sizeof(struct iwl_alive_resp));
 616                 pwork = &priv->alive_start;
 617         }
 618
 619         /* We delay the ALIVE response by 5ms to
 620          * give the HW RF Kill time to activate... */
 621         if (palive->is_valid == UCODE_VALID_OK)
 622                 queue_delayed_work(priv->workqueue, pwork,
 623                                    msecs_to_jiffies(5));
 624         else
 625                 IWL_WARN(priv, "uCode did not respond OK.\n");
 626 }
 627
 628 static void iwl_bg_beacon_update(struct work_struct *work)
 629 {
 630         struct iwl_priv *priv =
 631                 container_of(work, struct iwl_priv, beacon_update);
 632         struct sk_buff *beacon;
 633
 634         mutex_lock(&priv->mutex);
 635         if (!priv->beacon_ctx) {
 636                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 637                 goto out;
 638         }
 639
 640         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 641                 /*
 642                  * The ucode will send beacon notifications even in
 643                  * IBSS mode, but we don't want to process them. But
 644                  * we need to defer the type check to here due to
 645                  * requiring locking around the beacon_ctx access.
 646                  */
 647                 goto out;
 648         }
 649
 650         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 651         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 652         if (!beacon) {
 653                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 654                 goto out;
 655         }
 656
 657         /* new beacon skb is allocated every time; dispose previous.*/
 658         dev_kfree_skb(priv->beacon_skb);
 659
 660         priv->beacon_skb = beacon;
 661
 662         iwl_send_beacon_cmd(priv);
 663  out:
 664         mutex_unlock(&priv->mutex);
 665 }
 666
 667 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 668 {
 669         struct iwl_priv *priv =
 670                 container_of(work, struct iwl_priv, bt_runtime_config);
 671
 672         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 673                 return;
 674
 675         /* dont send host command if rf-kill is on */
 676         if (!iwl_is_ready_rf(priv))
 677                 return;
 678         priv->cfg->ops->hcmd->send_bt_config(priv);
 679 }
 680
 681 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 682 {
 683         struct iwl_priv *priv =
 684                 container_of(work, struct iwl_priv, bt_full_concurrency);
 685         struct iwl_rxon_context *ctx;
 686
 687         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 688                 return;
 689
 690         /* dont send host command if rf-kill is on */
 691         if (!iwl_is_ready_rf(priv))
 692                 return;
 693
 694         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 695                        priv->bt_full_concurrent ?
 696                        "full concurrency" : "3-wire");
 697
 698         /*
 699          * LQ & RXON updated cmds must be sent before BT Config cmd
 700          * to avoid 3-wire collisions
 701          */
 702         mutex_lock(&priv->mutex);
 703         for_each_context(priv, ctx) {
 704                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 705                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 706                 iwlcore_commit_rxon(priv, ctx);
 707         }
 708         mutex_unlock(&priv->mutex);
 709
 710         priv->cfg->ops->hcmd->send_bt_config(priv);
 711 }
 712
 713 /**
 714  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 715  *
 716  * This callback is provided in order to send a statistics request.
 717  *
 718  * This timer function is continually reset to execute within
 719  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 720  * was received.  We need to ensure we receive the statistics in order
 721  * to update the temperature used for calibrating the TXPOWER.
 722  */
 723 static void iwl_bg_statistics_periodic(unsigned long data)
 724 {
 725         struct iwl_priv *priv = (struct iwl_priv *)data;
 726
 727         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 728                 return;
 729
 730         /* dont send host command if rf-kill is on */
 731         if (!iwl_is_ready_rf(priv))
 732                 return;
 733
 734         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 735 }
 736
 737
 738 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 739                                         u32 start_idx, u32 num_events,
 740                                         u32 mode)
 741 {
 742         u32 i;
 743         u32 ptr;        /* SRAM byte address of log data */
 744         u32 ev, time, data; /* event log data */
 745         unsigned long reg_flags;
 746
 747         if (mode == 0)
 748                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 749         else
 750                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 751
 752         /* Make sure device is powered up for SRAM reads */
 753         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 754         if (iwl_grab_nic_access(priv)) {
 755                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 756                 return;
 757         }
 758
 759         /* Set starting address; reads will auto-increment */
 760         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 761         rmb();
 762
 763         /*
 764          * "time" is actually "data" for mode 0 (no timestamp).
 765          * place event id # at far right for easier visual parsing.
 766          */
 767         for (i = 0; i < num_events; i++) {
 768                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 769                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 770                 if (mode == 0) {
 771                         trace_iwlwifi_dev_ucode_cont_event(priv,
 772                                                         0, time, ev);
 773                 } else {
 774                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 775                         trace_iwlwifi_dev_ucode_cont_event(priv,
 776                                                 time, data, ev);
 777                 }
 778         }
 779         /* Allow device to power down */
 780         iwl_release_nic_access(priv);
 781         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 782 }
 783
 784 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 785 {
 786         u32 capacity;   /* event log capacity in # entries */
 787         u32 base;       /* SRAM byte address of event log header */
 788         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 789         u32 num_wraps;  /* # times uCode wrapped to top of log */
 790         u32 next_entry; /* index of next entry to be written by uCode */
 791
 792         if (priv->ucode_type == UCODE_INIT)
 793                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 794         else
 795                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 796         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 797                 capacity = iwl_read_targ_mem(priv, base);
 798                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 799                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 800                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 801         } else
 802                 return;
 803
 804         if (num_wraps == priv->event_log.num_wraps) {
 805                 iwl_print_cont_event_trace(priv,
 806                                        base, priv->event_log.next_entry,
 807                                        next_entry - priv->event_log.next_entry,
 808                                        mode);
 809                 priv->event_log.non_wraps_count++;
 810         } else {
 811                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 812                         priv->event_log.wraps_more_count++;
 813                 else
 814                         priv->event_log.wraps_once_count++;
 815                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 816                                 num_wraps - priv->event_log.num_wraps,
 817                                 next_entry, priv->event_log.next_entry);
 818                 if (next_entry < priv->event_log.next_entry) {
 819                         iwl_print_cont_event_trace(priv, base,
 820                                priv->event_log.next_entry,
 821                                capacity - priv->event_log.next_entry,
 822                                mode);
 823
 824                         iwl_print_cont_event_trace(priv, base, 0,
 825                                 next_entry, mode);
 826                 } else {
 827                         iwl_print_cont_event_trace(priv, base,
 828                                next_entry, capacity - next_entry,
 829                                mode);
 830
 831                         iwl_print_cont_event_trace(priv, base, 0,
 832                                 next_entry, mode);
 833                 }
 834         }
 835         priv->event_log.num_wraps = num_wraps;
 836         priv->event_log.next_entry = next_entry;
 837 }
 838
 839 /**
 840  * iwl_bg_ucode_trace - Timer callback to log ucode event
 841  *
 842  * The timer is continually set to execute every
 843  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 844  * this function is to perform continuous uCode event logging operation
 845  * if enabled
 846  */
 847 static void iwl_bg_ucode_trace(unsigned long data)
 848 {
 849         struct iwl_priv *priv = (struct iwl_priv *)data;
 850
 851         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 852                 return;
 853
 854         if (priv->event_log.ucode_trace) {
 855                 iwl_continuous_event_trace(priv);
 856                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 857                 mod_timer(&priv->ucode_trace,
 858                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 859         }
 860 }
 861
 862 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 863                                 struct iwl_rx_mem_buffer *rxb)
 864 {
 865         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 866         struct iwl4965_beacon_notif *beacon =
 867                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 868 #ifdef CONFIG_IWLWIFI_DEBUG
 869         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 870
 871         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 872                 "tsf %d %d rate %d\n",
 873                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 874                 beacon->beacon_notify_hdr.failure_frame,
 875                 le32_to_cpu(beacon->ibss_mgr_status),
 876                 le32_to_cpu(beacon->high_tsf),
 877                 le32_to_cpu(beacon->low_tsf), rate);
 878 #endif
 879
 880         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 881
 882         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 883                 queue_work(priv->workqueue, &priv->beacon_update);
 884 }
 885
 886 /* Handle notification from uCode that card's power state is changing
 887  * due to software, hardware, or critical temperature RFKILL */
 888 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 889                                     struct iwl_rx_mem_buffer *rxb)
 890 {
 891         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 892         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 893         unsigned long status = priv->status;
 894
 895         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 896                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 897                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 898                           (flags & CT_CARD_DISABLED) ?
 899                           "Reached" : "Not reached");
 900
 901         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 902                      CT_CARD_DISABLED)) {
 903
 904                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 905                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 906
 907                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 908                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 909
 910                 if (!(flags & RXON_CARD_DISABLED)) {
 911                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 912                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 913                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 914                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 915                 }
 916                 if (flags & CT_CARD_DISABLED)
 917                         iwl_tt_enter_ct_kill(priv);
 918         }
 919         if (!(flags & CT_CARD_DISABLED))
 920                 iwl_tt_exit_ct_kill(priv);
 921
 922         if (flags & HW_CARD_DISABLED)
 923                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 924         else
 925                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 926
 927
 928         if (!(flags & RXON_CARD_DISABLED))
 929                 iwl_scan_cancel(priv);
 930
 931         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 932              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 933                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 934                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 935         else
 936                 wake_up_interruptible(&priv->wait_command_queue);
 937 }
 938
 939 static void iwl_bg_tx_flush(struct work_struct *work)
 940 {
 941         struct iwl_priv *priv =
 942                 container_of(work, struct iwl_priv, tx_flush);
 943
 944         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 945                 return;
 946
 947         /* do nothing if rf-kill is on */
 948         if (!iwl_is_ready_rf(priv))
 949                 return;
 950
 951         if (priv->cfg->ops->lib->txfifo_flush) {
 952                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 953                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 954         }
 955 }
 956
 957 /**
 958  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 959  *
 960  * Setup the RX handlers for each of the reply types sent from the uCode
 961  * to the host.
 962  *
 963  * This function chains into the hardware specific files for them to setup
 964  * any hardware specific handlers as well.
 965  */
 966 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 967 {
 968         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 969         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 970         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 971         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 972                         iwl_rx_spectrum_measure_notif;
 973         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 974         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 975             iwl_rx_pm_debug_statistics_notif;
 976         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 977
 978         /*
 979          * The same handler is used for both the REPLY to a discrete
 980          * statistics request from the host as well as for the periodic
 981          * statistics notifications (after received beacons) from the uCode.
 982          */
 983         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 984         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 985
 986         iwl_setup_rx_scan_handlers(priv);
 987
 988         /* status change handler */
 989         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 990
 991         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 992             iwl_rx_missed_beacon_notif;
 993         /* Rx handlers */
 994         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 995         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 996         /* block ack */
 997         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 998         /* Set up hardware specific Rx handlers */
 999         priv->cfg->ops->lib->rx_handler_setup(priv);
1000 }
1001
1002 /**
1003  * iwl_rx_handle - Main entry function for receiving responses from uCode
1004  *
1005  * Uses the priv->rx_handlers callback function array to invoke
1006  * the appropriate handlers, including command responses,
1007  * frame-received notifications, and other notifications.
1008  */
1009 void iwl_rx_handle(struct iwl_priv *priv)
1010 {
1011         struct iwl_rx_mem_buffer *rxb;
1012         struct iwl_rx_packet *pkt;
1013         struct iwl_rx_queue *rxq = &priv->rxq;
1014         u32 r, i;
1015         int reclaim;
1016         unsigned long flags;
1017         u8 fill_rx = 0;
1018         u32 count = 8;
1019         int total_empty;
1020
1021         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1022          * buffer that the driver may process (last buffer filled by ucode). */
1023         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1024         i = rxq->read;
1025
1026         /* Rx interrupt, but nothing sent from uCode */
1027         if (i == r)
1028                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1029
1030         /* calculate total frames need to be restock after handling RX */
1031         total_empty = r - rxq->write_actual;
1032         if (total_empty < 0)
1033                 total_empty += RX_QUEUE_SIZE;
1034
1035         if (total_empty > (RX_QUEUE_SIZE / 2))
1036                 fill_rx = 1;
1037
1038         while (i != r) {
1039                 int len;
1040
1041                 rxb = rxq->queue[i];
1042
1043                 /* If an RXB doesn't have a Rx queue slot associated with it,
1044                  * then a bug has been introduced in the queue refilling
1045                  * routines -- catch it here */
1046                 BUG_ON(rxb == NULL);
1047
1048                 rxq->queue[i] = NULL;
1049
1050                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1051                                PAGE_SIZE << priv->hw_params.rx_page_order,
1052                                PCI_DMA_FROMDEVICE);
1053                 pkt = rxb_addr(rxb);
1054
1055                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1056                 len += sizeof(u32); /* account for status word */
1057                 trace_iwlwifi_dev_rx(priv, pkt, len);
1058
1059                 /* Reclaim a command buffer only if this packet is a response
1060                  *   to a (driver-originated) command.
1061                  * If the packet (e.g. Rx frame) originated from uCode,
1062                  *   there is no command buffer to reclaim.
1063                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1064                  *   but apparently a few don't get set; catch them here. */
1065                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1066                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1067                         (pkt->hdr.cmd != REPLY_RX) &&
1068                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1069                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1070                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1071                         (pkt->hdr.cmd != REPLY_TX);
1072
1073                 /* Based on type of command response or notification,
1074                  *   handle those that need handling via function in
1075                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1076                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1077                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1078                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1079                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1080                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1081                 } else {
1082                         /* No handling needed */
1083                         IWL_DEBUG_RX(priv,
1084                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1085                                 r, i, get_cmd_string(pkt->hdr.cmd),
1086                                 pkt->hdr.cmd);
1087                 }
1088
1089                 /*
1090                  * XXX: After here, we should always check rxb->page
1091                  * against NULL before touching it or its virtual
1092                  * memory (pkt). Because some rx_handler might have
1093                  * already taken or freed the pages.
1094                  */
1095
1096                 if (reclaim) {
1097                         /* Invoke any callbacks, transfer the buffer to caller,
1098                          * and fire off the (possibly) blocking iwl_send_cmd()
1099                          * as we reclaim the driver command queue */
1100                         if (rxb->page)
1101                                 iwl_tx_cmd_complete(priv, rxb);
1102                         else
1103                                 IWL_WARN(priv, "Claim null rxb?\n");
1104                 }
1105
1106                 /* Reuse the page if possible. For notification packets and
1107                  * SKBs that fail to Rx correctly, add them back into the
1108                  * rx_free list for reuse later. */
1109                 spin_lock_irqsave(&rxq->lock, flags);
1110                 if (rxb->page != NULL) {
1111                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1112                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1113                                 PCI_DMA_FROMDEVICE);
1114                         list_add_tail(&rxb->list, &rxq->rx_free);
1115                         rxq->free_count++;
1116                 } else
1117                         list_add_tail(&rxb->list, &rxq->rx_used);
1118
1119                 spin_unlock_irqrestore(&rxq->lock, flags);
1120
1121                 i = (i + 1) & RX_QUEUE_MASK;
1122                 /* If there are a lot of unused frames,
1123                  * restock the Rx queue so ucode wont assert. */
1124                 if (fill_rx) {
1125                         count++;
1126                         if (count >= 8) {
1127                                 rxq->read = i;
1128                                 iwlagn_rx_replenish_now(priv);
1129                                 count = 0;
1130                         }
1131                 }
1132         }
1133
1134         /* Backtrack one entry */
1135         rxq->read = i;
1136         if (fill_rx)
1137                 iwlagn_rx_replenish_now(priv);
1138         else
1139                 iwlagn_rx_queue_restock(priv);
1140 }
1141
1142 /* call this function to flush any scheduled tasklet */
1143 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1144 {
1145         /* wait to make sure we flush pending tasklet*/
1146         synchronize_irq(priv->pci_dev->irq);
1147         tasklet_kill(&priv->irq_tasklet);
1148 }
1149
1150 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1151 {
1152         u32 inta, handled = 0;
1153         u32 inta_fh;
1154         unsigned long flags;
1155         u32 i;
1156 #ifdef CONFIG_IWLWIFI_DEBUG
1157         u32 inta_mask;
1158 #endif
1159
1160         spin_lock_irqsave(&priv->lock, flags);
1161
1162         /* Ack/clear/reset pending uCode interrupts.
1163          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1164          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1165         inta = iwl_read32(priv, CSR_INT);
1166         iwl_write32(priv, CSR_INT, inta);
1167
1168         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1169          * Any new interrupts that happen after this, either while we're
1170          * in this tasklet, or later, will show up in next ISR/tasklet. */
1171         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1172         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1173
1174 #ifdef CONFIG_IWLWIFI_DEBUG
1175         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1176                 /* just for debug */
1177                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1178                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1179                               inta, inta_mask, inta_fh);
1180         }
1181 #endif
1182
1183         spin_unlock_irqrestore(&priv->lock, flags);
1184
1185         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1186          * atomic, make sure that inta covers all the interrupts that
1187          * we've discovered, even if FH interrupt came in just after
1188          * reading CSR_INT. */
1189         if (inta_fh & CSR49_FH_INT_RX_MASK)
1190                 inta |= CSR_INT_BIT_FH_RX;
1191         if (inta_fh & CSR49_FH_INT_TX_MASK)
1192                 inta |= CSR_INT_BIT_FH_TX;
1193
1194         /* Now service all interrupt bits discovered above. */
1195         if (inta & CSR_INT_BIT_HW_ERR) {
1196                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1197
1198                 /* Tell the device to stop sending interrupts */
1199                 iwl_disable_interrupts(priv);
1200
1201                 priv->isr_stats.hw++;
1202                 iwl_irq_handle_error(priv);
1203
1204                 handled |= CSR_INT_BIT_HW_ERR;
1205
1206                 return;
1207         }
1208
1209 #ifdef CONFIG_IWLWIFI_DEBUG
1210         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1211                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1212                 if (inta & CSR_INT_BIT_SCD) {
1213                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1214                                       "the frame/frames.\n");
1215                         priv->isr_stats.sch++;
1216                 }
1217
1218                 /* Alive notification via Rx interrupt will do the real work */
1219                 if (inta & CSR_INT_BIT_ALIVE) {
1220                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1221                         priv->isr_stats.alive++;
1222                 }
1223         }
1224 #endif
1225         /* Safely ignore these bits for debug checks below */
1226         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1227
1228         /* HW RF KILL switch toggled */
1229         if (inta & CSR_INT_BIT_RF_KILL) {
1230                 int hw_rf_kill = 0;
1231                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1232                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1233                         hw_rf_kill = 1;
1234
1235                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1236                                 hw_rf_kill ? "disable radio" : "enable radio");
1237
1238                 priv->isr_stats.rfkill++;
1239
1240                 /* driver only loads ucode once setting the interface up.
1241                  * the driver allows loading the ucode even if the radio
1242                  * is killed. Hence update the killswitch state here. The
1243                  * rfkill handler will care about restarting if needed.
1244                  */
1245                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1246                         if (hw_rf_kill)
1247                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1248                         else
1249                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1250                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1251                 }
1252
1253                 handled |= CSR_INT_BIT_RF_KILL;
1254         }
1255
1256         /* Chip got too hot and stopped itself */
1257         if (inta & CSR_INT_BIT_CT_KILL) {
1258                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1259                 priv->isr_stats.ctkill++;
1260                 handled |= CSR_INT_BIT_CT_KILL;
1261         }
1262
1263         /* Error detected by uCode */
1264         if (inta & CSR_INT_BIT_SW_ERR) {
1265                 IWL_ERR(priv, "Microcode SW error detected. "
1266                         " Restarting 0x%X.\n", inta);
1267                 priv->isr_stats.sw++;
1268                 iwl_irq_handle_error(priv);
1269                 handled |= CSR_INT_BIT_SW_ERR;
1270         }
1271
1272         /*
1273          * uCode wakes up after power-down sleep.
1274          * Tell device about any new tx or host commands enqueued,
1275          * and about any Rx buffers made available while asleep.
1276          */
1277         if (inta & CSR_INT_BIT_WAKEUP) {
1278                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1279                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1280                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1281                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1282                 priv->isr_stats.wakeup++;
1283                 handled |= CSR_INT_BIT_WAKEUP;
1284         }
1285
1286         /* All uCode command responses, including Tx command responses,
1287          * Rx "responses" (frame-received notification), and other
1288          * notifications from uCode come through here*/
1289         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1290                 iwl_rx_handle(priv);
1291                 priv->isr_stats.rx++;
1292                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1293         }
1294
1295         /* This "Tx" DMA channel is used only for loading uCode */
1296         if (inta & CSR_INT_BIT_FH_TX) {
1297                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1298                 priv->isr_stats.tx++;
1299                 handled |= CSR_INT_BIT_FH_TX;
1300                 /* Wake up uCode load routine, now that load is complete */
1301                 priv->ucode_write_complete = 1;
1302                 wake_up_interruptible(&priv->wait_command_queue);
1303         }
1304
1305         if (inta & ~handled) {
1306                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1307                 priv->isr_stats.unhandled++;
1308         }
1309
1310         if (inta & ~(priv->inta_mask)) {
1311                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1312                          inta & ~priv->inta_mask);
1313                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1314         }
1315
1316         /* Re-enable all interrupts */
1317         /* only Re-enable if diabled by irq */
1318         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1319                 iwl_enable_interrupts(priv);
1320
1321 #ifdef CONFIG_IWLWIFI_DEBUG
1322         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1323                 inta = iwl_read32(priv, CSR_INT);
1324                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1325                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1326                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1327                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1328         }
1329 #endif
1330 }
1331
1332 /* tasklet for iwlagn interrupt */
1333 static void iwl_irq_tasklet(struct iwl_priv *priv)
1334 {
1335         u32 inta = 0;
1336         u32 handled = 0;
1337         unsigned long flags;
1338         u32 i;
1339 #ifdef CONFIG_IWLWIFI_DEBUG
1340         u32 inta_mask;
1341 #endif
1342
1343         spin_lock_irqsave(&priv->lock, flags);
1344
1345         /* Ack/clear/reset pending uCode interrupts.
1346          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1347          */
1348         /* There is a hardware bug in the interrupt mask function that some
1349          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1350          * they are disabled in the CSR_INT_MASK register. Furthermore the
1351          * ICT interrupt handling mechanism has another bug that might cause
1352          * these unmasked interrupts fail to be detected. We workaround the
1353          * hardware bugs here by ACKing all the possible interrupts so that
1354          * interrupt coalescing can still be achieved.
1355          */
1356         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1357
1358         inta = priv->_agn.inta;
1359
1360 #ifdef CONFIG_IWLWIFI_DEBUG
1361         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1362                 /* just for debug */
1363                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1364                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1365                                 inta, inta_mask);
1366         }
1367 #endif
1368
1369         spin_unlock_irqrestore(&priv->lock, flags);
1370
1371         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1372         priv->_agn.inta = 0;
1373
1374         /* Now service all interrupt bits discovered above. */
1375         if (inta & CSR_INT_BIT_HW_ERR) {
1376                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1377
1378                 /* Tell the device to stop sending interrupts */
1379                 iwl_disable_interrupts(priv);
1380
1381                 priv->isr_stats.hw++;
1382                 iwl_irq_handle_error(priv);
1383
1384                 handled |= CSR_INT_BIT_HW_ERR;
1385
1386                 return;
1387         }
1388
1389 #ifdef CONFIG_IWLWIFI_DEBUG
1390         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1391                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1392                 if (inta & CSR_INT_BIT_SCD) {
1393                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1394                                       "the frame/frames.\n");
1395                         priv->isr_stats.sch++;
1396                 }
1397
1398                 /* Alive notification via Rx interrupt will do the real work */
1399                 if (inta & CSR_INT_BIT_ALIVE) {
1400                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1401                         priv->isr_stats.alive++;
1402                 }
1403         }
1404 #endif
1405         /* Safely ignore these bits for debug checks below */
1406         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1407
1408         /* HW RF KILL switch toggled */
1409         if (inta & CSR_INT_BIT_RF_KILL) {
1410                 int hw_rf_kill = 0;
1411                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1412                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1413                         hw_rf_kill = 1;
1414
1415                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1416                                 hw_rf_kill ? "disable radio" : "enable radio");
1417
1418                 priv->isr_stats.rfkill++;
1419
1420                 /* driver only loads ucode once setting the interface up.
1421                  * the driver allows loading the ucode even if the radio
1422                  * is killed. Hence update the killswitch state here. The
1423                  * rfkill handler will care about restarting if needed.
1424                  */
1425                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1426                         if (hw_rf_kill)
1427                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1428                         else
1429                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1430                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1431                 }
1432
1433                 handled |= CSR_INT_BIT_RF_KILL;
1434         }
1435
1436         /* Chip got too hot and stopped itself */
1437         if (inta & CSR_INT_BIT_CT_KILL) {
1438                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1439                 priv->isr_stats.ctkill++;
1440                 handled |= CSR_INT_BIT_CT_KILL;
1441         }
1442
1443         /* Error detected by uCode */
1444         if (inta & CSR_INT_BIT_SW_ERR) {
1445                 IWL_ERR(priv, "Microcode SW error detected. "
1446                         " Restarting 0x%X.\n", inta);
1447                 priv->isr_stats.sw++;
1448                 iwl_irq_handle_error(priv);
1449                 handled |= CSR_INT_BIT_SW_ERR;
1450         }
1451
1452         /* uCode wakes up after power-down sleep */
1453         if (inta & CSR_INT_BIT_WAKEUP) {
1454                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1455                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1456                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1457                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1458
1459                 priv->isr_stats.wakeup++;
1460
1461                 handled |= CSR_INT_BIT_WAKEUP;
1462         }
1463
1464         /* All uCode command responses, including Tx command responses,
1465          * Rx "responses" (frame-received notification), and other
1466          * notifications from uCode come through here*/
1467         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1468                         CSR_INT_BIT_RX_PERIODIC)) {
1469                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1470                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1471                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1472                         iwl_write32(priv, CSR_FH_INT_STATUS,
1473                                         CSR49_FH_INT_RX_MASK);
1474                 }
1475                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1476                         handled |= CSR_INT_BIT_RX_PERIODIC;
1477                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1478                 }
1479                 /* Sending RX interrupt require many steps to be done in the
1480                  * the device:
1481                  * 1- write interrupt to current index in ICT table.
1482                  * 2- dma RX frame.
1483                  * 3- update RX shared data to indicate last write index.
1484                  * 4- send interrupt.
1485                  * This could lead to RX race, driver could receive RX interrupt
1486                  * but the shared data changes does not reflect this;
1487                  * periodic interrupt will detect any dangling Rx activity.
1488                  */
1489
1490                 /* Disable periodic interrupt; we use it as just a one-shot. */
1491                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1492                             CSR_INT_PERIODIC_DIS);
1493                 iwl_rx_handle(priv);
1494
1495                 /*
1496                  * Enable periodic interrupt in 8 msec only if we received
1497                  * real RX interrupt (instead of just periodic int), to catch
1498                  * any dangling Rx interrupt.  If it was just the periodic
1499                  * interrupt, there was no dangling Rx activity, and no need
1500                  * to extend the periodic interrupt; one-shot is enough.
1501                  */
1502                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1503                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1504                                     CSR_INT_PERIODIC_ENA);
1505
1506                 priv->isr_stats.rx++;
1507         }
1508
1509         /* This "Tx" DMA channel is used only for loading uCode */
1510         if (inta & CSR_INT_BIT_FH_TX) {
1511                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1512                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1513                 priv->isr_stats.tx++;
1514                 handled |= CSR_INT_BIT_FH_TX;
1515                 /* Wake up uCode load routine, now that load is complete */
1516                 priv->ucode_write_complete = 1;
1517                 wake_up_interruptible(&priv->wait_command_queue);
1518         }
1519
1520         if (inta & ~handled) {
1521                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1522                 priv->isr_stats.unhandled++;
1523         }
1524
1525         if (inta & ~(priv->inta_mask)) {
1526                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1527                          inta & ~priv->inta_mask);
1528         }
1529
1530         /* Re-enable all interrupts */
1531         /* only Re-enable if diabled by irq */
1532         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1533                 iwl_enable_interrupts(priv);
1534 }
1535
1536 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1537 #define ACK_CNT_RATIO (50)
1538 #define BA_TIMEOUT_CNT (5)
1539 #define BA_TIMEOUT_MAX (16)
1540
1541 /**
1542  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1543  *
1544  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1545  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1546  * operation state.
1547  */
1548 bool iwl_good_ack_health(struct iwl_priv *priv,
1549                                 struct iwl_rx_packet *pkt)
1550 {
1551         bool rc = true;
1552         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1553         int ba_timeout_delta;
1554
1555         actual_ack_cnt_delta =
1556                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1557                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1558         expected_ack_cnt_delta =
1559                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1560                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1561         ba_timeout_delta =
1562                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1563                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1564         if ((priv->_agn.agg_tids_count > 0) &&
1565             (expected_ack_cnt_delta > 0) &&
1566             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1567                 < ACK_CNT_RATIO) &&
1568             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1569                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1570                                 " expected_ack_cnt = %d\n",
1571                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1572
1573 #ifdef CONFIG_IWLWIFI_DEBUGFS
1574                 /*
1575                  * This is ifdef'ed on DEBUGFS because otherwise the
1576                  * statistics aren't available. If DEBUGFS is set but
1577                  * DEBUG is not, these will just compile out.
1578                  */
1579                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1580                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1581                 IWL_DEBUG_RADIO(priv,
1582                                 "ack_or_ba_timeout_collision delta = %d\n",
1583                                 priv->_agn.delta_statistics.tx.
1584                                 ack_or_ba_timeout_collision);
1585 #endif
1586                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1587                                 ba_timeout_delta);
1588                 if (!actual_ack_cnt_delta &&
1589                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1590                         rc = false;
1591         }
1592         return rc;
1593 }
1594
1595
1596 /*****************************************************************************
1597  *
1598  * sysfs attributes
1599  *
1600  *****************************************************************************/
1601
1602 #ifdef CONFIG_IWLWIFI_DEBUG
1603
1604 /*
1605  * The following adds a new attribute to the sysfs representation
1606  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1607  * used for controlling the debug level.
1608  *
1609  * See the level definitions in iwl for details.
1610  *
1611  * The debug_level being managed using sysfs below is a per device debug
1612  * level that is used instead of the global debug level if it (the per
1613  * device debug level) is set.
1614  */
1615 static ssize_t show_debug_level(struct device *d,
1616                                 struct device_attribute *attr, char *buf)
1617 {
1618         struct iwl_priv *priv = dev_get_drvdata(d);
1619         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1620 }
1621 static ssize_t store_debug_level(struct device *d,
1622                                 struct device_attribute *attr,
1623                                  const char *buf, size_t count)
1624 {
1625         struct iwl_priv *priv = dev_get_drvdata(d);
1626         unsigned long val;
1627         int ret;
1628
1629         ret = strict_strtoul(buf, 0, &val);
1630         if (ret)
1631                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1632         else {
1633                 priv->debug_level = val;
1634                 if (iwl_alloc_traffic_mem(priv))
1635                         IWL_ERR(priv,
1636                                 "Not enough memory to generate traffic log\n");
1637         }
1638         return strnlen(buf, count);
1639 }
1640
1641 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1642                         show_debug_level, store_debug_level);
1643
1644
1645 #endif /* CONFIG_IWLWIFI_DEBUG */
1646
1647
1648 static ssize_t show_temperature(struct device *d,
1649                                 struct device_attribute *attr, char *buf)
1650 {
1651         struct iwl_priv *priv = dev_get_drvdata(d);
1652
1653         if (!iwl_is_alive(priv))
1654                 return -EAGAIN;
1655
1656         return sprintf(buf, "%d\n", priv->temperature);
1657 }
1658
1659 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1660
1661 static ssize_t show_tx_power(struct device *d,
1662                              struct device_attribute *attr, char *buf)
1663 {
1664         struct iwl_priv *priv = dev_get_drvdata(d);
1665
1666         if (!iwl_is_ready_rf(priv))
1667                 return sprintf(buf, "off\n");
1668         else
1669                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1670 }
1671
1672 static ssize_t store_tx_power(struct device *d,
1673                               struct device_attribute *attr,
1674                               const char *buf, size_t count)
1675 {
1676         struct iwl_priv *priv = dev_get_drvdata(d);
1677         unsigned long val;
1678         int ret;
1679
1680         ret = strict_strtoul(buf, 10, &val);
1681         if (ret)
1682                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1683         else {
1684                 ret = iwl_set_tx_power(priv, val, false);
1685                 if (ret)
1686                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1687                                 ret);
1688                 else
1689                         ret = count;
1690         }
1691         return ret;
1692 }
1693
1694 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1695
1696 static struct attribute *iwl_sysfs_entries[] = {
1697         &dev_attr_temperature.attr,
1698         &dev_attr_tx_power.attr,
1699 #ifdef CONFIG_IWLWIFI_DEBUG
1700         &dev_attr_debug_level.attr,
1701 #endif
1702         NULL
1703 };
1704
1705 static struct attribute_group iwl_attribute_group = {
1706         .name = NULL,           /* put in device directory */
1707         .attrs = iwl_sysfs_entries,
1708 };
1709
1710 /******************************************************************************
1711  *
1712  * uCode download functions
1713  *
1714  ******************************************************************************/
1715
1716 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1717 {
1718         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1719         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1720         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1721         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1722         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1723         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1724 }
1725
1726 static void iwl_nic_start(struct iwl_priv *priv)
1727 {
1728         /* Remove all resets to allow NIC to operate */
1729         iwl_write32(priv, CSR_RESET, 0);
1730 }
1731
1732 struct iwlagn_ucode_capabilities {
1733         u32 max_probe_length;
1734         u32 standard_phy_calibration_size;
1735         bool pan;
1736 };
1737
1738 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1739 static int iwl_mac_setup_register(struct iwl_priv *priv,
1740                                   struct iwlagn_ucode_capabilities *capa);
1741
1742 #define UCODE_EXPERIMENTAL_INDEX        100
1743 #define UCODE_EXPERIMENTAL_TAG          "exp"
1744
1745 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1746 {
1747         const char *name_pre = priv->cfg->fw_name_pre;
1748         char tag[8];
1749
1750         if (first) {
1751 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1752                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1753                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1754         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1755 #endif
1756                 priv->fw_index = priv->cfg->ucode_api_max;
1757                 sprintf(tag, "%d", priv->fw_index);
1758         } else {
1759                 priv->fw_index--;
1760                 sprintf(tag, "%d", priv->fw_index);
1761         }
1762
1763         if (priv->fw_index < priv->cfg->ucode_api_min) {
1764                 IWL_ERR(priv, "no suitable firmware found!\n");
1765                 return -ENOENT;
1766         }
1767
1768         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1769
1770         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1771                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1772                                 ? "EXPERIMENTAL " : "",
1773                        priv->firmware_name);
1774
1775         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1776                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1777                                        iwl_ucode_callback);
1778 }
1779
1780 struct iwlagn_firmware_pieces {
1781         const void *inst, *data, *init, *init_data, *boot;
1782         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1783
1784         u32 build;
1785
1786         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1787         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1788 };
1789
1790 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1791                                        const struct firmware *ucode_raw,
1792                                        struct iwlagn_firmware_pieces *pieces)
1793 {
1794         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1795         u32 api_ver, hdr_size;
1796         const u8 *src;
1797
1798         priv->ucode_ver = le32_to_cpu(ucode->ver);
1799         api_ver = IWL_UCODE_API(priv->ucode_ver);
1800
1801         switch (api_ver) {
1802         default:
1803                 /*
1804                  * 4965 doesn't revision the firmware file format
1805                  * along with the API version, it always uses v1
1806                  * file format.
1807                  */
1808                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1809                                 CSR_HW_REV_TYPE_4965) {
1810                         hdr_size = 28;
1811                         if (ucode_raw->size < hdr_size) {
1812                                 IWL_ERR(priv, "File size too small!\n");
1813                                 return -EINVAL;
1814                         }
1815                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1816                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1817                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1818                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1819                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1820                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1821                         src = ucode->u.v2.data;
1822                         break;
1823                 }
1824                 /* fall through for 4965 */
1825         case 0:
1826         case 1:
1827         case 2:
1828                 hdr_size = 24;
1829                 if (ucode_raw->size < hdr_size) {
1830                         IWL_ERR(priv, "File size too small!\n");
1831                         return -EINVAL;
1832                 }
1833                 pieces->build = 0;
1834                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1835                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1836                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1837                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1838                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1839                 src = ucode->u.v1.data;
1840                 break;
1841         }
1842
1843         /* Verify size of file vs. image size info in file's header */
1844         if (ucode_raw->size != hdr_size + pieces->inst_size +
1845                                 pieces->data_size + pieces->init_size +
1846                                 pieces->init_data_size + pieces->boot_size) {
1847
1848                 IWL_ERR(priv,
1849                         "uCode file size %d does not match expected size\n",
1850                         (int)ucode_raw->size);
1851                 return -EINVAL;
1852         }
1853
1854         pieces->inst = src;
1855         src += pieces->inst_size;
1856         pieces->data = src;
1857         src += pieces->data_size;
1858         pieces->init = src;
1859         src += pieces->init_size;
1860         pieces->init_data = src;
1861         src += pieces->init_data_size;
1862         pieces->boot = src;
1863         src += pieces->boot_size;
1864
1865         return 0;
1866 }
1867
1868 static int iwlagn_wanted_ucode_alternative = 1;
1869
1870 static int iwlagn_load_firmware(struct iwl_priv *priv,
1871                                 const struct firmware *ucode_raw,
1872                                 struct iwlagn_firmware_pieces *pieces,
1873                                 struct iwlagn_ucode_capabilities *capa)
1874 {
1875         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1876         struct iwl_ucode_tlv *tlv;
1877         size_t len = ucode_raw->size;
1878         const u8 *data;
1879         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1880         u64 alternatives;
1881         u32 tlv_len;
1882         enum iwl_ucode_tlv_type tlv_type;
1883         const u8 *tlv_data;
1884
1885         if (len < sizeof(*ucode)) {
1886                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1887                 return -EINVAL;
1888         }
1889
1890         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1891                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1892                         le32_to_cpu(ucode->magic));
1893                 return -EINVAL;
1894         }
1895
1896         /*
1897          * Check which alternatives are present, and "downgrade"
1898          * when the chosen alternative is not present, warning
1899          * the user when that happens. Some files may not have
1900          * any alternatives, so don't warn in that case.
1901          */
1902         alternatives = le64_to_cpu(ucode->alternatives);
1903         tmp = wanted_alternative;
1904         if (wanted_alternative > 63)
1905                 wanted_alternative = 63;
1906         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1907                 wanted_alternative--;
1908         if (wanted_alternative && wanted_alternative != tmp)
1909                 IWL_WARN(priv,
1910                          "uCode alternative %d not available, choosing %d\n",
1911                          tmp, wanted_alternative);
1912
1913         priv->ucode_ver = le32_to_cpu(ucode->ver);
1914         pieces->build = le32_to_cpu(ucode->build);
1915         data = ucode->data;
1916
1917         len -= sizeof(*ucode);
1918
1919         while (len >= sizeof(*tlv)) {
1920                 u16 tlv_alt;
1921
1922                 len -= sizeof(*tlv);
1923                 tlv = (void *)data;
1924
1925                 tlv_len = le32_to_cpu(tlv->length);
1926                 tlv_type = le16_to_cpu(tlv->type);
1927                 tlv_alt = le16_to_cpu(tlv->alternative);
1928                 tlv_data = tlv->data;
1929
1930                 if (len < tlv_len) {
1931                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1932                                 len, tlv_len);
1933                         return -EINVAL;
1934                 }
1935                 len -= ALIGN(tlv_len, 4);
1936                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1937
1938                 /*
1939                  * Alternative 0 is always valid.
1940                  *
1941                  * Skip alternative TLVs that are not selected.
1942                  */
1943                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1944                         continue;
1945
1946                 switch (tlv_type) {
1947                 case IWL_UCODE_TLV_INST:
1948                         pieces->inst = tlv_data;
1949                         pieces->inst_size = tlv_len;
1950                         break;
1951                 case IWL_UCODE_TLV_DATA:
1952                         pieces->data = tlv_data;
1953                         pieces->data_size = tlv_len;
1954                         break;
1955                 case IWL_UCODE_TLV_INIT:
1956                         pieces->init = tlv_data;
1957                         pieces->init_size = tlv_len;
1958                         break;
1959                 case IWL_UCODE_TLV_INIT_DATA:
1960                         pieces->init_data = tlv_data;
1961                         pieces->init_data_size = tlv_len;
1962                         break;
1963                 case IWL_UCODE_TLV_BOOT:
1964                         pieces->boot = tlv_data;
1965                         pieces->boot_size = tlv_len;
1966                         break;
1967                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1968                         if (tlv_len != sizeof(u32))
1969                                 goto invalid_tlv_len;
1970                         capa->max_probe_length =
1971                                         le32_to_cpup((__le32 *)tlv_data);
1972                         break;
1973                 case IWL_UCODE_TLV_PAN:
1974                         if (tlv_len)
1975                                 goto invalid_tlv_len;
1976                         capa->pan = true;
1977                         break;
1978                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1979                         if (tlv_len != sizeof(u32))
1980                                 goto invalid_tlv_len;
1981                         pieces->init_evtlog_ptr =
1982                                         le32_to_cpup((__le32 *)tlv_data);
1983                         break;
1984                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1985                         if (tlv_len != sizeof(u32))
1986                                 goto invalid_tlv_len;
1987                         pieces->init_evtlog_size =
1988                                         le32_to_cpup((__le32 *)tlv_data);
1989                         break;
1990                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1991                         if (tlv_len != sizeof(u32))
1992                                 goto invalid_tlv_len;
1993                         pieces->init_errlog_ptr =
1994                                         le32_to_cpup((__le32 *)tlv_data);
1995                         break;
1996                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1997                         if (tlv_len != sizeof(u32))
1998                                 goto invalid_tlv_len;
1999                         pieces->inst_evtlog_ptr =
2000                                         le32_to_cpup((__le32 *)tlv_data);
2001                         break;
2002                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
2003                         if (tlv_len != sizeof(u32))
2004                                 goto invalid_tlv_len;
2005                         pieces->inst_evtlog_size =
2006                                         le32_to_cpup((__le32 *)tlv_data);
2007                         break;
2008                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
2009                         if (tlv_len != sizeof(u32))
2010                                 goto invalid_tlv_len;
2011                         pieces->inst_errlog_ptr =
2012                                         le32_to_cpup((__le32 *)tlv_data);
2013                         break;
2014                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2015                         if (tlv_len)
2016                                 goto invalid_tlv_len;
2017                         priv->enhance_sensitivity_table = true;
2018                         break;
2019                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
2020                         if (tlv_len != sizeof(u32))
2021                                 goto invalid_tlv_len;
2022                         capa->standard_phy_calibration_size =
2023                                         le32_to_cpup((__le32 *)tlv_data);
2024                         break;
2025                 default:
2026                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2027                         break;
2028                 }
2029         }
2030
2031         if (len) {
2032                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2033                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2034                 return -EINVAL;
2035         }
2036
2037         return 0;
2038
2039  invalid_tlv_len:
2040         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2041         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2042
2043         return -EINVAL;
2044 }
2045
2046 /**
2047  * iwl_ucode_callback - callback when firmware was loaded
2048  *
2049  * If loaded successfully, copies the firmware into buffers
2050  * for the card to fetch (via DMA).
2051  */
2052 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2053 {
2054         struct iwl_priv *priv = context;
2055         struct iwl_ucode_header *ucode;
2056         int err;
2057         struct iwlagn_firmware_pieces pieces;
2058         const unsigned int api_max = priv->cfg->ucode_api_max;
2059         const unsigned int api_min = priv->cfg->ucode_api_min;
2060         u32 api_ver;
2061         char buildstr[25];
2062         u32 build;
2063         struct iwlagn_ucode_capabilities ucode_capa = {
2064                 .max_probe_length = 200,
2065                 .standard_phy_calibration_size =
2066                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2067         };
2068
2069         memset(&pieces, 0, sizeof(pieces));
2070
2071         if (!ucode_raw) {
2072                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2073                         IWL_ERR(priv,
2074                                 "request for firmware file '%s' failed.\n",
2075                                 priv->firmware_name);
2076                 goto try_again;
2077         }
2078
2079         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2080                        priv->firmware_name, ucode_raw->size);
2081
2082         /* Make sure that we got at least the API version number */
2083         if (ucode_raw->size < 4) {
2084                 IWL_ERR(priv, "File size way too small!\n");
2085                 goto try_again;
2086         }
2087
2088         /* Data from ucode file:  header followed by uCode images */
2089         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2090
2091         if (ucode->ver)
2092                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2093         else
2094                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2095                                            &ucode_capa);
2096
2097         if (err)
2098                 goto try_again;
2099
2100         api_ver = IWL_UCODE_API(priv->ucode_ver);
2101         build = pieces.build;
2102
2103         /*
2104          * api_ver should match the api version forming part of the
2105          * firmware filename ... but we don't check for that and only rely
2106          * on the API version read from firmware header from here on forward
2107          */
2108         /* no api version check required for experimental uCode */
2109         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
2110                 if (api_ver < api_min || api_ver > api_max) {
2111                         IWL_ERR(priv,
2112                                 "Driver unable to support your firmware API. "
2113                                 "Driver supports v%u, firmware is v%u.\n",
2114                                 api_max, api_ver);
2115                         goto try_again;
2116                 }
2117
2118                 if (api_ver != api_max)
2119                         IWL_ERR(priv,
2120                                 "Firmware has old API version. Expected v%u, "
2121                                 "got v%u. New firmware can be obtained "
2122                                 "from http://www.intellinuxwireless.org.\n",
2123                                 api_max, api_ver);
2124         }
2125
2126         if (build)
2127                 sprintf(buildstr, " build %u%s", build,
2128                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2129                                 ? " (EXP)" : "");
2130         else
2131                 buildstr[0] = '\0';
2132
2133         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2134                  IWL_UCODE_MAJOR(priv->ucode_ver),
2135                  IWL_UCODE_MINOR(priv->ucode_ver),
2136                  IWL_UCODE_API(priv->ucode_ver),
2137                  IWL_UCODE_SERIAL(priv->ucode_ver),
2138                  buildstr);
2139
2140         snprintf(priv->hw->wiphy->fw_version,
2141                  sizeof(priv->hw->wiphy->fw_version),
2142                  "%u.%u.%u.%u%s",
2143                  IWL_UCODE_MAJOR(priv->ucode_ver),
2144                  IWL_UCODE_MINOR(priv->ucode_ver),
2145                  IWL_UCODE_API(priv->ucode_ver),
2146                  IWL_UCODE_SERIAL(priv->ucode_ver),
2147                  buildstr);
2148
2149         /*
2150          * For any of the failures below (before allocating pci memory)
2151          * we will try to load a version with a smaller API -- maybe the
2152          * user just got a corrupted version of the latest API.
2153          */
2154
2155         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2156                        priv->ucode_ver);
2157         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2158                        pieces.inst_size);
2159         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2160                        pieces.data_size);
2161         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2162                        pieces.init_size);
2163         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2164                        pieces.init_data_size);
2165         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2166                        pieces.boot_size);
2167
2168         /* Verify that uCode images will fit in card's SRAM */
2169         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2170                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2171                         pieces.inst_size);
2172                 goto try_again;
2173         }
2174
2175         if (pieces.data_size > priv->hw_params.max_data_size) {
2176                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2177                         pieces.data_size);
2178                 goto try_again;
2179         }
2180
2181         if (pieces.init_size > priv->hw_params.max_inst_size) {
2182                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2183                         pieces.init_size);
2184                 goto try_again;
2185         }
2186
2187         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2188                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2189                         pieces.init_data_size);
2190                 goto try_again;
2191         }
2192
2193         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2194                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2195                         pieces.boot_size);
2196                 goto try_again;
2197         }
2198
2199         /* Allocate ucode buffers for card's bus-master loading ... */
2200
2201         /* Runtime instructions and 2 copies of data:
2202          * 1) unmodified from disk
2203          * 2) backup cache for save/restore during power-downs */
2204         priv->ucode_code.len = pieces.inst_size;
2205         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2206
2207         priv->ucode_data.len = pieces.data_size;
2208         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2209
2210         priv->ucode_data_backup.len = pieces.data_size;
2211         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2212
2213         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2214             !priv->ucode_data_backup.v_addr)
2215                 goto err_pci_alloc;
2216
2217         /* Initialization instructions and data */
2218         if (pieces.init_size && pieces.init_data_size) {
2219                 priv->ucode_init.len = pieces.init_size;
2220                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2221
2222                 priv->ucode_init_data.len = pieces.init_data_size;
2223                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2224
2225                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2226                         goto err_pci_alloc;
2227         }
2228
2229         /* Bootstrap (instructions only, no data) */
2230         if (pieces.boot_size) {
2231                 priv->ucode_boot.len = pieces.boot_size;
2232                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2233
2234                 if (!priv->ucode_boot.v_addr)
2235                         goto err_pci_alloc;
2236         }
2237
2238         /* Now that we can no longer fail, copy information */
2239
2240         /*
2241          * The (size - 16) / 12 formula is based on the information recorded
2242          * for each event, which is of mode 1 (including timestamp) for all
2243          * new microcodes that include this information.
2244          */
2245         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2246         if (pieces.init_evtlog_size)
2247                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2248         else
2249                 priv->_agn.init_evtlog_size =
2250                         priv->cfg->base_params->max_event_log_size;
2251         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2252         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2253         if (pieces.inst_evtlog_size)
2254                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2255         else
2256                 priv->_agn.inst_evtlog_size =
2257                         priv->cfg->base_params->max_event_log_size;
2258         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2259
2260         if (ucode_capa.pan) {
2261                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2262                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2263         } else
2264                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2265
2266         /* Copy images into buffers for card's bus-master reads ... */
2267
2268         /* Runtime instructions (first block of data in file) */
2269         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2270                         pieces.inst_size);
2271         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2272
2273         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2274                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2275
2276         /*
2277          * Runtime data
2278          * NOTE:  Copy into backup buffer will be done in iwl_up()
2279          */
2280         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2281                         pieces.data_size);
2282         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2283         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2284
2285         /* Initialization instructions */
2286         if (pieces.init_size) {
2287                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2288                                 pieces.init_size);
2289                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2290         }
2291
2292         /* Initialization data */
2293         if (pieces.init_data_size) {
2294                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2295                                pieces.init_data_size);
2296                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2297                        pieces.init_data_size);
2298         }
2299
2300         /* Bootstrap instructions */
2301         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2302                         pieces.boot_size);
2303         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2304
2305         /*
2306          * figure out the offset of chain noise reset and gain commands
2307          * base on the size of standard phy calibration commands table size
2308          */
2309         if (ucode_capa.standard_phy_calibration_size >
2310             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2311                 ucode_capa.standard_phy_calibration_size =
2312                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2313
2314         priv->_agn.phy_calib_chain_noise_reset_cmd =
2315                 ucode_capa.standard_phy_calibration_size;
2316         priv->_agn.phy_calib_chain_noise_gain_cmd =
2317                 ucode_capa.standard_phy_calibration_size + 1;
2318
2319         /**************************************************
2320          * This is still part of probe() in a sense...
2321          *
2322          * 9. Setup and register with mac80211 and debugfs
2323          **************************************************/
2324         err = iwl_mac_setup_register(priv, &ucode_capa);
2325         if (err)
2326                 goto out_unbind;
2327
2328         err = iwl_dbgfs_register(priv, DRV_NAME);
2329         if (err)
2330                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2331
2332         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2333                                         &iwl_attribute_group);
2334         if (err) {
2335                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2336                 goto out_unbind;
2337         }
2338
2339         /* We have our copies now, allow OS release its copies */
2340         release_firmware(ucode_raw);
2341         complete(&priv->_agn.firmware_loading_complete);
2342         return;
2343
2344  try_again:
2345         /* try next, if any */
2346         if (iwl_request_firmware(priv, false))
2347                 goto out_unbind;
2348         release_firmware(ucode_raw);
2349         return;
2350
2351  err_pci_alloc:
2352         IWL_ERR(priv, "failed to allocate pci memory\n");
2353         iwl_dealloc_ucode_pci(priv);
2354  out_unbind:
2355         complete(&priv->_agn.firmware_loading_complete);
2356         device_release_driver(&priv->pci_dev->dev);
2357         release_firmware(ucode_raw);
2358 }
2359
2360 static const char *desc_lookup_text[] = {
2361         "OK",
2362         "FAIL",
2363         "BAD_PARAM",
2364         "BAD_CHECKSUM",
2365         "NMI_INTERRUPT_WDG",
2366         "SYSASSERT",
2367         "FATAL_ERROR",
2368         "BAD_COMMAND",
2369         "HW_ERROR_TUNE_LOCK",
2370         "HW_ERROR_TEMPERATURE",
2371         "ILLEGAL_CHAN_FREQ",
2372         "VCC_NOT_STABLE",
2373         "FH_ERROR",
2374         "NMI_INTERRUPT_HOST",
2375         "NMI_INTERRUPT_ACTION_PT",
2376         "NMI_INTERRUPT_UNKNOWN",
2377         "UCODE_VERSION_MISMATCH",
2378         "HW_ERROR_ABS_LOCK",
2379         "HW_ERROR_CAL_LOCK_FAIL",
2380         "NMI_INTERRUPT_INST_ACTION_PT",
2381         "NMI_INTERRUPT_DATA_ACTION_PT",
2382         "NMI_TRM_HW_ER",
2383         "NMI_INTERRUPT_TRM",
2384         "NMI_INTERRUPT_BREAK_POINT"
2385         "DEBUG_0",
2386         "DEBUG_1",
2387         "DEBUG_2",
2388         "DEBUG_3",
2389 };
2390
2391 static struct { char *name; u8 num; } advanced_lookup[] = {
2392         { "NMI_INTERRUPT_WDG", 0x34 },
2393         { "SYSASSERT", 0x35 },
2394         { "UCODE_VERSION_MISMATCH", 0x37 },
2395         { "BAD_COMMAND", 0x38 },
2396         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2397         { "FATAL_ERROR", 0x3D },
2398         { "NMI_TRM_HW_ERR", 0x46 },
2399         { "NMI_INTERRUPT_TRM", 0x4C },
2400         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2401         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2402         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2403         { "NMI_INTERRUPT_HOST", 0x66 },
2404         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2405         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2406         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2407         { "ADVANCED_SYSASSERT", 0 },
2408 };
2409
2410 static const char *desc_lookup(u32 num)
2411 {
2412         int i;
2413         int max = ARRAY_SIZE(desc_lookup_text);
2414
2415         if (num < max)
2416                 return desc_lookup_text[num];
2417
2418         max = ARRAY_SIZE(advanced_lookup) - 1;
2419         for (i = 0; i < max; i++) {
2420                 if (advanced_lookup[i].num == num)
2421                         break;;
2422         }
2423         return advanced_lookup[i].name;
2424 }
2425
2426 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2427 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2428
2429 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2430 {
2431         u32 data2, line;
2432         u32 desc, time, count, base, data1;
2433         u32 blink1, blink2, ilink1, ilink2;
2434         u32 pc, hcmd;
2435
2436         if (priv->ucode_type == UCODE_INIT) {
2437                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2438                 if (!base)
2439                         base = priv->_agn.init_errlog_ptr;
2440         } else {
2441                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2442                 if (!base)
2443                         base = priv->_agn.inst_errlog_ptr;
2444         }
2445
2446         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2447                 IWL_ERR(priv,
2448                         "Not valid error log pointer 0x%08X for %s uCode\n",
2449                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2450                 return;
2451         }
2452
2453         count = iwl_read_targ_mem(priv, base);
2454
2455         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2456                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2457                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2458                         priv->status, count);
2459         }
2460
2461         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2462         priv->isr_stats.err_code = desc;
2463         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2464         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2465         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2466         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2467         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2468         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2469         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2470         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2471         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2472         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2473
2474         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2475                                       blink1, blink2, ilink1, ilink2);
2476
2477         IWL_ERR(priv, "Desc                                  Time       "
2478                 "data1      data2      line\n");
2479         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2480                 desc_lookup(desc), desc, time, data1, data2, line);
2481         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2482         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2483                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2484 }
2485
2486 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2487
2488 /**
2489  * iwl_print_event_log - Dump error event log to syslog
2490  *
2491  */
2492 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2493                                u32 num_events, u32 mode,
2494                                int pos, char **buf, size_t bufsz)
2495 {
2496         u32 i;
2497         u32 base;       /* SRAM byte address of event log header */
2498         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2499         u32 ptr;        /* SRAM byte address of log data */
2500         u32 ev, time, data; /* event log data */
2501         unsigned long reg_flags;
2502
2503         if (num_events == 0)
2504                 return pos;
2505
2506         if (priv->ucode_type == UCODE_INIT) {
2507                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2508                 if (!base)
2509                         base = priv->_agn.init_evtlog_ptr;
2510         } else {
2511                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2512                 if (!base)
2513                         base = priv->_agn.inst_evtlog_ptr;
2514         }
2515
2516         if (mode == 0)
2517                 event_size = 2 * sizeof(u32);
2518         else
2519                 event_size = 3 * sizeof(u32);
2520
2521         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2522
2523         /* Make sure device is powered up for SRAM reads */
2524         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2525         iwl_grab_nic_access(priv);
2526
2527         /* Set starting address; reads will auto-increment */
2528         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2529         rmb();
2530
2531         /* "time" is actually "data" for mode 0 (no timestamp).
2532         * place event id # at far right for easier visual parsing. */
2533         for (i = 0; i < num_events; i++) {
2534                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2535                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2536                 if (mode == 0) {
2537                         /* data, ev */
2538                         if (bufsz) {
2539                                 pos += scnprintf(*buf + pos, bufsz - pos,
2540                                                 "EVT_LOG:0x%08x:%04u\n",
2541                                                 time, ev);
2542                         } else {
2543                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2544                                         time, ev);
2545                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2546                                         time, ev);
2547                         }
2548                 } else {
2549                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2550                         if (bufsz) {
2551                                 pos += scnprintf(*buf + pos, bufsz - pos,
2552                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2553                                                  time, data, ev);
2554                         } else {
2555                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2556                                         time, data, ev);
2557                                 trace_iwlwifi_dev_ucode_event(priv, time,
2558                                         data, ev);
2559                         }
2560                 }
2561         }
2562
2563         /* Allow device to power down */
2564         iwl_release_nic_access(priv);
2565         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2566         return pos;
2567 }
2568
2569 /**
2570  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2571  */
2572 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2573                                     u32 num_wraps, u32 next_entry,
2574                                     u32 size, u32 mode,
2575                                     int pos, char **buf, size_t bufsz)
2576 {
2577         /*
2578          * display the newest DEFAULT_LOG_ENTRIES entries
2579          * i.e the entries just before the next ont that uCode would fill.
2580          */
2581         if (num_wraps) {
2582                 if (next_entry < size) {
2583                         pos = iwl_print_event_log(priv,
2584                                                 capacity - (size - next_entry),
2585                                                 size - next_entry, mode,
2586                                                 pos, buf, bufsz);
2587                         pos = iwl_print_event_log(priv, 0,
2588                                                   next_entry, mode,
2589                                                   pos, buf, bufsz);
2590                 } else
2591                         pos = iwl_print_event_log(priv, next_entry - size,
2592                                                   size, mode, pos, buf, bufsz);
2593         } else {
2594                 if (next_entry < size) {
2595                         pos = iwl_print_event_log(priv, 0, next_entry,
2596                                                   mode, pos, buf, bufsz);
2597                 } else {
2598                         pos = iwl_print_event_log(priv, next_entry - size,
2599                                                   size, mode, pos, buf, bufsz);
2600                 }
2601         }
2602         return pos;
2603 }
2604
2605 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2606
2607 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2608                             char **buf, bool display)
2609 {
2610         u32 base;       /* SRAM byte address of event log header */
2611         u32 capacity;   /* event log capacity in # entries */
2612         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2613         u32 num_wraps;  /* # times uCode wrapped to top of log */
2614         u32 next_entry; /* index of next entry to be written by uCode */
2615         u32 size;       /* # entries that we'll print */
2616         u32 logsize;
2617         int pos = 0;
2618         size_t bufsz = 0;
2619
2620         if (priv->ucode_type == UCODE_INIT) {
2621                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2622                 logsize = priv->_agn.init_evtlog_size;
2623                 if (!base)
2624                         base = priv->_agn.init_evtlog_ptr;
2625         } else {
2626                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2627                 logsize = priv->_agn.inst_evtlog_size;
2628                 if (!base)
2629                         base = priv->_agn.inst_evtlog_ptr;
2630         }
2631
2632         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2633                 IWL_ERR(priv,
2634                         "Invalid event log pointer 0x%08X for %s uCode\n",
2635                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2636                 return -EINVAL;
2637         }
2638
2639         /* event log header */
2640         capacity = iwl_read_targ_mem(priv, base);
2641         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2642         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2643         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2644
2645         if (capacity > logsize) {
2646                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2647                         capacity, logsize);
2648                 capacity = logsize;
2649         }
2650
2651         if (next_entry > logsize) {
2652                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2653                         next_entry, logsize);
2654                 next_entry = logsize;
2655         }
2656
2657         size = num_wraps ? capacity : next_entry;
2658
2659         /* bail out if nothing in log */
2660         if (size == 0) {
2661                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2662                 return pos;
2663         }
2664
2665         /* enable/disable bt channel announcement */
2666         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2667
2668 #ifdef CONFIG_IWLWIFI_DEBUG
2669         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2670                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2671                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2672 #else
2673         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2674                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2675 #endif
2676         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2677                 size);
2678
2679 #ifdef CONFIG_IWLWIFI_DEBUG
2680         if (display) {
2681                 if (full_log)
2682                         bufsz = capacity * 48;
2683                 else
2684                         bufsz = size * 48;
2685                 *buf = kmalloc(bufsz, GFP_KERNEL);
2686                 if (!*buf)
2687                         return -ENOMEM;
2688         }
2689         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2690                 /*
2691                  * if uCode has wrapped back to top of log,
2692                  * start at the oldest entry,
2693                  * i.e the next one that uCode would fill.
2694                  */
2695                 if (num_wraps)
2696                         pos = iwl_print_event_log(priv, next_entry,
2697                                                 capacity - next_entry, mode,
2698                                                 pos, buf, bufsz);
2699                 /* (then/else) start at top of log */
2700                 pos = iwl_print_event_log(priv, 0,
2701                                           next_entry, mode, pos, buf, bufsz);
2702         } else
2703                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2704                                                 next_entry, size, mode,
2705                                                 pos, buf, bufsz);
2706 #else
2707         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2708                                         next_entry, size, mode,
2709                                         pos, buf, bufsz);
2710 #endif
2711         return pos;
2712 }
2713
2714 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2715 {
2716         struct iwl_ct_kill_config cmd;
2717         struct iwl_ct_kill_throttling_config adv_cmd;
2718         unsigned long flags;
2719         int ret = 0;
2720
2721         spin_lock_irqsave(&priv->lock, flags);
2722         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2723                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2724         spin_unlock_irqrestore(&priv->lock, flags);
2725         priv->thermal_throttle.ct_kill_toggle = false;
2726
2727         if (priv->cfg->base_params->support_ct_kill_exit) {
2728                 adv_cmd.critical_temperature_enter =
2729                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2730                 adv_cmd.critical_temperature_exit =
2731                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2732
2733                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2734                                        sizeof(adv_cmd), &adv_cmd);
2735                 if (ret)
2736                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2737                 else
2738                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2739                                         "succeeded, "
2740                                         "critical temperature enter is %d,"
2741                                         "exit is %d\n",
2742                                        priv->hw_params.ct_kill_threshold,
2743                                        priv->hw_params.ct_kill_exit_threshold);
2744         } else {
2745                 cmd.critical_temperature_R =
2746                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2747
2748                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2749                                        sizeof(cmd), &cmd);
2750                 if (ret)
2751                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2752                 else
2753                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2754                                         "succeeded, "
2755                                         "critical temperature is %d\n",
2756                                         priv->hw_params.ct_kill_threshold);
2757         }
2758 }
2759
2760 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2761 {
2762         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2763         struct iwl_host_cmd cmd = {
2764                 .id = CALIBRATION_CFG_CMD,
2765                 .len = sizeof(struct iwl_calib_cfg_cmd),
2766                 .data = &calib_cfg_cmd,
2767         };
2768
2769         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2770         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2771         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2772
2773         return iwl_send_cmd(priv, &cmd);
2774 }
2775
2776
2777 /**
2778  * iwl_alive_start - called after REPLY_ALIVE notification received
2779  *                   from protocol/runtime uCode (initialization uCode's
2780  *                   Alive gets handled by iwl_init_alive_start()).
2781  */
2782 static void iwl_alive_start(struct iwl_priv *priv)
2783 {
2784         int ret = 0;
2785         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2786
2787         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2788
2789         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2790                 /* We had an error bringing up the hardware, so take it
2791                  * all the way back down so we can try again */
2792                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2793                 goto restart;
2794         }
2795
2796         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2797          * This is a paranoid check, because we would not have gotten the
2798          * "runtime" alive if code weren't properly loaded.  */
2799         if (iwl_verify_ucode(priv)) {
2800                 /* Runtime instruction load was bad;
2801                  * take it all the way back down so we can try again */
2802                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2803                 goto restart;
2804         }
2805
2806         ret = priv->cfg->ops->lib->alive_notify(priv);
2807         if (ret) {
2808                 IWL_WARN(priv,
2809                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2810                 goto restart;
2811         }
2812
2813
2814         /* After the ALIVE response, we can send host commands to the uCode */
2815         set_bit(STATUS_ALIVE, &priv->status);
2816
2817         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2818                 /* Enable timer to monitor the driver queues */
2819                 mod_timer(&priv->monitor_recover,
2820                         jiffies +
2821                         msecs_to_jiffies(
2822                           priv->cfg->base_params->monitor_recover_period));
2823         }
2824
2825         if (iwl_is_rfkill(priv))
2826                 return;
2827
2828         /* download priority table before any calibration request */
2829         if (priv->cfg->bt_params &&
2830             priv->cfg->bt_params->advanced_bt_coexist) {
2831                 /* Configure Bluetooth device coexistence support */
2832                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2833                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2834                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2835                 priv->cfg->ops->hcmd->send_bt_config(priv);
2836                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2837                 iwlagn_send_prio_tbl(priv);
2838
2839                 /* FIXME: w/a to force change uCode BT state machine */
2840                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2841                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2842                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2843                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2844         }
2845         if (priv->hw_params.calib_rt_cfg)
2846                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2847
2848         ieee80211_wake_queues(priv->hw);
2849
2850         priv->active_rate = IWL_RATES_MASK;
2851
2852         /* Configure Tx antenna selection based on H/W config */
2853         if (priv->cfg->ops->hcmd->set_tx_ant)
2854                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2855
2856         if (iwl_is_associated_ctx(ctx)) {
2857                 struct iwl_rxon_cmd *active_rxon =
2858                                 (struct iwl_rxon_cmd *)&ctx->active;
2859                 /* apply any changes in staging */
2860                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2861                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2862         } else {
2863                 struct iwl_rxon_context *tmp;
2864                 /* Initialize our rx_config data */
2865                 for_each_context(priv, tmp)
2866                         iwl_connection_init_rx_config(priv, tmp);
2867
2868                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2869                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2870         }
2871
2872         if (priv->cfg->bt_params &&
2873             !priv->cfg->bt_params->advanced_bt_coexist) {
2874                 /* Configure Bluetooth device coexistence support */
2875                 priv->cfg->ops->hcmd->send_bt_config(priv);
2876         }
2877
2878         iwl_reset_run_time_calib(priv);
2879
2880         /* Configure the adapter for unassociated operation */
2881         iwlcore_commit_rxon(priv, ctx);
2882
2883         /* At this point, the NIC is initialized and operational */
2884         iwl_rf_kill_ct_config(priv);
2885
2886         iwl_leds_init(priv);
2887
2888         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2889         set_bit(STATUS_READY, &priv->status);
2890         wake_up_interruptible(&priv->wait_command_queue);
2891
2892         iwl_power_update_mode(priv, true);
2893         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2894
2895
2896         return;
2897
2898  restart:
2899         queue_work(priv->workqueue, &priv->restart);
2900 }
2901
2902 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2903
2904 static void __iwl_down(struct iwl_priv *priv)
2905 {
2906         unsigned long flags;
2907         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2908
2909         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2910
2911         iwl_scan_cancel_timeout(priv, 200);
2912
2913         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2914
2915         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2916          * to prevent rearm timer */
2917         if (priv->cfg->ops->lib->recover_from_tx_stall)
2918                 del_timer_sync(&priv->monitor_recover);
2919
2920         iwl_clear_ucode_stations(priv, NULL);
2921         iwl_dealloc_bcast_stations(priv);
2922         iwl_clear_driver_stations(priv);
2923
2924         /* reset BT coex data */
2925         priv->bt_status = 0;
2926         if (priv->cfg->bt_params)
2927                 priv->bt_traffic_load =
2928                          priv->cfg->bt_params->bt_init_traffic_load;
2929         else
2930                 priv->bt_traffic_load = 0;
2931         priv->bt_sco_active = false;
2932         priv->bt_full_concurrent = false;
2933         priv->bt_ci_compliance = 0;
2934
2935         /* Unblock any waiting calls */
2936         wake_up_interruptible_all(&priv->wait_command_queue);
2937
2938         /* Wipe out the EXIT_PENDING status bit if we are not actually
2939          * exiting the module */
2940         if (!exit_pending)
2941                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2942
2943         /* stop and reset the on-board processor */
2944         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2945
2946         /* tell the device to stop sending interrupts */
2947         spin_lock_irqsave(&priv->lock, flags);
2948         iwl_disable_interrupts(priv);
2949         spin_unlock_irqrestore(&priv->lock, flags);
2950         iwl_synchronize_irq(priv);
2951
2952         if (priv->mac80211_registered)
2953                 ieee80211_stop_queues(priv->hw);
2954
2955         /* If we have not previously called iwl_init() then
2956          * clear all bits but the RF Kill bit and return */
2957         if (!iwl_is_init(priv)) {
2958                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2959                                         STATUS_RF_KILL_HW |
2960                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2961                                         STATUS_GEO_CONFIGURED |
2962                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2963                                         STATUS_EXIT_PENDING;
2964                 goto exit;
2965         }
2966
2967         /* ...otherwise clear out all the status bits but the RF Kill
2968          * bit and continue taking the NIC down. */
2969         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2970                                 STATUS_RF_KILL_HW |
2971                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2972                                 STATUS_GEO_CONFIGURED |
2973                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2974                                 STATUS_FW_ERROR |
2975                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2976                                 STATUS_EXIT_PENDING;
2977
2978         /* device going down, Stop using ICT table */
2979         iwl_disable_ict(priv);
2980
2981         iwlagn_txq_ctx_stop(priv);
2982         iwlagn_rxq_stop(priv);
2983
2984         /* Power-down device's busmaster DMA clocks */
2985         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2986         udelay(5);
2987
2988         /* Make sure (redundant) we've released our request to stay awake */
2989         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2990
2991         /* Stop the device, and put it in low power state */
2992         iwl_apm_stop(priv);
2993
2994  exit:
2995         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2996
2997         dev_kfree_skb(priv->beacon_skb);
2998         priv->beacon_skb = NULL;
2999
3000         /* clear out any free frames */
3001         iwl_clear_free_frames(priv);
3002 }
3003
3004 static void iwl_down(struct iwl_priv *priv)
3005 {
3006         mutex_lock(&priv->mutex);
3007         __iwl_down(priv);
3008         mutex_unlock(&priv->mutex);
3009
3010         iwl_cancel_deferred_work(priv);
3011 }
3012
3013 #define HW_READY_TIMEOUT (50)
3014
3015 static int iwl_set_hw_ready(struct iwl_priv *priv)
3016 {
3017         int ret = 0;
3018
3019         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3020                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3021
3022         /* See if we got it */
3023         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3024                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3025                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3026                                 HW_READY_TIMEOUT);
3027         if (ret != -ETIMEDOUT)
3028                 priv->hw_ready = true;
3029         else
3030                 priv->hw_ready = false;
3031
3032         IWL_DEBUG_INFO(priv, "hardware %s\n",
3033                       (priv->hw_ready == 1) ? "ready" : "not ready");
3034         return ret;
3035 }
3036
3037 static int iwl_prepare_card_hw(struct iwl_priv *priv)
3038 {
3039         int ret = 0;
3040
3041         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
3042
3043         ret = iwl_set_hw_ready(priv);
3044         if (priv->hw_ready)
3045                 return ret;
3046
3047         /* If HW is not ready, prepare the conditions to check again */
3048         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3049                         CSR_HW_IF_CONFIG_REG_PREPARE);
3050
3051         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3052                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3053                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3054
3055         /* HW should be ready by now, check again. */
3056         if (ret != -ETIMEDOUT)
3057                 iwl_set_hw_ready(priv);
3058
3059         return ret;
3060 }
3061
3062 #define MAX_HW_RESTARTS 5
3063
3064 static int __iwl_up(struct iwl_priv *priv)
3065 {
3066         struct iwl_rxon_context *ctx;
3067         int i;
3068         int ret;
3069
3070         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3071                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
3072                 return -EIO;
3073         }
3074
3075         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
3076                 IWL_ERR(priv, "ucode not available for device bringup\n");
3077                 return -EIO;
3078         }
3079
3080         for_each_context(priv, ctx) {
3081                 ret = iwlagn_alloc_bcast_station(priv, ctx);
3082                 if (ret) {
3083                         iwl_dealloc_bcast_stations(priv);
3084                         return ret;
3085                 }
3086         }
3087
3088         iwl_prepare_card_hw(priv);
3089
3090         if (!priv->hw_ready) {
3091                 IWL_WARN(priv, "Exit HW not ready\n");
3092                 return -EIO;
3093         }
3094
3095         /* If platform's RF_KILL switch is NOT set to KILL */
3096         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3097                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3098         else
3099                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3100
3101         if (iwl_is_rfkill(priv)) {
3102                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3103
3104                 iwl_enable_interrupts(priv);
3105                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3106                 return 0;
3107         }
3108
3109         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3110
3111         /* must be initialised before iwl_hw_nic_init */
3112         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3113                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3114         else
3115                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3116
3117         ret = iwlagn_hw_nic_init(priv);
3118         if (ret) {
3119                 IWL_ERR(priv, "Unable to init nic\n");
3120                 return ret;
3121         }
3122
3123         /* make sure rfkill handshake bits are cleared */
3124         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3125         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3126                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3127
3128         /* clear (again), then enable host interrupts */
3129         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3130         iwl_enable_interrupts(priv);
3131
3132         /* really make sure rfkill handshake bits are cleared */
3133         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3134         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3135
3136         /* Copy original ucode data image from disk into backup cache.
3137          * This will be used to initialize the on-board processor's
3138          * data SRAM for a clean start when the runtime program first loads. */
3139         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3140                priv->ucode_data.len);
3141
3142         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3143
3144                 /* load bootstrap state machine,
3145                  * load bootstrap program into processor's memory,
3146                  * prepare to load the "initialize" uCode */
3147                 ret = priv->cfg->ops->lib->load_ucode(priv);
3148
3149                 if (ret) {
3150                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3151                                 ret);
3152                         continue;
3153                 }
3154
3155                 /* start card; "initialize" will load runtime ucode */
3156                 iwl_nic_start(priv);
3157
3158                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3159
3160                 return 0;
3161         }
3162
3163         set_bit(STATUS_EXIT_PENDING, &priv->status);
3164         __iwl_down(priv);
3165         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3166
3167         /* tried to restart and config the device for as long as our
3168          * patience could withstand */
3169         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3170         return -EIO;
3171 }
3172
3173
3174 /*****************************************************************************
3175  *
3176  * Workqueue callbacks
3177  *
3178  *****************************************************************************/
3179
3180 static void iwl_bg_init_alive_start(struct work_struct *data)
3181 {
3182         struct iwl_priv *priv =
3183             container_of(data, struct iwl_priv, init_alive_start.work);
3184
3185         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3186                 return;
3187
3188         mutex_lock(&priv->mutex);
3189         priv->cfg->ops->lib->init_alive_start(priv);
3190         mutex_unlock(&priv->mutex);
3191 }
3192
3193 static void iwl_bg_alive_start(struct work_struct *data)
3194 {
3195         struct iwl_priv *priv =
3196             container_of(data, struct iwl_priv, alive_start.work);
3197
3198         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3199                 return;
3200
3201         /* enable dram interrupt */
3202         iwl_reset_ict(priv);
3203
3204         mutex_lock(&priv->mutex);
3205         iwl_alive_start(priv);
3206         mutex_unlock(&priv->mutex);
3207 }
3208
3209 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3210 {
3211         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3212                         run_time_calib_work);
3213
3214         mutex_lock(&priv->mutex);
3215
3216         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3217             test_bit(STATUS_SCANNING, &priv->status)) {
3218                 mutex_unlock(&priv->mutex);
3219                 return;
3220         }
3221
3222         if (priv->start_calib) {
3223                 if (priv->cfg->bt_params &&
3224                     priv->cfg->bt_params->bt_statistics) {
3225                         iwl_chain_noise_calibration(priv,
3226                                         (void *)&priv->_agn.statistics_bt);
3227                         iwl_sensitivity_calibration(priv,
3228                                         (void *)&priv->_agn.statistics_bt);
3229                 } else {
3230                         iwl_chain_noise_calibration(priv,
3231                                         (void *)&priv->_agn.statistics);
3232                         iwl_sensitivity_calibration(priv,
3233                                         (void *)&priv->_agn.statistics);
3234                 }
3235         }
3236
3237         mutex_unlock(&priv->mutex);
3238 }
3239
3240 static void iwl_bg_restart(struct work_struct *data)
3241 {
3242         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3243
3244         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3245                 return;
3246
3247         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3248                 struct iwl_rxon_context *ctx;
3249                 bool bt_sco, bt_full_concurrent;
3250                 u8 bt_ci_compliance;
3251                 u8 bt_load;
3252                 u8 bt_status;
3253
3254                 mutex_lock(&priv->mutex);
3255                 for_each_context(priv, ctx)
3256                         ctx->vif = NULL;
3257                 priv->is_open = 0;
3258
3259                 /*
3260                  * __iwl_down() will clear the BT status variables,
3261                  * which is correct, but when we restart we really
3262                  * want to keep them so restore them afterwards.
3263                  *
3264                  * The restart process will later pick them up and
3265                  * re-configure the hw when we reconfigure the BT
3266                  * command.
3267                  */
3268                 bt_sco = priv->bt_sco_active;
3269                 bt_full_concurrent = priv->bt_full_concurrent;
3270                 bt_ci_compliance = priv->bt_ci_compliance;
3271                 bt_load = priv->bt_traffic_load;
3272                 bt_status = priv->bt_status;
3273
3274                 __iwl_down(priv);
3275
3276                 priv->bt_sco_active = bt_sco;
3277                 priv->bt_full_concurrent = bt_full_concurrent;
3278                 priv->bt_ci_compliance = bt_ci_compliance;
3279                 priv->bt_traffic_load = bt_load;
3280                 priv->bt_status = bt_status;
3281
3282                 mutex_unlock(&priv->mutex);
3283                 iwl_cancel_deferred_work(priv);
3284                 ieee80211_restart_hw(priv->hw);
3285         } else {
3286                 iwl_down(priv);
3287
3288                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3289                         return;
3290
3291                 mutex_lock(&priv->mutex);
3292                 __iwl_up(priv);
3293                 mutex_unlock(&priv->mutex);
3294         }
3295 }
3296
3297 static void iwl_bg_rx_replenish(struct work_struct *data)
3298 {
3299         struct iwl_priv *priv =
3300             container_of(data, struct iwl_priv, rx_replenish);
3301
3302         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3303                 return;
3304
3305         mutex_lock(&priv->mutex);
3306         iwlagn_rx_replenish(priv);
3307         mutex_unlock(&priv->mutex);
3308 }
3309
3310 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3311
3312 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3313 {
3314         struct iwl_rxon_context *ctx;
3315         struct ieee80211_conf *conf = NULL;
3316         int ret = 0;
3317
3318         if (!vif || !priv->is_open)
3319                 return;
3320
3321         ctx = iwl_rxon_ctx_from_vif(vif);
3322
3323         if (vif->type == NL80211_IFTYPE_AP) {
3324                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3325                 return;
3326         }
3327
3328         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3329                 return;
3330
3331         iwl_scan_cancel_timeout(priv, 200);
3332
3333         conf = ieee80211_get_hw_conf(priv->hw);
3334
3335         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3336         iwlcore_commit_rxon(priv, ctx);
3337
3338         ret = iwl_send_rxon_timing(priv, ctx);
3339         if (ret)
3340                 IWL_WARN(priv, "RXON timing - "
3341                             "Attempting to continue.\n");
3342
3343         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3344
3345         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3346
3347         if (priv->cfg->ops->hcmd->set_rxon_chain)
3348                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3349
3350         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3351
3352         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3353                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3354
3355         if (vif->bss_conf.use_short_preamble)
3356                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3357         else
3358                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3359
3360         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3361                 if (vif->bss_conf.use_short_slot)
3362                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3363                 else
3364                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3365         }
3366
3367         iwlcore_commit_rxon(priv, ctx);
3368
3369         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3370                         vif->bss_conf.aid, ctx->active.bssid_addr);
3371
3372         switch (vif->type) {
3373         case NL80211_IFTYPE_STATION:
3374                 break;
3375         case NL80211_IFTYPE_ADHOC:
3376                 iwl_send_beacon_cmd(priv);
3377                 break;
3378         default:
3379                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3380                           __func__, vif->type);
3381                 break;
3382         }
3383
3384         /* the chain noise calibration will enabled PM upon completion
3385          * If chain noise has already been run, then we need to enable
3386          * power management here */
3387         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3388                 iwl_power_update_mode(priv, false);
3389
3390         /* Enable Rx differential gain and sensitivity calibrations */
3391         iwl_chain_noise_reset(priv);
3392         priv->start_calib = 1;
3393
3394 }
3395
3396 /*****************************************************************************
3397  *
3398  * mac80211 entry point functions
3399  *
3400  *****************************************************************************/
3401
3402 #define UCODE_READY_TIMEOUT     (4 * HZ)
3403
3404 /*
3405  * Not a mac80211 entry point function, but it fits in with all the
3406  * other mac80211 functions grouped here.
3407  */
3408 static int iwl_mac_setup_register(struct iwl_priv *priv,
3409                                   struct iwlagn_ucode_capabilities *capa)
3410 {
3411         int ret;
3412         struct ieee80211_hw *hw = priv->hw;
3413         struct iwl_rxon_context *ctx;
3414
3415         hw->rate_control_algorithm = "iwl-agn-rs";
3416
3417         /* Tell mac80211 our characteristics */
3418         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3419                     IEEE80211_HW_AMPDU_AGGREGATION |
3420                     IEEE80211_HW_NEED_DTIM_PERIOD |
3421                     IEEE80211_HW_SPECTRUM_MGMT;
3422
3423         if (!priv->cfg->base_params->broken_powersave)
3424                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3425                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3426
3427         if (priv->cfg->sku & IWL_SKU_N)
3428                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3429                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3430
3431         hw->sta_data_size = sizeof(struct iwl_station_priv);
3432         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3433
3434         for_each_context(priv, ctx) {
3435                 hw->wiphy->interface_modes |= ctx->interface_modes;
3436                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3437         }
3438
3439         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3440                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3441
3442         /*
3443          * For now, disable PS by default because it affects
3444          * RX performance significantly.
3445          */
3446         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3447
3448         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3449         /* we create the 802.11 header and a zero-length SSID element */
3450         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3451
3452         /* Default value; 4 EDCA QOS priorities */
3453         hw->queues = 4;
3454
3455         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3456
3457         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3458                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3459                         &priv->bands[IEEE80211_BAND_2GHZ];
3460         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3461                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3462                         &priv->bands[IEEE80211_BAND_5GHZ];
3463
3464         ret = ieee80211_register_hw(priv->hw);
3465         if (ret) {
3466                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3467                 return ret;
3468         }
3469         priv->mac80211_registered = 1;
3470
3471         return 0;
3472 }
3473
3474
3475 static int iwl_mac_start(struct ieee80211_hw *hw)
3476 {
3477         struct iwl_priv *priv = hw->priv;
3478         int ret;
3479
3480         IWL_DEBUG_MAC80211(priv, "enter\n");
3481
3482         /* we should be verifying the device is ready to be opened */
3483         mutex_lock(&priv->mutex);
3484         ret = __iwl_up(priv);
3485         mutex_unlock(&priv->mutex);
3486
3487         if (ret)
3488                 return ret;
3489
3490         if (iwl_is_rfkill(priv))
3491                 goto out;
3492
3493         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3494
3495         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3496          * mac80211 will not be run successfully. */
3497         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3498                         test_bit(STATUS_READY, &priv->status),
3499                         UCODE_READY_TIMEOUT);
3500         if (!ret) {
3501                 if (!test_bit(STATUS_READY, &priv->status)) {
3502                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3503                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3504                         return -ETIMEDOUT;
3505                 }
3506         }
3507
3508         iwl_led_start(priv);
3509
3510 out:
3511         priv->is_open = 1;
3512         IWL_DEBUG_MAC80211(priv, "leave\n");
3513         return 0;
3514 }
3515
3516 static void iwl_mac_stop(struct ieee80211_hw *hw)
3517 {
3518         struct iwl_priv *priv = hw->priv;
3519
3520         IWL_DEBUG_MAC80211(priv, "enter\n");
3521
3522         if (!priv->is_open)
3523                 return;
3524
3525         priv->is_open = 0;
3526
3527         iwl_down(priv);
3528
3529         flush_workqueue(priv->workqueue);
3530
3531         /* enable interrupts again in order to receive rfkill changes */
3532         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3533         iwl_enable_interrupts(priv);
3534
3535         IWL_DEBUG_MAC80211(priv, "leave\n");
3536 }
3537
3538 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3539 {
3540         struct iwl_priv *priv = hw->priv;
3541
3542         IWL_DEBUG_MACDUMP(priv, "enter\n");
3543
3544         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3545                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3546
3547         if (iwlagn_tx_skb(priv, skb))
3548                 dev_kfree_skb_any(skb);
3549
3550         IWL_DEBUG_MACDUMP(priv, "leave\n");
3551         return NETDEV_TX_OK;
3552 }
3553
3554 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3555 {
3556         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3557         int ret = 0;
3558
3559         lockdep_assert_held(&priv->mutex);
3560
3561         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3562                 return;
3563
3564         /* The following should be done only at AP bring up */
3565         if (!iwl_is_associated_ctx(ctx)) {
3566
3567                 /* RXON - unassoc (to set timing command) */
3568                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3569                 iwlcore_commit_rxon(priv, ctx);
3570
3571                 /* RXON Timing */
3572                 ret = iwl_send_rxon_timing(priv, ctx);
3573                 if (ret)
3574                         IWL_WARN(priv, "RXON timing failed - "
3575                                         "Attempting to continue.\n");
3576
3577                 /* AP has all antennas */
3578                 priv->chain_noise_data.active_chains =
3579                         priv->hw_params.valid_rx_ant;
3580                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3581                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3582                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3583
3584                 ctx->staging.assoc_id = 0;
3585
3586                 if (vif->bss_conf.use_short_preamble)
3587                         ctx->staging.flags |=
3588                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3589                 else
3590                         ctx->staging.flags &=
3591                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3592
3593                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3594                         if (vif->bss_conf.use_short_slot)
3595                                 ctx->staging.flags |=
3596                                         RXON_FLG_SHORT_SLOT_MSK;
3597                         else
3598                                 ctx->staging.flags &=
3599                                         ~RXON_FLG_SHORT_SLOT_MSK;
3600                 }
3601                 /* need to send beacon cmd before committing assoc RXON! */
3602                 iwl_send_beacon_cmd(priv);
3603                 /* restore RXON assoc */
3604                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3605                 iwlcore_commit_rxon(priv, ctx);
3606         }
3607         iwl_send_beacon_cmd(priv);
3608
3609         /* FIXME - we need to add code here to detect a totally new
3610          * configuration, reset the AP, unassoc, rxon timing, assoc,
3611          * clear sta table, add BCAST sta... */
3612 }
3613
3614 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3615                                     struct ieee80211_vif *vif,
3616                                     struct ieee80211_key_conf *keyconf,
3617                                     struct ieee80211_sta *sta,
3618                                     u32 iv32, u16 *phase1key)
3619 {
3620
3621         struct iwl_priv *priv = hw->priv;
3622         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3623
3624         IWL_DEBUG_MAC80211(priv, "enter\n");
3625
3626         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3627                             iv32, phase1key);
3628
3629         IWL_DEBUG_MAC80211(priv, "leave\n");
3630 }
3631
3632 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3633                            struct ieee80211_vif *vif,
3634                            struct ieee80211_sta *sta,
3635                            struct ieee80211_key_conf *key)
3636 {
3637         struct iwl_priv *priv = hw->priv;
3638         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3639         struct iwl_rxon_context *ctx = vif_priv->ctx;
3640         int ret;
3641         u8 sta_id;
3642         bool is_default_wep_key = false;
3643
3644         IWL_DEBUG_MAC80211(priv, "enter\n");
3645
3646         if (priv->cfg->mod_params->sw_crypto) {
3647                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3648                 return -EOPNOTSUPP;
3649         }
3650
3651         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3652         if (sta_id == IWL_INVALID_STATION)
3653                 return -EINVAL;
3654
3655         mutex_lock(&priv->mutex);
3656         iwl_scan_cancel_timeout(priv, 100);
3657
3658         /*
3659          * If we are getting WEP group key and we didn't receive any key mapping
3660          * so far, we are in legacy wep mode (group key only), otherwise we are
3661          * in 1X mode.
3662          * In legacy wep mode, we use another host command to the uCode.
3663          */
3664         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3665              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3666             !sta) {
3667                 if (cmd == SET_KEY)
3668                         is_default_wep_key = !ctx->key_mapping_keys;
3669                 else
3670                         is_default_wep_key =
3671                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3672         }
3673
3674         switch (cmd) {
3675         case SET_KEY:
3676                 if (is_default_wep_key)
3677                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3678                 else
3679                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3680                                                   key, sta_id);
3681
3682                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3683                 break;
3684         case DISABLE_KEY:
3685                 if (is_default_wep_key)
3686                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3687                 else
3688                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3689
3690                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3691                 break;
3692         default:
3693                 ret = -EINVAL;
3694         }
3695
3696         mutex_unlock(&priv->mutex);
3697         IWL_DEBUG_MAC80211(priv, "leave\n");
3698
3699         return ret;
3700 }
3701
3702 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3703                                 struct ieee80211_vif *vif,
3704                                 enum ieee80211_ampdu_mlme_action action,
3705                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3706 {
3707         struct iwl_priv *priv = hw->priv;
3708         int ret = -EINVAL;
3709
3710         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3711                      sta->addr, tid);
3712
3713         if (!(priv->cfg->sku & IWL_SKU_N))
3714                 return -EACCES;
3715
3716         mutex_lock(&priv->mutex);
3717
3718         switch (action) {
3719         case IEEE80211_AMPDU_RX_START:
3720                 IWL_DEBUG_HT(priv, "start Rx\n");
3721                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3722                 break;
3723         case IEEE80211_AMPDU_RX_STOP:
3724                 IWL_DEBUG_HT(priv, "stop Rx\n");
3725                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3726                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3727                         ret = 0;
3728                 break;
3729         case IEEE80211_AMPDU_TX_START:
3730                 IWL_DEBUG_HT(priv, "start Tx\n");
3731                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3732                 if (ret == 0) {
3733                         priv->_agn.agg_tids_count++;
3734                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3735                                      priv->_agn.agg_tids_count);
3736                 }
3737                 break;
3738         case IEEE80211_AMPDU_TX_STOP:
3739                 IWL_DEBUG_HT(priv, "stop Tx\n");
3740                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3741                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3742                         priv->_agn.agg_tids_count--;
3743                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3744                                      priv->_agn.agg_tids_count);
3745                 }
3746                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3747                         ret = 0;
3748                 if (priv->cfg->ht_params &&
3749                     priv->cfg->ht_params->use_rts_for_aggregation) {
3750                         struct iwl_station_priv *sta_priv =
3751                                 (void *) sta->drv_priv;
3752                         /*
3753                          * switch off RTS/CTS if it was previously enabled
3754                          */
3755
3756                         sta_priv->lq_sta.lq.general_params.flags &=
3757                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3758                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3759                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3760                 }
3761                 break;
3762         case IEEE80211_AMPDU_TX_OPERATIONAL:
3763                 if (priv->cfg->ht_params &&
3764                     priv->cfg->ht_params->use_rts_for_aggregation) {
3765                         struct iwl_station_priv *sta_priv =
3766                                 (void *) sta->drv_priv;
3767
3768                         /*
3769                          * switch to RTS/CTS if it is the prefer protection
3770                          * method for HT traffic
3771                          */
3772
3773                         sta_priv->lq_sta.lq.general_params.flags |=
3774                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3775                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3776                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3777                 }
3778                 ret = 0;
3779                 break;
3780         }
3781         mutex_unlock(&priv->mutex);
3782
3783         return ret;
3784 }
3785
3786 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3787                                struct ieee80211_vif *vif,
3788                                enum sta_notify_cmd cmd,
3789                                struct ieee80211_sta *sta)
3790 {
3791         struct iwl_priv *priv = hw->priv;
3792         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3793         int sta_id;
3794
3795         switch (cmd) {
3796         case STA_NOTIFY_SLEEP:
3797                 WARN_ON(!sta_priv->client);
3798                 sta_priv->asleep = true;
3799                 if (atomic_read(&sta_priv->pending_frames) > 0)
3800                         ieee80211_sta_block_awake(hw, sta, true);
3801                 break;
3802         case STA_NOTIFY_AWAKE:
3803                 WARN_ON(!sta_priv->client);
3804                 if (!sta_priv->asleep)
3805                         break;
3806                 sta_priv->asleep = false;
3807                 sta_id = iwl_sta_id(sta);
3808                 if (sta_id != IWL_INVALID_STATION)
3809                         iwl_sta_modify_ps_wake(priv, sta_id);
3810                 break;
3811         default:
3812                 break;
3813         }
3814 }
3815
3816 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3817                               struct ieee80211_vif *vif,
3818                               struct ieee80211_sta *sta)
3819 {
3820         struct iwl_priv *priv = hw->priv;
3821         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3822         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3823         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3824         int ret;
3825         u8 sta_id;
3826
3827         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3828                         sta->addr);
3829         mutex_lock(&priv->mutex);
3830         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3831                         sta->addr);
3832         sta_priv->common.sta_id = IWL_INVALID_STATION;
3833
3834         atomic_set(&sta_priv->pending_frames, 0);
3835         if (vif->type == NL80211_IFTYPE_AP)
3836                 sta_priv->client = true;
3837
3838         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3839                                      is_ap, sta, &sta_id);
3840         if (ret) {
3841                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3842                         sta->addr, ret);
3843                 /* Should we return success if return code is EEXIST ? */
3844                 mutex_unlock(&priv->mutex);
3845                 return ret;
3846         }
3847
3848         sta_priv->common.sta_id = sta_id;
3849
3850         /* Initialize rate scaling */
3851         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3852                        sta->addr);
3853         iwl_rs_rate_init(priv, sta, sta_id);
3854         mutex_unlock(&priv->mutex);
3855
3856         return 0;
3857 }
3858
3859 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3860                                    struct ieee80211_channel_switch *ch_switch)
3861 {
3862         struct iwl_priv *priv = hw->priv;
3863         const struct iwl_channel_info *ch_info;
3864         struct ieee80211_conf *conf = &hw->conf;
3865         struct ieee80211_channel *channel = ch_switch->channel;
3866         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3867         /*
3868          * MULTI-FIXME
3869          * When we add support for multiple interfaces, we need to
3870          * revisit this. The channel switch command in the device
3871          * only affects the BSS context, but what does that really
3872          * mean? And what if we get a CSA on the second interface?
3873          * This needs a lot of work.
3874          */
3875         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3876         u16 ch;
3877         unsigned long flags = 0;
3878
3879         IWL_DEBUG_MAC80211(priv, "enter\n");
3880
3881         if (iwl_is_rfkill(priv))
3882                 goto out_exit;
3883
3884         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3885             test_bit(STATUS_SCANNING, &priv->status))
3886                 goto out_exit;
3887
3888         if (!iwl_is_associated_ctx(ctx))
3889                 goto out_exit;
3890
3891         /* channel switch in progress */
3892         if (priv->switch_rxon.switch_in_progress == true)
3893                 goto out_exit;
3894
3895         mutex_lock(&priv->mutex);
3896         if (priv->cfg->ops->lib->set_channel_switch) {
3897
3898                 ch = channel->hw_value;
3899                 if (le16_to_cpu(ctx->active.channel) != ch) {
3900                         ch_info = iwl_get_channel_info(priv,
3901                                                        channel->band,
3902                                                        ch);
3903                         if (!is_channel_valid(ch_info)) {
3904                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3905                                 goto out;
3906                         }
3907                         spin_lock_irqsave(&priv->lock, flags);
3908
3909                         priv->current_ht_config.smps = conf->smps_mode;
3910
3911                         /* Configure HT40 channels */
3912                         ctx->ht.enabled = conf_is_ht(conf);
3913                         if (ctx->ht.enabled) {
3914                                 if (conf_is_ht40_minus(conf)) {
3915                                         ctx->ht.extension_chan_offset =
3916                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3917                                         ctx->ht.is_40mhz = true;
3918                                 } else if (conf_is_ht40_plus(conf)) {
3919                                         ctx->ht.extension_chan_offset =
3920                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3921                                         ctx->ht.is_40mhz = true;
3922                                 } else {
3923                                         ctx->ht.extension_chan_offset =
3924                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3925                                         ctx->ht.is_40mhz = false;
3926                                 }
3927                         } else
3928                                 ctx->ht.is_40mhz = false;
3929
3930                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3931                                 ctx->staging.flags = 0;
3932
3933                         iwl_set_rxon_channel(priv, channel, ctx);
3934                         iwl_set_rxon_ht(priv, ht_conf);
3935                         iwl_set_flags_for_band(priv, ctx, channel->band,
3936                                                ctx->vif);
3937                         spin_unlock_irqrestore(&priv->lock, flags);
3938
3939                         iwl_set_rate(priv);
3940                         /*
3941                          * at this point, staging_rxon has the
3942                          * configuration for channel switch
3943                          */
3944                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3945                                                                     ch_switch))
3946                                 priv->switch_rxon.switch_in_progress = false;
3947                 }
3948         }
3949 out:
3950         mutex_unlock(&priv->mutex);
3951 out_exit:
3952         if (!priv->switch_rxon.switch_in_progress)
3953                 ieee80211_chswitch_done(ctx->vif, false);
3954         IWL_DEBUG_MAC80211(priv, "leave\n");
3955 }
3956
3957 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3958                                     unsigned int changed_flags,
3959                                     unsigned int *total_flags,
3960                                     u64 multicast)
3961 {
3962         struct iwl_priv *priv = hw->priv;
3963         __le32 filter_or = 0, filter_nand = 0;
3964         struct iwl_rxon_context *ctx;
3965
3966 #define CHK(test, flag) do { \
3967         if (*total_flags & (test))              \
3968                 filter_or |= (flag);            \
3969         else                                    \
3970                 filter_nand |= (flag);          \
3971         } while (0)
3972
3973         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3974                         changed_flags, *total_flags);
3975
3976         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3977         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3978         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3979
3980 #undef CHK
3981
3982         mutex_lock(&priv->mutex);
3983
3984         for_each_context(priv, ctx) {
3985                 ctx->staging.filter_flags &= ~filter_nand;
3986                 ctx->staging.filter_flags |= filter_or;
3987                 iwlcore_commit_rxon(priv, ctx);
3988         }
3989
3990         mutex_unlock(&priv->mutex);
3991
3992         /*
3993          * Receiving all multicast frames is always enabled by the
3994          * default flags setup in iwl_connection_init_rx_config()
3995          * since we currently do not support programming multicast
3996          * filters into the device.
3997          */
3998         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3999                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4000 }
4001
4002 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
4003 {
4004         struct iwl_priv *priv = hw->priv;
4005
4006         mutex_lock(&priv->mutex);
4007         IWL_DEBUG_MAC80211(priv, "enter\n");
4008
4009         /* do not support "flush" */
4010         if (!priv->cfg->ops->lib->txfifo_flush)
4011                 goto done;
4012
4013         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4014                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
4015                 goto done;
4016         }
4017         if (iwl_is_rfkill(priv)) {
4018                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4019                 goto done;
4020         }
4021
4022         /*
4023          * mac80211 will not push any more frames for transmit
4024          * until the flush is completed
4025          */
4026         if (drop) {
4027                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4028                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4029                         IWL_ERR(priv, "flush request fail\n");
4030                         goto done;
4031                 }
4032         }
4033         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4034         iwlagn_wait_tx_queue_empty(priv);
4035 done:
4036         mutex_unlock(&priv->mutex);
4037         IWL_DEBUG_MAC80211(priv, "leave\n");
4038 }
4039
4040 /*****************************************************************************
4041  *
4042  * driver setup and teardown
4043  *
4044  *****************************************************************************/
4045
4046 static void iwl_setup_deferred_work(struct iwl_priv *priv)
4047 {
4048         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
4049
4050         init_waitqueue_head(&priv->wait_command_queue);
4051
4052         INIT_WORK(&priv->restart, iwl_bg_restart);
4053         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
4054         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
4055         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4056         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4057         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
4058         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4059         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4060         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4061
4062         iwl_setup_scan_deferred_work(priv);
4063
4064         if (priv->cfg->ops->lib->setup_deferred_work)
4065                 priv->cfg->ops->lib->setup_deferred_work(priv);
4066
4067         init_timer(&priv->statistics_periodic);
4068         priv->statistics_periodic.data = (unsigned long)priv;
4069         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
4070
4071         init_timer(&priv->ucode_trace);
4072         priv->ucode_trace.data = (unsigned long)priv;
4073         priv->ucode_trace.function = iwl_bg_ucode_trace;
4074
4075         if (priv->cfg->ops->lib->recover_from_tx_stall) {
4076                 init_timer(&priv->monitor_recover);
4077                 priv->monitor_recover.data = (unsigned long)priv;
4078                 priv->monitor_recover.function =
4079                         priv->cfg->ops->lib->recover_from_tx_stall;
4080         }
4081
4082         if (!priv->cfg->base_params->use_isr_legacy)
4083                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4084                         iwl_irq_tasklet, (unsigned long)priv);
4085         else
4086                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4087                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4088 }
4089
4090 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4091 {
4092         if (priv->cfg->ops->lib->cancel_deferred_work)
4093                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4094
4095         cancel_delayed_work_sync(&priv->init_alive_start);
4096         cancel_delayed_work(&priv->alive_start);
4097         cancel_work_sync(&priv->run_time_calib_work);
4098         cancel_work_sync(&priv->beacon_update);
4099
4100         iwl_cancel_scan_deferred_work(priv);
4101
4102         cancel_work_sync(&priv->bt_full_concurrency);
4103         cancel_work_sync(&priv->bt_runtime_config);
4104
4105         del_timer_sync(&priv->statistics_periodic);
4106         del_timer_sync(&priv->ucode_trace);
4107 }
4108
4109 static void iwl_init_hw_rates(struct iwl_priv *priv,
4110                               struct ieee80211_rate *rates)
4111 {
4112         int i;
4113
4114         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4115                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4116                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4117                 rates[i].hw_value_short = i;
4118                 rates[i].flags = 0;
4119                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4120                         /*
4121                          * If CCK != 1M then set short preamble rate flag.
4122                          */
4123                         rates[i].flags |=
4124                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4125                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4126                 }
4127         }
4128 }
4129
4130 static int iwl_init_drv(struct iwl_priv *priv)
4131 {
4132         int ret;
4133
4134         spin_lock_init(&priv->sta_lock);
4135         spin_lock_init(&priv->hcmd_lock);
4136
4137         INIT_LIST_HEAD(&priv->free_frames);
4138
4139         mutex_init(&priv->mutex);
4140         mutex_init(&priv->sync_cmd_mutex);
4141
4142         priv->ieee_channels = NULL;
4143         priv->ieee_rates = NULL;
4144         priv->band = IEEE80211_BAND_2GHZ;
4145
4146         priv->iw_mode = NL80211_IFTYPE_STATION;
4147         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4148         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4149         priv->_agn.agg_tids_count = 0;
4150
4151         /* initialize force reset */
4152         priv->force_reset[IWL_RF_RESET].reset_duration =
4153                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4154         priv->force_reset[IWL_FW_RESET].reset_duration =
4155                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4156
4157         /* Choose which receivers/antennas to use */
4158         if (priv->cfg->ops->hcmd->set_rxon_chain)
4159                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4160                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4161
4162         iwl_init_scan_params(priv);
4163
4164         /* init bt coex */
4165         if (priv->cfg->bt_params &&
4166             priv->cfg->bt_params->advanced_bt_coexist) {
4167                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4168                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4169                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4170                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4171                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4172                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4173                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4174         }
4175
4176         /* Set the tx_power_user_lmt to the lowest power level
4177          * this value will get overwritten by channel max power avg
4178          * from eeprom */
4179         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4180
4181         ret = iwl_init_channel_map(priv);
4182         if (ret) {
4183                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4184                 goto err;
4185         }
4186
4187         ret = iwlcore_init_geos(priv);
4188         if (ret) {
4189                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4190                 goto err_free_channel_map;
4191         }
4192         iwl_init_hw_rates(priv, priv->ieee_rates);
4193
4194         return 0;
4195
4196 err_free_channel_map:
4197         iwl_free_channel_map(priv);
4198 err:
4199         return ret;
4200 }
4201
4202 static void iwl_uninit_drv(struct iwl_priv *priv)
4203 {
4204         iwl_calib_free_results(priv);
4205         iwlcore_free_geos(priv);
4206         iwl_free_channel_map(priv);
4207         kfree(priv->scan_cmd);
4208 }
4209
4210 static struct ieee80211_ops iwl_hw_ops = {
4211         .tx = iwl_mac_tx,
4212         .start = iwl_mac_start,
4213         .stop = iwl_mac_stop,
4214         .add_interface = iwl_mac_add_interface,
4215         .remove_interface = iwl_mac_remove_interface,
4216         .config = iwl_mac_config,
4217         .configure_filter = iwlagn_configure_filter,
4218         .set_key = iwl_mac_set_key,
4219         .update_tkip_key = iwl_mac_update_tkip_key,
4220         .conf_tx = iwl_mac_conf_tx,
4221         .reset_tsf = iwl_mac_reset_tsf,
4222         .bss_info_changed = iwl_bss_info_changed,
4223         .ampdu_action = iwl_mac_ampdu_action,
4224         .hw_scan = iwl_mac_hw_scan,
4225         .sta_notify = iwl_mac_sta_notify,
4226         .sta_add = iwlagn_mac_sta_add,
4227         .sta_remove = iwl_mac_sta_remove,
4228         .channel_switch = iwl_mac_channel_switch,
4229         .flush = iwl_mac_flush,
4230         .tx_last_beacon = iwl_mac_tx_last_beacon,
4231 };
4232
4233 static void iwl_hw_detect(struct iwl_priv *priv)
4234 {
4235         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4236         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4237         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4238         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4239 }
4240
4241 static int iwl_set_hw_params(struct iwl_priv *priv)
4242 {
4243         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4244         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4245         if (priv->cfg->mod_params->amsdu_size_8K)
4246                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4247         else
4248                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4249
4250         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4251
4252         if (priv->cfg->mod_params->disable_11n)
4253                 priv->cfg->sku &= ~IWL_SKU_N;
4254
4255         /* Device-specific setup */
4256         return priv->cfg->ops->lib->set_hw_params(priv);
4257 }
4258
4259 static const u8 iwlagn_bss_ac_to_fifo[] = {
4260         IWL_TX_FIFO_VO,
4261         IWL_TX_FIFO_VI,
4262         IWL_TX_FIFO_BE,
4263         IWL_TX_FIFO_BK,
4264 };
4265
4266 static const u8 iwlagn_bss_ac_to_queue[] = {
4267         0, 1, 2, 3,
4268 };
4269
4270 static const u8 iwlagn_pan_ac_to_fifo[] = {
4271         IWL_TX_FIFO_VO_IPAN,
4272         IWL_TX_FIFO_VI_IPAN,
4273         IWL_TX_FIFO_BE_IPAN,
4274         IWL_TX_FIFO_BK_IPAN,
4275 };
4276
4277 static const u8 iwlagn_pan_ac_to_queue[] = {
4278         7, 6, 5, 4,
4279 };
4280
4281 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4282 {
4283         int err = 0, i;
4284         struct iwl_priv *priv;
4285         struct ieee80211_hw *hw;
4286         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4287         unsigned long flags;
4288         u16 pci_cmd, num_mac;
4289
4290         /************************
4291          * 1. Allocating HW data
4292          ************************/
4293
4294         /* Disabling hardware scan means that mac80211 will perform scans
4295          * "the hard way", rather than using device's scan. */
4296         if (cfg->mod_params->disable_hw_scan) {
4297                 dev_printk(KERN_DEBUG, &(pdev->dev),
4298                         "sw scan support is deprecated\n");
4299                 iwl_hw_ops.hw_scan = NULL;
4300         }
4301
4302         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4303         if (!hw) {
4304                 err = -ENOMEM;
4305                 goto out;
4306         }
4307         priv = hw->priv;
4308         /* At this point both hw and priv are allocated. */
4309
4310         /*
4311          * The default context is always valid,
4312          * more may be discovered when firmware
4313          * is loaded.
4314          */
4315         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4316
4317         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4318                 priv->contexts[i].ctxid = i;
4319
4320         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4321         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4322         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4323         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4324         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4325         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4326         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4327         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4328         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4329         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4330         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4331                 BIT(NL80211_IFTYPE_ADHOC);
4332         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4333                 BIT(NL80211_IFTYPE_STATION);
4334         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4335         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4336         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4337
4338         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4339         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4340         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4341         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4342         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4343         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4344         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4345         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4346         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4347         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4348         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4349         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4350                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4351         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4352         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4353         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4354
4355         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4356
4357         SET_IEEE80211_DEV(hw, &pdev->dev);
4358
4359         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4360         priv->cfg = cfg;
4361         priv->pci_dev = pdev;
4362         priv->inta_mask = CSR_INI_SET_MASK;
4363
4364         /* is antenna coupling more than 35dB ? */
4365         priv->bt_ant_couple_ok =
4366                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4367                 true : false;
4368
4369         /* enable/disable bt channel announcement */
4370         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4371
4372         if (iwl_alloc_traffic_mem(priv))
4373                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4374
4375         /**************************
4376          * 2. Initializing PCI bus
4377          **************************/
4378         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4379                                 PCIE_LINK_STATE_CLKPM);
4380
4381         if (pci_enable_device(pdev)) {
4382                 err = -ENODEV;
4383                 goto out_ieee80211_free_hw;
4384         }
4385
4386         pci_set_master(pdev);
4387
4388         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4389         if (!err)
4390                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4391         if (err) {
4392                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4393                 if (!err)
4394                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4395                 /* both attempts failed: */
4396                 if (err) {
4397                         IWL_WARN(priv, "No suitable DMA available.\n");
4398                         goto out_pci_disable_device;
4399                 }
4400         }
4401
4402         err = pci_request_regions(pdev, DRV_NAME);
4403         if (err)
4404                 goto out_pci_disable_device;
4405
4406         pci_set_drvdata(pdev, priv);
4407
4408
4409         /***********************
4410          * 3. Read REV register
4411          ***********************/
4412         priv->hw_base = pci_iomap(pdev, 0, 0);
4413         if (!priv->hw_base) {
4414                 err = -ENODEV;
4415                 goto out_pci_release_regions;
4416         }
4417
4418         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4419                 (unsigned long long) pci_resource_len(pdev, 0));
4420         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4421
4422         /* these spin locks will be used in apm_ops.init and EEPROM access
4423          * we should init now
4424          */
4425         spin_lock_init(&priv->reg_lock);
4426         spin_lock_init(&priv->lock);
4427
4428         /*
4429          * stop and reset the on-board processor just in case it is in a
4430          * strange state ... like being left stranded by a primary kernel
4431          * and this is now the kdump kernel trying to start up
4432          */
4433         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4434
4435         iwl_hw_detect(priv);
4436         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4437                 priv->cfg->name, priv->hw_rev);
4438
4439         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4440          * PCI Tx retries from interfering with C3 CPU state */
4441         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4442
4443         iwl_prepare_card_hw(priv);
4444         if (!priv->hw_ready) {
4445                 IWL_WARN(priv, "Failed, HW not ready\n");
4446                 goto out_iounmap;
4447         }
4448
4449         /*****************
4450          * 4. Read EEPROM
4451          *****************/
4452         /* Read the EEPROM */
4453         err = iwl_eeprom_init(priv);
4454         if (err) {
4455                 IWL_ERR(priv, "Unable to init EEPROM\n");
4456                 goto out_iounmap;
4457         }
4458         err = iwl_eeprom_check_version(priv);
4459         if (err)
4460                 goto out_free_eeprom;
4461
4462         /* extract MAC Address */
4463         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4464         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4465         priv->hw->wiphy->addresses = priv->addresses;
4466         priv->hw->wiphy->n_addresses = 1;
4467         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4468         if (num_mac > 1) {
4469                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4470                        ETH_ALEN);
4471                 priv->addresses[1].addr[5]++;
4472                 priv->hw->wiphy->n_addresses++;
4473         }
4474
4475         /************************
4476          * 5. Setup HW constants
4477          ************************/
4478         if (iwl_set_hw_params(priv)) {
4479                 IWL_ERR(priv, "failed to set hw parameters\n");
4480                 goto out_free_eeprom;
4481         }
4482
4483         /*******************
4484          * 6. Setup priv
4485          *******************/
4486
4487         err = iwl_init_drv(priv);
4488         if (err)
4489                 goto out_free_eeprom;
4490         /* At this point both hw and priv are initialized. */
4491
4492         /********************
4493          * 7. Setup services
4494          ********************/
4495         spin_lock_irqsave(&priv->lock, flags);
4496         iwl_disable_interrupts(priv);
4497         spin_unlock_irqrestore(&priv->lock, flags);
4498
4499         pci_enable_msi(priv->pci_dev);
4500
4501         iwl_alloc_isr_ict(priv);
4502         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4503                           IRQF_SHARED, DRV_NAME, priv);
4504         if (err) {
4505                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4506                 goto out_disable_msi;
4507         }
4508
4509         iwl_setup_deferred_work(priv);
4510         iwl_setup_rx_handlers(priv);
4511
4512         /*********************************************
4513          * 8. Enable interrupts and read RFKILL state
4514          *********************************************/
4515
4516         /* enable interrupts if needed: hw bug w/a */
4517         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4518         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4519                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4520                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4521         }
4522
4523         iwl_enable_interrupts(priv);
4524
4525         /* If platform's RF_KILL switch is NOT set to KILL */
4526         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4527                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4528         else
4529                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4530
4531         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4532                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4533
4534         iwl_power_initialize(priv);
4535         iwl_tt_initialize(priv);
4536
4537         init_completion(&priv->_agn.firmware_loading_complete);
4538
4539         err = iwl_request_firmware(priv, true);
4540         if (err)
4541                 goto out_destroy_workqueue;
4542
4543         return 0;
4544
4545  out_destroy_workqueue:
4546         destroy_workqueue(priv->workqueue);
4547         priv->workqueue = NULL;
4548         free_irq(priv->pci_dev->irq, priv);
4549         iwl_free_isr_ict(priv);
4550  out_disable_msi:
4551         pci_disable_msi(priv->pci_dev);
4552         iwl_uninit_drv(priv);
4553  out_free_eeprom:
4554         iwl_eeprom_free(priv);
4555  out_iounmap:
4556         pci_iounmap(pdev, priv->hw_base);
4557  out_pci_release_regions:
4558         pci_set_drvdata(pdev, NULL);
4559         pci_release_regions(pdev);
4560  out_pci_disable_device:
4561         pci_disable_device(pdev);
4562  out_ieee80211_free_hw:
4563         iwl_free_traffic_mem(priv);
4564         ieee80211_free_hw(priv->hw);
4565  out:
4566         return err;
4567 }
4568
4569 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4570 {
4571         struct iwl_priv *priv = pci_get_drvdata(pdev);
4572         unsigned long flags;
4573
4574         if (!priv)
4575                 return;
4576
4577         wait_for_completion(&priv->_agn.firmware_loading_complete);
4578
4579         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4580
4581         iwl_dbgfs_unregister(priv);
4582         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4583
4584         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4585          * to be called and iwl_down since we are removing the device
4586          * we need to set STATUS_EXIT_PENDING bit.
4587          */
4588         set_bit(STATUS_EXIT_PENDING, &priv->status);
4589         if (priv->mac80211_registered) {
4590                 ieee80211_unregister_hw(priv->hw);
4591                 priv->mac80211_registered = 0;
4592         } else {
4593                 iwl_down(priv);
4594         }
4595
4596         /*
4597          * Make sure device is reset to low power before unloading driver.
4598          * This may be redundant with iwl_down(), but there are paths to
4599          * run iwl_down() without calling apm_ops.stop(), and there are
4600          * paths to avoid running iwl_down() at all before leaving driver.
4601          * This (inexpensive) call *makes sure* device is reset.
4602          */
4603         iwl_apm_stop(priv);
4604
4605         iwl_tt_exit(priv);
4606
4607         /* make sure we flush any pending irq or
4608          * tasklet for the driver
4609          */
4610         spin_lock_irqsave(&priv->lock, flags);
4611         iwl_disable_interrupts(priv);
4612         spin_unlock_irqrestore(&priv->lock, flags);
4613
4614         iwl_synchronize_irq(priv);
4615
4616         iwl_dealloc_ucode_pci(priv);
4617
4618         if (priv->rxq.bd)
4619                 iwlagn_rx_queue_free(priv, &priv->rxq);
4620         iwlagn_hw_txq_ctx_free(priv);
4621
4622         iwl_eeprom_free(priv);
4623
4624
4625         /*netif_stop_queue(dev); */
4626         flush_workqueue(priv->workqueue);
4627
4628         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4629          * priv->workqueue... so we can't take down the workqueue
4630          * until now... */
4631         destroy_workqueue(priv->workqueue);
4632         priv->workqueue = NULL;
4633         iwl_free_traffic_mem(priv);
4634
4635         free_irq(priv->pci_dev->irq, priv);
4636         pci_disable_msi(priv->pci_dev);
4637         pci_iounmap(pdev, priv->hw_base);
4638         pci_release_regions(pdev);
4639         pci_disable_device(pdev);
4640         pci_set_drvdata(pdev, NULL);
4641
4642         iwl_uninit_drv(priv);
4643
4644         iwl_free_isr_ict(priv);
4645
4646         dev_kfree_skb(priv->beacon_skb);
4647
4648         ieee80211_free_hw(priv->hw);
4649 }
4650
4651
4652 /*****************************************************************************
4653  *
4654  * driver and module entry point
4655  *
4656  *****************************************************************************/
4657
4658 /* Hardware specific file defines the PCI IDs table for that hardware module */
4659 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4660 #ifdef CONFIG_IWL4965
4661         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4662         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4663 #endif /* CONFIG_IWL4965 */
4664 #ifdef CONFIG_IWL5000
4665 /* 5100 Series WiFi */
4666         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4667         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4668         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4669         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4670         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4671         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4672         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4673         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4674         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4675         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4676         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4677         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4678         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4679         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4680         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4681         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4682         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4683         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4684         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4685         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4686         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4687         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4688         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4689         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4690
4691 /* 5300 Series WiFi */
4692         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4693         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4694         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4695         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4696         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4697         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4698         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4699         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4700         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4701         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4702         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4703         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4704
4705 /* 5350 Series WiFi/WiMax */
4706         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4707         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4708         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4709
4710 /* 5150 Series Wifi/WiMax */
4711         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4712         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4713         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4714         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4715         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4716         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4717
4718         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4719         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4720         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4721         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4722
4723 /* 6x00 Series */
4724         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4725         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4726         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4727         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4728         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4729         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4730         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4731         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4732         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4733         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4734
4735 /* 6x00 Series Gen2a */
4736         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4737         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4738         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4739         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4740         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4741         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4742         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4743         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4744         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4745         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4746         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4747         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4748         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4749         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4750
4751 /* 6x00 Series Gen2b */
4752         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4753         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4754         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4755         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4756         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4757         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4758         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4759         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4760         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4761         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4762         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4763         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4764         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4765         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4766         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4767         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4768         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4769         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4770         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4771         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4772         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4773         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4774         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4775         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4776         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4777         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4778         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4779         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4780
4781 /* 6x50 WiFi/WiMax Series */
4782         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4783         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4784         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4785         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4786         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4787         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4788
4789 /* 6x50 WiFi/WiMax Series Gen2 */
4790         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4791         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4792         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4793         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4794         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4795         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4796
4797 /* 1000 Series WiFi */
4798         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4799         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4800         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4801         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4802         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4803         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4804         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4805         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4806         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4807         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4808         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4809         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4810
4811 /* 100 Series WiFi */
4812         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4813         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4814         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4815         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4816         {IWL_PCI_DEVICE(0x08AE, 0x1017, iwl100_bg_cfg)},
4817
4818 /* 130 Series WiFi */
4819         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4820         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4821         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4822         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4823         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4824         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4825
4826 #endif /* CONFIG_IWL5000 */
4827
4828         {0}
4829 };
4830 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4831
4832 static struct pci_driver iwl_driver = {
4833         .name = DRV_NAME,
4834         .id_table = iwl_hw_card_ids,
4835         .probe = iwl_pci_probe,
4836         .remove = __devexit_p(iwl_pci_remove),
4837 #ifdef CONFIG_PM
4838         .suspend = iwl_pci_suspend,
4839         .resume = iwl_pci_resume,
4840 #endif
4841 };
4842
4843 static int __init iwl_init(void)
4844 {
4845
4846         int ret;
4847         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4848         pr_info(DRV_COPYRIGHT "\n");
4849
4850         ret = iwlagn_rate_control_register();
4851         if (ret) {
4852                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4853                 return ret;
4854         }
4855
4856         ret = pci_register_driver(&iwl_driver);
4857         if (ret) {
4858                 pr_err("Unable to initialize PCI module\n");
4859                 goto error_register;
4860         }
4861
4862         return ret;
4863
4864 error_register:
4865         iwlagn_rate_control_unregister();
4866         return ret;
4867 }
4868
4869 static void __exit iwl_exit(void)
4870 {
4871         pci_unregister_driver(&iwl_driver);
4872         iwlagn_rate_control_unregister();
4873 }
4874
4875 module_exit(iwl_exit);
4876 module_init(iwl_init);
4877
4878 #ifdef CONFIG_IWLWIFI_DEBUG
4879 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4880 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4881 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4882 MODULE_PARM_DESC(debug, "debug output mask");
4883 #endif
4884
4885 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4886 MODULE_PARM_DESC(swcrypto50,
4887                  "using crypto in software (default 0 [hardware]) (deprecated)");
4888 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4889 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4890 module_param_named(queues_num50,
4891                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4892 MODULE_PARM_DESC(queues_num50,
4893                  "number of hw queues in 50xx series (deprecated)");
4894 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4895 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4896 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4897 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4898 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4899 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4900 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4901                    int, S_IRUGO);
4902 MODULE_PARM_DESC(amsdu_size_8K50,
4903                  "enable 8K amsdu size in 50XX series (deprecated)");
4904 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4905                    int, S_IRUGO);
4906 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4907 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4908 MODULE_PARM_DESC(fw_restart50,
4909                  "restart firmware in case of error (deprecated)");
4910 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4911 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4912 module_param_named(
4913         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4914 MODULE_PARM_DESC(disable_hw_scan,
4915                  "disable hardware scanning (default 0) (deprecated)");
4916
4917 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4918                    S_IRUGO);
4919 MODULE_PARM_DESC(ucode_alternative,
4920                  "specify ucode alternative to use from ucode file");
4921
4922 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4923 MODULE_PARM_DESC(antenna_coupling,
4924                  "specify antenna coupling in dB (defualt: 0 dB)");
4925
4926 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4927 MODULE_PARM_DESC(bt_ch_announce,
4928                  "Enable BT channel announcement mode (default: enable)");