drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89 MODULE_ALIAS("iwl4965");
  90
  91 static int iwlagn_ant_coupling;
  92 static bool iwlagn_bt_ch_announce = 1;
  93
  94 void iwl_update_chain_flags(struct iwl_priv *priv)
  95 {
  96         struct iwl_rxon_context *ctx;
  97
  98         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  99                 for_each_context(priv, ctx) {
 100                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 101                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 102                                 iwlcore_commit_rxon(priv, ctx);
 103                 }
 104         }
 105 }
 106
 107 static void iwl_clear_free_frames(struct iwl_priv *priv)
 108 {
 109         struct list_head *element;
 110
 111         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 112                        priv->frames_count);
 113
 114         while (!list_empty(&priv->free_frames)) {
 115                 element = priv->free_frames.next;
 116                 list_del(element);
 117                 kfree(list_entry(element, struct iwl_frame, list));
 118                 priv->frames_count--;
 119         }
 120
 121         if (priv->frames_count) {
 122                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 123                             priv->frames_count);
 124                 priv->frames_count = 0;
 125         }
 126 }
 127
 128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 129 {
 130         struct iwl_frame *frame;
 131         struct list_head *element;
 132         if (list_empty(&priv->free_frames)) {
 133                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 134                 if (!frame) {
 135                         IWL_ERR(priv, "Could not allocate frame!\n");
 136                         return NULL;
 137                 }
 138
 139                 priv->frames_count++;
 140                 return frame;
 141         }
 142
 143         element = priv->free_frames.next;
 144         list_del(element);
 145         return list_entry(element, struct iwl_frame, list);
 146 }
 147
 148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 149 {
 150         memset(frame, 0, sizeof(*frame));
 151         list_add(&frame->list, &priv->free_frames);
 152 }
 153
 154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 155                                  struct ieee80211_hdr *hdr,
 156                                  int left)
 157 {
 158         lockdep_assert_held(&priv->mutex);
 159
 160         if (!priv->beacon_skb)
 161                 return 0;
 162
 163         if (priv->beacon_skb->len > left)
 164                 return 0;
 165
 166         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 167
 168         return priv->beacon_skb->len;
 169 }
 170
 171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 173                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 174                                u8 *beacon, u32 frame_size)
 175 {
 176         u16 tim_idx;
 177         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 178
 179         /*
 180          * The index is relative to frame start but we start looking at the
 181          * variable-length part of the beacon.
 182          */
 183         tim_idx = mgmt->u.beacon.variable - beacon;
 184
 185         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 186         while ((tim_idx < (frame_size - 2)) &&
 187                         (beacon[tim_idx] != WLAN_EID_TIM))
 188                 tim_idx += beacon[tim_idx+1] + 2;
 189
 190         /* If TIM field was found, set variables */
 191         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 192                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 193                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 194         } else
 195                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 196 }
 197
 198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 199                                        struct iwl_frame *frame)
 200 {
 201         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 202         u32 frame_size;
 203         u32 rate_flags;
 204         u32 rate;
 205         /*
 206          * We have to set up the TX command, the TX Beacon command, and the
 207          * beacon contents.
 208          */
 209
 210         lockdep_assert_held(&priv->mutex);
 211
 212         if (!priv->beacon_ctx) {
 213                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 214                 return 0;
 215         }
 216
 217         /* Initialize memory */
 218         tx_beacon_cmd = &frame->u.beacon;
 219         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 220
 221         /* Set up TX beacon contents */
 222         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 223                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 224         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 225                 return 0;
 226         if (!frame_size)
 227                 return 0;
 228
 229         /* Set up TX command fields */
 230         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 231         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 232         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 233         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 234                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 235
 236         /* Set up TX beacon command fields */
 237         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 238                            frame_size);
 239
 240         /* Set up packet rate and flags */
 241         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 242         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 243                                               priv->hw_params.valid_tx_ant);
 244         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 245         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 246                 rate_flags |= RATE_MCS_CCK_MSK;
 247         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 248                         rate_flags);
 249
 250         return sizeof(*tx_beacon_cmd) + frame_size;
 251 }
 252
 253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 254 {
 255         struct iwl_frame *frame;
 256         unsigned int frame_size;
 257         int rc;
 258
 259         frame = iwl_get_free_frame(priv);
 260         if (!frame) {
 261                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 262                           "command.\n");
 263                 return -ENOMEM;
 264         }
 265
 266         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 267         if (!frame_size) {
 268                 IWL_ERR(priv, "Error configuring the beacon command\n");
 269                 iwl_free_frame(priv, frame);
 270                 return -EINVAL;
 271         }
 272
 273         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 274                               &frame->u.cmd[0]);
 275
 276         iwl_free_frame(priv, frame);
 277
 278         return rc;
 279 }
 280
 281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 282 {
 283         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 284
 285         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 286         if (sizeof(dma_addr_t) > sizeof(u32))
 287                 addr |=
 288                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 289
 290         return addr;
 291 }
 292
 293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 294 {
 295         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 296
 297         return le16_to_cpu(tb->hi_n_len) >> 4;
 298 }
 299
 300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 301                                   dma_addr_t addr, u16 len)
 302 {
 303         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 304         u16 hi_n_len = len << 4;
 305
 306         put_unaligned_le32(addr, &tb->lo);
 307         if (sizeof(dma_addr_t) > sizeof(u32))
 308                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 309
 310         tb->hi_n_len = cpu_to_le16(hi_n_len);
 311
 312         tfd->num_tbs = idx + 1;
 313 }
 314
 315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 316 {
 317         return tfd->num_tbs & 0x1f;
 318 }
 319
 320 /**
 321  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 322  * @priv - driver private data
 323  * @txq - tx queue
 324  *
 325  * Does NOT advance any TFD circular buffer read/write indexes
 326  * Does NOT free the TFD itself (which is within circular buffer)
 327  */
 328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 329 {
 330         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 331         struct iwl_tfd *tfd;
 332         struct pci_dev *dev = priv->pci_dev;
 333         int index = txq->q.read_ptr;
 334         int i;
 335         int num_tbs;
 336
 337         tfd = &tfd_tmp[index];
 338
 339         /* Sanity check on number of chunks */
 340         num_tbs = iwl_tfd_get_num_tbs(tfd);
 341
 342         if (num_tbs >= IWL_NUM_OF_TBS) {
 343                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 344                 /* @todo issue fatal error, it is quite serious situation */
 345                 return;
 346         }
 347
 348         /* Unmap tx_cmd */
 349         if (num_tbs)
 350                 pci_unmap_single(dev,
 351                                 dma_unmap_addr(&txq->meta[index], mapping),
 352                                 dma_unmap_len(&txq->meta[index], len),
 353                                 PCI_DMA_BIDIRECTIONAL);
 354
 355         /* Unmap chunks, if any. */
 356         for (i = 1; i < num_tbs; i++)
 357                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 358                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 359
 360         /* free SKB */
 361         if (txq->txb) {
 362                 struct sk_buff *skb;
 363
 364                 skb = txq->txb[txq->q.read_ptr].skb;
 365
 366                 /* can be called from irqs-disabled context */
 367                 if (skb) {
 368                         dev_kfree_skb_any(skb);
 369                         txq->txb[txq->q.read_ptr].skb = NULL;
 370                 }
 371         }
 372 }
 373
 374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 375                                  struct iwl_tx_queue *txq,
 376                                  dma_addr_t addr, u16 len,
 377                                  u8 reset, u8 pad)
 378 {
 379         struct iwl_queue *q;
 380         struct iwl_tfd *tfd, *tfd_tmp;
 381         u32 num_tbs;
 382
 383         q = &txq->q;
 384         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 385         tfd = &tfd_tmp[q->write_ptr];
 386
 387         if (reset)
 388                 memset(tfd, 0, sizeof(*tfd));
 389
 390         num_tbs = iwl_tfd_get_num_tbs(tfd);
 391
 392         /* Each TFD can point to a maximum 20 Tx buffers */
 393         if (num_tbs >= IWL_NUM_OF_TBS) {
 394                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 395                           IWL_NUM_OF_TBS);
 396                 return -EINVAL;
 397         }
 398
 399         BUG_ON(addr & ~DMA_BIT_MASK(36));
 400         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 401                 IWL_ERR(priv, "Unaligned address = %llx\n",
 402                           (unsigned long long)addr);
 403
 404         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 411  * given Tx queue, and enable the DMA channel used for that queue.
 412  *
 413  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 414  * channels supported in hardware.
 415  */
 416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 417                          struct iwl_tx_queue *txq)
 418 {
 419         int txq_id = txq->q.id;
 420
 421         /* Circular buffer (TFD queue in DRAM) physical base address */
 422         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 423                              txq->q.dma_addr >> 8);
 424
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  *
 430  * Generic RX handler implementations
 431  *
 432  ******************************************************************************/
 433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 434                                 struct iwl_rx_mem_buffer *rxb)
 435 {
 436         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 437         struct iwl_alive_resp *palive;
 438         struct delayed_work *pwork;
 439
 440         palive = &pkt->u.alive_frame;
 441
 442         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 443                        "0x%01X 0x%01X\n",
 444                        palive->is_valid, palive->ver_type,
 445                        palive->ver_subtype);
 446
 447         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 448                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 449                 memcpy(&priv->card_alive_init,
 450                        &pkt->u.alive_frame,
 451                        sizeof(struct iwl_init_alive_resp));
 452                 pwork = &priv->init_alive_start;
 453         } else {
 454                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 455                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 456                        sizeof(struct iwl_alive_resp));
 457                 pwork = &priv->alive_start;
 458         }
 459
 460         /* We delay the ALIVE response by 5ms to
 461          * give the HW RF Kill time to activate... */
 462         if (palive->is_valid == UCODE_VALID_OK)
 463                 queue_delayed_work(priv->workqueue, pwork,
 464                                    msecs_to_jiffies(5));
 465         else
 466                 IWL_WARN(priv, "uCode did not respond OK.\n");
 467 }
 468
 469 static void iwl_bg_beacon_update(struct work_struct *work)
 470 {
 471         struct iwl_priv *priv =
 472                 container_of(work, struct iwl_priv, beacon_update);
 473         struct sk_buff *beacon;
 474
 475         mutex_lock(&priv->mutex);
 476         if (!priv->beacon_ctx) {
 477                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 478                 goto out;
 479         }
 480
 481         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 482                 /*
 483                  * The ucode will send beacon notifications even in
 484                  * IBSS mode, but we don't want to process them. But
 485                  * we need to defer the type check to here due to
 486                  * requiring locking around the beacon_ctx access.
 487                  */
 488                 goto out;
 489         }
 490
 491         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 492         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 493         if (!beacon) {
 494                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 495                 goto out;
 496         }
 497
 498         /* new beacon skb is allocated every time; dispose previous.*/
 499         dev_kfree_skb(priv->beacon_skb);
 500
 501         priv->beacon_skb = beacon;
 502
 503         iwlagn_send_beacon_cmd(priv);
 504  out:
 505         mutex_unlock(&priv->mutex);
 506 }
 507
 508 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 509 {
 510         struct iwl_priv *priv =
 511                 container_of(work, struct iwl_priv, bt_runtime_config);
 512
 513         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 514                 return;
 515
 516         /* dont send host command if rf-kill is on */
 517         if (!iwl_is_ready_rf(priv))
 518                 return;
 519         priv->cfg->ops->hcmd->send_bt_config(priv);
 520 }
 521
 522 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 523 {
 524         struct iwl_priv *priv =
 525                 container_of(work, struct iwl_priv, bt_full_concurrency);
 526         struct iwl_rxon_context *ctx;
 527
 528         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 529                 return;
 530
 531         /* dont send host command if rf-kill is on */
 532         if (!iwl_is_ready_rf(priv))
 533                 return;
 534
 535         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 536                        priv->bt_full_concurrent ?
 537                        "full concurrency" : "3-wire");
 538
 539         /*
 540          * LQ & RXON updated cmds must be sent before BT Config cmd
 541          * to avoid 3-wire collisions
 542          */
 543         mutex_lock(&priv->mutex);
 544         for_each_context(priv, ctx) {
 545                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 546                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 547                 iwlcore_commit_rxon(priv, ctx);
 548         }
 549         mutex_unlock(&priv->mutex);
 550
 551         priv->cfg->ops->hcmd->send_bt_config(priv);
 552 }
 553
 554 /**
 555  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 556  *
 557  * This callback is provided in order to send a statistics request.
 558  *
 559  * This timer function is continually reset to execute within
 560  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 561  * was received.  We need to ensure we receive the statistics in order
 562  * to update the temperature used for calibrating the TXPOWER.
 563  */
 564 static void iwl_bg_statistics_periodic(unsigned long data)
 565 {
 566         struct iwl_priv *priv = (struct iwl_priv *)data;
 567
 568         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 569                 return;
 570
 571         /* dont send host command if rf-kill is on */
 572         if (!iwl_is_ready_rf(priv))
 573                 return;
 574
 575         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 576 }
 577
 578
 579 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 580                                         u32 start_idx, u32 num_events,
 581                                         u32 mode)
 582 {
 583         u32 i;
 584         u32 ptr;        /* SRAM byte address of log data */
 585         u32 ev, time, data; /* event log data */
 586         unsigned long reg_flags;
 587
 588         if (mode == 0)
 589                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 590         else
 591                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 592
 593         /* Make sure device is powered up for SRAM reads */
 594         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 595         if (iwl_grab_nic_access(priv)) {
 596                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 597                 return;
 598         }
 599
 600         /* Set starting address; reads will auto-increment */
 601         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 602         rmb();
 603
 604         /*
 605          * "time" is actually "data" for mode 0 (no timestamp).
 606          * place event id # at far right for easier visual parsing.
 607          */
 608         for (i = 0; i < num_events; i++) {
 609                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 610                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 611                 if (mode == 0) {
 612                         trace_iwlwifi_dev_ucode_cont_event(priv,
 613                                                         0, time, ev);
 614                 } else {
 615                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 616                         trace_iwlwifi_dev_ucode_cont_event(priv,
 617                                                 time, data, ev);
 618                 }
 619         }
 620         /* Allow device to power down */
 621         iwl_release_nic_access(priv);
 622         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 623 }
 624
 625 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 626 {
 627         u32 capacity;   /* event log capacity in # entries */
 628         u32 base;       /* SRAM byte address of event log header */
 629         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 630         u32 num_wraps;  /* # times uCode wrapped to top of log */
 631         u32 next_entry; /* index of next entry to be written by uCode */
 632
 633         if (priv->ucode_type == UCODE_INIT)
 634                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 635         else
 636                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 637         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 638                 capacity = iwl_read_targ_mem(priv, base);
 639                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 640                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 641                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 642         } else
 643                 return;
 644
 645         if (num_wraps == priv->event_log.num_wraps) {
 646                 iwl_print_cont_event_trace(priv,
 647                                        base, priv->event_log.next_entry,
 648                                        next_entry - priv->event_log.next_entry,
 649                                        mode);
 650                 priv->event_log.non_wraps_count++;
 651         } else {
 652                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 653                         priv->event_log.wraps_more_count++;
 654                 else
 655                         priv->event_log.wraps_once_count++;
 656                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 657                                 num_wraps - priv->event_log.num_wraps,
 658                                 next_entry, priv->event_log.next_entry);
 659                 if (next_entry < priv->event_log.next_entry) {
 660                         iwl_print_cont_event_trace(priv, base,
 661                                priv->event_log.next_entry,
 662                                capacity - priv->event_log.next_entry,
 663                                mode);
 664
 665                         iwl_print_cont_event_trace(priv, base, 0,
 666                                 next_entry, mode);
 667                 } else {
 668                         iwl_print_cont_event_trace(priv, base,
 669                                next_entry, capacity - next_entry,
 670                                mode);
 671
 672                         iwl_print_cont_event_trace(priv, base, 0,
 673                                 next_entry, mode);
 674                 }
 675         }
 676         priv->event_log.num_wraps = num_wraps;
 677         priv->event_log.next_entry = next_entry;
 678 }
 679
 680 /**
 681  * iwl_bg_ucode_trace - Timer callback to log ucode event
 682  *
 683  * The timer is continually set to execute every
 684  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 685  * this function is to perform continuous uCode event logging operation
 686  * if enabled
 687  */
 688 static void iwl_bg_ucode_trace(unsigned long data)
 689 {
 690         struct iwl_priv *priv = (struct iwl_priv *)data;
 691
 692         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 693                 return;
 694
 695         if (priv->event_log.ucode_trace) {
 696                 iwl_continuous_event_trace(priv);
 697                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 698                 mod_timer(&priv->ucode_trace,
 699                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 700         }
 701 }
 702
 703 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 704                                 struct iwl_rx_mem_buffer *rxb)
 705 {
 706         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 707         struct iwl4965_beacon_notif *beacon =
 708                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 709 #ifdef CONFIG_IWLWIFI_DEBUG
 710         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 711
 712         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 713                 "tsf %d %d rate %d\n",
 714                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 715                 beacon->beacon_notify_hdr.failure_frame,
 716                 le32_to_cpu(beacon->ibss_mgr_status),
 717                 le32_to_cpu(beacon->high_tsf),
 718                 le32_to_cpu(beacon->low_tsf), rate);
 719 #endif
 720
 721         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 722
 723         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 724                 queue_work(priv->workqueue, &priv->beacon_update);
 725 }
 726
 727 /* Handle notification from uCode that card's power state is changing
 728  * due to software, hardware, or critical temperature RFKILL */
 729 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 730                                     struct iwl_rx_mem_buffer *rxb)
 731 {
 732         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 733         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 734         unsigned long status = priv->status;
 735
 736         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 737                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 738                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 739                           (flags & CT_CARD_DISABLED) ?
 740                           "Reached" : "Not reached");
 741
 742         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 743                      CT_CARD_DISABLED)) {
 744
 745                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 746                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 747
 748                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 749                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 750
 751                 if (!(flags & RXON_CARD_DISABLED)) {
 752                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 753                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 754                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 755                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 756                 }
 757                 if (flags & CT_CARD_DISABLED)
 758                         iwl_tt_enter_ct_kill(priv);
 759         }
 760         if (!(flags & CT_CARD_DISABLED))
 761                 iwl_tt_exit_ct_kill(priv);
 762
 763         if (flags & HW_CARD_DISABLED)
 764                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 765         else
 766                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 767
 768
 769         if (!(flags & RXON_CARD_DISABLED))
 770                 iwl_scan_cancel(priv);
 771
 772         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 773              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 774                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 775                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 776         else
 777                 wake_up_interruptible(&priv->wait_command_queue);
 778 }
 779
 780 static void iwl_bg_tx_flush(struct work_struct *work)
 781 {
 782         struct iwl_priv *priv =
 783                 container_of(work, struct iwl_priv, tx_flush);
 784
 785         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 786                 return;
 787
 788         /* do nothing if rf-kill is on */
 789         if (!iwl_is_ready_rf(priv))
 790                 return;
 791
 792         if (priv->cfg->ops->lib->txfifo_flush) {
 793                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 794                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 795         }
 796 }
 797
 798 /**
 799  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 800  *
 801  * Setup the RX handlers for each of the reply types sent from the uCode
 802  * to the host.
 803  *
 804  * This function chains into the hardware specific files for them to setup
 805  * any hardware specific handlers as well.
 806  */
 807 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 808 {
 809         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 810         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 811         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 812         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 813                         iwl_rx_spectrum_measure_notif;
 814         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 815         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 816             iwl_rx_pm_debug_statistics_notif;
 817         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 818
 819         /*
 820          * The same handler is used for both the REPLY to a discrete
 821          * statistics request from the host as well as for the periodic
 822          * statistics notifications (after received beacons) from the uCode.
 823          */
 824         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 825         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 826
 827         iwl_setup_rx_scan_handlers(priv);
 828
 829         /* status change handler */
 830         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 831
 832         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 833             iwl_rx_missed_beacon_notif;
 834         /* Rx handlers */
 835         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 836         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 837         /* block ack */
 838         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 839         /* Set up hardware specific Rx handlers */
 840         priv->cfg->ops->lib->rx_handler_setup(priv);
 841 }
 842
 843 /**
 844  * iwl_rx_handle - Main entry function for receiving responses from uCode
 845  *
 846  * Uses the priv->rx_handlers callback function array to invoke
 847  * the appropriate handlers, including command responses,
 848  * frame-received notifications, and other notifications.
 849  */
 850 static void iwl_rx_handle(struct iwl_priv *priv)
 851 {
 852         struct iwl_rx_mem_buffer *rxb;
 853         struct iwl_rx_packet *pkt;
 854         struct iwl_rx_queue *rxq = &priv->rxq;
 855         u32 r, i;
 856         int reclaim;
 857         unsigned long flags;
 858         u8 fill_rx = 0;
 859         u32 count = 8;
 860         int total_empty;
 861
 862         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 863          * buffer that the driver may process (last buffer filled by ucode). */
 864         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 865         i = rxq->read;
 866
 867         /* Rx interrupt, but nothing sent from uCode */
 868         if (i == r)
 869                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 870
 871         /* calculate total frames need to be restock after handling RX */
 872         total_empty = r - rxq->write_actual;
 873         if (total_empty < 0)
 874                 total_empty += RX_QUEUE_SIZE;
 875
 876         if (total_empty > (RX_QUEUE_SIZE / 2))
 877                 fill_rx = 1;
 878
 879         while (i != r) {
 880                 int len;
 881
 882                 rxb = rxq->queue[i];
 883
 884                 /* If an RXB doesn't have a Rx queue slot associated with it,
 885                  * then a bug has been introduced in the queue refilling
 886                  * routines -- catch it here */
 887                 BUG_ON(rxb == NULL);
 888
 889                 rxq->queue[i] = NULL;
 890
 891                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 892                                PAGE_SIZE << priv->hw_params.rx_page_order,
 893                                PCI_DMA_FROMDEVICE);
 894                 pkt = rxb_addr(rxb);
 895
 896                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 897                 len += sizeof(u32); /* account for status word */
 898                 trace_iwlwifi_dev_rx(priv, pkt, len);
 899
 900                 /* Reclaim a command buffer only if this packet is a response
 901                  *   to a (driver-originated) command.
 902                  * If the packet (e.g. Rx frame) originated from uCode,
 903                  *   there is no command buffer to reclaim.
 904                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 905                  *   but apparently a few don't get set; catch them here. */
 906                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 907                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 908                         (pkt->hdr.cmd != REPLY_RX) &&
 909                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 910                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 911                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 912                         (pkt->hdr.cmd != REPLY_TX);
 913
 914                 /*
 915                  * Do the notification wait before RX handlers so
 916                  * even if the RX handler consumes the RXB we have
 917                  * access to it in the notification wait entry.
 918                  */
 919                 if (!list_empty(&priv->_agn.notif_waits)) {
 920                         struct iwl_notification_wait *w;
 921
 922                         spin_lock(&priv->_agn.notif_wait_lock);
 923                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 924                                 if (w->cmd == pkt->hdr.cmd) {
 925                                         w->triggered = true;
 926                                         if (w->fn)
 927                                                 w->fn(priv, pkt);
 928                                 }
 929                         }
 930                         spin_unlock(&priv->_agn.notif_wait_lock);
 931
 932                         wake_up_all(&priv->_agn.notif_waitq);
 933                 }
 934
 935                 /* Based on type of command response or notification,
 936                  *   handle those that need handling via function in
 937                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 938                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 939                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 940                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 941                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 942                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 943                 } else {
 944                         /* No handling needed */
 945                         IWL_DEBUG_RX(priv,
 946                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 947                                 r, i, get_cmd_string(pkt->hdr.cmd),
 948                                 pkt->hdr.cmd);
 949                 }
 950
 951                 /*
 952                  * XXX: After here, we should always check rxb->page
 953                  * against NULL before touching it or its virtual
 954                  * memory (pkt). Because some rx_handler might have
 955                  * already taken or freed the pages.
 956                  */
 957
 958                 if (reclaim) {
 959                         /* Invoke any callbacks, transfer the buffer to caller,
 960                          * and fire off the (possibly) blocking iwl_send_cmd()
 961                          * as we reclaim the driver command queue */
 962                         if (rxb->page)
 963                                 iwl_tx_cmd_complete(priv, rxb);
 964                         else
 965                                 IWL_WARN(priv, "Claim null rxb?\n");
 966                 }
 967
 968                 /* Reuse the page if possible. For notification packets and
 969                  * SKBs that fail to Rx correctly, add them back into the
 970                  * rx_free list for reuse later. */
 971                 spin_lock_irqsave(&rxq->lock, flags);
 972                 if (rxb->page != NULL) {
 973                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 974                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 975                                 PCI_DMA_FROMDEVICE);
 976                         list_add_tail(&rxb->list, &rxq->rx_free);
 977                         rxq->free_count++;
 978                 } else
 979                         list_add_tail(&rxb->list, &rxq->rx_used);
 980
 981                 spin_unlock_irqrestore(&rxq->lock, flags);
 982
 983                 i = (i + 1) & RX_QUEUE_MASK;
 984                 /* If there are a lot of unused frames,
 985                  * restock the Rx queue so ucode wont assert. */
 986                 if (fill_rx) {
 987                         count++;
 988                         if (count >= 8) {
 989                                 rxq->read = i;
 990                                 iwlagn_rx_replenish_now(priv);
 991                                 count = 0;
 992                         }
 993                 }
 994         }
 995
 996         /* Backtrack one entry */
 997         rxq->read = i;
 998         if (fill_rx)
 999                 iwlagn_rx_replenish_now(priv);
1000         else
1001                 iwlagn_rx_queue_restock(priv);
1002 }
1003
1004 /* call this function to flush any scheduled tasklet */
1005 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1006 {
1007         /* wait to make sure we flush pending tasklet*/
1008         synchronize_irq(priv->pci_dev->irq);
1009         tasklet_kill(&priv->irq_tasklet);
1010 }
1011
1012 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1013 {
1014         u32 inta, handled = 0;
1015         u32 inta_fh;
1016         unsigned long flags;
1017         u32 i;
1018 #ifdef CONFIG_IWLWIFI_DEBUG
1019         u32 inta_mask;
1020 #endif
1021
1022         spin_lock_irqsave(&priv->lock, flags);
1023
1024         /* Ack/clear/reset pending uCode interrupts.
1025          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1026          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1027         inta = iwl_read32(priv, CSR_INT);
1028         iwl_write32(priv, CSR_INT, inta);
1029
1030         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1031          * Any new interrupts that happen after this, either while we're
1032          * in this tasklet, or later, will show up in next ISR/tasklet. */
1033         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1034         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1035
1036 #ifdef CONFIG_IWLWIFI_DEBUG
1037         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1038                 /* just for debug */
1039                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1040                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1041                               inta, inta_mask, inta_fh);
1042         }
1043 #endif
1044
1045         spin_unlock_irqrestore(&priv->lock, flags);
1046
1047         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1048          * atomic, make sure that inta covers all the interrupts that
1049          * we've discovered, even if FH interrupt came in just after
1050          * reading CSR_INT. */
1051         if (inta_fh & CSR49_FH_INT_RX_MASK)
1052                 inta |= CSR_INT_BIT_FH_RX;
1053         if (inta_fh & CSR49_FH_INT_TX_MASK)
1054                 inta |= CSR_INT_BIT_FH_TX;
1055
1056         /* Now service all interrupt bits discovered above. */
1057         if (inta & CSR_INT_BIT_HW_ERR) {
1058                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1059
1060                 /* Tell the device to stop sending interrupts */
1061                 iwl_disable_interrupts(priv);
1062
1063                 priv->isr_stats.hw++;
1064                 iwl_irq_handle_error(priv);
1065
1066                 handled |= CSR_INT_BIT_HW_ERR;
1067
1068                 return;
1069         }
1070
1071 #ifdef CONFIG_IWLWIFI_DEBUG
1072         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1073                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1074                 if (inta & CSR_INT_BIT_SCD) {
1075                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1076                                       "the frame/frames.\n");
1077                         priv->isr_stats.sch++;
1078                 }
1079
1080                 /* Alive notification via Rx interrupt will do the real work */
1081                 if (inta & CSR_INT_BIT_ALIVE) {
1082                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1083                         priv->isr_stats.alive++;
1084                 }
1085         }
1086 #endif
1087         /* Safely ignore these bits for debug checks below */
1088         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1089
1090         /* HW RF KILL switch toggled */
1091         if (inta & CSR_INT_BIT_RF_KILL) {
1092                 int hw_rf_kill = 0;
1093                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1094                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1095                         hw_rf_kill = 1;
1096
1097                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1098                                 hw_rf_kill ? "disable radio" : "enable radio");
1099
1100                 priv->isr_stats.rfkill++;
1101
1102                 /* driver only loads ucode once setting the interface up.
1103                  * the driver allows loading the ucode even if the radio
1104                  * is killed. Hence update the killswitch state here. The
1105                  * rfkill handler will care about restarting if needed.
1106                  */
1107                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1108                         if (hw_rf_kill)
1109                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1110                         else
1111                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1112                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1113                 }
1114
1115                 handled |= CSR_INT_BIT_RF_KILL;
1116         }
1117
1118         /* Chip got too hot and stopped itself */
1119         if (inta & CSR_INT_BIT_CT_KILL) {
1120                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1121                 priv->isr_stats.ctkill++;
1122                 handled |= CSR_INT_BIT_CT_KILL;
1123         }
1124
1125         /* Error detected by uCode */
1126         if (inta & CSR_INT_BIT_SW_ERR) {
1127                 IWL_ERR(priv, "Microcode SW error detected. "
1128                         " Restarting 0x%X.\n", inta);
1129                 priv->isr_stats.sw++;
1130                 iwl_irq_handle_error(priv);
1131                 handled |= CSR_INT_BIT_SW_ERR;
1132         }
1133
1134         /*
1135          * uCode wakes up after power-down sleep.
1136          * Tell device about any new tx or host commands enqueued,
1137          * and about any Rx buffers made available while asleep.
1138          */
1139         if (inta & CSR_INT_BIT_WAKEUP) {
1140                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1141                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1142                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1143                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1144                 priv->isr_stats.wakeup++;
1145                 handled |= CSR_INT_BIT_WAKEUP;
1146         }
1147
1148         /* All uCode command responses, including Tx command responses,
1149          * Rx "responses" (frame-received notification), and other
1150          * notifications from uCode come through here*/
1151         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1152                 iwl_rx_handle(priv);
1153                 priv->isr_stats.rx++;
1154                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1155         }
1156
1157         /* This "Tx" DMA channel is used only for loading uCode */
1158         if (inta & CSR_INT_BIT_FH_TX) {
1159                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1160                 priv->isr_stats.tx++;
1161                 handled |= CSR_INT_BIT_FH_TX;
1162                 /* Wake up uCode load routine, now that load is complete */
1163                 priv->ucode_write_complete = 1;
1164                 wake_up_interruptible(&priv->wait_command_queue);
1165         }
1166
1167         if (inta & ~handled) {
1168                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1169                 priv->isr_stats.unhandled++;
1170         }
1171
1172         if (inta & ~(priv->inta_mask)) {
1173                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1174                          inta & ~priv->inta_mask);
1175                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1176         }
1177
1178         /* Re-enable all interrupts */
1179         /* only Re-enable if disabled by irq */
1180         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1181                 iwl_enable_interrupts(priv);
1182
1183 #ifdef CONFIG_IWLWIFI_DEBUG
1184         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1185                 inta = iwl_read32(priv, CSR_INT);
1186                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1187                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1188                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1189                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1190         }
1191 #endif
1192 }
1193
1194 /* tasklet for iwlagn interrupt */
1195 static void iwl_irq_tasklet(struct iwl_priv *priv)
1196 {
1197         u32 inta = 0;
1198         u32 handled = 0;
1199         unsigned long flags;
1200         u32 i;
1201 #ifdef CONFIG_IWLWIFI_DEBUG
1202         u32 inta_mask;
1203 #endif
1204
1205         spin_lock_irqsave(&priv->lock, flags);
1206
1207         /* Ack/clear/reset pending uCode interrupts.
1208          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1209          */
1210         /* There is a hardware bug in the interrupt mask function that some
1211          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1212          * they are disabled in the CSR_INT_MASK register. Furthermore the
1213          * ICT interrupt handling mechanism has another bug that might cause
1214          * these unmasked interrupts fail to be detected. We workaround the
1215          * hardware bugs here by ACKing all the possible interrupts so that
1216          * interrupt coalescing can still be achieved.
1217          */
1218         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1219
1220         inta = priv->_agn.inta;
1221
1222 #ifdef CONFIG_IWLWIFI_DEBUG
1223         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1224                 /* just for debug */
1225                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1226                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1227                                 inta, inta_mask);
1228         }
1229 #endif
1230
1231         spin_unlock_irqrestore(&priv->lock, flags);
1232
1233         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1234         priv->_agn.inta = 0;
1235
1236         /* Now service all interrupt bits discovered above. */
1237         if (inta & CSR_INT_BIT_HW_ERR) {
1238                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1239
1240                 /* Tell the device to stop sending interrupts */
1241                 iwl_disable_interrupts(priv);
1242
1243                 priv->isr_stats.hw++;
1244                 iwl_irq_handle_error(priv);
1245
1246                 handled |= CSR_INT_BIT_HW_ERR;
1247
1248                 return;
1249         }
1250
1251 #ifdef CONFIG_IWLWIFI_DEBUG
1252         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1253                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1254                 if (inta & CSR_INT_BIT_SCD) {
1255                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1256                                       "the frame/frames.\n");
1257                         priv->isr_stats.sch++;
1258                 }
1259
1260                 /* Alive notification via Rx interrupt will do the real work */
1261                 if (inta & CSR_INT_BIT_ALIVE) {
1262                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1263                         priv->isr_stats.alive++;
1264                 }
1265         }
1266 #endif
1267         /* Safely ignore these bits for debug checks below */
1268         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1269
1270         /* HW RF KILL switch toggled */
1271         if (inta & CSR_INT_BIT_RF_KILL) {
1272                 int hw_rf_kill = 0;
1273                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1274                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1275                         hw_rf_kill = 1;
1276
1277                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1278                                 hw_rf_kill ? "disable radio" : "enable radio");
1279
1280                 priv->isr_stats.rfkill++;
1281
1282                 /* driver only loads ucode once setting the interface up.
1283                  * the driver allows loading the ucode even if the radio
1284                  * is killed. Hence update the killswitch state here. The
1285                  * rfkill handler will care about restarting if needed.
1286                  */
1287                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1288                         if (hw_rf_kill)
1289                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1290                         else
1291                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1292                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1293                 }
1294
1295                 handled |= CSR_INT_BIT_RF_KILL;
1296         }
1297
1298         /* Chip got too hot and stopped itself */
1299         if (inta & CSR_INT_BIT_CT_KILL) {
1300                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1301                 priv->isr_stats.ctkill++;
1302                 handled |= CSR_INT_BIT_CT_KILL;
1303         }
1304
1305         /* Error detected by uCode */
1306         if (inta & CSR_INT_BIT_SW_ERR) {
1307                 IWL_ERR(priv, "Microcode SW error detected. "
1308                         " Restarting 0x%X.\n", inta);
1309                 priv->isr_stats.sw++;
1310                 iwl_irq_handle_error(priv);
1311                 handled |= CSR_INT_BIT_SW_ERR;
1312         }
1313
1314         /* uCode wakes up after power-down sleep */
1315         if (inta & CSR_INT_BIT_WAKEUP) {
1316                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1317                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1318                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1319                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1320
1321                 priv->isr_stats.wakeup++;
1322
1323                 handled |= CSR_INT_BIT_WAKEUP;
1324         }
1325
1326         /* All uCode command responses, including Tx command responses,
1327          * Rx "responses" (frame-received notification), and other
1328          * notifications from uCode come through here*/
1329         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1330                         CSR_INT_BIT_RX_PERIODIC)) {
1331                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1332                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1333                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1334                         iwl_write32(priv, CSR_FH_INT_STATUS,
1335                                         CSR49_FH_INT_RX_MASK);
1336                 }
1337                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1338                         handled |= CSR_INT_BIT_RX_PERIODIC;
1339                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1340                 }
1341                 /* Sending RX interrupt require many steps to be done in the
1342                  * the device:
1343                  * 1- write interrupt to current index in ICT table.
1344                  * 2- dma RX frame.
1345                  * 3- update RX shared data to indicate last write index.
1346                  * 4- send interrupt.
1347                  * This could lead to RX race, driver could receive RX interrupt
1348                  * but the shared data changes does not reflect this;
1349                  * periodic interrupt will detect any dangling Rx activity.
1350                  */
1351
1352                 /* Disable periodic interrupt; we use it as just a one-shot. */
1353                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1354                             CSR_INT_PERIODIC_DIS);
1355                 iwl_rx_handle(priv);
1356
1357                 /*
1358                  * Enable periodic interrupt in 8 msec only if we received
1359                  * real RX interrupt (instead of just periodic int), to catch
1360                  * any dangling Rx interrupt.  If it was just the periodic
1361                  * interrupt, there was no dangling Rx activity, and no need
1362                  * to extend the periodic interrupt; one-shot is enough.
1363                  */
1364                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1365                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1366                                     CSR_INT_PERIODIC_ENA);
1367
1368                 priv->isr_stats.rx++;
1369         }
1370
1371         /* This "Tx" DMA channel is used only for loading uCode */
1372         if (inta & CSR_INT_BIT_FH_TX) {
1373                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1374                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1375                 priv->isr_stats.tx++;
1376                 handled |= CSR_INT_BIT_FH_TX;
1377                 /* Wake up uCode load routine, now that load is complete */
1378                 priv->ucode_write_complete = 1;
1379                 wake_up_interruptible(&priv->wait_command_queue);
1380         }
1381
1382         if (inta & ~handled) {
1383                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1384                 priv->isr_stats.unhandled++;
1385         }
1386
1387         if (inta & ~(priv->inta_mask)) {
1388                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1389                          inta & ~priv->inta_mask);
1390         }
1391
1392         /* Re-enable all interrupts */
1393         /* only Re-enable if disabled by irq */
1394         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1395                 iwl_enable_interrupts(priv);
1396 }
1397
1398 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1399 #define ACK_CNT_RATIO (50)
1400 #define BA_TIMEOUT_CNT (5)
1401 #define BA_TIMEOUT_MAX (16)
1402
1403 /**
1404  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1405  *
1406  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1407  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1408  * operation state.
1409  */
1410 bool iwl_good_ack_health(struct iwl_priv *priv,
1411                                 struct iwl_rx_packet *pkt)
1412 {
1413         bool rc = true;
1414         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1415         int ba_timeout_delta;
1416
1417         actual_ack_cnt_delta =
1418                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1419                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1420         expected_ack_cnt_delta =
1421                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1422                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1423         ba_timeout_delta =
1424                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1425                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1426         if ((priv->_agn.agg_tids_count > 0) &&
1427             (expected_ack_cnt_delta > 0) &&
1428             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1429                 < ACK_CNT_RATIO) &&
1430             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1431                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1432                                 " expected_ack_cnt = %d\n",
1433                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1434
1435 #ifdef CONFIG_IWLWIFI_DEBUGFS
1436                 /*
1437                  * This is ifdef'ed on DEBUGFS because otherwise the
1438                  * statistics aren't available. If DEBUGFS is set but
1439                  * DEBUG is not, these will just compile out.
1440                  */
1441                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1442                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1443                 IWL_DEBUG_RADIO(priv,
1444                                 "ack_or_ba_timeout_collision delta = %d\n",
1445                                 priv->_agn.delta_statistics.tx.
1446                                 ack_or_ba_timeout_collision);
1447 #endif
1448                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1449                                 ba_timeout_delta);
1450                 if (!actual_ack_cnt_delta &&
1451                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1452                         rc = false;
1453         }
1454         return rc;
1455 }
1456
1457
1458 /*****************************************************************************
1459  *
1460  * sysfs attributes
1461  *
1462  *****************************************************************************/
1463
1464 #ifdef CONFIG_IWLWIFI_DEBUG
1465
1466 /*
1467  * The following adds a new attribute to the sysfs representation
1468  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1469  * used for controlling the debug level.
1470  *
1471  * See the level definitions in iwl for details.
1472  *
1473  * The debug_level being managed using sysfs below is a per device debug
1474  * level that is used instead of the global debug level if it (the per
1475  * device debug level) is set.
1476  */
1477 static ssize_t show_debug_level(struct device *d,
1478                                 struct device_attribute *attr, char *buf)
1479 {
1480         struct iwl_priv *priv = dev_get_drvdata(d);
1481         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1482 }
1483 static ssize_t store_debug_level(struct device *d,
1484                                 struct device_attribute *attr,
1485                                  const char *buf, size_t count)
1486 {
1487         struct iwl_priv *priv = dev_get_drvdata(d);
1488         unsigned long val;
1489         int ret;
1490
1491         ret = strict_strtoul(buf, 0, &val);
1492         if (ret)
1493                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1494         else {
1495                 priv->debug_level = val;
1496                 if (iwl_alloc_traffic_mem(priv))
1497                         IWL_ERR(priv,
1498                                 "Not enough memory to generate traffic log\n");
1499         }
1500         return strnlen(buf, count);
1501 }
1502
1503 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1504                         show_debug_level, store_debug_level);
1505
1506
1507 #endif /* CONFIG_IWLWIFI_DEBUG */
1508
1509
1510 static ssize_t show_temperature(struct device *d,
1511                                 struct device_attribute *attr, char *buf)
1512 {
1513         struct iwl_priv *priv = dev_get_drvdata(d);
1514
1515         if (!iwl_is_alive(priv))
1516                 return -EAGAIN;
1517
1518         return sprintf(buf, "%d\n", priv->temperature);
1519 }
1520
1521 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1522
1523 static ssize_t show_tx_power(struct device *d,
1524                              struct device_attribute *attr, char *buf)
1525 {
1526         struct iwl_priv *priv = dev_get_drvdata(d);
1527
1528         if (!iwl_is_ready_rf(priv))
1529                 return sprintf(buf, "off\n");
1530         else
1531                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1532 }
1533
1534 static ssize_t store_tx_power(struct device *d,
1535                               struct device_attribute *attr,
1536                               const char *buf, size_t count)
1537 {
1538         struct iwl_priv *priv = dev_get_drvdata(d);
1539         unsigned long val;
1540         int ret;
1541
1542         ret = strict_strtoul(buf, 10, &val);
1543         if (ret)
1544                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1545         else {
1546                 ret = iwl_set_tx_power(priv, val, false);
1547                 if (ret)
1548                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1549                                 ret);
1550                 else
1551                         ret = count;
1552         }
1553         return ret;
1554 }
1555
1556 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1557
1558 static struct attribute *iwl_sysfs_entries[] = {
1559         &dev_attr_temperature.attr,
1560         &dev_attr_tx_power.attr,
1561 #ifdef CONFIG_IWLWIFI_DEBUG
1562         &dev_attr_debug_level.attr,
1563 #endif
1564         NULL
1565 };
1566
1567 static struct attribute_group iwl_attribute_group = {
1568         .name = NULL,           /* put in device directory */
1569         .attrs = iwl_sysfs_entries,
1570 };
1571
1572 /******************************************************************************
1573  *
1574  * uCode download functions
1575  *
1576  ******************************************************************************/
1577
1578 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1579 {
1580         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1581         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1582         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1583         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1584         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1585         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1586 }
1587
1588 static void iwl_nic_start(struct iwl_priv *priv)
1589 {
1590         /* Remove all resets to allow NIC to operate */
1591         iwl_write32(priv, CSR_RESET, 0);
1592 }
1593
1594 struct iwlagn_ucode_capabilities {
1595         u32 max_probe_length;
1596         u32 standard_phy_calibration_size;
1597         bool pan;
1598 };
1599
1600 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1601 static int iwl_mac_setup_register(struct iwl_priv *priv,
1602                                   struct iwlagn_ucode_capabilities *capa);
1603
1604 #define UCODE_EXPERIMENTAL_INDEX        100
1605 #define UCODE_EXPERIMENTAL_TAG          "exp"
1606
1607 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1608 {
1609         const char *name_pre = priv->cfg->fw_name_pre;
1610         char tag[8];
1611
1612         if (first) {
1613 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1614                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1615                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1616         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1617 #endif
1618                 priv->fw_index = priv->cfg->ucode_api_max;
1619                 sprintf(tag, "%d", priv->fw_index);
1620         } else {
1621                 priv->fw_index--;
1622                 sprintf(tag, "%d", priv->fw_index);
1623         }
1624
1625         if (priv->fw_index < priv->cfg->ucode_api_min) {
1626                 IWL_ERR(priv, "no suitable firmware found!\n");
1627                 return -ENOENT;
1628         }
1629
1630         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1631
1632         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1633                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1634                                 ? "EXPERIMENTAL " : "",
1635                        priv->firmware_name);
1636
1637         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1638                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1639                                        iwl_ucode_callback);
1640 }
1641
1642 struct iwlagn_firmware_pieces {
1643         const void *inst, *data, *init, *init_data, *boot;
1644         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1645
1646         u32 build;
1647
1648         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1649         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1650 };
1651
1652 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1653                                        const struct firmware *ucode_raw,
1654                                        struct iwlagn_firmware_pieces *pieces)
1655 {
1656         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1657         u32 api_ver, hdr_size;
1658         const u8 *src;
1659
1660         priv->ucode_ver = le32_to_cpu(ucode->ver);
1661         api_ver = IWL_UCODE_API(priv->ucode_ver);
1662
1663         switch (api_ver) {
1664         default:
1665                 /*
1666                  * 4965 doesn't revision the firmware file format
1667                  * along with the API version, it always uses v1
1668                  * file format.
1669                  */
1670                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1671                                 CSR_HW_REV_TYPE_4965) {
1672                         hdr_size = 28;
1673                         if (ucode_raw->size < hdr_size) {
1674                                 IWL_ERR(priv, "File size too small!\n");
1675                                 return -EINVAL;
1676                         }
1677                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1678                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1679                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1680                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1681                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1682                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1683                         src = ucode->u.v2.data;
1684                         break;
1685                 }
1686                 /* fall through for 4965 */
1687         case 0:
1688         case 1:
1689         case 2:
1690                 hdr_size = 24;
1691                 if (ucode_raw->size < hdr_size) {
1692                         IWL_ERR(priv, "File size too small!\n");
1693                         return -EINVAL;
1694                 }
1695                 pieces->build = 0;
1696                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1697                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1698                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1699                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1700                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1701                 src = ucode->u.v1.data;
1702                 break;
1703         }
1704
1705         /* Verify size of file vs. image size info in file's header */
1706         if (ucode_raw->size != hdr_size + pieces->inst_size +
1707                                 pieces->data_size + pieces->init_size +
1708                                 pieces->init_data_size + pieces->boot_size) {
1709
1710                 IWL_ERR(priv,
1711                         "uCode file size %d does not match expected size\n",
1712                         (int)ucode_raw->size);
1713                 return -EINVAL;
1714         }
1715
1716         pieces->inst = src;
1717         src += pieces->inst_size;
1718         pieces->data = src;
1719         src += pieces->data_size;
1720         pieces->init = src;
1721         src += pieces->init_size;
1722         pieces->init_data = src;
1723         src += pieces->init_data_size;
1724         pieces->boot = src;
1725         src += pieces->boot_size;
1726
1727         return 0;
1728 }
1729
1730 static int iwlagn_wanted_ucode_alternative = 1;
1731
1732 static int iwlagn_load_firmware(struct iwl_priv *priv,
1733                                 const struct firmware *ucode_raw,
1734                                 struct iwlagn_firmware_pieces *pieces,
1735                                 struct iwlagn_ucode_capabilities *capa)
1736 {
1737         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1738         struct iwl_ucode_tlv *tlv;
1739         size_t len = ucode_raw->size;
1740         const u8 *data;
1741         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1742         u64 alternatives;
1743         u32 tlv_len;
1744         enum iwl_ucode_tlv_type tlv_type;
1745         const u8 *tlv_data;
1746
1747         if (len < sizeof(*ucode)) {
1748                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1749                 return -EINVAL;
1750         }
1751
1752         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1753                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1754                         le32_to_cpu(ucode->magic));
1755                 return -EINVAL;
1756         }
1757
1758         /*
1759          * Check which alternatives are present, and "downgrade"
1760          * when the chosen alternative is not present, warning
1761          * the user when that happens. Some files may not have
1762          * any alternatives, so don't warn in that case.
1763          */
1764         alternatives = le64_to_cpu(ucode->alternatives);
1765         tmp = wanted_alternative;
1766         if (wanted_alternative > 63)
1767                 wanted_alternative = 63;
1768         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1769                 wanted_alternative--;
1770         if (wanted_alternative && wanted_alternative != tmp)
1771                 IWL_WARN(priv,
1772                          "uCode alternative %d not available, choosing %d\n",
1773                          tmp, wanted_alternative);
1774
1775         priv->ucode_ver = le32_to_cpu(ucode->ver);
1776         pieces->build = le32_to_cpu(ucode->build);
1777         data = ucode->data;
1778
1779         len -= sizeof(*ucode);
1780
1781         while (len >= sizeof(*tlv)) {
1782                 u16 tlv_alt;
1783
1784                 len -= sizeof(*tlv);
1785                 tlv = (void *)data;
1786
1787                 tlv_len = le32_to_cpu(tlv->length);
1788                 tlv_type = le16_to_cpu(tlv->type);
1789                 tlv_alt = le16_to_cpu(tlv->alternative);
1790                 tlv_data = tlv->data;
1791
1792                 if (len < tlv_len) {
1793                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1794                                 len, tlv_len);
1795                         return -EINVAL;
1796                 }
1797                 len -= ALIGN(tlv_len, 4);
1798                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1799
1800                 /*
1801                  * Alternative 0 is always valid.
1802                  *
1803                  * Skip alternative TLVs that are not selected.
1804                  */
1805                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1806                         continue;
1807
1808                 switch (tlv_type) {
1809                 case IWL_UCODE_TLV_INST:
1810                         pieces->inst = tlv_data;
1811                         pieces->inst_size = tlv_len;
1812                         break;
1813                 case IWL_UCODE_TLV_DATA:
1814                         pieces->data = tlv_data;
1815                         pieces->data_size = tlv_len;
1816                         break;
1817                 case IWL_UCODE_TLV_INIT:
1818                         pieces->init = tlv_data;
1819                         pieces->init_size = tlv_len;
1820                         break;
1821                 case IWL_UCODE_TLV_INIT_DATA:
1822                         pieces->init_data = tlv_data;
1823                         pieces->init_data_size = tlv_len;
1824                         break;
1825                 case IWL_UCODE_TLV_BOOT:
1826                         pieces->boot = tlv_data;
1827                         pieces->boot_size = tlv_len;
1828                         break;
1829                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1830                         if (tlv_len != sizeof(u32))
1831                                 goto invalid_tlv_len;
1832                         capa->max_probe_length =
1833                                         le32_to_cpup((__le32 *)tlv_data);
1834                         break;
1835                 case IWL_UCODE_TLV_PAN:
1836                         if (tlv_len)
1837                                 goto invalid_tlv_len;
1838                         capa->pan = true;
1839                         break;
1840                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1841                         if (tlv_len != sizeof(u32))
1842                                 goto invalid_tlv_len;
1843                         pieces->init_evtlog_ptr =
1844                                         le32_to_cpup((__le32 *)tlv_data);
1845                         break;
1846                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1847                         if (tlv_len != sizeof(u32))
1848                                 goto invalid_tlv_len;
1849                         pieces->init_evtlog_size =
1850                                         le32_to_cpup((__le32 *)tlv_data);
1851                         break;
1852                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1853                         if (tlv_len != sizeof(u32))
1854                                 goto invalid_tlv_len;
1855                         pieces->init_errlog_ptr =
1856                                         le32_to_cpup((__le32 *)tlv_data);
1857                         break;
1858                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1859                         if (tlv_len != sizeof(u32))
1860                                 goto invalid_tlv_len;
1861                         pieces->inst_evtlog_ptr =
1862                                         le32_to_cpup((__le32 *)tlv_data);
1863                         break;
1864                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1865                         if (tlv_len != sizeof(u32))
1866                                 goto invalid_tlv_len;
1867                         pieces->inst_evtlog_size =
1868                                         le32_to_cpup((__le32 *)tlv_data);
1869                         break;
1870                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1871                         if (tlv_len != sizeof(u32))
1872                                 goto invalid_tlv_len;
1873                         pieces->inst_errlog_ptr =
1874                                         le32_to_cpup((__le32 *)tlv_data);
1875                         break;
1876                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1877                         if (tlv_len)
1878                                 goto invalid_tlv_len;
1879                         priv->enhance_sensitivity_table = true;
1880                         break;
1881                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1882                         if (tlv_len != sizeof(u32))
1883                                 goto invalid_tlv_len;
1884                         capa->standard_phy_calibration_size =
1885                                         le32_to_cpup((__le32 *)tlv_data);
1886                         break;
1887                 default:
1888                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1889                         break;
1890                 }
1891         }
1892
1893         if (len) {
1894                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1895                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1896                 return -EINVAL;
1897         }
1898
1899         return 0;
1900
1901  invalid_tlv_len:
1902         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1903         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1904
1905         return -EINVAL;
1906 }
1907
1908 /**
1909  * iwl_ucode_callback - callback when firmware was loaded
1910  *
1911  * If loaded successfully, copies the firmware into buffers
1912  * for the card to fetch (via DMA).
1913  */
1914 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1915 {
1916         struct iwl_priv *priv = context;
1917         struct iwl_ucode_header *ucode;
1918         int err;
1919         struct iwlagn_firmware_pieces pieces;
1920         const unsigned int api_max = priv->cfg->ucode_api_max;
1921         const unsigned int api_min = priv->cfg->ucode_api_min;
1922         u32 api_ver;
1923         char buildstr[25];
1924         u32 build;
1925         struct iwlagn_ucode_capabilities ucode_capa = {
1926                 .max_probe_length = 200,
1927                 .standard_phy_calibration_size =
1928                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1929         };
1930
1931         memset(&pieces, 0, sizeof(pieces));
1932
1933         if (!ucode_raw) {
1934                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1935                         IWL_ERR(priv,
1936                                 "request for firmware file '%s' failed.\n",
1937                                 priv->firmware_name);
1938                 goto try_again;
1939         }
1940
1941         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1942                        priv->firmware_name, ucode_raw->size);
1943
1944         /* Make sure that we got at least the API version number */
1945         if (ucode_raw->size < 4) {
1946                 IWL_ERR(priv, "File size way too small!\n");
1947                 goto try_again;
1948         }
1949
1950         /* Data from ucode file:  header followed by uCode images */
1951         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1952
1953         if (ucode->ver)
1954                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1955         else
1956                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1957                                            &ucode_capa);
1958
1959         if (err)
1960                 goto try_again;
1961
1962         api_ver = IWL_UCODE_API(priv->ucode_ver);
1963         build = pieces.build;
1964
1965         /*
1966          * api_ver should match the api version forming part of the
1967          * firmware filename ... but we don't check for that and only rely
1968          * on the API version read from firmware header from here on forward
1969          */
1970         /* no api version check required for experimental uCode */
1971         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1972                 if (api_ver < api_min || api_ver > api_max) {
1973                         IWL_ERR(priv,
1974                                 "Driver unable to support your firmware API. "
1975                                 "Driver supports v%u, firmware is v%u.\n",
1976                                 api_max, api_ver);
1977                         goto try_again;
1978                 }
1979
1980                 if (api_ver != api_max)
1981                         IWL_ERR(priv,
1982                                 "Firmware has old API version. Expected v%u, "
1983                                 "got v%u. New firmware can be obtained "
1984                                 "from http://www.intellinuxwireless.org.\n",
1985                                 api_max, api_ver);
1986         }
1987
1988         if (build)
1989                 sprintf(buildstr, " build %u%s", build,
1990                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1991                                 ? " (EXP)" : "");
1992         else
1993                 buildstr[0] = '\0';
1994
1995         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1996                  IWL_UCODE_MAJOR(priv->ucode_ver),
1997                  IWL_UCODE_MINOR(priv->ucode_ver),
1998                  IWL_UCODE_API(priv->ucode_ver),
1999                  IWL_UCODE_SERIAL(priv->ucode_ver),
2000                  buildstr);
2001
2002         snprintf(priv->hw->wiphy->fw_version,
2003                  sizeof(priv->hw->wiphy->fw_version),
2004                  "%u.%u.%u.%u%s",
2005                  IWL_UCODE_MAJOR(priv->ucode_ver),
2006                  IWL_UCODE_MINOR(priv->ucode_ver),
2007                  IWL_UCODE_API(priv->ucode_ver),
2008                  IWL_UCODE_SERIAL(priv->ucode_ver),
2009                  buildstr);
2010
2011         /*
2012          * For any of the failures below (before allocating pci memory)
2013          * we will try to load a version with a smaller API -- maybe the
2014          * user just got a corrupted version of the latest API.
2015          */
2016
2017         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2018                        priv->ucode_ver);
2019         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2020                        pieces.inst_size);
2021         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2022                        pieces.data_size);
2023         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2024                        pieces.init_size);
2025         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2026                        pieces.init_data_size);
2027         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2028                        pieces.boot_size);
2029
2030         /* Verify that uCode images will fit in card's SRAM */
2031         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2032                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2033                         pieces.inst_size);
2034                 goto try_again;
2035         }
2036
2037         if (pieces.data_size > priv->hw_params.max_data_size) {
2038                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2039                         pieces.data_size);
2040                 goto try_again;
2041         }
2042
2043         if (pieces.init_size > priv->hw_params.max_inst_size) {
2044                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2045                         pieces.init_size);
2046                 goto try_again;
2047         }
2048
2049         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2050                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2051                         pieces.init_data_size);
2052                 goto try_again;
2053         }
2054
2055         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2056                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2057                         pieces.boot_size);
2058                 goto try_again;
2059         }
2060
2061         /* Allocate ucode buffers for card's bus-master loading ... */
2062
2063         /* Runtime instructions and 2 copies of data:
2064          * 1) unmodified from disk
2065          * 2) backup cache for save/restore during power-downs */
2066         priv->ucode_code.len = pieces.inst_size;
2067         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2068
2069         priv->ucode_data.len = pieces.data_size;
2070         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2071
2072         priv->ucode_data_backup.len = pieces.data_size;
2073         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2074
2075         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2076             !priv->ucode_data_backup.v_addr)
2077                 goto err_pci_alloc;
2078
2079         /* Initialization instructions and data */
2080         if (pieces.init_size && pieces.init_data_size) {
2081                 priv->ucode_init.len = pieces.init_size;
2082                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2083
2084                 priv->ucode_init_data.len = pieces.init_data_size;
2085                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2086
2087                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2088                         goto err_pci_alloc;
2089         }
2090
2091         /* Bootstrap (instructions only, no data) */
2092         if (pieces.boot_size) {
2093                 priv->ucode_boot.len = pieces.boot_size;
2094                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2095
2096                 if (!priv->ucode_boot.v_addr)
2097                         goto err_pci_alloc;
2098         }
2099
2100         /* Now that we can no longer fail, copy information */
2101
2102         /*
2103          * The (size - 16) / 12 formula is based on the information recorded
2104          * for each event, which is of mode 1 (including timestamp) for all
2105          * new microcodes that include this information.
2106          */
2107         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2108         if (pieces.init_evtlog_size)
2109                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2110         else
2111                 priv->_agn.init_evtlog_size =
2112                         priv->cfg->base_params->max_event_log_size;
2113         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2114         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2115         if (pieces.inst_evtlog_size)
2116                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2117         else
2118                 priv->_agn.inst_evtlog_size =
2119                         priv->cfg->base_params->max_event_log_size;
2120         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2121
2122         if (ucode_capa.pan) {
2123                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2124                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2125         } else
2126                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2127
2128         /* Copy images into buffers for card's bus-master reads ... */
2129
2130         /* Runtime instructions (first block of data in file) */
2131         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2132                         pieces.inst_size);
2133         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2134
2135         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2136                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2137
2138         /*
2139          * Runtime data
2140          * NOTE:  Copy into backup buffer will be done in iwl_up()
2141          */
2142         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2143                         pieces.data_size);
2144         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2145         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2146
2147         /* Initialization instructions */
2148         if (pieces.init_size) {
2149                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2150                                 pieces.init_size);
2151                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2152         }
2153
2154         /* Initialization data */
2155         if (pieces.init_data_size) {
2156                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2157                                pieces.init_data_size);
2158                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2159                        pieces.init_data_size);
2160         }
2161
2162         /* Bootstrap instructions */
2163         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2164                         pieces.boot_size);
2165         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2166
2167         /*
2168          * figure out the offset of chain noise reset and gain commands
2169          * base on the size of standard phy calibration commands table size
2170          */
2171         if (ucode_capa.standard_phy_calibration_size >
2172             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2173                 ucode_capa.standard_phy_calibration_size =
2174                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2175
2176         priv->_agn.phy_calib_chain_noise_reset_cmd =
2177                 ucode_capa.standard_phy_calibration_size;
2178         priv->_agn.phy_calib_chain_noise_gain_cmd =
2179                 ucode_capa.standard_phy_calibration_size + 1;
2180
2181         /**************************************************
2182          * This is still part of probe() in a sense...
2183          *
2184          * 9. Setup and register with mac80211 and debugfs
2185          **************************************************/
2186         err = iwl_mac_setup_register(priv, &ucode_capa);
2187         if (err)
2188                 goto out_unbind;
2189
2190         err = iwl_dbgfs_register(priv, DRV_NAME);
2191         if (err)
2192                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2193
2194         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2195                                         &iwl_attribute_group);
2196         if (err) {
2197                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2198                 goto out_unbind;
2199         }
2200
2201         /* We have our copies now, allow OS release its copies */
2202         release_firmware(ucode_raw);
2203         complete(&priv->_agn.firmware_loading_complete);
2204         return;
2205
2206  try_again:
2207         /* try next, if any */
2208         if (iwl_request_firmware(priv, false))
2209                 goto out_unbind;
2210         release_firmware(ucode_raw);
2211         return;
2212
2213  err_pci_alloc:
2214         IWL_ERR(priv, "failed to allocate pci memory\n");
2215         iwl_dealloc_ucode_pci(priv);
2216  out_unbind:
2217         complete(&priv->_agn.firmware_loading_complete);
2218         device_release_driver(&priv->pci_dev->dev);
2219         release_firmware(ucode_raw);
2220 }
2221
2222 static const char *desc_lookup_text[] = {
2223         "OK",
2224         "FAIL",
2225         "BAD_PARAM",
2226         "BAD_CHECKSUM",
2227         "NMI_INTERRUPT_WDG",
2228         "SYSASSERT",
2229         "FATAL_ERROR",
2230         "BAD_COMMAND",
2231         "HW_ERROR_TUNE_LOCK",
2232         "HW_ERROR_TEMPERATURE",
2233         "ILLEGAL_CHAN_FREQ",
2234         "VCC_NOT_STABLE",
2235         "FH_ERROR",
2236         "NMI_INTERRUPT_HOST",
2237         "NMI_INTERRUPT_ACTION_PT",
2238         "NMI_INTERRUPT_UNKNOWN",
2239         "UCODE_VERSION_MISMATCH",
2240         "HW_ERROR_ABS_LOCK",
2241         "HW_ERROR_CAL_LOCK_FAIL",
2242         "NMI_INTERRUPT_INST_ACTION_PT",
2243         "NMI_INTERRUPT_DATA_ACTION_PT",
2244         "NMI_TRM_HW_ER",
2245         "NMI_INTERRUPT_TRM",
2246         "NMI_INTERRUPT_BREAK_POINT"
2247         "DEBUG_0",
2248         "DEBUG_1",
2249         "DEBUG_2",
2250         "DEBUG_3",
2251 };
2252
2253 static struct { char *name; u8 num; } advanced_lookup[] = {
2254         { "NMI_INTERRUPT_WDG", 0x34 },
2255         { "SYSASSERT", 0x35 },
2256         { "UCODE_VERSION_MISMATCH", 0x37 },
2257         { "BAD_COMMAND", 0x38 },
2258         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2259         { "FATAL_ERROR", 0x3D },
2260         { "NMI_TRM_HW_ERR", 0x46 },
2261         { "NMI_INTERRUPT_TRM", 0x4C },
2262         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2263         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2264         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2265         { "NMI_INTERRUPT_HOST", 0x66 },
2266         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2267         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2268         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2269         { "ADVANCED_SYSASSERT", 0 },
2270 };
2271
2272 static const char *desc_lookup(u32 num)
2273 {
2274         int i;
2275         int max = ARRAY_SIZE(desc_lookup_text);
2276
2277         if (num < max)
2278                 return desc_lookup_text[num];
2279
2280         max = ARRAY_SIZE(advanced_lookup) - 1;
2281         for (i = 0; i < max; i++) {
2282                 if (advanced_lookup[i].num == num)
2283                         break;;
2284         }
2285         return advanced_lookup[i].name;
2286 }
2287
2288 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2289 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2290
2291 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2292 {
2293         u32 data2, line;
2294         u32 desc, time, count, base, data1;
2295         u32 blink1, blink2, ilink1, ilink2;
2296         u32 pc, hcmd;
2297
2298         if (priv->ucode_type == UCODE_INIT) {
2299                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2300                 if (!base)
2301                         base = priv->_agn.init_errlog_ptr;
2302         } else {
2303                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2304                 if (!base)
2305                         base = priv->_agn.inst_errlog_ptr;
2306         }
2307
2308         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2309                 IWL_ERR(priv,
2310                         "Not valid error log pointer 0x%08X for %s uCode\n",
2311                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2312                 return;
2313         }
2314
2315         count = iwl_read_targ_mem(priv, base);
2316
2317         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2318                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2319                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2320                         priv->status, count);
2321         }
2322
2323         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2324         priv->isr_stats.err_code = desc;
2325         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2326         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2327         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2328         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2329         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2330         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2331         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2332         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2333         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2334         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2335
2336         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2337                                       blink1, blink2, ilink1, ilink2);
2338
2339         IWL_ERR(priv, "Desc                                  Time       "
2340                 "data1      data2      line\n");
2341         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2342                 desc_lookup(desc), desc, time, data1, data2, line);
2343         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2344         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2345                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2346 }
2347
2348 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2349
2350 /**
2351  * iwl_print_event_log - Dump error event log to syslog
2352  *
2353  */
2354 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2355                                u32 num_events, u32 mode,
2356                                int pos, char **buf, size_t bufsz)
2357 {
2358         u32 i;
2359         u32 base;       /* SRAM byte address of event log header */
2360         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2361         u32 ptr;        /* SRAM byte address of log data */
2362         u32 ev, time, data; /* event log data */
2363         unsigned long reg_flags;
2364
2365         if (num_events == 0)
2366                 return pos;
2367
2368         if (priv->ucode_type == UCODE_INIT) {
2369                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2370                 if (!base)
2371                         base = priv->_agn.init_evtlog_ptr;
2372         } else {
2373                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2374                 if (!base)
2375                         base = priv->_agn.inst_evtlog_ptr;
2376         }
2377
2378         if (mode == 0)
2379                 event_size = 2 * sizeof(u32);
2380         else
2381                 event_size = 3 * sizeof(u32);
2382
2383         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2384
2385         /* Make sure device is powered up for SRAM reads */
2386         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2387         iwl_grab_nic_access(priv);
2388
2389         /* Set starting address; reads will auto-increment */
2390         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2391         rmb();
2392
2393         /* "time" is actually "data" for mode 0 (no timestamp).
2394         * place event id # at far right for easier visual parsing. */
2395         for (i = 0; i < num_events; i++) {
2396                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2397                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2398                 if (mode == 0) {
2399                         /* data, ev */
2400                         if (bufsz) {
2401                                 pos += scnprintf(*buf + pos, bufsz - pos,
2402                                                 "EVT_LOG:0x%08x:%04u\n",
2403                                                 time, ev);
2404                         } else {
2405                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2406                                         time, ev);
2407                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2408                                         time, ev);
2409                         }
2410                 } else {
2411                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2412                         if (bufsz) {
2413                                 pos += scnprintf(*buf + pos, bufsz - pos,
2414                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2415                                                  time, data, ev);
2416                         } else {
2417                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2418                                         time, data, ev);
2419                                 trace_iwlwifi_dev_ucode_event(priv, time,
2420                                         data, ev);
2421                         }
2422                 }
2423         }
2424
2425         /* Allow device to power down */
2426         iwl_release_nic_access(priv);
2427         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2428         return pos;
2429 }
2430
2431 /**
2432  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2433  */
2434 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2435                                     u32 num_wraps, u32 next_entry,
2436                                     u32 size, u32 mode,
2437                                     int pos, char **buf, size_t bufsz)
2438 {
2439         /*
2440          * display the newest DEFAULT_LOG_ENTRIES entries
2441          * i.e the entries just before the next ont that uCode would fill.
2442          */
2443         if (num_wraps) {
2444                 if (next_entry < size) {
2445                         pos = iwl_print_event_log(priv,
2446                                                 capacity - (size - next_entry),
2447                                                 size - next_entry, mode,
2448                                                 pos, buf, bufsz);
2449                         pos = iwl_print_event_log(priv, 0,
2450                                                   next_entry, mode,
2451                                                   pos, buf, bufsz);
2452                 } else
2453                         pos = iwl_print_event_log(priv, next_entry - size,
2454                                                   size, mode, pos, buf, bufsz);
2455         } else {
2456                 if (next_entry < size) {
2457                         pos = iwl_print_event_log(priv, 0, next_entry,
2458                                                   mode, pos, buf, bufsz);
2459                 } else {
2460                         pos = iwl_print_event_log(priv, next_entry - size,
2461                                                   size, mode, pos, buf, bufsz);
2462                 }
2463         }
2464         return pos;
2465 }
2466
2467 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2468
2469 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2470                             char **buf, bool display)
2471 {
2472         u32 base;       /* SRAM byte address of event log header */
2473         u32 capacity;   /* event log capacity in # entries */
2474         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2475         u32 num_wraps;  /* # times uCode wrapped to top of log */
2476         u32 next_entry; /* index of next entry to be written by uCode */
2477         u32 size;       /* # entries that we'll print */
2478         u32 logsize;
2479         int pos = 0;
2480         size_t bufsz = 0;
2481
2482         if (priv->ucode_type == UCODE_INIT) {
2483                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2484                 logsize = priv->_agn.init_evtlog_size;
2485                 if (!base)
2486                         base = priv->_agn.init_evtlog_ptr;
2487         } else {
2488                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2489                 logsize = priv->_agn.inst_evtlog_size;
2490                 if (!base)
2491                         base = priv->_agn.inst_evtlog_ptr;
2492         }
2493
2494         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2495                 IWL_ERR(priv,
2496                         "Invalid event log pointer 0x%08X for %s uCode\n",
2497                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2498                 return -EINVAL;
2499         }
2500
2501         /* event log header */
2502         capacity = iwl_read_targ_mem(priv, base);
2503         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2504         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2505         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2506
2507         if (capacity > logsize) {
2508                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2509                         capacity, logsize);
2510                 capacity = logsize;
2511         }
2512
2513         if (next_entry > logsize) {
2514                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2515                         next_entry, logsize);
2516                 next_entry = logsize;
2517         }
2518
2519         size = num_wraps ? capacity : next_entry;
2520
2521         /* bail out if nothing in log */
2522         if (size == 0) {
2523                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2524                 return pos;
2525         }
2526
2527         /* enable/disable bt channel inhibition */
2528         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2529
2530 #ifdef CONFIG_IWLWIFI_DEBUG
2531         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2532                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2533                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2534 #else
2535         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2536                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2537 #endif
2538         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2539                 size);
2540
2541 #ifdef CONFIG_IWLWIFI_DEBUG
2542         if (display) {
2543                 if (full_log)
2544                         bufsz = capacity * 48;
2545                 else
2546                         bufsz = size * 48;
2547                 *buf = kmalloc(bufsz, GFP_KERNEL);
2548                 if (!*buf)
2549                         return -ENOMEM;
2550         }
2551         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2552                 /*
2553                  * if uCode has wrapped back to top of log,
2554                  * start at the oldest entry,
2555                  * i.e the next one that uCode would fill.
2556                  */
2557                 if (num_wraps)
2558                         pos = iwl_print_event_log(priv, next_entry,
2559                                                 capacity - next_entry, mode,
2560                                                 pos, buf, bufsz);
2561                 /* (then/else) start at top of log */
2562                 pos = iwl_print_event_log(priv, 0,
2563                                           next_entry, mode, pos, buf, bufsz);
2564         } else
2565                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2566                                                 next_entry, size, mode,
2567                                                 pos, buf, bufsz);
2568 #else
2569         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2570                                         next_entry, size, mode,
2571                                         pos, buf, bufsz);
2572 #endif
2573         return pos;
2574 }
2575
2576 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2577 {
2578         struct iwl_ct_kill_config cmd;
2579         struct iwl_ct_kill_throttling_config adv_cmd;
2580         unsigned long flags;
2581         int ret = 0;
2582
2583         spin_lock_irqsave(&priv->lock, flags);
2584         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2585                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2586         spin_unlock_irqrestore(&priv->lock, flags);
2587         priv->thermal_throttle.ct_kill_toggle = false;
2588
2589         if (priv->cfg->base_params->support_ct_kill_exit) {
2590                 adv_cmd.critical_temperature_enter =
2591                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2592                 adv_cmd.critical_temperature_exit =
2593                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2594
2595                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2596                                        sizeof(adv_cmd), &adv_cmd);
2597                 if (ret)
2598                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2599                 else
2600                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2601                                         "succeeded, "
2602                                         "critical temperature enter is %d,"
2603                                         "exit is %d\n",
2604                                        priv->hw_params.ct_kill_threshold,
2605                                        priv->hw_params.ct_kill_exit_threshold);
2606         } else {
2607                 cmd.critical_temperature_R =
2608                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2609
2610                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2611                                        sizeof(cmd), &cmd);
2612                 if (ret)
2613                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2614                 else
2615                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2616                                         "succeeded, "
2617                                         "critical temperature is %d\n",
2618                                         priv->hw_params.ct_kill_threshold);
2619         }
2620 }
2621
2622 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2623 {
2624         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2625         struct iwl_host_cmd cmd = {
2626                 .id = CALIBRATION_CFG_CMD,
2627                 .len = sizeof(struct iwl_calib_cfg_cmd),
2628                 .data = &calib_cfg_cmd,
2629         };
2630
2631         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2632         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2633         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2634
2635         return iwl_send_cmd(priv, &cmd);
2636 }
2637
2638
2639 /**
2640  * iwl_alive_start - called after REPLY_ALIVE notification received
2641  *                   from protocol/runtime uCode (initialization uCode's
2642  *                   Alive gets handled by iwl_init_alive_start()).
2643  */
2644 static void iwl_alive_start(struct iwl_priv *priv)
2645 {
2646         int ret = 0;
2647         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2648
2649         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2650
2651         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2652                 /* We had an error bringing up the hardware, so take it
2653                  * all the way back down so we can try again */
2654                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2655                 goto restart;
2656         }
2657
2658         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2659          * This is a paranoid check, because we would not have gotten the
2660          * "runtime" alive if code weren't properly loaded.  */
2661         if (iwl_verify_ucode(priv)) {
2662                 /* Runtime instruction load was bad;
2663                  * take it all the way back down so we can try again */
2664                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2665                 goto restart;
2666         }
2667
2668         ret = priv->cfg->ops->lib->alive_notify(priv);
2669         if (ret) {
2670                 IWL_WARN(priv,
2671                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2672                 goto restart;
2673         }
2674
2675
2676         /* After the ALIVE response, we can send host commands to the uCode */
2677         set_bit(STATUS_ALIVE, &priv->status);
2678
2679         /* Enable watchdog to monitor the driver tx queues */
2680         iwl_setup_watchdog(priv);
2681
2682         if (iwl_is_rfkill(priv))
2683                 return;
2684
2685         /* download priority table before any calibration request */
2686         if (priv->cfg->bt_params &&
2687             priv->cfg->bt_params->advanced_bt_coexist) {
2688                 /* Configure Bluetooth device coexistence support */
2689                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2690                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2691                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2692                 priv->cfg->ops->hcmd->send_bt_config(priv);
2693                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2694                 iwlagn_send_prio_tbl(priv);
2695
2696                 /* FIXME: w/a to force change uCode BT state machine */
2697                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2698                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2699                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2700                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2701         }
2702         if (priv->hw_params.calib_rt_cfg)
2703                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2704
2705         ieee80211_wake_queues(priv->hw);
2706
2707         priv->active_rate = IWL_RATES_MASK;
2708
2709         /* Configure Tx antenna selection based on H/W config */
2710         if (priv->cfg->ops->hcmd->set_tx_ant)
2711                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2712
2713         if (iwl_is_associated_ctx(ctx)) {
2714                 struct iwl_rxon_cmd *active_rxon =
2715                                 (struct iwl_rxon_cmd *)&ctx->active;
2716                 /* apply any changes in staging */
2717                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2718                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2719         } else {
2720                 struct iwl_rxon_context *tmp;
2721                 /* Initialize our rx_config data */
2722                 for_each_context(priv, tmp)
2723                         iwl_connection_init_rx_config(priv, tmp);
2724
2725                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2726                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2727         }
2728
2729         if (priv->cfg->bt_params &&
2730             !priv->cfg->bt_params->advanced_bt_coexist) {
2731                 /* Configure Bluetooth device coexistence support */
2732                 priv->cfg->ops->hcmd->send_bt_config(priv);
2733         }
2734
2735         iwl_reset_run_time_calib(priv);
2736
2737         set_bit(STATUS_READY, &priv->status);
2738
2739         /* Configure the adapter for unassociated operation */
2740         iwlcore_commit_rxon(priv, ctx);
2741
2742         /* At this point, the NIC is initialized and operational */
2743         iwl_rf_kill_ct_config(priv);
2744
2745         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2746         wake_up_interruptible(&priv->wait_command_queue);
2747
2748         iwl_power_update_mode(priv, true);
2749         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2750
2751
2752         return;
2753
2754  restart:
2755         queue_work(priv->workqueue, &priv->restart);
2756 }
2757
2758 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2759
2760 static void __iwl_down(struct iwl_priv *priv)
2761 {
2762         unsigned long flags;
2763         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2764
2765         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2766
2767         iwl_scan_cancel_timeout(priv, 200);
2768
2769         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2770
2771         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2772          * to prevent rearm timer */
2773         del_timer_sync(&priv->watchdog);
2774
2775         iwl_clear_ucode_stations(priv, NULL);
2776         iwl_dealloc_bcast_stations(priv);
2777         iwl_clear_driver_stations(priv);
2778
2779         /* reset BT coex data */
2780         priv->bt_status = 0;
2781         if (priv->cfg->bt_params)
2782                 priv->bt_traffic_load =
2783                          priv->cfg->bt_params->bt_init_traffic_load;
2784         else
2785                 priv->bt_traffic_load = 0;
2786         priv->bt_sco_active = false;
2787         priv->bt_full_concurrent = false;
2788         priv->bt_ci_compliance = 0;
2789
2790         /* Unblock any waiting calls */
2791         wake_up_interruptible_all(&priv->wait_command_queue);
2792
2793         /* Wipe out the EXIT_PENDING status bit if we are not actually
2794          * exiting the module */
2795         if (!exit_pending)
2796                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2797
2798         /* stop and reset the on-board processor */
2799         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2800
2801         /* tell the device to stop sending interrupts */
2802         spin_lock_irqsave(&priv->lock, flags);
2803         iwl_disable_interrupts(priv);
2804         spin_unlock_irqrestore(&priv->lock, flags);
2805         iwl_synchronize_irq(priv);
2806
2807         if (priv->mac80211_registered)
2808                 ieee80211_stop_queues(priv->hw);
2809
2810         /* If we have not previously called iwl_init() then
2811          * clear all bits but the RF Kill bit and return */
2812         if (!iwl_is_init(priv)) {
2813                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2814                                         STATUS_RF_KILL_HW |
2815                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2816                                         STATUS_GEO_CONFIGURED |
2817                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2818                                         STATUS_EXIT_PENDING;
2819                 goto exit;
2820         }
2821
2822         /* ...otherwise clear out all the status bits but the RF Kill
2823          * bit and continue taking the NIC down. */
2824         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2825                                 STATUS_RF_KILL_HW |
2826                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2827                                 STATUS_GEO_CONFIGURED |
2828                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2829                                 STATUS_FW_ERROR |
2830                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2831                                 STATUS_EXIT_PENDING;
2832
2833         /* device going down, Stop using ICT table */
2834         if (priv->cfg->ops->lib->isr_ops.disable)
2835                 priv->cfg->ops->lib->isr_ops.disable(priv);
2836
2837         iwlagn_txq_ctx_stop(priv);
2838         iwlagn_rxq_stop(priv);
2839
2840         /* Power-down device's busmaster DMA clocks */
2841         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2842         udelay(5);
2843
2844         /* Make sure (redundant) we've released our request to stay awake */
2845         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2846
2847         /* Stop the device, and put it in low power state */
2848         iwl_apm_stop(priv);
2849
2850  exit:
2851         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2852
2853         dev_kfree_skb(priv->beacon_skb);
2854         priv->beacon_skb = NULL;
2855
2856         /* clear out any free frames */
2857         iwl_clear_free_frames(priv);
2858 }
2859
2860 static void iwl_down(struct iwl_priv *priv)
2861 {
2862         mutex_lock(&priv->mutex);
2863         __iwl_down(priv);
2864         mutex_unlock(&priv->mutex);
2865
2866         iwl_cancel_deferred_work(priv);
2867 }
2868
2869 #define HW_READY_TIMEOUT (50)
2870
2871 static int iwl_set_hw_ready(struct iwl_priv *priv)
2872 {
2873         int ret = 0;
2874
2875         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2876                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2877
2878         /* See if we got it */
2879         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2880                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2881                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2882                                 HW_READY_TIMEOUT);
2883         if (ret != -ETIMEDOUT)
2884                 priv->hw_ready = true;
2885         else
2886                 priv->hw_ready = false;
2887
2888         IWL_DEBUG_INFO(priv, "hardware %s\n",
2889                       (priv->hw_ready == 1) ? "ready" : "not ready");
2890         return ret;
2891 }
2892
2893 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2894 {
2895         int ret = 0;
2896
2897         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2898
2899         ret = iwl_set_hw_ready(priv);
2900         if (priv->hw_ready)
2901                 return ret;
2902
2903         /* If HW is not ready, prepare the conditions to check again */
2904         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2905                         CSR_HW_IF_CONFIG_REG_PREPARE);
2906
2907         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2908                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2909                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2910
2911         /* HW should be ready by now, check again. */
2912         if (ret != -ETIMEDOUT)
2913                 iwl_set_hw_ready(priv);
2914
2915         return ret;
2916 }
2917
2918 #define MAX_HW_RESTARTS 5
2919
2920 static int __iwl_up(struct iwl_priv *priv)
2921 {
2922         struct iwl_rxon_context *ctx;
2923         int i;
2924         int ret;
2925
2926         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2927                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2928                 return -EIO;
2929         }
2930
2931         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2932                 IWL_ERR(priv, "ucode not available for device bringup\n");
2933                 return -EIO;
2934         }
2935
2936         for_each_context(priv, ctx) {
2937                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2938                 if (ret) {
2939                         iwl_dealloc_bcast_stations(priv);
2940                         return ret;
2941                 }
2942         }
2943
2944         iwl_prepare_card_hw(priv);
2945
2946         if (!priv->hw_ready) {
2947                 IWL_WARN(priv, "Exit HW not ready\n");
2948                 return -EIO;
2949         }
2950
2951         /* If platform's RF_KILL switch is NOT set to KILL */
2952         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2953                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2954         else
2955                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2956
2957         if (iwl_is_rfkill(priv)) {
2958                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2959
2960                 iwl_enable_interrupts(priv);
2961                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2962                 return 0;
2963         }
2964
2965         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2966
2967         /* must be initialised before iwl_hw_nic_init */
2968         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2969                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2970         else
2971                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2972
2973         ret = iwlagn_hw_nic_init(priv);
2974         if (ret) {
2975                 IWL_ERR(priv, "Unable to init nic\n");
2976                 return ret;
2977         }
2978
2979         /* make sure rfkill handshake bits are cleared */
2980         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2981         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2982                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2983
2984         /* clear (again), then enable host interrupts */
2985         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2986         iwl_enable_interrupts(priv);
2987
2988         /* really make sure rfkill handshake bits are cleared */
2989         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2990         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2991
2992         /* Copy original ucode data image from disk into backup cache.
2993          * This will be used to initialize the on-board processor's
2994          * data SRAM for a clean start when the runtime program first loads. */
2995         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2996                priv->ucode_data.len);
2997
2998         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2999
3000                 /* load bootstrap state machine,
3001                  * load bootstrap program into processor's memory,
3002                  * prepare to load the "initialize" uCode */
3003                 ret = priv->cfg->ops->lib->load_ucode(priv);
3004
3005                 if (ret) {
3006                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3007                                 ret);
3008                         continue;
3009                 }
3010
3011                 /* start card; "initialize" will load runtime ucode */
3012                 iwl_nic_start(priv);
3013
3014                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3015
3016                 return 0;
3017         }
3018
3019         set_bit(STATUS_EXIT_PENDING, &priv->status);
3020         __iwl_down(priv);
3021         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3022
3023         /* tried to restart and config the device for as long as our
3024          * patience could withstand */
3025         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3026         return -EIO;
3027 }
3028
3029
3030 /*****************************************************************************
3031  *
3032  * Workqueue callbacks
3033  *
3034  *****************************************************************************/
3035
3036 static void iwl_bg_init_alive_start(struct work_struct *data)
3037 {
3038         struct iwl_priv *priv =
3039             container_of(data, struct iwl_priv, init_alive_start.work);
3040
3041         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3042                 return;
3043
3044         mutex_lock(&priv->mutex);
3045         priv->cfg->ops->lib->init_alive_start(priv);
3046         mutex_unlock(&priv->mutex);
3047 }
3048
3049 static void iwl_bg_alive_start(struct work_struct *data)
3050 {
3051         struct iwl_priv *priv =
3052             container_of(data, struct iwl_priv, alive_start.work);
3053
3054         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3055                 return;
3056
3057         /* enable dram interrupt */
3058         if (priv->cfg->ops->lib->isr_ops.reset)
3059                 priv->cfg->ops->lib->isr_ops.reset(priv);
3060
3061         mutex_lock(&priv->mutex);
3062         iwl_alive_start(priv);
3063         mutex_unlock(&priv->mutex);
3064 }
3065
3066 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3067 {
3068         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3069                         run_time_calib_work);
3070
3071         mutex_lock(&priv->mutex);
3072
3073         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3074             test_bit(STATUS_SCANNING, &priv->status)) {
3075                 mutex_unlock(&priv->mutex);
3076                 return;
3077         }
3078
3079         if (priv->start_calib) {
3080                 if (priv->cfg->bt_params &&
3081                     priv->cfg->bt_params->bt_statistics) {
3082                         iwl_chain_noise_calibration(priv,
3083                                         (void *)&priv->_agn.statistics_bt);
3084                         iwl_sensitivity_calibration(priv,
3085                                         (void *)&priv->_agn.statistics_bt);
3086                 } else {
3087                         iwl_chain_noise_calibration(priv,
3088                                         (void *)&priv->_agn.statistics);
3089                         iwl_sensitivity_calibration(priv,
3090                                         (void *)&priv->_agn.statistics);
3091                 }
3092         }
3093
3094         mutex_unlock(&priv->mutex);
3095 }
3096
3097 static void iwl_bg_restart(struct work_struct *data)
3098 {
3099         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3100
3101         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3102                 return;
3103
3104         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3105                 struct iwl_rxon_context *ctx;
3106                 bool bt_sco, bt_full_concurrent;
3107                 u8 bt_ci_compliance;
3108                 u8 bt_load;
3109                 u8 bt_status;
3110
3111                 mutex_lock(&priv->mutex);
3112                 for_each_context(priv, ctx)
3113                         ctx->vif = NULL;
3114                 priv->is_open = 0;
3115
3116                 /*
3117                  * __iwl_down() will clear the BT status variables,
3118                  * which is correct, but when we restart we really
3119                  * want to keep them so restore them afterwards.
3120                  *
3121                  * The restart process will later pick them up and
3122                  * re-configure the hw when we reconfigure the BT
3123                  * command.
3124                  */
3125                 bt_sco = priv->bt_sco_active;
3126                 bt_full_concurrent = priv->bt_full_concurrent;
3127                 bt_ci_compliance = priv->bt_ci_compliance;
3128                 bt_load = priv->bt_traffic_load;
3129                 bt_status = priv->bt_status;
3130
3131                 __iwl_down(priv);
3132
3133                 priv->bt_sco_active = bt_sco;
3134                 priv->bt_full_concurrent = bt_full_concurrent;
3135                 priv->bt_ci_compliance = bt_ci_compliance;
3136                 priv->bt_traffic_load = bt_load;
3137                 priv->bt_status = bt_status;
3138
3139                 mutex_unlock(&priv->mutex);
3140                 iwl_cancel_deferred_work(priv);
3141                 ieee80211_restart_hw(priv->hw);
3142         } else {
3143                 iwl_down(priv);
3144
3145                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3146                         return;
3147
3148                 mutex_lock(&priv->mutex);
3149                 __iwl_up(priv);
3150                 mutex_unlock(&priv->mutex);
3151         }
3152 }
3153
3154 static void iwl_bg_rx_replenish(struct work_struct *data)
3155 {
3156         struct iwl_priv *priv =
3157             container_of(data, struct iwl_priv, rx_replenish);
3158
3159         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3160                 return;
3161
3162         mutex_lock(&priv->mutex);
3163         iwlagn_rx_replenish(priv);
3164         mutex_unlock(&priv->mutex);
3165 }
3166
3167 /*****************************************************************************
3168  *
3169  * mac80211 entry point functions
3170  *
3171  *****************************************************************************/
3172
3173 #define UCODE_READY_TIMEOUT     (4 * HZ)
3174
3175 /*
3176  * Not a mac80211 entry point function, but it fits in with all the
3177  * other mac80211 functions grouped here.
3178  */
3179 static int iwl_mac_setup_register(struct iwl_priv *priv,
3180                                   struct iwlagn_ucode_capabilities *capa)
3181 {
3182         int ret;
3183         struct ieee80211_hw *hw = priv->hw;
3184         struct iwl_rxon_context *ctx;
3185
3186         hw->rate_control_algorithm = "iwl-agn-rs";
3187
3188         /* Tell mac80211 our characteristics */
3189         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3190                     IEEE80211_HW_AMPDU_AGGREGATION |
3191                     IEEE80211_HW_NEED_DTIM_PERIOD |
3192                     IEEE80211_HW_SPECTRUM_MGMT |
3193                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3194
3195         if (!priv->cfg->base_params->broken_powersave)
3196                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3197                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3198
3199         if (priv->cfg->sku & IWL_SKU_N)
3200                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3201                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3202
3203         hw->sta_data_size = sizeof(struct iwl_station_priv);
3204         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3205
3206         for_each_context(priv, ctx) {
3207                 hw->wiphy->interface_modes |= ctx->interface_modes;
3208                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3209         }
3210
3211         hw->wiphy->max_remain_on_channel_duration = 1000;
3212
3213         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3214                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3215
3216         /*
3217          * For now, disable PS by default because it affects
3218          * RX performance significantly.
3219          */
3220         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3221
3222         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3223         /* we create the 802.11 header and a zero-length SSID element */
3224         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3225
3226         /* Default value; 4 EDCA QOS priorities */
3227         hw->queues = 4;
3228
3229         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3230
3231         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3232                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3233                         &priv->bands[IEEE80211_BAND_2GHZ];
3234         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3235                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3236                         &priv->bands[IEEE80211_BAND_5GHZ];
3237
3238         iwl_leds_init(priv);
3239
3240         ret = ieee80211_register_hw(priv->hw);
3241         if (ret) {
3242                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3243                 return ret;
3244         }
3245         priv->mac80211_registered = 1;
3246
3247         return 0;
3248 }
3249
3250
3251 int iwlagn_mac_start(struct ieee80211_hw *hw)
3252 {
3253         struct iwl_priv *priv = hw->priv;
3254         int ret;
3255
3256         IWL_DEBUG_MAC80211(priv, "enter\n");
3257
3258         /* we should be verifying the device is ready to be opened */
3259         mutex_lock(&priv->mutex);
3260         ret = __iwl_up(priv);
3261         mutex_unlock(&priv->mutex);
3262
3263         if (ret)
3264                 return ret;
3265
3266         if (iwl_is_rfkill(priv))
3267                 goto out;
3268
3269         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3270
3271         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3272          * mac80211 will not be run successfully. */
3273         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3274                         test_bit(STATUS_READY, &priv->status),
3275                         UCODE_READY_TIMEOUT);
3276         if (!ret) {
3277                 if (!test_bit(STATUS_READY, &priv->status)) {
3278                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3279                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3280                         return -ETIMEDOUT;
3281                 }
3282         }
3283
3284         iwlagn_led_enable(priv);
3285
3286 out:
3287         priv->is_open = 1;
3288         IWL_DEBUG_MAC80211(priv, "leave\n");
3289         return 0;
3290 }
3291
3292 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3293 {
3294         struct iwl_priv *priv = hw->priv;
3295
3296         IWL_DEBUG_MAC80211(priv, "enter\n");
3297
3298         if (!priv->is_open)
3299                 return;
3300
3301         priv->is_open = 0;
3302
3303         iwl_down(priv);
3304
3305         flush_workqueue(priv->workqueue);
3306
3307         /* User space software may expect getting rfkill changes
3308          * even if interface is down */
3309         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3310         iwl_enable_rfkill_int(priv);
3311
3312         IWL_DEBUG_MAC80211(priv, "leave\n");
3313 }
3314
3315 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3316 {
3317         struct iwl_priv *priv = hw->priv;
3318
3319         IWL_DEBUG_MACDUMP(priv, "enter\n");
3320
3321         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3322                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3323
3324         if (iwlagn_tx_skb(priv, skb))
3325                 dev_kfree_skb_any(skb);
3326
3327         IWL_DEBUG_MACDUMP(priv, "leave\n");
3328         return NETDEV_TX_OK;
3329 }
3330
3331 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3332                                 struct ieee80211_vif *vif,
3333                                 struct ieee80211_key_conf *keyconf,
3334                                 struct ieee80211_sta *sta,
3335                                 u32 iv32, u16 *phase1key)
3336 {
3337         struct iwl_priv *priv = hw->priv;
3338         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3339
3340         IWL_DEBUG_MAC80211(priv, "enter\n");
3341
3342         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3343                             iv32, phase1key);
3344
3345         IWL_DEBUG_MAC80211(priv, "leave\n");
3346 }
3347
3348 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3349                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3350                        struct ieee80211_key_conf *key)
3351 {
3352         struct iwl_priv *priv = hw->priv;
3353         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3354         struct iwl_rxon_context *ctx = vif_priv->ctx;
3355         int ret;
3356         u8 sta_id;
3357         bool is_default_wep_key = false;
3358
3359         IWL_DEBUG_MAC80211(priv, "enter\n");
3360
3361         if (priv->cfg->mod_params->sw_crypto) {
3362                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3363                 return -EOPNOTSUPP;
3364         }
3365
3366         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3367         if (sta_id == IWL_INVALID_STATION)
3368                 return -EINVAL;
3369
3370         mutex_lock(&priv->mutex);
3371         iwl_scan_cancel_timeout(priv, 100);
3372
3373         /*
3374          * If we are getting WEP group key and we didn't receive any key mapping
3375          * so far, we are in legacy wep mode (group key only), otherwise we are
3376          * in 1X mode.
3377          * In legacy wep mode, we use another host command to the uCode.
3378          */
3379         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3380              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3381             !sta) {
3382                 if (cmd == SET_KEY)
3383                         is_default_wep_key = !ctx->key_mapping_keys;
3384                 else
3385                         is_default_wep_key =
3386                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3387         }
3388
3389         switch (cmd) {
3390         case SET_KEY:
3391                 if (is_default_wep_key)
3392                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3393                 else
3394                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3395                                                   key, sta_id);
3396
3397                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3398                 break;
3399         case DISABLE_KEY:
3400                 if (is_default_wep_key)
3401                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3402                 else
3403                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3404
3405                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3406                 break;
3407         default:
3408                 ret = -EINVAL;
3409         }
3410
3411         mutex_unlock(&priv->mutex);
3412         IWL_DEBUG_MAC80211(priv, "leave\n");
3413
3414         return ret;
3415 }
3416
3417 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3418                             struct ieee80211_vif *vif,
3419                             enum ieee80211_ampdu_mlme_action action,
3420                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3421                             u8 buf_size)
3422 {
3423         struct iwl_priv *priv = hw->priv;
3424         int ret = -EINVAL;
3425
3426         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3427                      sta->addr, tid);
3428
3429         if (!(priv->cfg->sku & IWL_SKU_N))
3430                 return -EACCES;
3431
3432         mutex_lock(&priv->mutex);
3433
3434         switch (action) {
3435         case IEEE80211_AMPDU_RX_START:
3436                 IWL_DEBUG_HT(priv, "start Rx\n");
3437                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3438                 break;
3439         case IEEE80211_AMPDU_RX_STOP:
3440                 IWL_DEBUG_HT(priv, "stop Rx\n");
3441                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3442                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3443                         ret = 0;
3444                 break;
3445         case IEEE80211_AMPDU_TX_START:
3446                 IWL_DEBUG_HT(priv, "start Tx\n");
3447                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3448                 if (ret == 0) {
3449                         priv->_agn.agg_tids_count++;
3450                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3451                                      priv->_agn.agg_tids_count);
3452                 }
3453                 break;
3454         case IEEE80211_AMPDU_TX_STOP:
3455                 IWL_DEBUG_HT(priv, "stop Tx\n");
3456                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3457                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3458                         priv->_agn.agg_tids_count--;
3459                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3460                                      priv->_agn.agg_tids_count);
3461                 }
3462                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3463                         ret = 0;
3464                 if (priv->cfg->ht_params &&
3465                     priv->cfg->ht_params->use_rts_for_aggregation) {
3466                         struct iwl_station_priv *sta_priv =
3467                                 (void *) sta->drv_priv;
3468                         /*
3469                          * switch off RTS/CTS if it was previously enabled
3470                          */
3471
3472                         sta_priv->lq_sta.lq.general_params.flags &=
3473                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3474                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3475                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3476                 }
3477                 break;
3478         case IEEE80211_AMPDU_TX_OPERATIONAL:
3479                 if (priv->cfg->ht_params &&
3480                     priv->cfg->ht_params->use_rts_for_aggregation) {
3481                         struct iwl_station_priv *sta_priv =
3482                                 (void *) sta->drv_priv;
3483
3484                         /*
3485                          * switch to RTS/CTS if it is the prefer protection
3486                          * method for HT traffic
3487                          */
3488
3489                         sta_priv->lq_sta.lq.general_params.flags |=
3490                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3491                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3492                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3493                 }
3494                 ret = 0;
3495                 break;
3496         }
3497         mutex_unlock(&priv->mutex);
3498
3499         return ret;
3500 }
3501
3502 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3503                        struct ieee80211_vif *vif,
3504                        struct ieee80211_sta *sta)
3505 {
3506         struct iwl_priv *priv = hw->priv;
3507         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3508         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3509         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3510         int ret;
3511         u8 sta_id;
3512
3513         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3514                         sta->addr);
3515         mutex_lock(&priv->mutex);
3516         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3517                         sta->addr);
3518         sta_priv->common.sta_id = IWL_INVALID_STATION;
3519
3520         atomic_set(&sta_priv->pending_frames, 0);
3521         if (vif->type == NL80211_IFTYPE_AP)
3522                 sta_priv->client = true;
3523
3524         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3525                                      is_ap, sta, &sta_id);
3526         if (ret) {
3527                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3528                         sta->addr, ret);
3529                 /* Should we return success if return code is EEXIST ? */
3530                 mutex_unlock(&priv->mutex);
3531                 return ret;
3532         }
3533
3534         sta_priv->common.sta_id = sta_id;
3535
3536         /* Initialize rate scaling */
3537         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3538                        sta->addr);
3539         iwl_rs_rate_init(priv, sta, sta_id);
3540         mutex_unlock(&priv->mutex);
3541
3542         return 0;
3543 }
3544
3545 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3546                                struct ieee80211_channel_switch *ch_switch)
3547 {
3548         struct iwl_priv *priv = hw->priv;
3549         const struct iwl_channel_info *ch_info;
3550         struct ieee80211_conf *conf = &hw->conf;
3551         struct ieee80211_channel *channel = ch_switch->channel;
3552         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3553         /*
3554          * MULTI-FIXME
3555          * When we add support for multiple interfaces, we need to
3556          * revisit this. The channel switch command in the device
3557          * only affects the BSS context, but what does that really
3558          * mean? And what if we get a CSA on the second interface?
3559          * This needs a lot of work.
3560          */
3561         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3562         u16 ch;
3563         unsigned long flags = 0;
3564
3565         IWL_DEBUG_MAC80211(priv, "enter\n");
3566
3567         if (iwl_is_rfkill(priv))
3568                 goto out_exit;
3569
3570         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3571             test_bit(STATUS_SCANNING, &priv->status))
3572                 goto out_exit;
3573
3574         if (!iwl_is_associated_ctx(ctx))
3575                 goto out_exit;
3576
3577         /* channel switch in progress */
3578         if (priv->switch_rxon.switch_in_progress == true)
3579                 goto out_exit;
3580
3581         mutex_lock(&priv->mutex);
3582         if (priv->cfg->ops->lib->set_channel_switch) {
3583
3584                 ch = channel->hw_value;
3585                 if (le16_to_cpu(ctx->active.channel) != ch) {
3586                         ch_info = iwl_get_channel_info(priv,
3587                                                        channel->band,
3588                                                        ch);
3589                         if (!is_channel_valid(ch_info)) {
3590                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3591                                 goto out;
3592                         }
3593                         spin_lock_irqsave(&priv->lock, flags);
3594
3595                         priv->current_ht_config.smps = conf->smps_mode;
3596
3597                         /* Configure HT40 channels */
3598                         ctx->ht.enabled = conf_is_ht(conf);
3599                         if (ctx->ht.enabled) {
3600                                 if (conf_is_ht40_minus(conf)) {
3601                                         ctx->ht.extension_chan_offset =
3602                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3603                                         ctx->ht.is_40mhz = true;
3604                                 } else if (conf_is_ht40_plus(conf)) {
3605                                         ctx->ht.extension_chan_offset =
3606                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3607                                         ctx->ht.is_40mhz = true;
3608                                 } else {
3609                                         ctx->ht.extension_chan_offset =
3610                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3611                                         ctx->ht.is_40mhz = false;
3612                                 }
3613                         } else
3614                                 ctx->ht.is_40mhz = false;
3615
3616                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3617                                 ctx->staging.flags = 0;
3618
3619                         iwl_set_rxon_channel(priv, channel, ctx);
3620                         iwl_set_rxon_ht(priv, ht_conf);
3621                         iwl_set_flags_for_band(priv, ctx, channel->band,
3622                                                ctx->vif);
3623                         spin_unlock_irqrestore(&priv->lock, flags);
3624
3625                         iwl_set_rate(priv);
3626                         /*
3627                          * at this point, staging_rxon has the
3628                          * configuration for channel switch
3629                          */
3630                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3631                                                                     ch_switch))
3632                                 priv->switch_rxon.switch_in_progress = false;
3633                 }
3634         }
3635 out:
3636         mutex_unlock(&priv->mutex);
3637 out_exit:
3638         if (!priv->switch_rxon.switch_in_progress)
3639                 ieee80211_chswitch_done(ctx->vif, false);
3640         IWL_DEBUG_MAC80211(priv, "leave\n");
3641 }
3642
3643 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3644                              unsigned int changed_flags,
3645                              unsigned int *total_flags,
3646                              u64 multicast)
3647 {
3648         struct iwl_priv *priv = hw->priv;
3649         __le32 filter_or = 0, filter_nand = 0;
3650         struct iwl_rxon_context *ctx;
3651
3652 #define CHK(test, flag) do { \
3653         if (*total_flags & (test))              \
3654                 filter_or |= (flag);            \
3655         else                                    \
3656                 filter_nand |= (flag);          \
3657         } while (0)
3658
3659         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3660                         changed_flags, *total_flags);
3661
3662         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3663         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3664         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3665         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3666
3667 #undef CHK
3668
3669         mutex_lock(&priv->mutex);
3670
3671         for_each_context(priv, ctx) {
3672                 ctx->staging.filter_flags &= ~filter_nand;
3673                 ctx->staging.filter_flags |= filter_or;
3674
3675                 /*
3676                  * Not committing directly because hardware can perform a scan,
3677                  * but we'll eventually commit the filter flags change anyway.
3678                  */
3679         }
3680
3681         mutex_unlock(&priv->mutex);
3682
3683         /*
3684          * Receiving all multicast frames is always enabled by the
3685          * default flags setup in iwl_connection_init_rx_config()
3686          * since we currently do not support programming multicast
3687          * filters into the device.
3688          */
3689         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3690                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3691 }
3692
3693 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3694 {
3695         struct iwl_priv *priv = hw->priv;
3696
3697         mutex_lock(&priv->mutex);
3698         IWL_DEBUG_MAC80211(priv, "enter\n");
3699
3700         /* do not support "flush" */
3701         if (!priv->cfg->ops->lib->txfifo_flush)
3702                 goto done;
3703
3704         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3705                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3706                 goto done;
3707         }
3708         if (iwl_is_rfkill(priv)) {
3709                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3710                 goto done;
3711         }
3712
3713         /*
3714          * mac80211 will not push any more frames for transmit
3715          * until the flush is completed
3716          */
3717         if (drop) {
3718                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3719                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3720                         IWL_ERR(priv, "flush request fail\n");
3721                         goto done;
3722                 }
3723         }
3724         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3725         iwlagn_wait_tx_queue_empty(priv);
3726 done:
3727         mutex_unlock(&priv->mutex);
3728         IWL_DEBUG_MAC80211(priv, "leave\n");
3729 }
3730
3731 static void iwlagn_disable_roc(struct iwl_priv *priv)
3732 {
3733         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3734         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3735
3736         lockdep_assert_held(&priv->mutex);
3737
3738         if (!ctx->is_active)
3739                 return;
3740
3741         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3742         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3743         iwl_set_rxon_channel(priv, chan, ctx);
3744         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3745
3746         priv->_agn.hw_roc_channel = NULL;
3747
3748         iwlagn_commit_rxon(priv, ctx);
3749
3750         ctx->is_active = false;
3751 }
3752
3753 static void iwlagn_bg_roc_done(struct work_struct *work)
3754 {
3755         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3756                                              _agn.hw_roc_work.work);
3757
3758         mutex_lock(&priv->mutex);
3759         ieee80211_remain_on_channel_expired(priv->hw);
3760         iwlagn_disable_roc(priv);
3761         mutex_unlock(&priv->mutex);
3762 }
3763
3764 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3765                                      struct ieee80211_channel *channel,
3766                                      enum nl80211_channel_type channel_type,
3767                                      int duration)
3768 {
3769         struct iwl_priv *priv = hw->priv;
3770         int err = 0;
3771
3772         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3773                 return -EOPNOTSUPP;
3774
3775         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3776                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3777                 return -EOPNOTSUPP;
3778
3779         mutex_lock(&priv->mutex);
3780
3781         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3782             test_bit(STATUS_SCAN_HW, &priv->status)) {
3783                 err = -EBUSY;
3784                 goto out;
3785         }
3786
3787         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3788         priv->_agn.hw_roc_channel = channel;
3789         priv->_agn.hw_roc_chantype = channel_type;
3790         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3791         iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3792         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3793                            msecs_to_jiffies(duration + 20));
3794
3795         msleep(20);
3796         ieee80211_ready_on_channel(priv->hw);
3797
3798  out:
3799         mutex_unlock(&priv->mutex);
3800
3801         return err;
3802 }
3803
3804 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3805 {
3806         struct iwl_priv *priv = hw->priv;
3807
3808         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3809                 return -EOPNOTSUPP;
3810
3811         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3812
3813         mutex_lock(&priv->mutex);
3814         iwlagn_disable_roc(priv);
3815         mutex_unlock(&priv->mutex);
3816
3817         return 0;
3818 }
3819
3820 /*****************************************************************************
3821  *
3822  * driver setup and teardown
3823  *
3824  *****************************************************************************/
3825
3826 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3827 {
3828         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3829
3830         init_waitqueue_head(&priv->wait_command_queue);
3831
3832         INIT_WORK(&priv->restart, iwl_bg_restart);
3833         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3834         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3835         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3836         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3837         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3838         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3839         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3840         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3841         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3842
3843         iwl_setup_scan_deferred_work(priv);
3844
3845         if (priv->cfg->ops->lib->setup_deferred_work)
3846                 priv->cfg->ops->lib->setup_deferred_work(priv);
3847
3848         init_timer(&priv->statistics_periodic);
3849         priv->statistics_periodic.data = (unsigned long)priv;
3850         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3851
3852         init_timer(&priv->ucode_trace);
3853         priv->ucode_trace.data = (unsigned long)priv;
3854         priv->ucode_trace.function = iwl_bg_ucode_trace;
3855
3856         init_timer(&priv->watchdog);
3857         priv->watchdog.data = (unsigned long)priv;
3858         priv->watchdog.function = iwl_bg_watchdog;
3859
3860         if (!priv->cfg->base_params->use_isr_legacy)
3861                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3862                         iwl_irq_tasklet, (unsigned long)priv);
3863         else
3864                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3865                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3866 }
3867
3868 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3869 {
3870         if (priv->cfg->ops->lib->cancel_deferred_work)
3871                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3872
3873         cancel_delayed_work_sync(&priv->init_alive_start);
3874         cancel_delayed_work(&priv->alive_start);
3875         cancel_work_sync(&priv->run_time_calib_work);
3876         cancel_work_sync(&priv->beacon_update);
3877
3878         iwl_cancel_scan_deferred_work(priv);
3879
3880         cancel_work_sync(&priv->bt_full_concurrency);
3881         cancel_work_sync(&priv->bt_runtime_config);
3882
3883         del_timer_sync(&priv->statistics_periodic);
3884         del_timer_sync(&priv->ucode_trace);
3885 }
3886
3887 static void iwl_init_hw_rates(struct iwl_priv *priv,
3888                               struct ieee80211_rate *rates)
3889 {
3890         int i;
3891
3892         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3893                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3894                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3895                 rates[i].hw_value_short = i;
3896                 rates[i].flags = 0;
3897                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3898                         /*
3899                          * If CCK != 1M then set short preamble rate flag.
3900                          */
3901                         rates[i].flags |=
3902                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3903                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3904                 }
3905         }
3906 }
3907
3908 static int iwl_init_drv(struct iwl_priv *priv)
3909 {
3910         int ret;
3911
3912         spin_lock_init(&priv->sta_lock);
3913         spin_lock_init(&priv->hcmd_lock);
3914
3915         INIT_LIST_HEAD(&priv->free_frames);
3916
3917         mutex_init(&priv->mutex);
3918         mutex_init(&priv->sync_cmd_mutex);
3919
3920         priv->ieee_channels = NULL;
3921         priv->ieee_rates = NULL;
3922         priv->band = IEEE80211_BAND_2GHZ;
3923
3924         priv->iw_mode = NL80211_IFTYPE_STATION;
3925         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3926         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3927         priv->_agn.agg_tids_count = 0;
3928
3929         /* initialize force reset */
3930         priv->force_reset[IWL_RF_RESET].reset_duration =
3931                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3932         priv->force_reset[IWL_FW_RESET].reset_duration =
3933                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3934
3935         /* Choose which receivers/antennas to use */
3936         if (priv->cfg->ops->hcmd->set_rxon_chain)
3937                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3938                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3939
3940         iwl_init_scan_params(priv);
3941
3942         /* init bt coex */
3943         if (priv->cfg->bt_params &&
3944             priv->cfg->bt_params->advanced_bt_coexist) {
3945                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3946                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3947                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3948                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3949                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3950                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3951         }
3952
3953         /* Set the tx_power_user_lmt to the lowest power level
3954          * this value will get overwritten by channel max power avg
3955          * from eeprom */
3956         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3957         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3958
3959         ret = iwl_init_channel_map(priv);
3960         if (ret) {
3961                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3962                 goto err;
3963         }
3964
3965         ret = iwlcore_init_geos(priv);
3966         if (ret) {
3967                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3968                 goto err_free_channel_map;
3969         }
3970         iwl_init_hw_rates(priv, priv->ieee_rates);
3971
3972         return 0;
3973
3974 err_free_channel_map:
3975         iwl_free_channel_map(priv);
3976 err:
3977         return ret;
3978 }
3979
3980 static void iwl_uninit_drv(struct iwl_priv *priv)
3981 {
3982         iwl_calib_free_results(priv);
3983         iwlcore_free_geos(priv);
3984         iwl_free_channel_map(priv);
3985         kfree(priv->scan_cmd);
3986 }
3987
3988 #ifdef CONFIG_IWL5000
3989 struct ieee80211_ops iwlagn_hw_ops = {
3990         .tx = iwlagn_mac_tx,
3991         .start = iwlagn_mac_start,
3992         .stop = iwlagn_mac_stop,
3993         .add_interface = iwl_mac_add_interface,
3994         .remove_interface = iwl_mac_remove_interface,
3995         .change_interface = iwl_mac_change_interface,
3996         .config = iwlagn_mac_config,
3997         .configure_filter = iwlagn_configure_filter,
3998         .set_key = iwlagn_mac_set_key,
3999         .update_tkip_key = iwlagn_mac_update_tkip_key,
4000         .conf_tx = iwl_mac_conf_tx,
4001         .bss_info_changed = iwlagn_bss_info_changed,
4002         .ampdu_action = iwlagn_mac_ampdu_action,
4003         .hw_scan = iwl_mac_hw_scan,
4004         .sta_notify = iwlagn_mac_sta_notify,
4005         .sta_add = iwlagn_mac_sta_add,
4006         .sta_remove = iwl_mac_sta_remove,
4007         .channel_switch = iwlagn_mac_channel_switch,
4008         .flush = iwlagn_mac_flush,
4009         .tx_last_beacon = iwl_mac_tx_last_beacon,
4010         .remain_on_channel = iwl_mac_remain_on_channel,
4011         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4012 };
4013 #endif
4014
4015 static void iwl_hw_detect(struct iwl_priv *priv)
4016 {
4017         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4018         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4019         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4020         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4021 }
4022
4023 static int iwl_set_hw_params(struct iwl_priv *priv)
4024 {
4025         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4026         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4027         if (priv->cfg->mod_params->amsdu_size_8K)
4028                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4029         else
4030                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4031
4032         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4033
4034         if (priv->cfg->mod_params->disable_11n)
4035                 priv->cfg->sku &= ~IWL_SKU_N;
4036
4037         /* Device-specific setup */
4038         return priv->cfg->ops->lib->set_hw_params(priv);
4039 }
4040
4041 static const u8 iwlagn_bss_ac_to_fifo[] = {
4042         IWL_TX_FIFO_VO,
4043         IWL_TX_FIFO_VI,
4044         IWL_TX_FIFO_BE,
4045         IWL_TX_FIFO_BK,
4046 };
4047
4048 static const u8 iwlagn_bss_ac_to_queue[] = {
4049         0, 1, 2, 3,
4050 };
4051
4052 static const u8 iwlagn_pan_ac_to_fifo[] = {
4053         IWL_TX_FIFO_VO_IPAN,
4054         IWL_TX_FIFO_VI_IPAN,
4055         IWL_TX_FIFO_BE_IPAN,
4056         IWL_TX_FIFO_BK_IPAN,
4057 };
4058
4059 static const u8 iwlagn_pan_ac_to_queue[] = {
4060         7, 6, 5, 4,
4061 };
4062
4063 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4064 {
4065         int err = 0, i;
4066         struct iwl_priv *priv;
4067         struct ieee80211_hw *hw;
4068         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4069         unsigned long flags;
4070         u16 pci_cmd, num_mac;
4071
4072         /************************
4073          * 1. Allocating HW data
4074          ************************/
4075
4076         /* Disabling hardware scan means that mac80211 will perform scans
4077          * "the hard way", rather than using device's scan. */
4078         if (cfg->mod_params->disable_hw_scan) {
4079                 dev_printk(KERN_DEBUG, &(pdev->dev),
4080                         "sw scan support is deprecated\n");
4081 #ifdef CONFIG_IWL5000
4082                 iwlagn_hw_ops.hw_scan = NULL;
4083 #endif
4084 #ifdef CONFIG_IWL4965
4085                 iwl4965_hw_ops.hw_scan = NULL;
4086 #endif
4087         }
4088
4089         hw = iwl_alloc_all(cfg);
4090         if (!hw) {
4091                 err = -ENOMEM;
4092                 goto out;
4093         }
4094         priv = hw->priv;
4095         /* At this point both hw and priv are allocated. */
4096
4097         /*
4098          * The default context is always valid,
4099          * more may be discovered when firmware
4100          * is loaded.
4101          */
4102         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4103
4104         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4105                 priv->contexts[i].ctxid = i;
4106
4107         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4108         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4109         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4110         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4111         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4112         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4113         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4114         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4115         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4116         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4117         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4118                 BIT(NL80211_IFTYPE_ADHOC);
4119         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4120                 BIT(NL80211_IFTYPE_STATION);
4121         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4122         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4123         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4124         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4125
4126         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4127         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4128         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4129         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4130         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4131         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4132         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4133         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4134         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4135         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4136         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4137         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4138                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4139         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4140         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4141         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4142
4143         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4144
4145         SET_IEEE80211_DEV(hw, &pdev->dev);
4146
4147         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4148         priv->cfg = cfg;
4149         priv->pci_dev = pdev;
4150         priv->inta_mask = CSR_INI_SET_MASK;
4151
4152         /* is antenna coupling more than 35dB ? */
4153         priv->bt_ant_couple_ok =
4154                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4155                 true : false;
4156
4157         /* enable/disable bt channel inhibition */
4158         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4159         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4160                        (priv->bt_ch_announce) ? "On" : "Off");
4161
4162         if (iwl_alloc_traffic_mem(priv))
4163                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4164
4165         /**************************
4166          * 2. Initializing PCI bus
4167          **************************/
4168         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4169                                 PCIE_LINK_STATE_CLKPM);
4170
4171         if (pci_enable_device(pdev)) {
4172                 err = -ENODEV;
4173                 goto out_ieee80211_free_hw;
4174         }
4175
4176         pci_set_master(pdev);
4177
4178         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4179         if (!err)
4180                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4181         if (err) {
4182                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4183                 if (!err)
4184                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4185                 /* both attempts failed: */
4186                 if (err) {
4187                         IWL_WARN(priv, "No suitable DMA available.\n");
4188                         goto out_pci_disable_device;
4189                 }
4190         }
4191
4192         err = pci_request_regions(pdev, DRV_NAME);
4193         if (err)
4194                 goto out_pci_disable_device;
4195
4196         pci_set_drvdata(pdev, priv);
4197
4198
4199         /***********************
4200          * 3. Read REV register
4201          ***********************/
4202         priv->hw_base = pci_iomap(pdev, 0, 0);
4203         if (!priv->hw_base) {
4204                 err = -ENODEV;
4205                 goto out_pci_release_regions;
4206         }
4207
4208         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4209                 (unsigned long long) pci_resource_len(pdev, 0));
4210         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4211
4212         /* these spin locks will be used in apm_ops.init and EEPROM access
4213          * we should init now
4214          */
4215         spin_lock_init(&priv->reg_lock);
4216         spin_lock_init(&priv->lock);
4217
4218         /*
4219          * stop and reset the on-board processor just in case it is in a
4220          * strange state ... like being left stranded by a primary kernel
4221          * and this is now the kdump kernel trying to start up
4222          */
4223         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4224
4225         iwl_hw_detect(priv);
4226         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4227                 priv->cfg->name, priv->hw_rev);
4228
4229         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4230          * PCI Tx retries from interfering with C3 CPU state */
4231         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4232
4233         iwl_prepare_card_hw(priv);
4234         if (!priv->hw_ready) {
4235                 IWL_WARN(priv, "Failed, HW not ready\n");
4236                 goto out_iounmap;
4237         }
4238
4239         /*****************
4240          * 4. Read EEPROM
4241          *****************/
4242         /* Read the EEPROM */
4243         err = iwl_eeprom_init(priv);
4244         if (err) {
4245                 IWL_ERR(priv, "Unable to init EEPROM\n");
4246                 goto out_iounmap;
4247         }
4248         err = iwl_eeprom_check_version(priv);
4249         if (err)
4250                 goto out_free_eeprom;
4251
4252         err = iwl_eeprom_check_sku(priv);
4253         if (err)
4254                 goto out_free_eeprom;
4255
4256         /* extract MAC Address */
4257         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4258         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4259         priv->hw->wiphy->addresses = priv->addresses;
4260         priv->hw->wiphy->n_addresses = 1;
4261         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4262         if (num_mac > 1) {
4263                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4264                        ETH_ALEN);
4265                 priv->addresses[1].addr[5]++;
4266                 priv->hw->wiphy->n_addresses++;
4267         }
4268
4269         /************************
4270          * 5. Setup HW constants
4271          ************************/
4272         if (iwl_set_hw_params(priv)) {
4273                 IWL_ERR(priv, "failed to set hw parameters\n");
4274                 goto out_free_eeprom;
4275         }
4276
4277         /*******************
4278          * 6. Setup priv
4279          *******************/
4280
4281         err = iwl_init_drv(priv);
4282         if (err)
4283                 goto out_free_eeprom;
4284         /* At this point both hw and priv are initialized. */
4285
4286         /********************
4287          * 7. Setup services
4288          ********************/
4289         spin_lock_irqsave(&priv->lock, flags);
4290         iwl_disable_interrupts(priv);
4291         spin_unlock_irqrestore(&priv->lock, flags);
4292
4293         pci_enable_msi(priv->pci_dev);
4294
4295         if (priv->cfg->ops->lib->isr_ops.alloc)
4296                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4297
4298         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4299                           IRQF_SHARED, DRV_NAME, priv);
4300         if (err) {
4301                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4302                 goto out_disable_msi;
4303         }
4304
4305         iwl_setup_deferred_work(priv);
4306         iwl_setup_rx_handlers(priv);
4307
4308         /*********************************************
4309          * 8. Enable interrupts and read RFKILL state
4310          *********************************************/
4311
4312         /* enable rfkill interrupt: hw bug w/a */
4313         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4314         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4315                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4316                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4317         }
4318
4319         iwl_enable_rfkill_int(priv);
4320
4321         /* If platform's RF_KILL switch is NOT set to KILL */
4322         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4323                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4324         else
4325                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4326
4327         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4328                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4329
4330         iwl_power_initialize(priv);
4331         iwl_tt_initialize(priv);
4332
4333         init_completion(&priv->_agn.firmware_loading_complete);
4334
4335         err = iwl_request_firmware(priv, true);
4336         if (err)
4337                 goto out_destroy_workqueue;
4338
4339         return 0;
4340
4341  out_destroy_workqueue:
4342         destroy_workqueue(priv->workqueue);
4343         priv->workqueue = NULL;
4344         free_irq(priv->pci_dev->irq, priv);
4345         if (priv->cfg->ops->lib->isr_ops.free)
4346                 priv->cfg->ops->lib->isr_ops.free(priv);
4347  out_disable_msi:
4348         pci_disable_msi(priv->pci_dev);
4349         iwl_uninit_drv(priv);
4350  out_free_eeprom:
4351         iwl_eeprom_free(priv);
4352  out_iounmap:
4353         pci_iounmap(pdev, priv->hw_base);
4354  out_pci_release_regions:
4355         pci_set_drvdata(pdev, NULL);
4356         pci_release_regions(pdev);
4357  out_pci_disable_device:
4358         pci_disable_device(pdev);
4359  out_ieee80211_free_hw:
4360         iwl_free_traffic_mem(priv);
4361         ieee80211_free_hw(priv->hw);
4362  out:
4363         return err;
4364 }
4365
4366 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4367 {
4368         struct iwl_priv *priv = pci_get_drvdata(pdev);
4369         unsigned long flags;
4370
4371         if (!priv)
4372                 return;
4373
4374         wait_for_completion(&priv->_agn.firmware_loading_complete);
4375
4376         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4377
4378         iwl_dbgfs_unregister(priv);
4379         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4380
4381         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4382          * to be called and iwl_down since we are removing the device
4383          * we need to set STATUS_EXIT_PENDING bit.
4384          */
4385         set_bit(STATUS_EXIT_PENDING, &priv->status);
4386
4387         iwl_leds_exit(priv);
4388
4389         if (priv->mac80211_registered) {
4390                 ieee80211_unregister_hw(priv->hw);
4391                 priv->mac80211_registered = 0;
4392         } else {
4393                 iwl_down(priv);
4394         }
4395
4396         /*
4397          * Make sure device is reset to low power before unloading driver.
4398          * This may be redundant with iwl_down(), but there are paths to
4399          * run iwl_down() without calling apm_ops.stop(), and there are
4400          * paths to avoid running iwl_down() at all before leaving driver.
4401          * This (inexpensive) call *makes sure* device is reset.
4402          */
4403         iwl_apm_stop(priv);
4404
4405         iwl_tt_exit(priv);
4406
4407         /* make sure we flush any pending irq or
4408          * tasklet for the driver
4409          */
4410         spin_lock_irqsave(&priv->lock, flags);
4411         iwl_disable_interrupts(priv);
4412         spin_unlock_irqrestore(&priv->lock, flags);
4413
4414         iwl_synchronize_irq(priv);
4415
4416         iwl_dealloc_ucode_pci(priv);
4417
4418         if (priv->rxq.bd)
4419                 iwlagn_rx_queue_free(priv, &priv->rxq);
4420         iwlagn_hw_txq_ctx_free(priv);
4421
4422         iwl_eeprom_free(priv);
4423
4424
4425         /*netif_stop_queue(dev); */
4426         flush_workqueue(priv->workqueue);
4427
4428         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4429          * priv->workqueue... so we can't take down the workqueue
4430          * until now... */
4431         destroy_workqueue(priv->workqueue);
4432         priv->workqueue = NULL;
4433         iwl_free_traffic_mem(priv);
4434
4435         free_irq(priv->pci_dev->irq, priv);
4436         pci_disable_msi(priv->pci_dev);
4437         pci_iounmap(pdev, priv->hw_base);
4438         pci_release_regions(pdev);
4439         pci_disable_device(pdev);
4440         pci_set_drvdata(pdev, NULL);
4441
4442         iwl_uninit_drv(priv);
4443
4444         if (priv->cfg->ops->lib->isr_ops.free)
4445                 priv->cfg->ops->lib->isr_ops.free(priv);
4446
4447         dev_kfree_skb(priv->beacon_skb);
4448
4449         ieee80211_free_hw(priv->hw);
4450 }
4451
4452
4453 /*****************************************************************************
4454  *
4455  * driver and module entry point
4456  *
4457  *****************************************************************************/
4458
4459 /* Hardware specific file defines the PCI IDs table for that hardware module */
4460 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4461 #ifdef CONFIG_IWL4965
4462         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4463         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4464 #endif /* CONFIG_IWL4965 */
4465 #ifdef CONFIG_IWL5000
4466 /* 5100 Series WiFi */
4467         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4468         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4469         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4470         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4471         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4472         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4473         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4474         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4475         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4476         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4477         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4478         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4479         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4480         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4481         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4482         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4483         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4484         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4485         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4486         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4487         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4488         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4489         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4490         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4491
4492 /* 5300 Series WiFi */
4493         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4494         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4495         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4496         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4497         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4498         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4499         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4500         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4501         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4502         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4503         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4504         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4505
4506 /* 5350 Series WiFi/WiMax */
4507         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4508         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4509         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4510
4511 /* 5150 Series Wifi/WiMax */
4512         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4513         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4514         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4515         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4516         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4517         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4518
4519         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4520         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4521         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4522         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4523
4524 /* 6x00 Series */
4525         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4526         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4527         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4528         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4529         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4530         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4531         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4532         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4533         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4534         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4535
4536 /* 6x05 Series */
4537         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4538         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4539         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4540         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4541         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4542         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4543         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4544
4545 /* 6x30 Series */
4546         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4547         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4548         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4549         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4550         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4551         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4552         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4553         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4554         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4555         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4556         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4557         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4558         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4559         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4560         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4561         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4562
4563 /* 6x50 WiFi/WiMax Series */
4564         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4565         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4566         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4567         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4568         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4569         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4570
4571 /* 6150 WiFi/WiMax Series */
4572         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4573         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4574         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4575         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4576         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4577         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4578
4579 /* 1000 Series WiFi */
4580         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4581         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4582         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4583         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4584         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4585         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4586         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4587         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4588         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4589         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4590         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4591         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4592
4593 /* 100 Series WiFi */
4594         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4595         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4596         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4597         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4598         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4599         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4600
4601 /* 130 Series WiFi */
4602         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4603         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4604         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4605         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4606         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4607         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4608
4609 /* 2x00 Series */
4610         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4611         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4612         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4613         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4614         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4615         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4616
4617 /* 2x30 Series */
4618         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4621         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4622         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4623         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4624
4625 /* 6x35 Series */
4626         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4627         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4628         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4629         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4630         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4631         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4632         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4633         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4634         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4635
4636 /* 200 Series */
4637         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4638         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4639         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4640         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4641         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4642         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4643
4644 /* 230 Series */
4645         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4646         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4647         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4648         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4649         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4650         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4651
4652 #endif /* CONFIG_IWL5000 */
4653
4654         {0}
4655 };
4656 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4657
4658 static struct pci_driver iwl_driver = {
4659         .name = DRV_NAME,
4660         .id_table = iwl_hw_card_ids,
4661         .probe = iwl_pci_probe,
4662         .remove = __devexit_p(iwl_pci_remove),
4663         .driver.pm = IWL_PM_OPS,
4664 };
4665
4666 static int __init iwl_init(void)
4667 {
4668
4669         int ret;
4670         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4671         pr_info(DRV_COPYRIGHT "\n");
4672
4673         ret = iwlagn_rate_control_register();
4674         if (ret) {
4675                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4676                 return ret;
4677         }
4678
4679         ret = pci_register_driver(&iwl_driver);
4680         if (ret) {
4681                 pr_err("Unable to initialize PCI module\n");
4682                 goto error_register;
4683         }
4684
4685         return ret;
4686
4687 error_register:
4688         iwlagn_rate_control_unregister();
4689         return ret;
4690 }
4691
4692 static void __exit iwl_exit(void)
4693 {
4694         pci_unregister_driver(&iwl_driver);
4695         iwlagn_rate_control_unregister();
4696 }
4697
4698 module_exit(iwl_exit);
4699 module_init(iwl_init);
4700
4701 #ifdef CONFIG_IWLWIFI_DEBUG
4702 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4703 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4704 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4705 MODULE_PARM_DESC(debug, "debug output mask");
4706 #endif
4707
4708 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4709 MODULE_PARM_DESC(swcrypto50,
4710                  "using crypto in software (default 0 [hardware]) (deprecated)");
4711 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4712 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4713 module_param_named(queues_num50,
4714                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4715 MODULE_PARM_DESC(queues_num50,
4716                  "number of hw queues in 50xx series (deprecated)");
4717 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4718 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4719 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4720 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4721 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4722 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4723 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4724                    int, S_IRUGO);
4725 MODULE_PARM_DESC(amsdu_size_8K50,
4726                  "enable 8K amsdu size in 50XX series (deprecated)");
4727 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4728                    int, S_IRUGO);
4729 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4730 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4731 MODULE_PARM_DESC(fw_restart50,
4732                  "restart firmware in case of error (deprecated)");
4733 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4734 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4735 module_param_named(
4736         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4737 MODULE_PARM_DESC(disable_hw_scan,
4738                  "disable hardware scanning (default 0) (deprecated)");
4739
4740 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4741                    S_IRUGO);
4742 MODULE_PARM_DESC(ucode_alternative,
4743                  "specify ucode alternative to use from ucode file");
4744
4745 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4746 MODULE_PARM_DESC(antenna_coupling,
4747                  "specify antenna coupling in dB (defualt: 0 dB)");
4748
4749 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4750 MODULE_PARM_DESC(bt_ch_inhibition,
4751                  "Disable BT channel inhibition (default: enable)");